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1061 lines
32 KiB
C
1061 lines
32 KiB
C
/**
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******************************************************************************
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* @file stm32h747i_discovery_qspi.c
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* @author MCD Application Team
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* @brief This file includes a standard driver for the MT25TL01G QSPI
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* memory mounted on STM32H747I-DISCO board.
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@verbatim
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How To use this driver:
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-----------------------
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- This driver is used to drive the MT25TL01G QSPI external
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memory mounted on STM32H747I-DISCO board.
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- This driver need a specific component driver (MT25TL01G) to be included with.
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Driver description:
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-------------------
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- Initialization steps:
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+ Initialize the QPSI external memory using the BSP_QSPI_Init() function. This
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function includes the MSP layer hardware resources initialization and the
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QSPI interface with the external memory.
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STR and DTR transfer rates are supported.
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SPI, SPI 2-IO, SPI-4IO and QPI modes are supported
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- QSPI memory operations
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+ QSPI memory can be accessed with read/write operations once it is
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initialized.
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Read/write operation can be performed with AHB access using the functions
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BSP_QSPI_Read()/BSP_QSPI_Write().
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+ The function BSP_QSPI_GetInfo() returns the configuration of the QSPI memory.
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(see the QSPI memory data sheet)
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+ Perform erase block operation using the function BSP_QSPI_EraseBlock() and by
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specifying the block address. You can perform an erase operation of the whole
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chip by calling the function BSP_QSPI_EraseChip().
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+ The function BSP_QSPI_GetStatus() returns the current status of the QSPI memory.
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(see the QSPI memory data sheet)
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+ The function BSP_QSPI_EnableMemoryMappedMode enables the QSPI memory mapped mode
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+ The function BSP_QSPI_DisableMemoryMappedMode disables the QSPI memory mapped mode
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+ The function BSP_QSPI_ConfigFlash() allow to configure the QSPI mode and transfer rate
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Note:
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--------
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Regarding the "Instance" parameter, needed for all functions, it is used to select
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an QSPI instance. On the STM32H747I_DISCO board, there's one instance. Then, this
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parameter should be 0.
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@endverbatim
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2018 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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*/
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/* Includes ------------------------------------------------------------------*/
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#include "stm32h747i_discovery_qspi.h"
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/** @addtogroup BSP
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* @{
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*/
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/** @addtogroup STM32H747I_DISCO
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* @{
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*/
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/** @defgroup STM32H747I_DISCO_QSPI QSPI
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* @{
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*/
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/* Private variables ---------------------------------------------------------*/
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/** @defgroup STM32H747I_DISCO_QSPI_Exported_Variables Exported Variables
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* @{
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*/
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QSPI_HandleTypeDef hqspi;
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BSP_QSPI_Ctx_t QSPI_Ctx[QSPI_INSTANCES_NUMBER];
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/**
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* @}
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*/
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/* Private functions ---------------------------------------------------------*/
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/** @defgroup STM32H747I_DISCO_QSPI_Private_Functions Private Functions
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* @{
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*/
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static void QSPI_MspInit(QSPI_HandleTypeDef *hQspi);
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static void QSPI_MspDeInit(QSPI_HandleTypeDef *hSspi);
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static int32_t QSPI_ResetMemory(uint32_t Instance);
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static int32_t QSPI_DummyCyclesCfg(uint32_t Instance);
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/**
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* @}
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*/
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/** @defgroup STM32H747I_DISCO_QSPI_Exported_Functions Exported Functions
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* @{
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*/
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/**
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* @brief Initializes the QSPI interface.
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* Instance management :
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* Instance can running at Indirect or MMP mode.
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* Every indirect instance can switch between.
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* Once MMP instance active then Instance switch function disabled.
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* Only 1 MMP instance can run.
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* Instance switch function enabled after MMP instance exit to Indirect mode.
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*
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* MT25TL01G action :
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* QE(Quad Enable, Non-volatile) bit of Status Register
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* QE = 0; WP# & RESET# pin active
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* Accept 1-1-1, 1-1-2, 1-2-2 commands
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* QE = 1; WP# become SIO2 pin, RESET# become SIO3 pin
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* Accept 1-1-1, 1-1-2, 1-2-2, 1-1-4, 1-4-4 commands
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* Enter QPI mode by issue EQIO(0x35) command from 1-1-1 mode
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* Accept 4-4-4 commands
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* Exit QPI mode by issue RSTQIO(0xF5) command from 4-4-4 mode
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* Accept commands, dependent QE bit status
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* Memory Read commands support STR(Single Transfer Rate) & DTR(Double Transfer Rate) mode
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*
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* Force QE = 1, Enter 4-Byte address mode
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* Configure Dummy cycle & ODS(Out Driver Strength)
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* STR/DTR effect read commands only
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* @param Instance QSPI Instance
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* @param Init QSPI Init structure
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* @retval BSP status
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*/
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int32_t BSP_QSPI_Init(uint32_t Instance, BSP_QSPI_Init_t *Init)
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{
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int32_t ret = BSP_ERROR_NONE;
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BSP_QSPI_Info_t pInfo;
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MX_QSPI_Init_t qspi_init;
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/* Table to handle clock prescalers:
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1: For STR mode to reach max 108Mhz
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3: For DTR mode to reach max 54Mhz
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*/
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static const uint32_t PrescalerTab[2] = {1, 3};
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/* Check if the instance is supported */
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if(Instance >= QSPI_INSTANCES_NUMBER)
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{
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ret = BSP_ERROR_WRONG_PARAM;
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}
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else
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{
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/* Check if instance is already initialized */
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if(QSPI_Ctx[Instance].IsInitialized == QSPI_ACCESS_NONE)
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{
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#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
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/* Register the QSPI MSP Callbacks */
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if(QSPI_Ctx[Instance].IsMspCallbacksValid == 0UL)
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{
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if(BSP_QSPI_RegisterDefaultMspCallbacks(Instance) != BSP_ERROR_NONE)
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{
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ret = BSP_ERROR_PERIPH_FAILURE;
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}
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}
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#else
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/* Msp QSPI initialization */
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QSPI_MspInit(&hqspi);
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#endif /* USE_HAL_QSPI_REGISTER_CALLBACKS */
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if(ret == BSP_ERROR_NONE)
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{
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/* STM32 QSPI interface initialization */
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(void)MT25TL01G_GetFlashInfo(&pInfo);
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qspi_init.ClockPrescaler = PrescalerTab[Init->TransferRate];
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qspi_init.DualFlashMode = QSPI_DUALFLASH_ENABLE;
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qspi_init.FlashSize = (uint32_t)POSITION_VAL((uint32_t)pInfo.FlashSize) - 1U;
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qspi_init.SampleShifting = (Init->TransferRate == BSP_QSPI_STR_TRANSFER) ? QSPI_SAMPLE_SHIFTING_HALFCYCLE : QSPI_SAMPLE_SHIFTING_NONE;
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if(MX_QSPI_Init(&hqspi, &qspi_init) != HAL_OK)
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{
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ret = BSP_ERROR_PERIPH_FAILURE;
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}/* QSPI memory reset */
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else if(QSPI_ResetMemory(Instance) != BSP_ERROR_NONE)
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{
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ret = BSP_ERROR_COMPONENT_FAILURE;
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}/* Force Flash enter 4 Byte address mode */
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else if(MT25TL01G_AutoPollingMemReady(&hqspi, QSPI_Ctx[Instance].InterfaceMode) != MT25TL01G_OK)
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{
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ret = BSP_ERROR_COMPONENT_FAILURE;
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}
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else if(MT25TL01G_Enter4BytesAddressMode(&hqspi, QSPI_Ctx[Instance].InterfaceMode) != MT25TL01G_OK)
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{
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ret = BSP_ERROR_COMPONENT_FAILURE;
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}/* Configuration of the dummy cycles on QSPI memory side */
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else if(QSPI_DummyCyclesCfg(Instance) != BSP_ERROR_NONE)
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{
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ret = BSP_ERROR_COMPONENT_FAILURE;
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}
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else
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{
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/* Configure Flash to desired mode */
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if(BSP_QSPI_ConfigFlash(Instance, Init->InterfaceMode, Init->TransferRate) != BSP_ERROR_NONE)
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{
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ret = BSP_ERROR_COMPONENT_FAILURE;
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}
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}
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}
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}
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}
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/* Return BSP status */
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return ret;
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}
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/**
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* @brief De-Initializes the QSPI interface.
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* @param Instance QSPI Instance
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* @retval BSP status
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*/
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int32_t BSP_QSPI_DeInit(uint32_t Instance)
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{
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int32_t ret = BSP_ERROR_NONE;
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/* Check if the instance is supported */
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if(Instance >= QSPI_INSTANCES_NUMBER)
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{
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ret = BSP_ERROR_WRONG_PARAM;
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}
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else
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{
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if(QSPI_Ctx[Instance].IsInitialized == QSPI_ACCESS_MMP)
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{
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if(BSP_QSPI_DisableMemoryMappedMode(Instance) != BSP_ERROR_NONE)
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{
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ret = BSP_ERROR_COMPONENT_FAILURE;
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}
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}
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if(ret == BSP_ERROR_NONE)
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{
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/* Set default QSPI_Ctx values */
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QSPI_Ctx[Instance].IsInitialized = QSPI_ACCESS_NONE;
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QSPI_Ctx[Instance].InterfaceMode = BSP_QSPI_SPI_MODE;
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QSPI_Ctx[Instance].TransferRate = BSP_QSPI_STR_TRANSFER;
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QSPI_Ctx[Instance].DualFlashMode = QSPI_DUALFLASH_ENABLE;
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#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 0)
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QSPI_MspDeInit(&hqspi);
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#endif /* (USE_HAL_QSPI_REGISTER_CALLBACKS == 0) */
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/* Call the DeInit function to reset the driver */
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if (HAL_QSPI_DeInit(&hqspi) != HAL_OK)
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{
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ret = BSP_ERROR_PERIPH_FAILURE;
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}
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}
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}
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/* Return BSP status */
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return ret;
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}
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/**
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* @brief Initializes the QSPI interface.
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* @param hQspi QSPI handle
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* @param Config QSPI configuration structure
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* @retval BSP status
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*/
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__weak HAL_StatusTypeDef MX_QSPI_Init(QSPI_HandleTypeDef *hQspi, MX_QSPI_Init_t *Config)
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{
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/* QSPI initialization */
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/* QSPI freq = SYSCLK /(1 + ClockPrescaler) Mhz */
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hQspi->Instance = QUADSPI;
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hQspi->Init.ClockPrescaler = Config->ClockPrescaler;
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hQspi->Init.FifoThreshold = 1;
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hQspi->Init.SampleShifting = Config->SampleShifting;
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hQspi->Init.FlashSize = Config->FlashSize;
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hQspi->Init.ChipSelectHighTime = QSPI_CS_HIGH_TIME_4_CYCLE; /* Min 50ns for nonRead */
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hQspi->Init.ClockMode = QSPI_CLOCK_MODE_0;
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hQspi->Init.FlashID = QSPI_FLASH_ID_1;
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hQspi->Init.DualFlash = Config->DualFlashMode;
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return HAL_QSPI_Init(hQspi);
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}
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#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
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/**
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* @brief Default BSP QSPI Msp Callbacks
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* @param Instance QSPI Instance
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* @retval BSP status
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*/
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int32_t BSP_QSPI_RegisterDefaultMspCallbacks (uint32_t Instance)
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{
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int32_t ret = BSP_ERROR_NONE;
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/* Check if the instance is supported */
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if(Instance >= QSPI_INSTANCES_NUMBER)
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{
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ret = BSP_ERROR_WRONG_PARAM;
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}
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else
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{
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/* Register MspInit/MspDeInit Callbacks */
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if(HAL_QSPI_RegisterCallback(&hqspi, HAL_QSPI_MSPINIT_CB_ID, QSPI_MspInit) != HAL_OK)
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{
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ret = BSP_ERROR_PERIPH_FAILURE;
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}
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else if(HAL_QSPI_RegisterCallback(&hqspi, HAL_QSPI_MSPDEINIT_CB_ID, QSPI_MspDeInit) != HAL_OK)
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{
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ret = BSP_ERROR_PERIPH_FAILURE;
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}
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else
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{
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QSPI_Ctx[Instance].IsMspCallbacksValid = 1U;
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}
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}
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/* Return BSP status */
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return ret;
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}
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/**
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* @brief BSP QSPI Msp Callback registering
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* @param Instance QSPI Instance
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* @param CallBacks pointer to MspInit/MspDeInit callbacks functions
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* @retval BSP status
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*/
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int32_t BSP_QSPI_RegisterMspCallbacks (uint32_t Instance, BSP_QSPI_Cb_t *CallBacks)
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{
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int32_t ret = BSP_ERROR_NONE;
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/* Check if the instance is supported */
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if(Instance >= QSPI_INSTANCES_NUMBER)
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{
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ret = BSP_ERROR_WRONG_PARAM;
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}
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else
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{
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/* Register MspInit/MspDeInit Callbacks */
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if(HAL_QSPI_RegisterCallback(&hqspi, HAL_QSPI_MSPINIT_CB_ID, CallBacks->pMspInitCb) != HAL_OK)
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{
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ret = BSP_ERROR_PERIPH_FAILURE;
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}
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else if(HAL_QSPI_RegisterCallback(&hqspi, HAL_QSPI_MSPDEINIT_CB_ID, CallBacks->pMspDeInitCb) != HAL_OK)
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{
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ret = BSP_ERROR_PERIPH_FAILURE;
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}
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else
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{
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QSPI_Ctx[Instance].IsMspCallbacksValid = 1U;
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}
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}
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/* Return BSP status */
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return ret;
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}
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#endif /* (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) */
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/**
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* @brief Reads an amount of data from the QSPI memory.
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* @param Instance QSPI instance
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* @param pData Pointer to data to be read
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* @param ReadAddr Read start address
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* @param Size Size of data to read
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* @retval BSP status
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*/
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int32_t BSP_QSPI_Read(uint32_t Instance, uint8_t *pData, uint32_t ReadAddr, uint32_t Size)
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{
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int32_t ret = BSP_ERROR_NONE;
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/* Check if the instance is supported */
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if(Instance >= QSPI_INSTANCES_NUMBER)
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{
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ret = BSP_ERROR_WRONG_PARAM;
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}
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else
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{
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if(QSPI_Ctx[Instance].TransferRate == BSP_QSPI_STR_TRANSFER)
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{
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if(MT25TL01G_ReadSTR(&hqspi, QSPI_Ctx[Instance].InterfaceMode, pData, ReadAddr, Size) != MT25TL01G_OK)
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{
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ret = BSP_ERROR_COMPONENT_FAILURE;
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}
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}
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else
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{
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if(MT25TL01G_ReadDTR(&hqspi, QSPI_Ctx[Instance].InterfaceMode, pData, ReadAddr, Size) != MT25TL01G_OK)
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{
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ret = BSP_ERROR_COMPONENT_FAILURE;
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}
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}
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}
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/* Return BSP status */
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return ret;
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}
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|
|
/**
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* @brief Writes an amount of data to the QSPI memory.
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* @param Instance QSPI instance
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* @param pData Pointer to data to be written
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* @param WriteAddr Write start address
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* @param Size Size of data to write
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* @retval BSP status
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*/
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int32_t BSP_QSPI_Write(uint32_t Instance, uint8_t *pData, uint32_t WriteAddr, uint32_t Size)
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{
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int32_t ret = BSP_ERROR_NONE;
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uint32_t end_addr, current_size, current_addr;
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uint8_t *write_data;
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|
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/* Check if the instance is supported */
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if(Instance >= QSPI_INSTANCES_NUMBER)
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{
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ret = BSP_ERROR_WRONG_PARAM;
|
|
}
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else
|
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{
|
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/* Calculation of the size between the write address and the end of the page */
|
|
current_size = MT25TL01G_PAGE_SIZE - (WriteAddr % MT25TL01G_PAGE_SIZE);
|
|
|
|
/* Check if the size of the data is less than the remaining place in the page */
|
|
if (current_size > Size)
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{
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current_size = Size;
|
|
}
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|
|
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/* Initialize the address variables */
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current_addr = WriteAddr;
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end_addr = WriteAddr + Size;
|
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write_data = pData;
|
|
|
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/* Perform the write page by page */
|
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do
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{
|
|
/* Check if Flash busy ? */
|
|
if(MT25TL01G_AutoPollingMemReady(&hqspi, QSPI_Ctx[Instance].InterfaceMode) != MT25TL01G_OK)
|
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{
|
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ret = BSP_ERROR_COMPONENT_FAILURE;
|
|
}/* Enable write operations */
|
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else if(MT25TL01G_WriteEnable(&hqspi, QSPI_Ctx[Instance].InterfaceMode) != MT25TL01G_OK)
|
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{
|
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ret = BSP_ERROR_COMPONENT_FAILURE;
|
|
}/* Issue page program command */
|
|
else if(MT25TL01G_PageProgram(&hqspi, QSPI_Ctx[Instance].InterfaceMode, write_data, current_addr, current_size) != MT25TL01G_OK)
|
|
{
|
|
ret = BSP_ERROR_COMPONENT_FAILURE;
|
|
}/* Configure automatic polling mode to wait for end of program */
|
|
else if (MT25TL01G_AutoPollingMemReady(&hqspi, QSPI_Ctx[Instance].InterfaceMode) != MT25TL01G_OK)
|
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{
|
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ret = BSP_ERROR_COMPONENT_FAILURE;
|
|
}
|
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else
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|
{
|
|
/* Update the address and size variables for next page programming */
|
|
current_addr += current_size;
|
|
write_data += current_size;
|
|
current_size = ((current_addr + MT25TL01G_PAGE_SIZE) > end_addr) ? (end_addr - current_addr) : MT25TL01G_PAGE_SIZE;
|
|
}
|
|
} while ((current_addr < end_addr) && (ret == BSP_ERROR_NONE));
|
|
}
|
|
|
|
/* Return BSP status */
|
|
return ret;
|
|
}
|
|
|
|
/**
|
|
* @brief Erases the specified block of the QSPI memory.
|
|
* MT25TL01G support 4K, 32K, 64K size block erase commands for each Die.
|
|
* i.e 8K, 64K, 128K at BSP level (see BSP_QSPI_Erase_t type definition)
|
|
* @param Instance QSPI instance
|
|
* @param BlockAddress Block address to erase
|
|
* @param BlockSize Erase Block size
|
|
* @retval BSP status
|
|
*/
|
|
int32_t BSP_QSPI_EraseBlock(uint32_t Instance, uint32_t BlockAddress, BSP_QSPI_Erase_t BlockSize)
|
|
{
|
|
int32_t ret = BSP_ERROR_NONE;
|
|
|
|
/* Check if the instance is supported */
|
|
if(Instance >= QSPI_INSTANCES_NUMBER)
|
|
{
|
|
ret = BSP_ERROR_WRONG_PARAM;
|
|
}
|
|
else
|
|
{
|
|
/* Check Flash busy ? */
|
|
if(MT25TL01G_AutoPollingMemReady(&hqspi, QSPI_Ctx[Instance].InterfaceMode) != MT25TL01G_OK)
|
|
{
|
|
ret = BSP_ERROR_COMPONENT_FAILURE;
|
|
}/* Enable write operations */
|
|
else if(MT25TL01G_WriteEnable(&hqspi, QSPI_Ctx[Instance].InterfaceMode) != MT25TL01G_OK)
|
|
{
|
|
ret = BSP_ERROR_COMPONENT_FAILURE;
|
|
}
|
|
else
|
|
{
|
|
/* Issue Block Erase command */
|
|
if(MT25TL01G_BlockErase(&hqspi, QSPI_Ctx[Instance].InterfaceMode, BlockAddress, (MT25TL01G_Erase_t)BlockSize) != MT25TL01G_OK)
|
|
{
|
|
ret = BSP_ERROR_COMPONENT_FAILURE;
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Return BSP status */
|
|
return ret;
|
|
}
|
|
|
|
/**
|
|
* @brief Erases the entire QSPI memory.
|
|
* @param Instance QSPI instance
|
|
* @retval BSP status
|
|
*/
|
|
int32_t BSP_QSPI_EraseChip(uint32_t Instance)
|
|
{
|
|
int32_t ret = BSP_ERROR_NONE;
|
|
|
|
/* Check if the instance is supported */
|
|
if(Instance >= QSPI_INSTANCES_NUMBER)
|
|
{
|
|
ret = BSP_ERROR_WRONG_PARAM;
|
|
}
|
|
else
|
|
{
|
|
/* Check Flash busy ? */
|
|
if(MT25TL01G_AutoPollingMemReady(&hqspi, QSPI_Ctx[Instance].InterfaceMode) != MT25TL01G_OK)
|
|
{
|
|
ret = BSP_ERROR_COMPONENT_FAILURE;
|
|
}/* Enable write operations */
|
|
else if (MT25TL01G_WriteEnable(&hqspi, QSPI_Ctx[Instance].InterfaceMode) != MT25TL01G_OK)
|
|
{
|
|
ret = BSP_ERROR_COMPONENT_FAILURE;
|
|
}
|
|
else
|
|
{
|
|
/* Issue Chip erase command */
|
|
if(MT25TL01G_ChipErase(&hqspi, QSPI_Ctx[Instance].InterfaceMode) != MT25TL01G_OK)
|
|
{
|
|
ret = BSP_ERROR_COMPONENT_FAILURE;
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Return BSP status */
|
|
return ret;
|
|
}
|
|
|
|
/**
|
|
* @brief Reads current status of the QSPI memory.
|
|
* If WIP != 0 then return busy.
|
|
* @param Instance QSPI instance
|
|
* @retval QSPI memory status: whether busy or not
|
|
*/
|
|
int32_t BSP_QSPI_GetStatus(uint32_t Instance)
|
|
{
|
|
int32_t ret = BSP_ERROR_NONE;
|
|
uint8_t reg;
|
|
|
|
/* Check if the instance is supported */
|
|
if(Instance >= QSPI_INSTANCES_NUMBER)
|
|
{
|
|
ret = BSP_ERROR_WRONG_PARAM;
|
|
}
|
|
else
|
|
{
|
|
if(MT25TL01G_ReadStatusRegister(&hqspi, QSPI_Ctx[Instance].InterfaceMode, ®) != MT25TL01G_OK)
|
|
{
|
|
ret = BSP_ERROR_COMPONENT_FAILURE;
|
|
}
|
|
else
|
|
{
|
|
/* Check the value of the register */
|
|
if ((reg & MT25TL01G_SR_WIP) != 0U)
|
|
{
|
|
ret = BSP_ERROR_BUSY;
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Return BSP status */
|
|
return ret;
|
|
}
|
|
|
|
/**
|
|
* @brief Return the configuration of the QSPI memory.
|
|
* @param Instance QSPI instance
|
|
* @param pInfo pointer on the configuration structure
|
|
* @retval BSP status
|
|
*/
|
|
int32_t BSP_QSPI_GetInfo(uint32_t Instance, BSP_QSPI_Info_t *pInfo)
|
|
{
|
|
int32_t ret = BSP_ERROR_NONE;
|
|
|
|
/* Check if the instance is supported */
|
|
if(Instance >= QSPI_INSTANCES_NUMBER)
|
|
{
|
|
ret = BSP_ERROR_WRONG_PARAM;
|
|
}
|
|
else
|
|
{
|
|
(void)MT25TL01G_GetFlashInfo(pInfo);
|
|
}
|
|
|
|
/* Return BSP status */
|
|
return ret;
|
|
}
|
|
|
|
/**
|
|
* @brief Configure the QSPI in memory-mapped mode
|
|
* Only 1 Instance can running MMP mode. And it will lock system at this mode.
|
|
* @param Instance QSPI instance
|
|
* @retval BSP status
|
|
*/
|
|
int32_t BSP_QSPI_EnableMemoryMappedMode(uint32_t Instance)
|
|
{
|
|
int32_t ret = BSP_ERROR_NONE;
|
|
|
|
/* Check if the instance is supported */
|
|
if(Instance >= QSPI_INSTANCES_NUMBER)
|
|
{
|
|
ret = BSP_ERROR_WRONG_PARAM;
|
|
}
|
|
else
|
|
{
|
|
if(QSPI_Ctx[Instance].TransferRate == BSP_QSPI_STR_TRANSFER)
|
|
{
|
|
if(MT25TL01G_EnableMemoryMappedModeSTR(&hqspi, QSPI_Ctx[Instance].InterfaceMode) != MT25TL01G_OK)
|
|
{
|
|
ret = BSP_ERROR_COMPONENT_FAILURE;
|
|
}
|
|
else /* Update QSPI context if all operations are well done */
|
|
{
|
|
QSPI_Ctx[Instance].IsInitialized = QSPI_ACCESS_MMP;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
if(MT25TL01G_EnableMemoryMappedModeDTR(&hqspi, QSPI_Ctx[Instance].InterfaceMode) != MT25TL01G_OK)
|
|
{
|
|
ret = BSP_ERROR_COMPONENT_FAILURE;
|
|
}
|
|
else /* Update QSPI context if all operations are well done */
|
|
{
|
|
QSPI_Ctx[Instance].IsInitialized = QSPI_ACCESS_MMP;
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Return BSP status */
|
|
return ret;
|
|
}
|
|
|
|
/**
|
|
* @brief Exit form memory-mapped mode
|
|
* Only 1 Instance can running MMP mode. And it will lock system at this mode.
|
|
* @param Instance QSPI instance
|
|
* @retval BSP status
|
|
*/
|
|
int32_t BSP_QSPI_DisableMemoryMappedMode(uint32_t Instance)
|
|
{
|
|
uint8_t Dummy;
|
|
int32_t ret = BSP_ERROR_NONE;
|
|
|
|
/* Check if the instance is supported */
|
|
if(Instance >= QSPI_INSTANCES_NUMBER)
|
|
{
|
|
ret = BSP_ERROR_WRONG_PARAM;
|
|
}
|
|
else
|
|
{
|
|
if(QSPI_Ctx[Instance].IsInitialized != QSPI_ACCESS_MMP)
|
|
{
|
|
ret = BSP_ERROR_QSPI_MMP_UNLOCK_FAILURE;
|
|
}/* Abort MMP back to indirect mode */
|
|
else if(HAL_QSPI_Abort(&hqspi) != HAL_OK)
|
|
{
|
|
ret = BSP_ERROR_PERIPH_FAILURE;
|
|
}
|
|
else
|
|
{
|
|
/* Force QSPI interface Sampling Shift to half cycle */
|
|
hqspi.Init.SampleShifting = QSPI_SAMPLE_SHIFTING_HALFCYCLE;
|
|
|
|
if(HAL_QSPI_Init(&hqspi)!= HAL_OK)
|
|
{
|
|
ret = BSP_ERROR_PERIPH_FAILURE;
|
|
}
|
|
/* Dummy read for exit from Performance Enhance mode */
|
|
else if(MT25TL01G_ReadSTR(&hqspi, QSPI_Ctx[Instance].InterfaceMode, &Dummy, 0, 1) != MT25TL01G_OK)
|
|
{
|
|
ret = BSP_ERROR_COMPONENT_FAILURE;
|
|
}
|
|
else /* Update QSPI context if all operations are well done */
|
|
{
|
|
QSPI_Ctx[Instance].IsInitialized = QSPI_ACCESS_INDIRECT;
|
|
}
|
|
}
|
|
}
|
|
/* Return BSP status */
|
|
return ret;
|
|
}
|
|
|
|
/**
|
|
* @brief Get flash ID, 3 Byte
|
|
* Manufacturer ID, Memory type, Memory density
|
|
* @param Instance QSPI instance
|
|
* @param Id QSPI Identifier
|
|
* @retval BSP status
|
|
*/
|
|
int32_t BSP_QSPI_ReadID(uint32_t Instance, uint8_t *Id)
|
|
{
|
|
int32_t ret = BSP_ERROR_NONE;
|
|
|
|
/* Check if the instance is supported */
|
|
if(Instance >= QSPI_INSTANCES_NUMBER)
|
|
{
|
|
ret = BSP_ERROR_WRONG_PARAM;
|
|
}
|
|
else
|
|
{
|
|
if(MT25TL01G_ReadID(&hqspi, QSPI_Ctx[Instance].InterfaceMode, Id) != MT25TL01G_OK)
|
|
{
|
|
ret = BSP_ERROR_COMPONENT_FAILURE;
|
|
}
|
|
}
|
|
|
|
/* Return BSP status */
|
|
return ret;
|
|
}
|
|
|
|
/**
|
|
* @brief Set Flash to desired Interface mode. And this instance becomes current instance.
|
|
* If current instance running at MMP mode then this function isn't work.
|
|
* Indirect -> Indirect
|
|
* @param Instance QSPI instance
|
|
* @param Mode QSPI mode
|
|
* @param Rate QSPI transfer rate
|
|
* @retval BSP status
|
|
*/
|
|
int32_t BSP_QSPI_ConfigFlash(uint32_t Instance, BSP_QSPI_Interface_t Mode, BSP_QSPI_Transfer_t Rate)
|
|
{
|
|
int32_t ret = BSP_ERROR_NONE;
|
|
|
|
/* Check if the instance is supported */
|
|
if(Instance >= QSPI_INSTANCES_NUMBER)
|
|
{
|
|
ret = BSP_ERROR_WRONG_PARAM;
|
|
}
|
|
else
|
|
{
|
|
/* Check if MMP mode locked ************************************************/
|
|
if(QSPI_Ctx[Instance].IsInitialized == QSPI_ACCESS_MMP)
|
|
{
|
|
ret = BSP_ERROR_QSPI_MMP_LOCK_FAILURE;
|
|
}
|
|
else
|
|
{
|
|
/* Setup MCU transfer rate setting ***************************************************/
|
|
hqspi.Init.SampleShifting = (Rate == BSP_QSPI_STR_TRANSFER) ? QSPI_SAMPLE_SHIFTING_HALFCYCLE : QSPI_SAMPLE_SHIFTING_NONE;
|
|
|
|
if(HAL_QSPI_Init(&hqspi)!= HAL_OK)
|
|
{
|
|
ret = BSP_ERROR_PERIPH_FAILURE;
|
|
}
|
|
else
|
|
{
|
|
/* Setup Flash interface ***************************************************/
|
|
switch(QSPI_Ctx[Instance].InterfaceMode)
|
|
{
|
|
case MT25TL01G_QPI_MODE : /* 4-4-4 commands */
|
|
if(Mode != MT25TL01G_QPI_MODE)
|
|
{
|
|
if(MT25TL01G_ExitQPIMode(&hqspi) != MT25TL01G_OK)
|
|
{
|
|
ret = BSP_ERROR_COMPONENT_FAILURE;
|
|
}
|
|
}
|
|
break;
|
|
|
|
case BSP_QSPI_SPI_MODE : /* 1-1-1 commands, Power on H/W default setting */
|
|
case BSP_QSPI_SPI_2IO_MODE : /* 1-2-2 read commands */
|
|
case BSP_QSPI_SPI_4IO_MODE : /* 1-4-4 read commands */
|
|
default :
|
|
if(Mode == MT25TL01G_QPI_MODE)
|
|
{
|
|
if(MT25TL01G_EnterQPIMode(&hqspi) != MT25TL01G_OK)
|
|
{
|
|
ret = BSP_ERROR_COMPONENT_FAILURE;
|
|
}
|
|
}
|
|
break;
|
|
}
|
|
|
|
/* Update QSPI context if all operations are well done */
|
|
if(ret == BSP_ERROR_NONE)
|
|
{
|
|
/* Update current status parameter *****************************************/
|
|
QSPI_Ctx[Instance].IsInitialized = QSPI_ACCESS_INDIRECT;
|
|
QSPI_Ctx[Instance].InterfaceMode = Mode;
|
|
QSPI_Ctx[Instance].TransferRate = Rate;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Return BSP status */
|
|
return ret;
|
|
}
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup STM32H747I_DISCO_QSPI_Private_Functions Private Functions
|
|
* @{
|
|
*/
|
|
|
|
/**
|
|
* @brief QSPI MSP Initialization
|
|
* @param hQspi : QSPI handle
|
|
* This function configures the hardware resources used in this example:
|
|
* - Peripheral's clock enable
|
|
* - Peripheral's GPIO Configuration
|
|
* - NVIC configuration for QSPI interrupt
|
|
* @retval None
|
|
*/
|
|
static void QSPI_MspInit(QSPI_HandleTypeDef *hQspi)
|
|
{
|
|
GPIO_InitTypeDef gpio_init_structure;
|
|
|
|
/*##-1- Enable peripherals and GPIO Clocks #################################*/
|
|
/* Enable the QuadSPI memory interface clock */
|
|
QSPI_CLK_ENABLE();
|
|
/* Reset the QuadSPI memory interface */
|
|
QSPI_FORCE_RESET();
|
|
QSPI_RELEASE_RESET();
|
|
/* Enable GPIO clocks */
|
|
QSPI_CLK_GPIO_CLK_ENABLE();
|
|
QSPI_BK1_CS_GPIO_CLK_ENABLE();
|
|
QSPI_BK1_D0_GPIO_CLK_ENABLE();
|
|
QSPI_BK1_D1_GPIO_CLK_ENABLE();
|
|
QSPI_BK1_D2_GPIO_CLK_ENABLE();
|
|
QSPI_BK1_D3_GPIO_CLK_ENABLE();
|
|
|
|
QSPI_BK2_CS_GPIO_CLK_ENABLE();
|
|
QSPI_BK2_D0_GPIO_CLK_ENABLE();
|
|
QSPI_BK2_D1_GPIO_CLK_ENABLE();
|
|
QSPI_BK2_D2_GPIO_CLK_ENABLE();
|
|
QSPI_BK2_D3_GPIO_CLK_ENABLE();
|
|
|
|
/*##-2- Configure peripheral GPIO ##########################################*/
|
|
/* QSPI CLK GPIO pin configuration */
|
|
gpio_init_structure.Pin = QSPI_CLK_PIN;
|
|
gpio_init_structure.Mode = GPIO_MODE_AF_PP;
|
|
gpio_init_structure.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
gpio_init_structure.Pull = GPIO_NOPULL;
|
|
gpio_init_structure.Alternate = GPIO_AF9_QUADSPI;
|
|
HAL_GPIO_Init(QSPI_CLK_GPIO_PORT, &gpio_init_structure);
|
|
|
|
/* QSPI CS GPIO pin configuration */
|
|
gpio_init_structure.Pin = QSPI_BK1_CS_PIN;
|
|
gpio_init_structure.Pull = GPIO_PULLUP;
|
|
gpio_init_structure.Alternate = GPIO_AF10_QUADSPI;
|
|
HAL_GPIO_Init(QSPI_BK1_CS_GPIO_PORT, &gpio_init_structure);
|
|
|
|
/* QSPI D0 GPIO pin configuration */
|
|
gpio_init_structure.Pin = QSPI_BK1_D0_PIN;
|
|
gpio_init_structure.Pull = GPIO_NOPULL;
|
|
gpio_init_structure.Alternate = GPIO_AF9_QUADSPI;
|
|
HAL_GPIO_Init(QSPI_BK1_D0_GPIO_PORT, &gpio_init_structure);
|
|
|
|
gpio_init_structure.Pin = QSPI_BK2_D0_PIN;
|
|
gpio_init_structure.Alternate = GPIO_AF9_QUADSPI;
|
|
HAL_GPIO_Init(QSPI_BK2_D0_GPIO_PORT, &gpio_init_structure);
|
|
|
|
/* QSPI D1 GPIO pin configuration */
|
|
gpio_init_structure.Pin = QSPI_BK1_D1_PIN;
|
|
gpio_init_structure.Alternate = GPIO_AF10_QUADSPI;
|
|
HAL_GPIO_Init(QSPI_BK1_D1_GPIO_PORT, &gpio_init_structure);
|
|
|
|
gpio_init_structure.Pin = QSPI_BK2_D1_PIN;
|
|
gpio_init_structure.Alternate = GPIO_AF9_QUADSPI;
|
|
HAL_GPIO_Init(QSPI_BK2_D1_GPIO_PORT, &gpio_init_structure);
|
|
|
|
/* QSPI D2 GPIO pin configuration */
|
|
gpio_init_structure.Pin = QSPI_BK1_D2_PIN;
|
|
gpio_init_structure.Alternate = GPIO_AF9_QUADSPI;
|
|
HAL_GPIO_Init(QSPI_BK1_D2_GPIO_PORT, &gpio_init_structure);
|
|
|
|
gpio_init_structure.Pin = QSPI_BK2_D2_PIN;
|
|
HAL_GPIO_Init(QSPI_BK2_D2_GPIO_PORT, &gpio_init_structure);
|
|
|
|
/* QSPI D3 GPIO pin configuration */
|
|
gpio_init_structure.Pin = QSPI_BK1_D3_PIN;
|
|
HAL_GPIO_Init(QSPI_BK1_D3_GPIO_PORT, &gpio_init_structure);
|
|
|
|
gpio_init_structure.Pin = QSPI_BK2_D3_PIN;
|
|
HAL_GPIO_Init(QSPI_BK2_D3_GPIO_PORT, &gpio_init_structure);
|
|
|
|
/*##-3- Configure the NVIC for QSPI #########################################*/
|
|
/* NVIC configuration for QSPI interrupt */
|
|
HAL_NVIC_SetPriority(QUADSPI_IRQn, 0x0F, 0);
|
|
HAL_NVIC_EnableIRQ(QUADSPI_IRQn);
|
|
}
|
|
|
|
/**
|
|
* @brief QSPI MSP De-Initialization
|
|
* @param hQspi QSPI handle
|
|
* This function frees the hardware resources used in this example:
|
|
* - Disable the Peripheral's clock
|
|
* - Revert GPIO and NVIC configuration to their default state
|
|
* @retval None
|
|
*/
|
|
static void QSPI_MspDeInit(QSPI_HandleTypeDef *hQspi)
|
|
{
|
|
/* Prevent unused argument(s) compilation warning */
|
|
UNUSED(hQspi);
|
|
|
|
/*##-2- Disable peripherals and GPIO Clocks ################################*/
|
|
/* De-Configure QSPI pins */
|
|
HAL_GPIO_DeInit(QSPI_CLK_GPIO_PORT, QSPI_CLK_PIN);
|
|
HAL_GPIO_DeInit(QSPI_BK1_CS_GPIO_PORT, QSPI_BK1_CS_PIN);
|
|
HAL_GPIO_DeInit(QSPI_BK1_D0_GPIO_PORT, QSPI_BK1_D0_PIN);
|
|
HAL_GPIO_DeInit(QSPI_BK1_D1_GPIO_PORT, QSPI_BK1_D1_PIN);
|
|
HAL_GPIO_DeInit(QSPI_BK1_D2_GPIO_PORT, QSPI_BK1_D2_PIN);
|
|
HAL_GPIO_DeInit(QSPI_BK1_D3_GPIO_PORT, QSPI_BK1_D3_PIN);
|
|
|
|
HAL_GPIO_DeInit(QSPI_BK2_CS_GPIO_PORT, QSPI_BK2_CS_PIN);
|
|
HAL_GPIO_DeInit(QSPI_BK2_D0_GPIO_PORT, QSPI_BK2_D0_PIN);
|
|
HAL_GPIO_DeInit(QSPI_BK2_D1_GPIO_PORT, QSPI_BK2_D1_PIN);
|
|
HAL_GPIO_DeInit(QSPI_BK2_D2_GPIO_PORT, QSPI_BK2_D2_PIN);
|
|
HAL_GPIO_DeInit(QSPI_BK2_D3_GPIO_PORT, QSPI_BK2_D3_PIN);
|
|
|
|
/*##-3- Reset peripherals ##################################################*/
|
|
/* Reset the QuadSPI memory interface */
|
|
QSPI_FORCE_RESET();
|
|
QSPI_RELEASE_RESET();
|
|
|
|
/* Disable the QuadSPI memory interface clock */
|
|
QSPI_CLK_DISABLE();
|
|
}
|
|
|
|
/**
|
|
* @brief This function reset the QSPI Flash memory.
|
|
* Fore QPI+SPI reset to avoid system come from unknown status.
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* Flash accept 1-1-1, 1-1-2, 1-2-2 commands after reset.
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* @param Instance QSPI instance
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* @retval BSP status
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*/
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static int32_t QSPI_ResetMemory(uint32_t Instance)
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|
{
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int32_t ret = BSP_ERROR_NONE;
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|
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/* Send RESET ENABLE command in QPI mode (QUAD I/Os, 4-4-4) */
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if(MT25TL01G_ResetEnable(&hqspi, MT25TL01G_QPI_MODE) != MT25TL01G_OK)
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{
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ret =BSP_ERROR_COMPONENT_FAILURE;
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}/* Send RESET memory command in QPI mode (QUAD I/Os, 4-4-4) */
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else if(MT25TL01G_ResetMemory(&hqspi, MT25TL01G_QPI_MODE) != MT25TL01G_OK)
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{
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ret = BSP_ERROR_COMPONENT_FAILURE;
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}/* Wait Flash ready */
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else if(MT25TL01G_AutoPollingMemReady(&hqspi, QSPI_Ctx[Instance].InterfaceMode) != MT25TL01G_OK)
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|
{
|
|
ret = BSP_ERROR_COMPONENT_FAILURE;
|
|
}/* Send RESET ENABLE command in SPI mode (1-1-1) */
|
|
else if(MT25TL01G_ResetEnable(&hqspi, BSP_QSPI_SPI_MODE) != MT25TL01G_OK)
|
|
{
|
|
ret = BSP_ERROR_COMPONENT_FAILURE;
|
|
}/* Send RESET memory command in SPI mode (1-1-1) */
|
|
else if(MT25TL01G_ResetMemory(&hqspi, BSP_QSPI_SPI_MODE) != MT25TL01G_OK)
|
|
{
|
|
ret = BSP_ERROR_COMPONENT_FAILURE;
|
|
}
|
|
else
|
|
{
|
|
QSPI_Ctx[Instance].IsInitialized = QSPI_ACCESS_INDIRECT; /* After reset S/W setting to indirect access */
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QSPI_Ctx[Instance].InterfaceMode = BSP_QSPI_SPI_MODE; /* After reset H/W back to SPI mode by default */
|
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QSPI_Ctx[Instance].TransferRate = BSP_QSPI_STR_TRANSFER; /* After reset S/W setting to STR mode */
|
|
}
|
|
|
|
/* Return BSP status */
|
|
return ret;
|
|
}
|
|
|
|
/**
|
|
* @brief This function configure the dummy cycles on memory side.
|
|
* Dummy cycle bit locate in Configuration Register[7:6]
|
|
* @param Instance QSPI instance
|
|
* @retval BSP status
|
|
*/
|
|
static int32_t QSPI_DummyCyclesCfg(uint32_t Instance)
|
|
{
|
|
int32_t ret= BSP_ERROR_NONE;
|
|
QSPI_CommandTypeDef s_command;
|
|
uint16_t reg=0;
|
|
|
|
/* Initialize the read volatile configuration register command */
|
|
s_command.InstructionMode = QSPI_INSTRUCTION_4_LINES;
|
|
s_command.Instruction = MT25TL01G_READ_VOL_CFG_REG_CMD;
|
|
s_command.AddressMode = QSPI_ADDRESS_NONE;
|
|
s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
|
|
s_command.DataMode = QSPI_DATA_4_LINES;
|
|
s_command.DummyCycles = 0;
|
|
s_command.NbData = 2;
|
|
s_command.DdrMode = QSPI_DDR_MODE_DISABLE;
|
|
s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
|
|
s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
|
|
|
|
/* Configure the command */
|
|
if (HAL_QSPI_Command(&hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
|
|
{
|
|
return BSP_ERROR_COMPONENT_FAILURE;
|
|
}
|
|
|
|
/* Reception of the data */
|
|
if (HAL_QSPI_Receive(&hqspi, (uint8_t *)(®), HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
|
|
{
|
|
return BSP_ERROR_COMPONENT_FAILURE;
|
|
}
|
|
|
|
/* Enable write operations */
|
|
if (MT25TL01G_WriteEnable(&hqspi, QSPI_Ctx[Instance].InterfaceMode) != MT25TL01G_OK)
|
|
{
|
|
return BSP_ERROR_COMPONENT_FAILURE;
|
|
}
|
|
|
|
/* Update volatile configuration register (with new dummy cycles) */
|
|
s_command.Instruction = MT25TL01G_WRITE_VOL_CFG_REG_CMD;
|
|
MODIFY_REG(reg, 0xF0F0, ((MT25TL01G_DUMMY_CYCLES_READ_QUAD << 4) |
|
|
(MT25TL01G_DUMMY_CYCLES_READ_QUAD << 12)));
|
|
|
|
/* Configure the write volatile configuration register command */
|
|
if (HAL_QSPI_Command(&hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
|
|
{
|
|
return BSP_ERROR_COMPONENT_FAILURE;
|
|
}
|
|
|
|
/* Transmission of the data */
|
|
if (HAL_QSPI_Transmit(&hqspi, (uint8_t *)(®), HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
|
|
{
|
|
return BSP_ERROR_COMPONENT_FAILURE;
|
|
}
|
|
|
|
/* Return BSP status */
|
|
return ret;
|
|
}
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|