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@@ -0,0 +1,395 @@
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/**
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******************************************************************************
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* @file stm32h735g_discovery_ospi.h
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* @author MCD Application Team
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* @brief This file contains the common defines and functions prototypes for
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* the stm32h735g_discovery_ospi.c driver.
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2019 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef STM32H735G_DK_OSPI_H
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#define STM32H735G_DK_OSPI_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "stm32h735g_discovery_conf.h"
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#include "stm32h735g_discovery_errno.h"
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#include "../Components/mx25lm51245g/mx25lm51245g.h"
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#include "../Components/s70kl1281/s70kl1281.h"
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/** @addtogroup BSP
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* @{
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*/
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/** @addtogroup STM32H735G_DK
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* @{
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*/
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/** @addtogroup STM32H735G_DK_OSPI
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* @{
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*/
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/* Exported types ------------------------------------------------------------*/
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/** @defgroup STM32H735G_DK_OSPI_Exported_Types Exported Types
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* @{
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*/
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typedef enum
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{
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OSPI_ACCESS_NONE = 0, /*!< Instance not initialized, */
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OSPI_ACCESS_INDIRECT, /*!< Instance use indirect mode access */
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OSPI_ACCESS_MMP /*!< Instance use Memory Mapped Mode read */
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} OSPI_Access_t;
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#if (USE_HAL_OSPI_REGISTER_CALLBACKS == 1)
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typedef struct
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{
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pOSPI_CallbackTypeDef pMspInitCb;
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pOSPI_CallbackTypeDef pMspDeInitCb;
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} BSP_OSPI_Cb_t;
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#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS == 1) */
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typedef struct
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{
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uint32_t MemorySize;
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uint32_t ClockPrescaler;
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uint32_t SampleShifting;
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uint32_t TransferRate;
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} MX_OSPI_InitTypeDef;
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/**
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* @}
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*/
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/** @defgroup STM32H735G_DK_OSPI_NOR_Exported_Types OSPI_NOR Exported Types
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* @{
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*/
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#define BSP_OSPI_NOR_Info_t MX25LM51245G_Info_t
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#define BSP_OSPI_NOR_Interface_t MX25LM51245G_Interface_t
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#define BSP_OSPI_NOR_Transfer_t MX25LM51245G_Transfer_t
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#define BSP_OSPI_NOR_Erase_t MX25LM51245G_Erase_t
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typedef struct
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{
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OSPI_Access_t IsInitialized; /*!< Instance access Flash method */
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BSP_OSPI_NOR_Interface_t InterfaceMode; /*!< Flash Interface mode of Instance */
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BSP_OSPI_NOR_Transfer_t TransferRate; /*!< Flash Transfer mode of Instance */
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uint32_t IsMspCallbacksValid;
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} OSPI_NOR_Ctx_t;
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typedef struct
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{
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BSP_OSPI_NOR_Interface_t InterfaceMode; /*!< Current Flash Interface mode */
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BSP_OSPI_NOR_Transfer_t TransferRate; /*!< Current Flash Transfer rate */
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} BSP_OSPI_NOR_Init_t;
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/**
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* @}
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*/
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/** @defgroup STM32H735G_DK_OSPI_RAM_Exported_Types OSPI_RAM Exported Types
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* @{
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*/
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#define BSP_OSPI_RAM_BurstLength_t S70KL1281_BurstLength_t
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typedef enum
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{
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BSP_OSPI_RAM_VARIABLE_LATENCY = HAL_OSPI_VARIABLE_LATENCY,
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BSP_OSPI_RAM_FIXED_LATENCY = HAL_OSPI_FIXED_LATENCY
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} BSP_OSPI_RAM_Latency_t;
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typedef enum
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{
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BSP_OSPI_RAM_HYBRID_BURST = 0,
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BSP_OSPI_RAM_LINEAR_BURST
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} BSP_OSPI_RAM_BurstType_t;
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typedef struct
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{
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OSPI_Access_t IsInitialized; /*!< Instance access Flash method */
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BSP_OSPI_RAM_Latency_t LatencyType; /*!< Latency Type of Instance */
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BSP_OSPI_RAM_BurstType_t BurstType; /*!< Burst Type of Instance */
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BSP_OSPI_RAM_BurstLength_t BurstLength; /*!< Burst Length of Instance */
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uint32_t IsMspCallbacksValid;
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} OSPI_RAM_Ctx_t;
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typedef struct
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{
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BSP_OSPI_RAM_Latency_t LatencyType; /*!< Current HyperRAM Latency Type */
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BSP_OSPI_RAM_BurstType_t BurstType; /*!< Current HyperRAM Burst Type */
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BSP_OSPI_RAM_BurstLength_t BurstLength; /*!< Current HyperRAM Burst Length */
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} BSP_OSPI_RAM_Init_t;
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/**
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* @}
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*/
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/* Exported constants --------------------------------------------------------*/
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/** @defgroup STM32H735G_DK_OSPI_NOR_Exported_Constants OSPI_NOR Exported Constants
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* @{
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*/
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#define OSPI_NOR_INSTANCES_NUMBER 1U
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/* Definition for OSPI modes */
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#define BSP_OSPI_NOR_SPI_MODE (BSP_OSPI_NOR_Interface_t)MX25LM51245G_SPI_MODE /* 1 Cmd Line, 1 Address Line and 1 Data Line */
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#define BSP_OSPI_NOR_OPI_MODE (BSP_OSPI_NOR_Interface_t)MX25LM51245G_OPI_MODE /* 8 Cmd Lines, 8 Address Lines and 8 Data Lines */
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/* Definition for OSPI transfer rates */
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#define BSP_OSPI_NOR_STR_TRANSFER (BSP_OSPI_NOR_Transfer_t)MX25LM51245G_STR_TRANSFER /* Single Transfer Rate */
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#define BSP_OSPI_NOR_DTR_TRANSFER (BSP_OSPI_NOR_Transfer_t)MX25LM51245G_DTR_TRANSFER /* Double Transfer Rate */
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/* OSPI erase types */
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#define BSP_OSPI_NOR_ERASE_4K MX25LM51245G_ERASE_4K
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#define BSP_OSPI_NOR_ERASE_64K MX25LM51245G_ERASE_64K
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#define BSP_OSPI_NOR_ERASE_CHIP MX25LM51245G_ERASE_BULK
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/* OSPI block sizes */
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#define BSP_OSPI_NOR_BLOCK_4K MX25LM51245G_SUBSECTOR_4K
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#define BSP_OSPI_NOR_BLOCK_64K MX25LM51245G_SECTOR_64K
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/* Definition for OSPI clock resources */
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#define OSPI_NOR_CLK_ENABLE() __HAL_RCC_OSPI1_CLK_ENABLE()
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#define OSPI_NOR_CLK_DISABLE() __HAL_RCC_OSPI1_CLK_DISABLE()
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#define OSPI_NOR_FORCE_RESET() __HAL_RCC_OSPI1_FORCE_RESET()
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#define OSPI_NOR_RELEASE_RESET() __HAL_RCC_OSPI1_RELEASE_RESET()
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/* Definition for OSPI NOR Pins */
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#define OSPI_NOR_CS_GPIO_CLK_ENABLE() __HAL_RCC_GPIOG_CLK_ENABLE()
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#define OSPI_NOR_CS_PIN GPIO_PIN_6
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#define OSPI_NOR_CS_GPIO_PORT GPIOG
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#define OSPI_NOR_CS_PIN_AF GPIO_AF10_OCTOSPIM_P1
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#define OSPI_NOR_CLK_GPIO_CLK_ENABLE() __HAL_RCC_GPIOF_CLK_ENABLE()
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#define OSPI_NOR_CLK_PIN GPIO_PIN_10
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#define OSPI_NOR_CLK_GPIO_PORT GPIOF
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#define OSPI_NOR_CLK_PIN_AF GPIO_AF9_OCTOSPIM_P1
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#define OSPI_NOR_DQS_GPIO_CLK_ENABLE() __HAL_RCC_GPIOB_CLK_ENABLE()
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#define OSPI_NOR_DQS_PIN GPIO_PIN_2
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#define OSPI_NOR_DQS_GPIO_PORT GPIOB
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#define OSPI_NOR_DQS_PIN_AF GPIO_AF10_OCTOSPIM_P1
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#define OSPI_NOR_D0_GPIO_CLK_ENABLE() __HAL_RCC_GPIOD_CLK_ENABLE()
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#define OSPI_NOR_D0_PIN GPIO_PIN_11
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#define OSPI_NOR_D0_GPIO_PORT GPIOD
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#define OSPI_NOR_D0_PIN_AF GPIO_AF9_OCTOSPIM_P1
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#define OSPI_NOR_D1_GPIO_CLK_ENABLE() __HAL_RCC_GPIOD_CLK_ENABLE()
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#define OSPI_NOR_D1_PIN GPIO_PIN_12
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#define OSPI_NOR_D1_GPIO_PORT GPIOD
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#define OSPI_NOR_D1_PIN_AF GPIO_AF9_OCTOSPIM_P1
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#define OSPI_NOR_D2_GPIO_CLK_ENABLE() __HAL_RCC_GPIOE_CLK_ENABLE()
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#define OSPI_NOR_D2_PIN GPIO_PIN_2
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#define OSPI_NOR_D2_GPIO_PORT GPIOE
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#define OSPI_NOR_D2_PIN_AF GPIO_AF9_OCTOSPIM_P1
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#define OSPI_NOR_D3_GPIO_CLK_ENABLE() __HAL_RCC_GPIOD_CLK_ENABLE()
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#define OSPI_NOR_D3_PIN GPIO_PIN_13
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#define OSPI_NOR_D3_GPIO_PORT GPIOD
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#define OSPI_NOR_D3_PIN_AF GPIO_AF9_OCTOSPIM_P1
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#define OSPI_NOR_D4_GPIO_CLK_ENABLE() __HAL_RCC_GPIOD_CLK_ENABLE()
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#define OSPI_NOR_D4_PIN GPIO_PIN_4
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#define OSPI_NOR_D4_GPIO_PORT GPIOD
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#define OSPI_NOR_D4_PIN_AF GPIO_AF10_OCTOSPIM_P1
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#define OSPI_NOR_D5_GPIO_CLK_ENABLE() __HAL_RCC_GPIOD_CLK_ENABLE()
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#define OSPI_NOR_D5_PIN GPIO_PIN_5
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#define OSPI_NOR_D5_GPIO_PORT GPIOD
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#define OSPI_NOR_D5_PIN_AF GPIO_AF10_OCTOSPIM_P1
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#define OSPI_NOR_D6_GPIO_CLK_ENABLE() __HAL_RCC_GPIOG_CLK_ENABLE()
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#define OSPI_NOR_D6_PIN GPIO_PIN_9
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#define OSPI_NOR_D6_GPIO_PORT GPIOG
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#define OSPI_NOR_D6_PIN_AF GPIO_AF9_OCTOSPIM_P1
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#define OSPI_NOR_D7_GPIO_CLK_ENABLE() __HAL_RCC_GPIOD_CLK_ENABLE()
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#define OSPI_NOR_D7_PIN GPIO_PIN_7
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#define OSPI_NOR_D7_GPIO_PORT GPIOD
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#define OSPI_NOR_D7_PIN_AF GPIO_AF10_OCTOSPIM_P1
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/**
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* @}
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*/
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/** @defgroup STM32H735G_DK_OSPI_RAM_Exported_Constants OSPI_RAM Exported Constants
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* @{
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*/
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#define OSPI_RAM_INSTANCES_NUMBER 1U
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/* OSPI Burst length */
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#define BSP_OSPI_RAM_BURST_16_BYTES (BSP_OSPI_RAM_BurstLength_t)S70KL1281_BURST_16_BYTES
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#define BSP_OSPI_RAM_BURST_32_BYTES (BSP_OSPI_RAM_BurstLength_t)S70KL1281_BURST_32_BYTES
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#define BSP_OSPI_RAM_BURST_64_BYTES (BSP_OSPI_RAM_BurstLength_t)S70KL1281_BURST_64_BYTES
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#define BSP_OSPI_RAM_BURST_128_BYTES (BSP_OSPI_RAM_BurstLength_t)S70KL1281_BURST_128_BYTES
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/* DMA definitions for OSPI RAM DMA transfer */
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#define OSPI_RAM_MDMAx_CLK_ENABLE __HAL_RCC_MDMA_CLK_ENABLE
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#define OSPI_RAM_MDMAx_CLK_DISABLE __HAL_RCC_MDMA_CLK_DISABLE
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#define OSPI_RAM_MDMAx_CHANNEL MDMA_Channel0
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#define OSPI_RAM_MDMAx_IRQn MDMA_IRQn
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#define OPSI_RAM_MDMA_IRQHandler MDMA_IRQHandler
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/* Definition for OSPI clock resources */
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#define OSPI_RAM_CLK_ENABLE() __HAL_RCC_OSPI2_CLK_ENABLE()
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#define OSPI_RAM_CLK_DISABLE() __HAL_RCC_OSPI2_CLK_DISABLE()
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#define OSPI_RAM_FORCE_RESET() __HAL_RCC_OSPI2_FORCE_RESET()
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#define OSPI_RAM_RELEASE_RESET() __HAL_RCC_OSPI2_RELEASE_RESET()
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/* Definition for OSPI RAM Pins */
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#define OSPI_RAM_CS_GPIO_CLK_ENABLE() __HAL_RCC_GPIOG_CLK_ENABLE()
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#define OSPI_RAM_CS_PIN GPIO_PIN_12
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#define OSPI_RAM_CS_GPIO_PORT GPIOG
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#define OSPI_RAM_CS_PIN_AF GPIO_AF3_OCTOSPIM_P2
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#define OSPI_RAM_CLK_GPIO_CLK_ENABLE() __HAL_RCC_GPIOF_CLK_ENABLE()
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#define OSPI_RAM_CLK_PIN GPIO_PIN_4
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#define OSPI_RAM_CLK_GPIO_PORT GPIOF
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#define OSPI_RAM_CLK_PIN_AF GPIO_AF9_OCTOSPIM_P2
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#define OSPI_RAM_DQS_GPIO_CLK_ENABLE() __HAL_RCC_GPIOF_CLK_ENABLE()
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#define OSPI_RAM_DQS_PIN GPIO_PIN_12
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#define OSPI_RAM_DQS_GPIO_PORT GPIOF
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#define OSPI_RAM_DQS_PIN_AF GPIO_AF9_OCTOSPIM_P2
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#define OSPI_RAM_D0_GPIO_CLK_ENABLE() __HAL_RCC_GPIOF_CLK_ENABLE()
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#define OSPI_RAM_D0_PIN GPIO_PIN_0
|
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#define OSPI_RAM_D0_GPIO_PORT GPIOF
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#define OSPI_RAM_D0_PIN_AF GPIO_AF9_OCTOSPIM_P2
|
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#define OSPI_RAM_D1_GPIO_CLK_ENABLE() __HAL_RCC_GPIOF_CLK_ENABLE()
|
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#define OSPI_RAM_D1_PIN GPIO_PIN_1
|
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#define OSPI_RAM_D1_GPIO_PORT GPIOF
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#define OSPI_RAM_D1_PIN_AF GPIO_AF9_OCTOSPIM_P2
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#define OSPI_RAM_D2_GPIO_CLK_ENABLE() __HAL_RCC_GPIOF_CLK_ENABLE()
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#define OSPI_RAM_D2_PIN GPIO_PIN_2
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#define OSPI_RAM_D2_GPIO_PORT GPIOF
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#define OSPI_RAM_D2_PIN_AF GPIO_AF9_OCTOSPIM_P2
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#define OSPI_RAM_D3_GPIO_CLK_ENABLE() __HAL_RCC_GPIOF_CLK_ENABLE()
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#define OSPI_RAM_D3_PIN GPIO_PIN_3
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#define OSPI_RAM_D3_GPIO_PORT GPIOF
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#define OSPI_RAM_D3_PIN_AF GPIO_AF9_OCTOSPIM_P2
|
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|
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#define OSPI_RAM_D4_GPIO_CLK_ENABLE() __HAL_RCC_GPIOG_CLK_ENABLE()
|
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#define OSPI_RAM_D4_PIN GPIO_PIN_0
|
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#define OSPI_RAM_D4_GPIO_PORT GPIOG
|
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#define OSPI_RAM_D4_PIN_AF GPIO_AF9_OCTOSPIM_P2
|
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|
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#define OSPI_RAM_D5_GPIO_CLK_ENABLE() __HAL_RCC_GPIOG_CLK_ENABLE()
|
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#define OSPI_RAM_D5_PIN GPIO_PIN_1
|
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#define OSPI_RAM_D5_GPIO_PORT GPIOG
|
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#define OSPI_RAM_D5_PIN_AF GPIO_AF9_OCTOSPIM_P2
|
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|
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#define OSPI_RAM_D6_GPIO_CLK_ENABLE() __HAL_RCC_GPIOG_CLK_ENABLE()
|
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#define OSPI_RAM_D6_PIN GPIO_PIN_10
|
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#define OSPI_RAM_D6_GPIO_PORT GPIOG
|
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#define OSPI_RAM_D6_PIN_AF GPIO_AF3_OCTOSPIM_P2
|
||||
|
||||
#define OSPI_RAM_D7_GPIO_CLK_ENABLE() __HAL_RCC_GPIOG_CLK_ENABLE()
|
||||
#define OSPI_RAM_D7_PIN GPIO_PIN_11
|
||||
#define OSPI_RAM_D7_GPIO_PORT GPIOG
|
||||
#define OSPI_RAM_D7_PIN_AF GPIO_AF9_OCTOSPIM_P2
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported variables --------------------------------------------------------*/
|
||||
/** @addtogroup STM32H735G_DK_OSPI_NOR_Exported_Variables NOR Exported Variables
|
||||
* @{
|
||||
*/
|
||||
extern OSPI_HandleTypeDef hospi_nor[];
|
||||
extern OSPI_NOR_Ctx_t OSPINORCtx[];
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup STM32H735G_DK_OSPI_NOR_Exported_Functions NOR Exported Functions
|
||||
* @{
|
||||
*/
|
||||
int32_t BSP_OSPI_NOR_Init(uint32_t Instance, BSP_OSPI_NOR_Init_t *Init);
|
||||
int32_t BSP_OSPI_NOR_DeInit(uint32_t Instance);
|
||||
#if (USE_HAL_OSPI_REGISTER_CALLBACKS == 1)
|
||||
int32_t BSP_OSPI_NOR_RegisterMspCallbacks(uint32_t Instance, BSP_OSPI_Cb_t *CallBacks);
|
||||
int32_t BSP_OSPI_NOR_RegisterDefaultMspCallbacks(uint32_t Instance);
|
||||
#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS == 1) */
|
||||
int32_t BSP_OSPI_NOR_Read(uint32_t Instance, uint8_t *pData, uint32_t ReadAddr, uint32_t Size);
|
||||
int32_t BSP_OSPI_NOR_Write(uint32_t Instance, uint8_t *pData, uint32_t WriteAddr, uint32_t Size);
|
||||
int32_t BSP_OSPI_NOR_Erase_Block(uint32_t Instance, uint32_t BlockAddress, BSP_OSPI_NOR_Erase_t BlockSize);
|
||||
int32_t BSP_OSPI_NOR_Erase_Chip(uint32_t Instance);
|
||||
int32_t BSP_OSPI_NOR_GetStatus(uint32_t Instance);
|
||||
int32_t BSP_OSPI_NOR_GetInfo(uint32_t Instance, BSP_OSPI_NOR_Info_t *pInfo);
|
||||
int32_t BSP_OSPI_NOR_EnableMemoryMappedMode(uint32_t Instance);
|
||||
int32_t BSP_OSPI_NOR_DisableMemoryMappedMode(uint32_t Instance);
|
||||
int32_t BSP_OSPI_NOR_ReadID(uint32_t Instance, uint8_t *Id);
|
||||
int32_t BSP_OSPI_NOR_ConfigFlash(uint32_t Instance, BSP_OSPI_NOR_Interface_t Mode, BSP_OSPI_NOR_Transfer_t Rate);
|
||||
int32_t BSP_OSPI_NOR_SuspendErase(uint32_t Instance);
|
||||
int32_t BSP_OSPI_NOR_ResumeErase(uint32_t Instance);
|
||||
|
||||
/* These functions can be modified in case the current settings
|
||||
need to be changed for specific application needs */
|
||||
HAL_StatusTypeDef MX_OSPI_NOR_Init(OSPI_HandleTypeDef *hospi, MX_OSPI_InitTypeDef *Config);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/** @defgroup STM32H735G_DK_OSPI_RAM_Exported_FunctionsPrototypes OSPI_RAM Exported Functions Prototypes
|
||||
* @{
|
||||
*/
|
||||
int32_t BSP_OSPI_RAM_Init(uint32_t Instance, BSP_OSPI_RAM_Init_t *Init);
|
||||
int32_t BSP_OSPI_RAM_DeInit(uint32_t Instance);
|
||||
#if (USE_HAL_OSPI_REGISTER_CALLBACKS == 1)
|
||||
int32_t BSP_OSPI_RAM_RegisterMspCallbacks(uint32_t Instance, BSP_OSPI_Cb_t *CallBacks);
|
||||
int32_t BSP_OSPI_RAM_RegisterDefaultMspCallbacks(uint32_t Instance);
|
||||
#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS == 1) */
|
||||
int32_t BSP_OSPI_RAM_Read(uint32_t Instance, uint8_t *pData, uint32_t ReadAddr, uint32_t Size);
|
||||
int32_t BSP_OSPI_RAM_Read_DMA(uint32_t Instance, uint8_t *pData, uint32_t ReadAddr, uint32_t Size);
|
||||
int32_t BSP_OSPI_RAM_Write(uint32_t Instance, uint8_t *pData, uint32_t WriteAddr, uint32_t Size);
|
||||
int32_t BSP_OSPI_RAM_Write_DMA(uint32_t Instance, uint8_t *pData, uint32_t WriteAddr, uint32_t Size);
|
||||
int32_t BSP_OSPI_RAM_EnableMemoryMappedMode(uint32_t Instance);
|
||||
int32_t BSP_OSPI_RAM_DisableMemoryMappedMode(uint32_t Instance);
|
||||
int32_t BSP_OSPI_RAM_ConfigHyperRAM(uint32_t Instance, BSP_OSPI_RAM_Latency_t Latency,
|
||||
BSP_OSPI_RAM_BurstType_t BurstType, BSP_OSPI_RAM_BurstLength_t BurstLength);
|
||||
|
||||
void BSP_OSPI_RAM_DMA_IRQHandler(uint32_t Instance);
|
||||
void BSP_OSPI_RAM_IRQHandler(uint32_t Instance);
|
||||
|
||||
/* These functions can be modified in case the current settings
|
||||
need to be changed for specific application needs */
|
||||
HAL_StatusTypeDef MX_OSPI_RAM_Init(OSPI_HandleTypeDef *hospi, MX_OSPI_InitTypeDef *Init);
|
||||
HAL_StatusTypeDef MX_OSPI_ClockConfig(OSPI_HandleTypeDef *hospi);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32H735G_DK_OSPI_H */
|
||||
Reference in New Issue
Block a user