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<meta charset="utf-8" />
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<meta name="generator" content="pandoc" />
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<meta name="viewport" content="width=device-width, initial-scale=1.0, user-scalable=yes" />
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<title>Release Notes for S70KL1281 OCTOSPI HyperRAM Component Driver</title>
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<style type="text/css">
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code{white-space: pre-wrap;}
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span.smallcaps{font-variant: small-caps;}
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<body>
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<div class="row">
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<div class="col-sm-12 col-lg-4">
|
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<div class="card fluid">
|
||||
<div class="sectione dark">
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||||
<center>
|
||||
<h1 id="release-notes-for-s70kl1281-component-driver"><strong>Release Notes for S70KL1281 Component Driver</strong></h1>
|
||||
<p>Copyright © 2020 STMicroelectronics<br />
|
||||
</p>
|
||||
<a href="https://www.st.com" class="logo"><img src="_htmresc/st_logo.png" alt="ST logo" /></a>
|
||||
</center>
|
||||
</div>
|
||||
</div>
|
||||
<h1 id="license">License</h1>
|
||||
This software component is licensed by ST under BSD 3-Clause license, the “License”; You may not use this component except in compliance with the License. You may obtain a copy of the License at:
|
||||
<center>
|
||||
<a href="https://opensource.org/licenses/BSD-3-Clause">https://opensource.org/licenses/BSD-3-Clause</a>
|
||||
</center>
|
||||
<h1 id="purpose">Purpose</h1>
|
||||
<p>This driver provides a set of functions offered by S70KL1281 OCTOSPI HyperRAM component</p>
|
||||
</div>
|
||||
<div class="col-sm-12 col-lg-8">
|
||||
<h1 id="update-history">Update History</h1>
|
||||
<div class="collapse">
|
||||
<input type="checkbox" id="collapse-section1" checked aria-hidden="true"> <label for="collapse-section1" aria-hidden="true"><strong>V1.0.0 / 11-March-2020</strong></label>
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||||
<div>
|
||||
<h2 id="main-changes">Main Changes</h2>
|
||||
<ul>
|
||||
<li>First official release of <strong>S70KL1281</strong> OCTOSPI HyperRAM driver</li>
|
||||
</ul>
|
||||
</div>
|
||||
</div>
|
||||
</div>
|
||||
</div>
|
||||
<footer class="sticky">
|
||||
For complete documentation on <mark>STM32 Microcontrollers</mark> , visit: <span style="font-color: blue;"><a href="http://www.st.com/STM32">www.st.com</a></span>
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||||
</footer>
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||||
</body>
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</html>
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||||
@@ -0,0 +1,54 @@
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||||
---
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||||
pagetitle: Release Notes for S70KL1281 OCTOSPI HyperRAM Component Driver
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||||
lang: en
|
||||
---
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||||
::: {.row}
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||||
::: {.col-sm-12 .col-lg-4}
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||||
|
||||
::: {.card .fluid}
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::: {.sectione .dark}
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||||
<center>
|
||||
# **Release Notes for S70KL1281 Component Driver**
|
||||
Copyright © 2020 STMicroelectronics\
|
||||
|
||||
[](https://www.st.com){.logo}
|
||||
</center>
|
||||
:::
|
||||
:::
|
||||
|
||||
# License
|
||||
|
||||
This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this component except in
|
||||
compliance with the License. You may obtain a copy of the License at:
|
||||
<center>
|
||||
[https://opensource.org/licenses/BSD-3-Clause](https://opensource.org/licenses/BSD-3-Clause)
|
||||
</center>
|
||||
|
||||
# Purpose
|
||||
|
||||
This driver provides a set of functions offered by S70KL1281 OCTOSPI HyperRAM component
|
||||
|
||||
:::
|
||||
|
||||
::: {.col-sm-12 .col-lg-8}
|
||||
# Update History
|
||||
|
||||
::: {.collapse}
|
||||
<input type="checkbox" id="collapse-section1" checked aria-hidden="true">
|
||||
<label for="collapse-section1" aria-hidden="true">__V1.0.0 / 11-March-2020__</label>
|
||||
<div>
|
||||
|
||||
## Main Changes
|
||||
|
||||
- First official release of **S70KL1281** OCTOSPI HyperRAM driver
|
||||
|
||||
</div>
|
||||
:::
|
||||
|
||||
:::
|
||||
:::
|
||||
|
||||
<footer class="sticky">
|
||||
For complete documentation on <mark>STM32 Microcontrollers</mark> ,
|
||||
visit: [[www.st.com](http://www.st.com/STM32)]{style="font-color: blue;"}
|
||||
</footer>
|
||||
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||||
/**
|
||||
******************************************************************************
|
||||
* @file s70kl1281.c
|
||||
* @modify MCD Application Team
|
||||
* @brief This file provides the S70KL1281 OSPI drivers.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2020 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "s70kl1281.h"
|
||||
|
||||
/** @addtogroup BSP
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup Components
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup S70KL1281 S70KL1281
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup S70KL1281_Exported_Functions S70KL1281 Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Read/Write Array Commands *********************/
|
||||
/**
|
||||
* @brief Reads an amount of data from the OSPI memory.
|
||||
* @param Ctx Component object pointer
|
||||
* @param pData Pointer to data to be read
|
||||
* @param ReadAddr Read start address
|
||||
* @param Size Size of data to read
|
||||
* @retval OSPI memory status
|
||||
*/
|
||||
int32_t S70KL1281_Read(OSPI_HandleTypeDef *Ctx, uint8_t *pData, uint32_t ReadAddr, uint32_t Size)
|
||||
{
|
||||
OSPI_HyperbusCmdTypeDef sCommand;
|
||||
|
||||
/* Initialize the read command */
|
||||
sCommand.AddressSpace = HAL_OSPI_MEMORY_ADDRESS_SPACE;
|
||||
sCommand.AddressSize = HAL_OSPI_ADDRESS_32_BITS;
|
||||
sCommand.Address = ReadAddr;
|
||||
sCommand.DQSMode = HAL_OSPI_DQS_ENABLE;
|
||||
sCommand.NbData = Size;
|
||||
|
||||
/* Configure the command */
|
||||
if (HAL_OSPI_HyperbusCmd(Ctx, &sCommand, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
|
||||
{
|
||||
return S70KL1281_ERROR;
|
||||
}
|
||||
|
||||
/* Reception of the data */
|
||||
if (HAL_OSPI_Receive(Ctx, pData, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
|
||||
{
|
||||
return S70KL1281_ERROR;
|
||||
}
|
||||
|
||||
return S70KL1281_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reads an amount of data in DMA mode from the OSPI memory.
|
||||
* @param Ctx Component object pointer
|
||||
* @param pData Pointer to data to be read
|
||||
* @param ReadAddr Read start address
|
||||
* @param Size Size of data to read
|
||||
* @retval OSPI memory status
|
||||
*/
|
||||
int32_t S70KL1281_Read_DMA(OSPI_HandleTypeDef *Ctx, uint8_t *pData, uint32_t ReadAddr, uint32_t Size)
|
||||
{
|
||||
OSPI_HyperbusCmdTypeDef sCommand;
|
||||
|
||||
/* Initialize the read command */
|
||||
sCommand.AddressSpace = HAL_OSPI_MEMORY_ADDRESS_SPACE;
|
||||
sCommand.AddressSize = HAL_OSPI_ADDRESS_32_BITS;
|
||||
sCommand.Address = ReadAddr;
|
||||
sCommand.DQSMode = HAL_OSPI_DQS_ENABLE;
|
||||
sCommand.NbData = Size;
|
||||
|
||||
/* Configure the command */
|
||||
if (HAL_OSPI_HyperbusCmd(Ctx, &sCommand, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
|
||||
{
|
||||
return S70KL1281_ERROR;
|
||||
}
|
||||
|
||||
/* Reception of the data */
|
||||
if (HAL_OSPI_Receive_DMA(Ctx, pData) != HAL_OK)
|
||||
{
|
||||
return S70KL1281_ERROR;
|
||||
}
|
||||
|
||||
return S70KL1281_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Writes an amount of data to the OSPI memory.
|
||||
* @param Ctx Component object pointer
|
||||
* @param pData Pointer to data to be written
|
||||
* @param WriteAddr Write start address
|
||||
* @param Size Size of data to write
|
||||
* @retval OSPI memory status
|
||||
*/
|
||||
int32_t S70KL1281_Write(OSPI_HandleTypeDef *Ctx, uint8_t *pData, uint32_t WriteAddr, uint32_t Size)
|
||||
{
|
||||
OSPI_HyperbusCmdTypeDef sCommand;
|
||||
|
||||
/* Initialize the write command */
|
||||
sCommand.AddressSpace = HAL_OSPI_MEMORY_ADDRESS_SPACE;
|
||||
sCommand.AddressSize = HAL_OSPI_ADDRESS_32_BITS;
|
||||
sCommand.Address = WriteAddr;
|
||||
sCommand.DQSMode = HAL_OSPI_DQS_ENABLE;
|
||||
sCommand.NbData = Size;
|
||||
|
||||
/* Configure the command */
|
||||
if (HAL_OSPI_HyperbusCmd(Ctx, &sCommand, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
|
||||
{
|
||||
return S70KL1281_ERROR;
|
||||
}
|
||||
|
||||
/* Transmission of the data */
|
||||
if (HAL_OSPI_Transmit(Ctx, pData, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
|
||||
{
|
||||
return S70KL1281_ERROR;
|
||||
}
|
||||
|
||||
return S70KL1281_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Writes an amount of data in DMA mode to the OSPI memory.
|
||||
* @param Ctx Component object pointer
|
||||
* @param pData Pointer to data to be written
|
||||
* @param WriteAddr Write start address
|
||||
* @param Size Size of data to write
|
||||
* @retval OSPI memory status
|
||||
*/
|
||||
int32_t S70KL1281_Write_DMA(OSPI_HandleTypeDef *Ctx, uint8_t *pData, uint32_t WriteAddr, uint32_t Size)
|
||||
{
|
||||
OSPI_HyperbusCmdTypeDef sCommand;
|
||||
|
||||
/* Initialize the write command */
|
||||
sCommand.AddressSpace = HAL_OSPI_MEMORY_ADDRESS_SPACE;
|
||||
sCommand.AddressSize = HAL_OSPI_ADDRESS_32_BITS;
|
||||
sCommand.Address = WriteAddr;
|
||||
sCommand.DQSMode = HAL_OSPI_DQS_ENABLE;
|
||||
sCommand.NbData = Size;
|
||||
|
||||
/* Configure the command */
|
||||
if (HAL_OSPI_HyperbusCmd(Ctx, &sCommand, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
|
||||
{
|
||||
return S70KL1281_ERROR;
|
||||
}
|
||||
|
||||
/* Transmission of the data */
|
||||
if (HAL_OSPI_Transmit_DMA(Ctx, pData) != HAL_OK)
|
||||
{
|
||||
return S70KL1281_ERROR;
|
||||
}
|
||||
|
||||
return S70KL1281_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable memory mapped mode for the OSPI memory.
|
||||
* @param Ctx Component object pointer
|
||||
* @retval OSPI memory status
|
||||
*/
|
||||
int32_t S70KL1281_EnableMemoryMappedMode(OSPI_HandleTypeDef *Ctx)
|
||||
{
|
||||
OSPI_HyperbusCmdTypeDef sCommand;
|
||||
OSPI_MemoryMappedTypeDef sMemMappedCfg;
|
||||
|
||||
/* OctoSPI Hyperbus command configuration */
|
||||
sCommand.AddressSpace = HAL_OSPI_MEMORY_ADDRESS_SPACE;
|
||||
sCommand.AddressSize = HAL_OSPI_ADDRESS_32_BITS;
|
||||
sCommand.Address = 0;
|
||||
sCommand.DQSMode = HAL_OSPI_DQS_ENABLE;
|
||||
sCommand.NbData = 1;
|
||||
|
||||
if (HAL_OSPI_HyperbusCmd(Ctx, &sCommand, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
|
||||
{
|
||||
return S70KL1281_ERROR;
|
||||
}
|
||||
|
||||
/* OctoSPI activation of memory-mapped mode */
|
||||
sMemMappedCfg.TimeOutActivation = HAL_OSPI_TIMEOUT_COUNTER_DISABLE;
|
||||
|
||||
if (HAL_OSPI_MemoryMapped(Ctx, &sMemMappedCfg) != HAL_OK)
|
||||
{
|
||||
return S70KL1281_ERROR;
|
||||
}
|
||||
|
||||
return S70KL1281_OK;
|
||||
}
|
||||
|
||||
/* Register/Setting Commands **************************************************/
|
||||
/**
|
||||
* @brief Read configuration register 0 value
|
||||
* @param Ctx Component object pointer
|
||||
* @param Value Register value pointer
|
||||
* @retval error status
|
||||
*/
|
||||
int32_t S70KL1281_ReadCfgReg0(OSPI_HandleTypeDef *Ctx, uint16_t *Value)
|
||||
{
|
||||
OSPI_HyperbusCmdTypeDef sCommand;
|
||||
|
||||
/* Initialize the read command */
|
||||
sCommand.AddressSpace = HAL_OSPI_REGISTER_ADDRESS_SPACE;
|
||||
sCommand.AddressSize = HAL_OSPI_ADDRESS_32_BITS;
|
||||
sCommand.Address = S70KL1281_CR0_ADDRESS;
|
||||
sCommand.DQSMode = HAL_OSPI_DQS_ENABLE;
|
||||
sCommand.NbData = 2U;
|
||||
|
||||
/* Configure the command */
|
||||
if (HAL_OSPI_HyperbusCmd(Ctx, &sCommand, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
|
||||
{
|
||||
return S70KL1281_ERROR;
|
||||
}
|
||||
|
||||
/* Reception of the data */
|
||||
if (HAL_OSPI_Receive(Ctx, (uint8_t *)Value, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
|
||||
{
|
||||
return S70KL1281_ERROR;
|
||||
}
|
||||
|
||||
return S70KL1281_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Write configuration register 0
|
||||
* @param Ctx Component object pointer
|
||||
* @param Value Value to write to register
|
||||
* @retval error status
|
||||
*/
|
||||
int32_t S70KL1281_WriteCfgReg0(OSPI_HandleTypeDef *Ctx, uint16_t Value, uint32_t LatencyMode, uint32_t InitialLatency)
|
||||
{
|
||||
OSPI_HyperbusCfgTypeDef sHyperbusCfg;
|
||||
OSPI_HyperbusCmdTypeDef sCommand;
|
||||
|
||||
/* Reconfigure peripheral as no write latency to write in registers */
|
||||
sHyperbusCfg.RWRecoveryTime = RW_RECOVERY_TIME;
|
||||
sHyperbusCfg.AccessTime = InitialLatency;
|
||||
sHyperbusCfg.WriteZeroLatency = HAL_OSPI_NO_LATENCY_ON_WRITE;
|
||||
sHyperbusCfg.LatencyMode = LatencyMode;
|
||||
|
||||
if (HAL_OSPI_HyperbusCfg(Ctx, &sHyperbusCfg, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
|
||||
{
|
||||
return S70KL1281_ERROR;
|
||||
}
|
||||
|
||||
/* Initialize the write command */
|
||||
sCommand.AddressSpace = HAL_OSPI_REGISTER_ADDRESS_SPACE;
|
||||
sCommand.AddressSize = HAL_OSPI_ADDRESS_32_BITS;
|
||||
sCommand.Address = S70KL1281_CR0_ADDRESS;
|
||||
sCommand.DQSMode = HAL_OSPI_DQS_ENABLE;
|
||||
sCommand.NbData = 2U;
|
||||
|
||||
/* Configure the command */
|
||||
if (HAL_OSPI_HyperbusCmd(Ctx, &sCommand, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
|
||||
{
|
||||
return S70KL1281_ERROR;
|
||||
}
|
||||
|
||||
/* Transmission of the data */
|
||||
if (HAL_OSPI_Transmit(Ctx, (uint8_t *)(&Value), HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
|
||||
{
|
||||
return S70KL1281_ERROR;
|
||||
}
|
||||
|
||||
/* Reconfigure peripheral for correct write access */
|
||||
sHyperbusCfg.WriteZeroLatency = HAL_OSPI_LATENCY_ON_WRITE;
|
||||
|
||||
if (HAL_OSPI_HyperbusCfg(Ctx, &sHyperbusCfg, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
|
||||
{
|
||||
return S70KL1281_ERROR;
|
||||
}
|
||||
|
||||
return S70KL1281_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Read configuration register 1 value
|
||||
* @param Ctx Component object pointer
|
||||
* @param Value Register value pointer
|
||||
* @retval error status
|
||||
*/
|
||||
int32_t S70KL1281_ReadCfgReg1(OSPI_HandleTypeDef *Ctx, uint16_t *Value)
|
||||
{
|
||||
OSPI_HyperbusCmdTypeDef sCommand;
|
||||
|
||||
/* Initialize the read command */
|
||||
sCommand.AddressSpace = HAL_OSPI_REGISTER_ADDRESS_SPACE;
|
||||
sCommand.AddressSize = HAL_OSPI_ADDRESS_32_BITS;
|
||||
sCommand.Address = S70KL1281_CR1_ADDRESS;
|
||||
sCommand.DQSMode = HAL_OSPI_DQS_ENABLE;
|
||||
sCommand.NbData = 2U;
|
||||
|
||||
/* Configure the command */
|
||||
if (HAL_OSPI_HyperbusCmd(Ctx, &sCommand, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
|
||||
{
|
||||
return S70KL1281_ERROR;
|
||||
}
|
||||
|
||||
/* Reception of the data */
|
||||
if (HAL_OSPI_Receive(Ctx, (uint8_t *)Value, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
|
||||
{
|
||||
return S70KL1281_ERROR;
|
||||
}
|
||||
|
||||
return S70KL1281_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Write configuration register 1
|
||||
* @param Ctx Component object pointer
|
||||
* @param Value Value to write to register
|
||||
* @retval error status
|
||||
*/
|
||||
int32_t S70KL1281_WriteCfgReg1(OSPI_HandleTypeDef *Ctx, uint16_t Value, uint32_t LatencyMode, uint32_t InitialLatency)
|
||||
{
|
||||
OSPI_HyperbusCfgTypeDef sHyperbusCfg;
|
||||
OSPI_HyperbusCmdTypeDef sCommand;
|
||||
|
||||
/* Reconfigure peripheral as no write latency to write in registers */
|
||||
sHyperbusCfg.RWRecoveryTime = RW_RECOVERY_TIME;
|
||||
sHyperbusCfg.AccessTime = InitialLatency;
|
||||
sHyperbusCfg.WriteZeroLatency = HAL_OSPI_NO_LATENCY_ON_WRITE;
|
||||
sHyperbusCfg.LatencyMode = LatencyMode;
|
||||
|
||||
if (HAL_OSPI_HyperbusCfg(Ctx, &sHyperbusCfg, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
|
||||
{
|
||||
return S70KL1281_ERROR;
|
||||
}
|
||||
|
||||
/* Initialize the write command */
|
||||
sCommand.AddressSpace = HAL_OSPI_REGISTER_ADDRESS_SPACE;
|
||||
sCommand.AddressSize = HAL_OSPI_ADDRESS_32_BITS;
|
||||
sCommand.Address = S70KL1281_CR1_ADDRESS;
|
||||
sCommand.DQSMode = HAL_OSPI_DQS_ENABLE;
|
||||
sCommand.NbData = 2U;
|
||||
|
||||
/* Configure the command */
|
||||
if (HAL_OSPI_HyperbusCmd(Ctx, &sCommand, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
|
||||
{
|
||||
return S70KL1281_ERROR;
|
||||
}
|
||||
|
||||
/* Transmission of the data */
|
||||
if (HAL_OSPI_Transmit(Ctx, (uint8_t *)(&Value), HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
|
||||
{
|
||||
return S70KL1281_ERROR;
|
||||
}
|
||||
|
||||
/* Reconfigure peripheral for correct write access */
|
||||
sHyperbusCfg.WriteZeroLatency = HAL_OSPI_LATENCY_ON_WRITE;
|
||||
|
||||
if (HAL_OSPI_HyperbusCfg(Ctx, &sHyperbusCfg, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
|
||||
{
|
||||
return S70KL1281_ERROR;
|
||||
}
|
||||
|
||||
return S70KL1281_OK;
|
||||
}
|
||||
|
||||
/* ID Commands ****************************************************************/
|
||||
/**
|
||||
* @brief Read Flash IDs.
|
||||
* Manufacturer ID, Memory type, Memory density
|
||||
* @param Ctx Component object pointer
|
||||
* @param ID IDs pointer (2 * 16-bits value)
|
||||
* @retval error status
|
||||
*/
|
||||
int32_t S70KL1281_ReadID(OSPI_HandleTypeDef *Ctx, uint16_t *ID)
|
||||
{
|
||||
OSPI_HyperbusCmdTypeDef sCommand;
|
||||
uint16_t *data = ID;
|
||||
|
||||
/* Initialize the write command */
|
||||
sCommand.AddressSpace = HAL_OSPI_REGISTER_ADDRESS_SPACE;
|
||||
sCommand.AddressSize = HAL_OSPI_ADDRESS_32_BITS;
|
||||
sCommand.Address = S70KL1281_DIR0_ADDRESS;
|
||||
sCommand.DQSMode = HAL_OSPI_DQS_ENABLE;
|
||||
sCommand.NbData = 2U;
|
||||
|
||||
/* Configure the command */
|
||||
if (HAL_OSPI_HyperbusCmd(Ctx, &sCommand, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
|
||||
{
|
||||
return S70KL1281_ERROR;
|
||||
}
|
||||
|
||||
/* Reception of the data */
|
||||
if (HAL_OSPI_Receive(Ctx, (uint8_t *)data, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
|
||||
{
|
||||
return S70KL1281_ERROR;
|
||||
}
|
||||
|
||||
data++;
|
||||
sCommand.Address = S70KL1281_DIR1_ADDRESS;
|
||||
|
||||
/* Configure the command */
|
||||
if (HAL_OSPI_HyperbusCmd(Ctx, &sCommand, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
|
||||
{
|
||||
return S70KL1281_ERROR;
|
||||
}
|
||||
|
||||
/* Reception of the data */
|
||||
if (HAL_OSPI_Receive(Ctx, (uint8_t *)data, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
|
||||
{
|
||||
return S70KL1281_ERROR;
|
||||
}
|
||||
|
||||
return S70KL1281_OK;
|
||||
}
|
||||
|
||||
/* Power down Commands ********************************************************/
|
||||
/**
|
||||
* @brief Flash enter deep power-down command
|
||||
* @param Ctx Component object pointer
|
||||
* @retval error status
|
||||
*/
|
||||
int32_t S70KL1281_EnterPowerDown(OSPI_HandleTypeDef *Ctx, uint32_t LatencyMode, uint32_t InitialLatency)
|
||||
{
|
||||
uint16_t reg;
|
||||
|
||||
/* Read the value of the CR0 register */
|
||||
if (S70KL1281_ReadCfgReg0(Ctx, ®) != S70KL1281_OK)
|
||||
{
|
||||
return S70KL1281_ERROR;
|
||||
}
|
||||
|
||||
/* Update the deep power down value of the CR0 register */
|
||||
SET_BIT(reg, S70KL1281_CR0_DPDE);
|
||||
|
||||
if (S70KL1281_WriteCfgReg0(Ctx, reg, LatencyMode, InitialLatency) != S70KL1281_OK)
|
||||
{
|
||||
return S70KL1281_ERROR;
|
||||
}
|
||||
|
||||
/* --- Memory takes 10us min to enter deep power down --- */
|
||||
/* --- At least 30us should be respected before leaving deep power down --- */
|
||||
|
||||
return S70KL1281_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Flash leave deep power-down command
|
||||
* @param Ctx Component object pointer
|
||||
* @retval error status
|
||||
*/
|
||||
int32_t S70KL1281_LeavePowerDown(OSPI_HandleTypeDef *Ctx)
|
||||
{
|
||||
/* --- A dummy command is sent to the memory, as the nCS should be low for at least 200 ns --- */
|
||||
/* --- Memory takes 150us max to leave deep power down --- */
|
||||
|
||||
OSPI_HyperbusCmdTypeDef sCommand;
|
||||
uint32_t data;
|
||||
|
||||
/* Initialize the read command */
|
||||
sCommand.AddressSpace = HAL_OSPI_MEMORY_ADDRESS_SPACE;
|
||||
sCommand.AddressSize = HAL_OSPI_ADDRESS_32_BITS;
|
||||
sCommand.Address = 0;
|
||||
sCommand.DQSMode = HAL_OSPI_DQS_ENABLE;
|
||||
sCommand.NbData = 4;
|
||||
|
||||
/* Configure the command */
|
||||
if (HAL_OSPI_HyperbusCmd(Ctx, &sCommand, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
|
||||
{
|
||||
return S70KL1281_ERROR;
|
||||
}
|
||||
|
||||
/* Reception of the data */
|
||||
if (HAL_OSPI_Receive(Ctx, (uint8_t*)(&data), HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
|
||||
{
|
||||
return S70KL1281_ERROR;
|
||||
}
|
||||
|
||||
return S70KL1281_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,183 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file s70kl1281.h
|
||||
* @author MCD Application Team
|
||||
* @brief This file contains all the description of the S70KL1281 Octal memory.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2020 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef S70KL1281_H
|
||||
#define S70KL1281_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "s70kl1281_conf.h"
|
||||
|
||||
/** @addtogroup BSP
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup Components
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup S70KL1281
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup S70KL1281_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup S70KL1281_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief S70KL1281 Configuration
|
||||
*/
|
||||
#define S70KL1281_RAM_SIZE 0x1000000 /* 128 MBits => 16 MBytes */
|
||||
|
||||
/**
|
||||
* @brief MX25LM51245G Error codes
|
||||
*/
|
||||
#define S70KL1281_OK (0)
|
||||
#define S70KL1281_ERROR (-1)
|
||||
|
||||
/******************************************************************************
|
||||
* @brief S70KL1281 Registers
|
||||
****************************************************************************/
|
||||
/* Device Identification Register 0 */
|
||||
#define S70KL1281_DIR0_ADDRESS 0x00000000U
|
||||
|
||||
#define S70KL1281_DIR0_MANUFACTURER 0x000FU /*!< Manufacturer */
|
||||
#define S70KL1281_DIR0_CADC 0x00F0U /*!< Column Address Bit Count */
|
||||
#define S70KL1281_DIR0_RABC 0x1F00U /*!< Row Address Bit Count */
|
||||
#define S70KL1281_DIR0_DADDR 0xC000U /*!< Die Address */
|
||||
#define S70KL1281_DIR0_DADDR_DIE_0 0x0000U /*!< Die 0 Address */
|
||||
#define S70KL1281_DIR0_DADDR_DIE_1 0x4000U /*!< Die 1 Address */
|
||||
#define S70KL1281_DIR0_DADDR_DIE_2 0x8000U /*!< Die 2 Address */
|
||||
#define S70KL1281_DIR0_DADDR_DIE_3 0xC000U /*!< Die 3 Address */
|
||||
|
||||
/* Device Identification Register 1 */
|
||||
#define S70KL1281_DIR1_ADDRESS 0x00000002U
|
||||
|
||||
#define S70KL1281_DIR1_DTYPE 0x000FU /*!< Device Type */
|
||||
#define S70KL1281_DIR1_DTYPE_HYPERRAM 0x0000U /*!< HyperRAM Device Type */
|
||||
|
||||
/* Configuration Register 0 */
|
||||
#define S70KL1281_CR0_ADDRESS 0x00001000U
|
||||
|
||||
#define S70KL1281_CR0_BLENGTH 0x0003U /*!< Burst length */
|
||||
#define S70KL1281_CR0_BLENGTH_128 0x0000U /*!< 128 bytes burst length */
|
||||
#define S70KL1281_CR0_BLENGTH_64 0x0001U /*!< 64 bytes burst length */
|
||||
#define S70KL1281_CR0_BLENGTH_16 0x0002U /*!< 16 bytes burst length */
|
||||
#define S70KL1281_CR0_BLENGTH_32 0x0003U /*!< 32 bytes burst length */
|
||||
#define S70KL1281_CR0_HBE 0x0004U /*!< Hybrid burst enable */
|
||||
#define S70KL1281_CR0_FLE 0x0008U /*!< Fixed latency enable */
|
||||
#define S70KL1281_CR0_IL 0x00F0U /*!< Initial latency */
|
||||
#define S70KL1281_CR0_IL_5_CLOCK 0x0000U /*!< 5 clock latency */
|
||||
#define S70KL1281_CR0_IL_6_CLOCK 0x0010U /*!< 6 clock latency */
|
||||
#define S70KL1281_CR0_IL_3_CLOCK 0x00E0U /*!< 3 clock latency */
|
||||
#define S70KL1281_CR0_IL_4_CLOCK 0x00F0U /*!< 4 clock latency */
|
||||
#define S70KL1281_CR0_DS 0x7000U /*!< Drive strength */
|
||||
#define S70KL1281_CR0_DS_34 0x0000U /*!< 34 ohms drive strength */
|
||||
#define S70KL1281_CR0_DS_115 0x1000U /*!< 115 ohms drive strength */
|
||||
#define S70KL1281_CR0_DS_67 0x2000U /*!< 67 ohms drive strength */
|
||||
#define S70KL1281_CR0_DS_46 0x3000U /*!< 46 ohms drive strength */
|
||||
#define S70KL1281_CR0_DS_34_2 0x4000U /*!< 34 ohms drive strength */
|
||||
#define S70KL1281_CR0_DS_27 0x5000U /*!< 27 ohms drive strength */
|
||||
#define S70KL1281_CR0_DS_22 0x6000U /*!< 22 ohms drive strength */
|
||||
#define S70KL1281_CR0_DS_19 0x7000U /*!< 19 ohms drive strength */
|
||||
#define S70KL1281_CR0_DPDE 0x8000U /*!< Deep Power down enable */
|
||||
|
||||
/* Configuration Register 1 */
|
||||
#define S70KL1281_CR1_ADDRESS 0x00001002U
|
||||
|
||||
#define S70KL1281_CR1_DRI 0x0003U /*!< Distributed refresh interval */
|
||||
#define S70KL1281_CR1_DRI_2_TIMES 0x0000U /*!< 2 times default distributed refresh interval */
|
||||
#define S70KL1281_CR1_DRI_4_TIMES 0x0001U /*!< 4 times default distributed refresh interval */
|
||||
#define S70KL1281_CR1_DRI_DEFAULT 0x0002U /*!< Default distributed refresh interval */
|
||||
#define S70KL1281_CR1_DRI_1_5_TIMES 0x0003U /*!< 1.5 times default distributed refresh interval */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/** @defgroup S70KL1281_Exported_Types S70KL1281Exported Types
|
||||
* @{
|
||||
*/
|
||||
typedef enum {
|
||||
S70KL1281_BURST_16_BYTES = S70KL1281_CR0_BLENGTH_16,
|
||||
S70KL1281_BURST_32_BYTES = S70KL1281_CR0_BLENGTH_32,
|
||||
S70KL1281_BURST_64_BYTES = S70KL1281_CR0_BLENGTH_64,
|
||||
S70KL1281_BURST_128_BYTES = S70KL1281_CR0_BLENGTH_128
|
||||
} S70KL1281_BurstLength_t;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup S70KL1281_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
/* Read/Write Array Commands **************************************************/
|
||||
int32_t S70KL1281_Read(OSPI_HandleTypeDef *Ctx, uint8_t *pData, uint32_t ReadAddr, uint32_t Size);
|
||||
int32_t S70KL1281_Read_DMA(OSPI_HandleTypeDef *Ctx, uint8_t *pData, uint32_t ReadAddr, uint32_t Size);
|
||||
int32_t S70KL1281_Write(OSPI_HandleTypeDef *Ctx, uint8_t *pData, uint32_t WriteAddr, uint32_t Size);
|
||||
int32_t S70KL1281_Write_DMA(OSPI_HandleTypeDef *Ctx, uint8_t *pData, uint32_t WriteAddr, uint32_t Size);
|
||||
int32_t S70KL1281_EnableMemoryMappedMode(OSPI_HandleTypeDef *Ctx);
|
||||
|
||||
/* Register/Setting Commands **************************************************/
|
||||
int32_t S70KL1281_ReadCfgReg0(OSPI_HandleTypeDef *Ctx, uint16_t *Value);
|
||||
int32_t S70KL1281_WriteCfgReg0(OSPI_HandleTypeDef *Ctx, uint16_t Value, uint32_t LatencyMode, uint32_t InitialLatency);
|
||||
int32_t S70KL1281_ReadCfgReg1(OSPI_HandleTypeDef *Ctx, uint16_t *Value);
|
||||
int32_t S70KL1281_WriteCfgReg1(OSPI_HandleTypeDef *Ctx, uint16_t Value, uint32_t LatencyMode, uint32_t InitialLatency);
|
||||
|
||||
/* ID Commands ****************************************************************/
|
||||
int32_t S70KL1281_ReadID(OSPI_HandleTypeDef *Ctx, uint16_t *ID);
|
||||
|
||||
/* Power down Commands ********************************************************/
|
||||
int32_t S70KL1281_EnterPowerDown(OSPI_HandleTypeDef *Ctx, uint32_t LatencyMode, uint32_t InitialLatency);
|
||||
int32_t S70KL1281_LeavePowerDown(OSPI_HandleTypeDef *Ctx);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* S70KL1281_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,55 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file s70kl1281_conf.h
|
||||
* @author MCD Application Team
|
||||
* @brief S70KL1281 OctalSPI memory configuration template file.
|
||||
* This file should be copied to the application folder and renamed
|
||||
* to s70kl1281_conf.h
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2020 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef S70KL1281_CONF_H
|
||||
#define S70KL1281_CONF_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32xxxx_hal.h"
|
||||
|
||||
/** @addtogroup BSP
|
||||
* @{
|
||||
*/
|
||||
#define CONF_OSPI_RAM_ODS S70KL1281_CR0_DS_34 /* S70KL1281 Output Driver Strength */
|
||||
|
||||
#define RW_RECOVERY_TIME 3U /* 40ns @ 60MHz */
|
||||
#define DEFAULT_INITIAL_LATENCY 6U
|
||||
#define OPTIMAL_FIXED_INITIAL_LATENCY 3U
|
||||
#define OPTIMAL_FIXED_INITIAL_LATENCY_REG_VAL S70KL1281_CR0_IL_3_CLOCK
|
||||
#define OPTIMAL_VARIABLE_INITIAL_LATENCY 6U
|
||||
#define OPTIMAL_VARIABLE_INITIAL_LATENCY_REG_VAL S70KL1281_CR0_IL_6_CLOCK
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* S70KL1281_CONF_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
Reference in New Issue
Block a user