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+<html xmlns="http://www.w3.org/1999/xhtml" lang="en" xml:lang="en">
+<head>
+  <meta charset="utf-8" />
+  <meta name="generator" content="pandoc" />
+  <meta name="viewport" content="width=device-width, initial-scale=1.0, user-scalable=yes" />
+  <title>Release Notes for IS42S32800G Component Driver</title>
+  <style type="text/css">
+      code{white-space: pre-wrap;}
+      span.smallcaps{font-variant: small-caps;}
+      span.underline{text-decoration: underline;}
+      div.column{display: inline-block; vertical-align: top; width: 50%;}
+  </style>
+  <link rel="stylesheet" href="_htmresc/mini-st.css" />
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+  <![endif]-->
+</head>
+<body>
+<div class="row">
+<div class="col-sm-12 col-lg-4">
+<div class="card fluid">
+<div class="sectione dark">
+<center>
+<h1 id="release-notes-for-is42s32800g-component-driver"><strong>Release Notes for IS42S32800G Component Driver</strong></h1>
+<p>Copyright © 2019 STMicroelectronics<br />
+</p>
+<a href="https://www.st.com" class="logo"><img src="_htmresc/st_logo.png" alt="ST logo" /></a>
+</center>
+</div>
+</div>
+<h1 id="license">License</h1>
+This software component is licensed by ST under BSD 3-Clause license, the “License”; You may not use this component except in compliance with the License. You may obtain a copy of the License at:
+<center>
+<a href="https://opensource.org/licenses/BSD-3-Clause">https://opensource.org/licenses/BSD-3-Clause</a>
+</center>
+<h1 id="purpose">Purpose</h1>
+<p>This driver provides a set of SDRAM functions offered by IS42S32800G component</p>
+</div>
+<div class="col-sm-12 col-lg-8">
+<h1 id="update-history">Update History</h1>
+<div class="collapse">
+<input type="checkbox" id="collapse-section1" checked aria-hidden="true"> <label for="collapse-section1" aria-hidden="true"><strong>V1.0.0 / 23-November-2019</strong></label>
+<div>
+<h2 id="main-changes">Main Changes</h2>
+<ul>
+<li>First official release of <strong>IS42S32800G</strong> SDRAM Component drivers in line with STM32Cube BSP drivers development guidelines (UM2298)</li>
+</ul>
+</div>
+</div>
+</div>
+</div>
+<footer class="sticky">
+For complete documentation on <mark>STM32 Microcontrollers</mark> , visit: <span style="font-color: blue;"><a href="http://www.st.com/STM32">www.st.com</a></span>
+</footer>
+</body>
+</html>
@@ -0,0 +1,55 @@
+---
+pagetitle: Release Notes for IS42S32800G Component Driver
+lang: en
+---
+
+::: {.row}
+::: {.col-sm-12 .col-lg-4}
+
+::: {.card .fluid}
+::: {.sectione .dark}
+<center>
+# **Release Notes for IS42S32800G Component Driver**
+Copyright &copy; 2019 STMicroelectronics\
+    
+[![ST logo](_htmresc/st_logo.png)](https://www.st.com){.logo}
+</center>
+:::
+:::
+
+# License
+
+This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this component except in 
+compliance with the License. You may obtain a copy of the License at:
+<center>
+[https://opensource.org/licenses/BSD-3-Clause](https://opensource.org/licenses/BSD-3-Clause)
+</center>
+
+# Purpose
+
+This driver provides a set of SDRAM functions offered by IS42S32800G component
+
+:::
+
+::: {.col-sm-12 .col-lg-8}
+# Update History
+
+::: {.collapse}
+<input type="checkbox" id="collapse-section1" checked aria-hidden="true">
+<label for="collapse-section1" aria-hidden="true">__V1.0.0 / 23-November-2019__</label>
+<div>			
+
+## Main Changes
+
+-	First official release of **IS42S32800G** SDRAM Component drivers in line with STM32Cube BSP drivers development guidelines (UM2298)
+
+</div>
+:::
+
+:::
+:::
+
+<footer class="sticky">
+For complete documentation on <mark>STM32 Microcontrollers</mark> ,
+visit: [[www.st.com](http://www.st.com/STM32)]{style="font-color: blue;"}
+</footer>
@@ -0,0 +1,346 @@
+                                                 /**
+ ******************************************************************************
+ * @file    is42s32800g.c
+ * @author  MCD Application Team
+ * @brief   IS42S32800G sdram 8MBx32 driver file
+ ******************************************************************************
+ * @attention
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "is42s32800g.h"
+
+/** @addtogroup BSP
+  * @{
+  */
+
+/** @addtogroup Components
+  * @{
+  */
+
+/** @defgroup IS42S32800G IS42S32800G
+  * @brief     This file provides a set of functions needed to drive the
+  *            IS42S32800G SDRAM memory.
+  * @{
+  */
+
+/** @defgroup IS42S32800G_Private_Variables IS42S32800G Private Variables
+  * @{
+  */
+static FMC_SDRAM_CommandTypeDef Command;
+/**
+  * @}
+  */
+
+/** @defgroup IS42S32800G_Function_Prototypes IS42S32800G Function Prototypes
+  * @{
+  */
+static int32_t IS42S32800G_Delay(uint32_t Delay);
+
+/**
+  * @}
+  */
+
+/** @defgroup IS42S32800G_Exported_Functions IS42S32800G Exported Functions
+  * @{
+  */
+/**
+  * @brief  Initializes the IS42S32800G SDRAm memory
+  * @param  Ctx Component object pointer
+  * @param  pRegMode : Pointer to Register Mode structure
+  * @retval error status
+  */
+int32_t IS42S32800G_Init(SDRAM_HandleTypeDef *Ctx, IS42S32800G_Context_t *pRegMode)
+{
+  int32_t ret = IS42S32800G_ERROR;
+
+  /* Step 1: Configure a clock configuration enable command */
+  if(IS42S32800G_ClockEnable(Ctx, pRegMode->TargetBank) == IS42S32800G_OK)
+  {
+    /* Step 2: Insert 100 us minimum delay */
+    /* Inserted delay is equal to 1 ms due to systick time base unit (ms) */
+    (void)IS42S32800G_Delay(1);
+
+    /* Step 3: Configure a PALL (precharge all) command */
+    if(IS42S32800G_Precharge(Ctx, pRegMode->TargetBank) == IS42S32800G_OK)
+    {
+      /* Step 4: Configure a Refresh command */
+      if(IS42S32800G_RefreshMode(Ctx, pRegMode->TargetBank, pRegMode->RefreshMode) == IS42S32800G_OK)
+      {
+        /* Step 5: Program the external memory mode register */
+        if(IS42S32800G_ModeRegConfig(Ctx, pRegMode) == IS42S32800G_OK)
+        {
+          /* Step 6: Set the refresh rate counter */
+          if(IS42S32800G_RefreshRate(Ctx, pRegMode->RefreshRate) == IS42S32800G_OK)
+          {
+            ret = IS42S32800G_OK;
+          }
+        }
+      }
+    }
+  }
+  return ret;
+}
+
+/**
+  * @brief  Enable SDRAM clock
+  * @param  Ctx Component object pointer
+  * @param  Interface Could be FMC_SDRAM_CMD_TARGET_BANK1 or FMC_SDRAM_CMD_TARGET_BANK2
+  * @retval error status
+  */
+int32_t IS42S32800G_ClockEnable(SDRAM_HandleTypeDef *Ctx, uint32_t Interface)
+{
+  Command.CommandMode            = IS42S32800G_CLK_ENABLE_CMD;
+  Command.CommandTarget          = Interface;
+  Command.AutoRefreshNumber      = 1;
+  Command.ModeRegisterDefinition = 0;
+
+  /* Send the command */
+  if(HAL_SDRAM_SendCommand(Ctx, &Command, IS42S32800G_TIMEOUT) != HAL_OK)
+  {
+    return IS42S32800G_ERROR;
+  }
+  else
+  {
+    return IS42S32800G_OK;
+  }
+}
+
+/**
+  * @brief  Precharge all sdram banks
+  * @param  Ctx Component object pointer
+  * @param  Interface Could be FMC_SDRAM_CMD_TARGET_BANK1 or FMC_SDRAM_CMD_TARGET_BANK2
+  * @retval error status
+  */
+int32_t IS42S32800G_Precharge(SDRAM_HandleTypeDef *Ctx, uint32_t Interface)
+{
+  Command.CommandMode            = IS42S32800G_PALL_CMD   ;
+  Command.CommandTarget          = Interface;
+  Command.AutoRefreshNumber      = 1;
+  Command.ModeRegisterDefinition = 0;
+
+  /* Send the command */
+  if(HAL_SDRAM_SendCommand(Ctx, &Command, IS42S32800G_TIMEOUT) != HAL_OK)
+  {
+    return IS42S32800G_ERROR;
+  }
+  else
+  {
+    return IS42S32800G_OK;
+  }
+}
+
+/**
+  * @brief  Program the external memory mode register
+  * @param  Ctx Component object pointer
+  * @param  pRegMode : Pointer to Register Mode structure
+  * @retval error status
+  */
+int32_t IS42S32800G_ModeRegConfig(SDRAM_HandleTypeDef *Ctx, IS42S32800G_Context_t *pRegMode)
+{
+  uint32_t tmpmrd;
+
+  /* Program the external memory mode register */
+  tmpmrd = (uint32_t)pRegMode->BurstLength   |\
+                     pRegMode->BurstType     |\
+                     pRegMode->CASLatency    |\
+                     pRegMode->OperationMode |\
+                     pRegMode->WriteBurstMode;
+
+  Command.CommandMode            = IS42S32800G_LOAD_MODE_CMD;
+  Command.CommandTarget          = pRegMode->TargetBank;
+  Command.AutoRefreshNumber      = 1;
+  Command.ModeRegisterDefinition = tmpmrd;
+
+  /* Send the command */
+  if(HAL_SDRAM_SendCommand(Ctx, &Command, IS42S32800G_TIMEOUT) != HAL_OK)
+  {
+    return IS42S32800G_ERROR;
+  }
+  else
+  {
+    return IS42S32800G_OK;
+  }
+}
+
+/**
+  * @brief  Program the SDRAM timing
+  * @param  Ctx Component object pointer
+  * @param  pTiming Pointer to SDRAM timing configuration structure
+  * @retval error status
+  */
+int32_t IS42S32800G_TimingConfig(SDRAM_HandleTypeDef *Ctx, FMC_SDRAM_TimingTypeDef *pTiming)
+{
+  /* Program the SDRAM timing */
+  if(HAL_SDRAM_Init(Ctx, pTiming) != HAL_OK)
+  {
+    return IS42S32800G_ERROR;
+  }
+  else
+  {
+    return IS42S32800G_OK;
+  }
+}
+
+/**
+  * @brief  Configure Refresh mode
+  * @param  Ctx Component object pointer
+  * @param  Interface Could be FMC_SDRAM_CMD_TARGET_BANK1 or FMC_SDRAM_CMD_TARGET_BANK2
+  * @param  RefreshMode Could be IS42S32800G_CMD_AUTOREFRESH_MODE or
+  *                      IS42S32800G_CMD_SELFREFRESH_MODE
+  * @retval error status
+  */
+int32_t IS42S32800G_RefreshMode(SDRAM_HandleTypeDef *Ctx, uint32_t Interface, uint32_t RefreshMode)
+{
+  Command.CommandMode            = RefreshMode;
+  Command.CommandTarget          = Interface;
+  Command.AutoRefreshNumber      = 8;
+  Command.ModeRegisterDefinition = 0;
+
+  /* Send the command */
+  if(HAL_SDRAM_SendCommand(Ctx, &Command, IS42S32800G_TIMEOUT) != HAL_OK)
+  {
+    return IS42S32800G_ERROR;
+  }
+  else
+  {
+    return IS42S32800G_OK;
+  }
+}
+
+/**
+  * @brief  Set the device refresh rate
+  * @param  Ctx Component object pointer
+  * @param  RefreshCount The refresh rate to be programmed
+  * @retval error status
+  */
+int32_t IS42S32800G_RefreshRate(SDRAM_HandleTypeDef *Ctx, uint32_t RefreshCount)
+{
+  /* Set the device refresh rate */
+  if(HAL_SDRAM_ProgramRefreshRate(Ctx, RefreshCount) != HAL_OK)
+  {
+    return IS42S32800G_ERROR;
+  }
+  else
+  {
+    return IS42S32800G_OK;
+  }
+}
+
+/**
+  * @brief  Enter Power mode
+  * @param  Ctx Component object pointer
+  * @param  Interface Could be FMC_SDRAM_CMD_TARGET_BANK1 or FMC_SDRAM_CMD_TARGET_BANK2
+  * @retval error status
+  */
+int32_t IS42S32800G_EnterPowerMode(SDRAM_HandleTypeDef *Ctx, uint32_t Interface)
+{
+  Command.CommandMode            = IS42S32800G_POWERDOWN_MODE_CMD;
+  Command.CommandTarget          = Interface;
+  Command.AutoRefreshNumber      = 1;
+  Command.ModeRegisterDefinition = 0;
+
+  /* Send the command */
+  if(HAL_SDRAM_SendCommand(Ctx, &Command, IS42S32800G_TIMEOUT) != HAL_OK)
+  {
+    return IS42S32800G_ERROR;
+  }
+  else
+  {
+    return IS42S32800G_OK;
+  }
+}
+
+/**
+  * @brief  Exit Power mode
+  * @param  Ctx Component object pointer
+  * @param  Interface Could be FMC_SDRAM_CMD_TARGET_BANK1 or FMC_SDRAM_CMD_TARGET_BANK2
+  * @retval error status
+  */
+int32_t IS42S32800G_ExitPowerMode(SDRAM_HandleTypeDef *Ctx, uint32_t Interface)
+{
+  Command.CommandMode            = IS42S32800G_NORMAL_MODE_CMD;
+  Command.CommandTarget          = Interface;
+  Command.AutoRefreshNumber      = 1;
+  Command.ModeRegisterDefinition = 0;
+
+  /* Send the command */
+  if(HAL_SDRAM_SendCommand(Ctx, &Command, IS42S32800G_TIMEOUT) != HAL_OK)
+  {
+    return IS42S32800G_ERROR;
+  }
+  else
+  {
+    return IS42S32800G_OK;
+  }
+}
+
+/**
+  * @brief  Sends command to the SDRAM bank.
+  * @param  Ctx Component object pointer
+  * @param  SdramCmd : Pointer to SDRAM command structure
+  * @retval SDRAM status
+  */
+int32_t IS42S32800G_Sendcmd(SDRAM_HandleTypeDef *Ctx, FMC_SDRAM_CommandTypeDef *SdramCmd)
+{
+  if(HAL_SDRAM_SendCommand(Ctx, SdramCmd, IS42S32800G_TIMEOUT) != HAL_OK)
+  {
+    return IS42S32800G_ERROR;
+  }
+  else
+  {
+    return IS42S32800G_OK;
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup IS42S32800G_Private_Functions IS42S32800G Private Functions
+  * @{
+  */
+
+/**
+  * @brief This function provides accurate delay (in milliseconds)
+  * @param Delay : specifies the delay time length, in milliseconds
+  * @retval IS42S32800G_OK
+  */
+static int32_t IS42S32800G_Delay(uint32_t Delay)
+{
+  uint32_t tickstart;
+  tickstart = HAL_GetTick();
+  while((HAL_GetTick() - tickstart) < Delay)
+  {
+  }
+  return IS42S32800G_OK;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
@@ -0,0 +1,131 @@
+/**
+  ******************************************************************************
+  * @file    is42s32800g.h
+  * @author  MCD Application Team
+  * @brief   This file contains all the description of the IS42S32800G SDRAM
+  *          memory.
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef IS42S32800G_H
+#define IS42S32800G_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "is42s32800g_conf.h"
+/** @addtogroup BSP
+  * @{
+  */
+
+/** @addtogroup Components
+  * @{
+  */
+
+/** @addtogroup IS42S32800G
+  * @{
+  */
+
+/** @defgroup IS42S32800G_Exported_Types Exported Types
+  * @{
+  */
+typedef struct
+{
+  uint32_t TargetBank;           /*!< Target Bank                             */
+  uint32_t RefreshMode;          /*!< Refresh Mode                            */
+  uint32_t RefreshRate;          /*!< Refresh Rate                            */
+  uint32_t BurstLength;          /*!< Burst Length                            */
+  uint32_t BurstType;            /*!< Burst Type                              */
+  uint32_t CASLatency;           /*!< CAS Latency                             */
+  uint32_t OperationMode;        /*!< Operation Mode                          */
+  uint32_t WriteBurstMode;       /*!< Write Burst Mode                        */
+} IS42S32800G_Context_t;
+
+/**
+  * @}
+  */
+
+/** @defgroup IS42S32800G_Exported_Constants
+  * @{
+  */
+#define IS42S32800G_OK                         (0)
+#define IS42S32800G_ERROR                      (-1)
+
+/* Register Mode */
+#define IS42S32800G_BURST_LENGTH_1              0x00000000U
+#define IS42S32800G_BURST_LENGTH_2              0x00000001U
+#define IS42S32800G_BURST_LENGTH_4              0x00000002U
+#define IS42S32800G_BURST_LENGTH_8              0x00000004U
+#define IS42S32800G_BURST_TYPE_SEQUENTIAL       0x00000000U
+#define IS42S32800G_BURST_TYPE_INTERLEAVED      0x00000008U
+#define IS42S32800G_CAS_LATENCY_2               0x00000020U
+#define IS42S32800G_CAS_LATENCY_3               0x00000030U
+#define IS42S32800G_OPERATING_MODE_STANDARD     0x00000000U
+#define IS42S32800G_WRITEBURST_MODE_PROGRAMMED  0x00000000U
+#define IS42S32800G_WRITEBURST_MODE_SINGLE      0x00000200U
+
+/* Command Mode */
+#define IS42S32800G_NORMAL_MODE_CMD             0x00000000U
+#define IS42S32800G_CLK_ENABLE_CMD              0x00000001U
+#define IS42S32800G_PALL_CMD                    0x00000002U
+#define IS42S32800G_AUTOREFRESH_MODE_CMD        0x00000003U
+#define IS42S32800G_LOAD_MODE_CMD               0x00000004U
+#define IS42S32800G_SELFREFRESH_MODE_CMD        0x00000005U
+#define IS42S32800G_POWERDOWN_MODE_CMD          0x00000006U
+
+/**
+  * @}
+  */
+
+/** @addtogroup IS42S32800G_Private_Functions
+  * @{
+  */
+int32_t IS42S32800G_Init(SDRAM_HandleTypeDef *Ctx, IS42S32800G_Context_t *pRegMode);
+int32_t IS42S32800G_ClockEnable(SDRAM_HandleTypeDef *Ctx, uint32_t Interface);
+int32_t IS42S32800G_Precharge(SDRAM_HandleTypeDef *Ctx, uint32_t Interface);
+int32_t IS42S32800G_ModeRegConfig(SDRAM_HandleTypeDef *Ctx, IS42S32800G_Context_t *pRegMode);
+int32_t IS42S32800G_TimingConfig(SDRAM_HandleTypeDef *Ctx, FMC_SDRAM_TimingTypeDef *pTiming);
+int32_t IS42S32800G_RefreshMode(SDRAM_HandleTypeDef *Ctx, uint32_t Interface, uint32_t RefreshMode);
+int32_t IS42S32800G_RefreshRate(SDRAM_HandleTypeDef *Ctx, uint32_t RefreshCount);
+int32_t IS42S32800G_EnterPowerMode(SDRAM_HandleTypeDef *Ctx, uint32_t Interface);
+int32_t IS42S32800G_ExitPowerMode(SDRAM_HandleTypeDef *Ctx, uint32_t Interface);
+int32_t IS42S32800G_Sendcmd(SDRAM_HandleTypeDef *Ctx, FMC_SDRAM_CommandTypeDef *SdramCmd);
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* IS42S32800G_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
@@ -0,0 +1,72 @@
+/**
+  ******************************************************************************
+  * @file    is42s32800g_conf.h
+  * @author  MCD Application Team
+  * @brief   This file contains some configurations required for the
+  *          IS42S32800G SDRAM memory.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef IS42S32800G_CONF_H
+#define IS42S32800G_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32xxxx_hal.h"
+   
+/** @addtogroup BSP
+  * @{
+  */
+  
+/** @addtogroup Components
+  * @{
+  */
+
+/** @addtogroup IS42S32800G
+  * @{
+  */
+
+/** @addtogroup IS42S32800G_Exported_Constants
+  * @{
+  */  
+#define REFRESH_COUNT                    ((uint32_t)0x0603)   /* SDRAM refresh counter (100Mhz SD clock) */
+   
+#define IS42S32800G_TIMEOUT             ((uint32_t)0xFFFF)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* IS42S32800G_CONF_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/