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This commit is contained in:
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,75 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32_assert.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.2
|
||||
* @date 14-April-2017
|
||||
* @brief STM32 assert template file.
|
||||
* This file should be copied to the application folder and renamed
|
||||
* to stm32_assert.h.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32_ASSERT_H
|
||||
#define __STM32_ASSERT_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
#ifdef USE_FULL_ASSERT
|
||||
/**
|
||||
* @brief The assert_param macro is used for function's parameters check.
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||||
* @param expr: If expr is false, it calls assert_failed function
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||||
* which reports the name of the source file and the source
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||||
* line number of the call that failed.
|
||||
* If expr is true, it returns no value.
|
||||
* @retval None
|
||||
*/
|
||||
#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
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||||
/* Exported functions ------------------------------------------------------- */
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||||
void assert_failed(uint8_t* file, uint32_t line);
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||||
#else
|
||||
#define assert_param(expr) ((void)0U)
|
||||
#endif /* USE_FULL_ASSERT */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32_ASSERT_H */
|
||||
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,253 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_hal.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.2
|
||||
* @date 14-April-2017
|
||||
* @brief This file contains all the functions prototypes for the HAL
|
||||
* module driver.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F7xx_HAL_H
|
||||
#define __STM32F7xx_HAL_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx_hal_conf.h"
|
||||
|
||||
/** @addtogroup STM32F7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup HAL
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup HAL_Exported_Constants HAL Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup SYSCFG_BootMode Boot Mode
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||||
* @{
|
||||
*/
|
||||
#define SYSCFG_MEM_BOOT_ADD0 ((uint32_t)0x00000000U)
|
||||
#define SYSCFG_MEM_BOOT_ADD1 SYSCFG_MEMRMP_MEM_BOOT
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup HAL_Exported_Macros HAL Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Freeze/Unfreeze Peripherals in Debug mode
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||||
*/
|
||||
#define __HAL_DBGMCU_FREEZE_TIM2() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM2_STOP))
|
||||
#define __HAL_DBGMCU_FREEZE_TIM3() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM3_STOP))
|
||||
#define __HAL_DBGMCU_FREEZE_TIM4() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM4_STOP))
|
||||
#define __HAL_DBGMCU_FREEZE_TIM5() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM5_STOP))
|
||||
#define __HAL_DBGMCU_FREEZE_TIM6() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM6_STOP))
|
||||
#define __HAL_DBGMCU_FREEZE_TIM7() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM7_STOP))
|
||||
#define __HAL_DBGMCU_FREEZE_TIM12() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM12_STOP))
|
||||
#define __HAL_DBGMCU_FREEZE_TIM13() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM13_STOP))
|
||||
#define __HAL_DBGMCU_FREEZE_TIM14() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM14_STOP))
|
||||
#define __HAL_DBGMCU_FREEZE_LPTIM1() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_LPTIM1_STOP))
|
||||
#define __HAL_DBGMCU_FREEZE_RTC() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_RTC_STOP))
|
||||
#define __HAL_DBGMCU_FREEZE_WWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_WWDG_STOP))
|
||||
#define __HAL_DBGMCU_FREEZE_IWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_IWDG_STOP))
|
||||
#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
|
||||
#define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))
|
||||
#define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT))
|
||||
#define __HAL_DBGMCU_FREEZE_I2C4_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT))
|
||||
#define __HAL_DBGMCU_FREEZE_CAN1() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN1_STOP))
|
||||
#define __HAL_DBGMCU_FREEZE_CAN2() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN2_STOP))
|
||||
#define __HAL_DBGMCU_FREEZE_TIM1() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM1_STOP))
|
||||
#define __HAL_DBGMCU_FREEZE_TIM8() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM8_STOP))
|
||||
#define __HAL_DBGMCU_FREEZE_TIM9() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM9_STOP))
|
||||
#define __HAL_DBGMCU_FREEZE_TIM10() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM10_STOP))
|
||||
#define __HAL_DBGMCU_FREEZE_TIM11() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM11_STOP))
|
||||
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM2() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM2_STOP))
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM3() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM3_STOP))
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM4() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM4_STOP))
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM5() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM5_STOP))
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM6() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM6_STOP))
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM7() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM7_STOP))
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM12() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM12_STOP))
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM13() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM13_STOP))
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM14() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM14_STOP))
|
||||
#define __HAL_DBGMCU_UNFREEZE_LPTIM1() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_LPTIM1_STOP))
|
||||
#define __HAL_DBGMCU_UNFREEZE_RTC() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_RTC_STOP))
|
||||
#define __HAL_DBGMCU_UNFREEZE_WWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_WWDG_STOP))
|
||||
#define __HAL_DBGMCU_UNFREEZE_IWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_IWDG_STOP))
|
||||
#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
|
||||
#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))
|
||||
#define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT))
|
||||
#define __HAL_DBGMCU_UNFREEZE_I2C4_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT))
|
||||
#define __HAL_DBGMCU_UNFREEZE_CAN1() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN1_STOP))
|
||||
#define __HAL_DBGMCU_UNFREEZE_CAN2() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN2_STOP))
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM1() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM1_STOP))
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM8() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM8_STOP))
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM9() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM9_STOP))
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM10() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM10_STOP))
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM11() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM11_STOP))
|
||||
|
||||
|
||||
/** @brief FMC (NOR/RAM) mapped at 0x60000000 and SDRAM mapped at 0xC0000000
|
||||
*/
|
||||
#define __HAL_SYSCFG_REMAPMEMORY_FMC() (SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_SWP_FMC))
|
||||
|
||||
|
||||
/** @brief FMC/SDRAM mapped at 0x60000000 (NOR/RAM) mapped at 0xC0000000
|
||||
*/
|
||||
#define __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_SWP_FMC);\
|
||||
SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_SWP_FMC_0);\
|
||||
}while(0);
|
||||
/**
|
||||
* @brief Return the memory boot mapping as configured by user.
|
||||
* @retval The boot mode as configured by user. The returned value can be one
|
||||
* of the following values:
|
||||
* @arg @ref SYSCFG_MEM_BOOT_ADD0
|
||||
* @arg @ref SYSCFG_MEM_BOOT_ADD1
|
||||
*/
|
||||
#define __HAL_SYSCFG_GET_BOOT_MODE() READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_BOOT)
|
||||
|
||||
#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
|
||||
/** @brief SYSCFG Break Cortex-M7 Lockup lock.
|
||||
* Enable and lock the connection of Cortex-M7 LOCKUP (Hardfault) output to TIM1/8 Break input.
|
||||
* @note The selected configuration is locked and can be unlocked only by system reset.
|
||||
*/
|
||||
#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() SET_BIT(SYSCFG->CBR, SYSCFG_CBR_CLL)
|
||||
|
||||
/** @brief SYSCFG Break PVD lock.
|
||||
* Enable and lock the PVD connection to Timer1/8 Break input, as well as the PVDE and PLS[2:0] in the PWR_CR1 register.
|
||||
* @note The selected configuration is locked and can be unlocked only by system reset.
|
||||
*/
|
||||
#define __HAL_SYSCFG_BREAK_PVD_LOCK() SET_BIT(SYSCFG->CBR, SYSCFG_CBR_PVDL)
|
||||
#endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup HAL_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
/** @addtogroup HAL_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Initialization and de-initialization functions ******************************/
|
||||
HAL_StatusTypeDef HAL_Init(void);
|
||||
HAL_StatusTypeDef HAL_DeInit(void);
|
||||
void HAL_MspInit(void);
|
||||
void HAL_MspDeInit(void);
|
||||
HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup HAL_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral Control functions ************************************************/
|
||||
void HAL_IncTick(void);
|
||||
void HAL_Delay(__IO uint32_t Delay);
|
||||
uint32_t HAL_GetTick(void);
|
||||
void HAL_SuspendTick(void);
|
||||
void HAL_ResumeTick(void);
|
||||
uint32_t HAL_GetHalVersion(void);
|
||||
uint32_t HAL_GetREVID(void);
|
||||
uint32_t HAL_GetDEVID(void);
|
||||
void HAL_DBGMCU_EnableDBGSleepMode(void);
|
||||
void HAL_DBGMCU_DisableDBGSleepMode(void);
|
||||
void HAL_DBGMCU_EnableDBGStopMode(void);
|
||||
void HAL_DBGMCU_DisableDBGStopMode(void);
|
||||
void HAL_DBGMCU_EnableDBGStandbyMode(void);
|
||||
void HAL_DBGMCU_DisableDBGStandbyMode(void);
|
||||
void HAL_EnableCompensationCell(void);
|
||||
void HAL_DisableCompensationCell(void);
|
||||
void HAL_EnableFMCMemorySwapping(void);
|
||||
void HAL_DisableFMCMemorySwapping(void);
|
||||
#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
|
||||
void HAL_EnableMemorySwappingBank(void);
|
||||
void HAL_DisableMemorySwappingBank(void);
|
||||
#endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/** @defgroup HAL_Private_Variables HAL Private Variables
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup HAL_Private_Constants HAL Private Constants
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F7xx_HAL_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,915 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_hal_adc.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.2
|
||||
* @date 14-April-2017
|
||||
* @brief Header file of ADC HAL extension module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F7xx_ADC_H
|
||||
#define __STM32F7xx_ADC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup ADC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup ADC_Exported_Types ADC Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Structure definition of ADC and regular group initialization
|
||||
* @note Parameters of this structure are shared within 2 scopes:
|
||||
* - Scope entire ADC (affects regular and injected groups): ClockPrescaler, Resolution, ScanConvMode, DataAlign, ScanConvMode, EOCSelection, LowPowerAutoWait, LowPowerAutoPowerOff, ChannelsBank.
|
||||
* - Scope regular group: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConvEdge, ExternalTrigConv.
|
||||
* @note The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state.
|
||||
* ADC state can be either:
|
||||
* - For all parameters: ADC disabled
|
||||
* - For all parameters except 'Resolution', 'ScanConvMode', 'DiscontinuousConvMode', 'NbrOfDiscConversion' : ADC enabled without conversion on going on regular group.
|
||||
* - For parameters 'ExternalTrigConv' and 'ExternalTrigConvEdge': ADC enabled, even with conversion on going.
|
||||
* If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
|
||||
* without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fullfills the ADC state condition) on the fly).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t ClockPrescaler; /*!< Select ADC clock prescaler. The clock is common for
|
||||
all the ADCs.
|
||||
This parameter can be a value of @ref ADC_ClockPrescaler */
|
||||
uint32_t Resolution; /*!< Configures the ADC resolution.
|
||||
This parameter can be a value of @ref ADC_Resolution */
|
||||
uint32_t DataAlign; /*!< Specifies ADC data alignment to right (MSB on register bit 11 and LSB on register bit 0) (default setting)
|
||||
or to left (if regular group: MSB on register bit 15 and LSB on register bit 4, if injected group (MSB kept as signed value due to potential negative value after offset application): MSB on register bit 14 and LSB on register bit 3).
|
||||
This parameter can be a value of @ref ADC_Data_Align */
|
||||
uint32_t ScanConvMode; /*!< Configures the sequencer of regular and injected groups.
|
||||
This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.
|
||||
If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1).
|
||||
Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1).
|
||||
If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank).
|
||||
Scan direction is upward: from rank1 to rank 'n'.
|
||||
This parameter can be a value of @ref ADC_Scan_mode.
|
||||
This parameter can be set to ENABLE or DISABLE */
|
||||
uint32_t EOCSelection; /*!< Specifies what EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of conversion of each rank or complete sequence.
|
||||
This parameter can be a value of @ref ADC_EOCSelection.
|
||||
Note: For injected group, end of conversion (flag&IT) is raised only at the end of the sequence.
|
||||
Therefore, if end of conversion is set to end of each conversion, injected group should not be used with interruption (HAL_ADCEx_InjectedStart_IT)
|
||||
or polling (HAL_ADCEx_InjectedStart and HAL_ADCEx_InjectedPollForConversion). By the way, polling is still possible since driver will use an estimated timing for end of injected conversion.
|
||||
Note: If overrun feature is intended to be used, use ADC in mode 'interruption' (function HAL_ADC_Start_IT() ) with parameter EOCSelection set to end of each conversion or in mode 'transfer by DMA' (function HAL_ADC_Start_DMA()).
|
||||
If overrun feature is intended to be bypassed, use ADC in mode 'polling' or 'interruption' with parameter EOCSelection must be set to end of sequence */
|
||||
uint32_t ContinuousConvMode; /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group,
|
||||
after the selected trigger occurred (software start or external trigger).
|
||||
This parameter can be set to ENABLE or DISABLE. */
|
||||
uint32_t NbrOfConversion; /*!< Specifies the number of ranks that will be converted within the regular group sequencer.
|
||||
To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
|
||||
This parameter must be a number between Min_Data = 1 and Max_Data = 16. */
|
||||
uint32_t DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
|
||||
Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
|
||||
Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
|
||||
This parameter can be set to ENABLE or DISABLE. */
|
||||
uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of regular group (parameter NbrOfConversion) will be subdivided.
|
||||
If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded.
|
||||
This parameter must be a number between Min_Data = 1 and Max_Data = 8. */
|
||||
uint32_t ExternalTrigConv; /*!< Selects the external event used to trigger the conversion start of regular group.
|
||||
If set to ADC_SOFTWARE_START, external triggers are disabled.
|
||||
If set to external trigger source, triggering is on event rising edge by default.
|
||||
This parameter can be a value of @ref ADC_External_trigger_Source_Regular */
|
||||
uint32_t ExternalTrigConvEdge; /*!< Selects the external trigger edge of regular group.
|
||||
If trigger is set to ADC_SOFTWARE_START, this parameter is discarded.
|
||||
This parameter can be a value of @ref ADC_External_trigger_edge_Regular */
|
||||
uint32_t DMAContinuousRequests; /*!< Specifies whether the DMA requests are performed in one shot mode (DMA transfer stop when number of conversions is reached)
|
||||
or in Continuous mode (DMA transfer unlimited, whatever number of conversions).
|
||||
Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached.
|
||||
Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion).
|
||||
This parameter can be set to ENABLE or DISABLE. */
|
||||
}ADC_InitTypeDef;
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Structure definition of ADC channel for regular group
|
||||
* @note The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state.
|
||||
* ADC can be either disabled or enabled without conversion on going on regular group.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Channel; /*!< Specifies the channel to configure into ADC regular group.
|
||||
This parameter can be a value of @ref ADC_channels */
|
||||
uint32_t Rank; /*!< Specifies the rank in the regular group sequencer.
|
||||
This parameter must be a number between Min_Data = 1 and Max_Data = 16
|
||||
This parameter can be a value of @ref ADC_regular_rank */
|
||||
uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel.
|
||||
Unit: ADC clock cycles
|
||||
Conversion time is the addition of sampling time and processing time (12 ADC clock cycles at ADC resolution 12 bits, 11 cycles at 10 bits, 9 cycles at 8 bits, 7 cycles at 6 bits).
|
||||
This parameter can be a value of @ref ADC_sampling_times
|
||||
Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
|
||||
If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
|
||||
Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
|
||||
sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
|
||||
Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 4us min). */
|
||||
uint32_t Offset; /*!< Reserved for future use, can be set to 0 */
|
||||
}ADC_ChannelConfTypeDef;
|
||||
|
||||
/**
|
||||
* @brief ADC Configuration multi-mode structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t WatchdogMode; /*!< Configures the ADC analog watchdog mode.
|
||||
This parameter can be a value of @ref ADC_analog_watchdog_selection */
|
||||
uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value.
|
||||
This parameter must be a 12-bit value. */
|
||||
uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value.
|
||||
This parameter must be a 12-bit value. */
|
||||
uint32_t Channel; /*!< Configures ADC channel for the analog watchdog.
|
||||
This parameter has an effect only if watchdog mode is configured on single channel
|
||||
This parameter can be a value of @ref ADC_channels */
|
||||
uint32_t ITMode; /*!< Specifies whether the analog watchdog is configured
|
||||
is interrupt mode or in polling mode.
|
||||
This parameter can be set to ENABLE or DISABLE */
|
||||
uint32_t WatchdogNumber; /*!< Reserved for future use, can be set to 0 */
|
||||
}ADC_AnalogWDGConfTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL ADC state machine: ADC states definition (bitfields)
|
||||
*/
|
||||
/* States of ADC global scope */
|
||||
#define HAL_ADC_STATE_RESET ((uint32_t)0x00000000U) /*!< ADC not yet initialized or disabled */
|
||||
#define HAL_ADC_STATE_READY ((uint32_t)0x00000001U) /*!< ADC peripheral ready for use */
|
||||
#define HAL_ADC_STATE_BUSY_INTERNAL ((uint32_t)0x00000002U) /*!< ADC is busy to internal process (initialization, calibration) */
|
||||
#define HAL_ADC_STATE_TIMEOUT ((uint32_t)0x00000004U) /*!< TimeOut occurrence */
|
||||
|
||||
/* States of ADC errors */
|
||||
#define HAL_ADC_STATE_ERROR_INTERNAL ((uint32_t)0x00000010U) /*!< Internal error occurrence */
|
||||
#define HAL_ADC_STATE_ERROR_CONFIG ((uint32_t)0x00000020U) /*!< Configuration error occurrence */
|
||||
#define HAL_ADC_STATE_ERROR_DMA ((uint32_t)0x00000040U) /*!< DMA error occurrence */
|
||||
|
||||
/* States of ADC group regular */
|
||||
#define HAL_ADC_STATE_REG_BUSY ((uint32_t)0x00000100U) /*!< A conversion on group regular is ongoing or can occur (either by continuous mode,
|
||||
external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
|
||||
#define HAL_ADC_STATE_REG_EOC ((uint32_t)0x00000200U) /*!< Conversion data available on group regular */
|
||||
#define HAL_ADC_STATE_REG_OVR ((uint32_t)0x00000400U) /*!< Overrun occurrence */
|
||||
|
||||
/* States of ADC group injected */
|
||||
#define HAL_ADC_STATE_INJ_BUSY ((uint32_t)0x00001000U) /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode,
|
||||
external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
|
||||
#define HAL_ADC_STATE_INJ_EOC ((uint32_t)0x00002000U) /*!< Conversion data available on group injected */
|
||||
|
||||
/* States of ADC analog watchdogs */
|
||||
#define HAL_ADC_STATE_AWD1 ((uint32_t)0x00010000U) /*!< Out-of-window occurrence of analog watchdog 1 */
|
||||
#define HAL_ADC_STATE_AWD2 ((uint32_t)0x00020000U) /*!< Not available on STM32F7 device: Out-of-window occurrence of analog watchdog 2 */
|
||||
#define HAL_ADC_STATE_AWD3 ((uint32_t)0x00040000U) /*!< Not available on STM32F7 device: Out-of-window occurrence of analog watchdog 3 */
|
||||
|
||||
/* States of ADC multi-mode */
|
||||
#define HAL_ADC_STATE_MULTIMODE_SLAVE ((uint32_t)0x00100000U) /*!< Not available on STM32F7 device: ADC in multimode slave state, controlled by another ADC master ( */
|
||||
|
||||
|
||||
/**
|
||||
* @brief ADC handle Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
ADC_TypeDef *Instance; /*!< Register base address */
|
||||
|
||||
ADC_InitTypeDef Init; /*!< ADC required parameters */
|
||||
|
||||
__IO uint32_t NbrOfCurrentConversionRank; /*!< ADC number of current conversion rank */
|
||||
|
||||
DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< ADC locking object */
|
||||
|
||||
__IO uint32_t State; /*!< ADC communication state */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< ADC Error code */
|
||||
}ADC_HandleTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup ADC_Exported_Constants ADC Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_Error_Code ADC Error Code
|
||||
* @{
|
||||
*/
|
||||
#define HAL_ADC_ERROR_NONE ((uint32_t)0x00U) /*!< No error */
|
||||
#define HAL_ADC_ERROR_INTERNAL ((uint32_t)0x01U) /*!< ADC IP internal error: if problem of clocking,
|
||||
enable/disable, erroneous state */
|
||||
#define HAL_ADC_ERROR_OVR ((uint32_t)0x02U) /*!< Overrun error */
|
||||
#define HAL_ADC_ERROR_DMA ((uint32_t)0x04U) /*!< DMA transfer error */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup ADC_ClockPrescaler ADC Clock Prescaler
|
||||
* @{
|
||||
*/
|
||||
#define ADC_CLOCK_SYNC_PCLK_DIV2 ((uint32_t)0x00000000U)
|
||||
#define ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC_CCR_ADCPRE_0)
|
||||
#define ADC_CLOCK_SYNC_PCLK_DIV6 ((uint32_t)ADC_CCR_ADCPRE_1)
|
||||
#define ADC_CLOCK_SYNC_PCLK_DIV8 ((uint32_t)ADC_CCR_ADCPRE)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_delay_between_2_sampling_phases ADC Delay Between 2 Sampling Phases
|
||||
* @{
|
||||
*/
|
||||
#define ADC_TWOSAMPLINGDELAY_5CYCLES ((uint32_t)0x00000000U)
|
||||
#define ADC_TWOSAMPLINGDELAY_6CYCLES ((uint32_t)ADC_CCR_DELAY_0)
|
||||
#define ADC_TWOSAMPLINGDELAY_7CYCLES ((uint32_t)ADC_CCR_DELAY_1)
|
||||
#define ADC_TWOSAMPLINGDELAY_8CYCLES ((uint32_t)(ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
|
||||
#define ADC_TWOSAMPLINGDELAY_9CYCLES ((uint32_t)ADC_CCR_DELAY_2)
|
||||
#define ADC_TWOSAMPLINGDELAY_10CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0))
|
||||
#define ADC_TWOSAMPLINGDELAY_11CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1))
|
||||
#define ADC_TWOSAMPLINGDELAY_12CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
|
||||
#define ADC_TWOSAMPLINGDELAY_13CYCLES ((uint32_t)ADC_CCR_DELAY_3)
|
||||
#define ADC_TWOSAMPLINGDELAY_14CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0))
|
||||
#define ADC_TWOSAMPLINGDELAY_15CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1))
|
||||
#define ADC_TWOSAMPLINGDELAY_16CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
|
||||
#define ADC_TWOSAMPLINGDELAY_17CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2))
|
||||
#define ADC_TWOSAMPLINGDELAY_18CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0))
|
||||
#define ADC_TWOSAMPLINGDELAY_19CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1))
|
||||
#define ADC_TWOSAMPLINGDELAY_20CYCLES ((uint32_t)ADC_CCR_DELAY)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_Resolution ADC Resolution
|
||||
* @{
|
||||
*/
|
||||
#define ADC_RESOLUTION_12B ((uint32_t)0x00000000U)
|
||||
#define ADC_RESOLUTION_10B ((uint32_t)ADC_CR1_RES_0)
|
||||
#define ADC_RESOLUTION_8B ((uint32_t)ADC_CR1_RES_1)
|
||||
#define ADC_RESOLUTION_6B ((uint32_t)ADC_CR1_RES)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_External_trigger_edge_Regular ADC External Trigger Edge Regular
|
||||
* @{
|
||||
*/
|
||||
#define ADC_EXTERNALTRIGCONVEDGE_NONE ((uint32_t)0x00000000U)
|
||||
#define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTEN_0)
|
||||
#define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CR2_EXTEN_1)
|
||||
#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CR2_EXTEN)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_External_trigger_Source_Regular ADC External Trigger Source Regular
|
||||
* @{
|
||||
*/
|
||||
/* Note: Parameter ADC_SOFTWARE_START is a software parameter used for */
|
||||
/* compatibility with other STM32 devices. */
|
||||
|
||||
|
||||
#define ADC_EXTERNALTRIGCONV_T1_CC1 ((uint32_t)0x00000000U)
|
||||
#define ADC_EXTERNALTRIGCONV_T1_CC2 ((uint32_t)ADC_CR2_EXTSEL_0)
|
||||
#define ADC_EXTERNALTRIGCONV_T1_CC3 ((uint32_t)ADC_CR2_EXTSEL_1)
|
||||
#define ADC_EXTERNALTRIGCONV_T2_CC2 ((uint32_t)(ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
|
||||
#define ADC_EXTERNALTRIGCONV_T5_TRGO ((uint32_t)ADC_CR2_EXTSEL_2)
|
||||
#define ADC_EXTERNALTRIGCONV_T4_CC4 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))
|
||||
#define ADC_EXTERNALTRIGCONV_T3_CC4 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1))
|
||||
#define ADC_EXTERNALTRIGCONV_T8_TRGO ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
|
||||
#define ADC_EXTERNALTRIGCONV_T8_TRGO2 ((uint32_t)ADC_CR2_EXTSEL_3)
|
||||
#define ADC_EXTERNALTRIGCONV_T1_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_0))
|
||||
#define ADC_EXTERNALTRIGCONV_T1_TRGO2 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1))
|
||||
#define ADC_EXTERNALTRIGCONV_T2_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
|
||||
#define ADC_EXTERNALTRIGCONV_T4_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2))
|
||||
#define ADC_EXTERNALTRIGCONV_T6_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))
|
||||
|
||||
#define ADC_EXTERNALTRIGCONV_EXT_IT11 ((uint32_t)ADC_CR2_EXTSEL)
|
||||
#define ADC_SOFTWARE_START ((uint32_t)ADC_CR2_EXTSEL + 1)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_Data_Align ADC Data Align
|
||||
* @{
|
||||
*/
|
||||
#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000U)
|
||||
#define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_Scan_mode ADC sequencer scan mode
|
||||
* @{
|
||||
*/
|
||||
#define ADC_SCAN_DISABLE ((uint32_t)0x00000000) /*!< Scan mode disabled */
|
||||
#define ADC_SCAN_ENABLE ((uint32_t)0x00000001) /*!< Scan mode enabled */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_regular_rank ADC group regular sequencer rank
|
||||
* @{
|
||||
*/
|
||||
#define ADC_REGULAR_RANK_1 ((uint32_t)0x00000001) /*!< ADC regular conversion rank 1 */
|
||||
#define ADC_REGULAR_RANK_2 ((uint32_t)0x00000002) /*!< ADC regular conversion rank 2 */
|
||||
#define ADC_REGULAR_RANK_3 ((uint32_t)0x00000003) /*!< ADC regular conversion rank 3 */
|
||||
#define ADC_REGULAR_RANK_4 ((uint32_t)0x00000004) /*!< ADC regular conversion rank 4 */
|
||||
#define ADC_REGULAR_RANK_5 ((uint32_t)0x00000005) /*!< ADC regular conversion rank 5 */
|
||||
#define ADC_REGULAR_RANK_6 ((uint32_t)0x00000006) /*!< ADC regular conversion rank 6 */
|
||||
#define ADC_REGULAR_RANK_7 ((uint32_t)0x00000007) /*!< ADC regular conversion rank 7 */
|
||||
#define ADC_REGULAR_RANK_8 ((uint32_t)0x00000008) /*!< ADC regular conversion rank 8 */
|
||||
#define ADC_REGULAR_RANK_9 ((uint32_t)0x00000009) /*!< ADC regular conversion rank 9 */
|
||||
#define ADC_REGULAR_RANK_10 ((uint32_t)0x0000000A) /*!< ADC regular conversion rank 10 */
|
||||
#define ADC_REGULAR_RANK_11 ((uint32_t)0x0000000B) /*!< ADC regular conversion rank 11 */
|
||||
#define ADC_REGULAR_RANK_12 ((uint32_t)0x0000000C) /*!< ADC regular conversion rank 12 */
|
||||
#define ADC_REGULAR_RANK_13 ((uint32_t)0x0000000D) /*!< ADC regular conversion rank 13 */
|
||||
#define ADC_REGULAR_RANK_14 ((uint32_t)0x0000000E) /*!< ADC regular conversion rank 14 */
|
||||
#define ADC_REGULAR_RANK_15 ((uint32_t)0x0000000F) /*!< ADC regular conversion rank 15 */
|
||||
#define ADC_REGULAR_RANK_16 ((uint32_t)0x00000010) /*!< ADC regular conversion rank 16 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_channels ADC Common Channels
|
||||
* @{
|
||||
*/
|
||||
#define ADC_CHANNEL_0 ((uint32_t)0x00000000U)
|
||||
#define ADC_CHANNEL_1 ((uint32_t)ADC_CR1_AWDCH_0)
|
||||
#define ADC_CHANNEL_2 ((uint32_t)ADC_CR1_AWDCH_1)
|
||||
#define ADC_CHANNEL_3 ((uint32_t)(ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
|
||||
#define ADC_CHANNEL_4 ((uint32_t)ADC_CR1_AWDCH_2)
|
||||
#define ADC_CHANNEL_5 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0))
|
||||
#define ADC_CHANNEL_6 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1))
|
||||
#define ADC_CHANNEL_7 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
|
||||
#define ADC_CHANNEL_8 ((uint32_t)ADC_CR1_AWDCH_3)
|
||||
#define ADC_CHANNEL_9 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_0))
|
||||
#define ADC_CHANNEL_10 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1))
|
||||
#define ADC_CHANNEL_11 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
|
||||
#define ADC_CHANNEL_12 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2))
|
||||
#define ADC_CHANNEL_13 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0))
|
||||
#define ADC_CHANNEL_14 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1))
|
||||
#define ADC_CHANNEL_15 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
|
||||
#define ADC_CHANNEL_16 ((uint32_t)ADC_CR1_AWDCH_4)
|
||||
#define ADC_CHANNEL_17 ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_0))
|
||||
#define ADC_CHANNEL_18 ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_1))
|
||||
|
||||
#define ADC_CHANNEL_VREFINT ((uint32_t)ADC_CHANNEL_17)
|
||||
#define ADC_CHANNEL_VBAT ((uint32_t)ADC_CHANNEL_18)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_sampling_times ADC Sampling Times
|
||||
* @{
|
||||
*/
|
||||
#define ADC_SAMPLETIME_3CYCLES ((uint32_t)0x00000000U)
|
||||
#define ADC_SAMPLETIME_15CYCLES ((uint32_t)ADC_SMPR1_SMP10_0)
|
||||
#define ADC_SAMPLETIME_28CYCLES ((uint32_t)ADC_SMPR1_SMP10_1)
|
||||
#define ADC_SAMPLETIME_56CYCLES ((uint32_t)(ADC_SMPR1_SMP10_1 | ADC_SMPR1_SMP10_0))
|
||||
#define ADC_SAMPLETIME_84CYCLES ((uint32_t)ADC_SMPR1_SMP10_2)
|
||||
#define ADC_SAMPLETIME_112CYCLES ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_0))
|
||||
#define ADC_SAMPLETIME_144CYCLES ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_1))
|
||||
#define ADC_SAMPLETIME_480CYCLES ((uint32_t)ADC_SMPR1_SMP10)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_EOCSelection ADC EOC Selection
|
||||
* @{
|
||||
*/
|
||||
#define ADC_EOC_SEQ_CONV ((uint32_t)0x00000000U)
|
||||
#define ADC_EOC_SINGLE_CONV ((uint32_t)0x00000001U)
|
||||
#define ADC_EOC_SINGLE_SEQ_CONV ((uint32_t)0x00000002U) /*!< reserved for future use */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_Event_type ADC Event Type
|
||||
* @{
|
||||
*/
|
||||
#define ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD)
|
||||
#define ADC_OVR_EVENT ((uint32_t)ADC_FLAG_OVR)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_analog_watchdog_selection ADC Analog Watchdog Selection
|
||||
* @{
|
||||
*/
|
||||
#define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN))
|
||||
#define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN))
|
||||
#define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
|
||||
#define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t)ADC_CR1_AWDEN)
|
||||
#define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t)ADC_CR1_JAWDEN)
|
||||
#define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
|
||||
#define ADC_ANALOGWATCHDOG_NONE ((uint32_t)0x00000000U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_interrupts_definition ADC Interrupts Definition
|
||||
* @{
|
||||
*/
|
||||
#define ADC_IT_EOC ((uint32_t)ADC_CR1_EOCIE)
|
||||
#define ADC_IT_AWD ((uint32_t)ADC_CR1_AWDIE)
|
||||
#define ADC_IT_JEOC ((uint32_t)ADC_CR1_JEOCIE)
|
||||
#define ADC_IT_OVR ((uint32_t)ADC_CR1_OVRIE)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_flags_definition ADC Flags Definition
|
||||
* @{
|
||||
*/
|
||||
#define ADC_FLAG_AWD ((uint32_t)ADC_SR_AWD)
|
||||
#define ADC_FLAG_EOC ((uint32_t)ADC_SR_EOC)
|
||||
#define ADC_FLAG_JEOC ((uint32_t)ADC_SR_JEOC)
|
||||
#define ADC_FLAG_JSTRT ((uint32_t)ADC_SR_JSTRT)
|
||||
#define ADC_FLAG_STRT ((uint32_t)ADC_SR_STRT)
|
||||
#define ADC_FLAG_OVR ((uint32_t)ADC_SR_OVR)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_channels_type ADC Channels Type
|
||||
* @{
|
||||
*/
|
||||
#define ADC_ALL_CHANNELS ((uint32_t)0x00000001U)
|
||||
#define ADC_REGULAR_CHANNELS ((uint32_t)0x00000002U) /*!< reserved for future use */
|
||||
#define ADC_INJECTED_CHANNELS ((uint32_t)0x00000003U) /*!< reserved for future use */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup ADC_Exported_Macros ADC Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset ADC handle state
|
||||
* @param __HANDLE__: ADC handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
|
||||
|
||||
/**
|
||||
* @brief Enable the ADC peripheral.
|
||||
* @param __HANDLE__: ADC handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_ADC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 |= ADC_CR2_ADON)
|
||||
|
||||
/**
|
||||
* @brief Disable the ADC peripheral.
|
||||
* @param __HANDLE__: ADC handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_ADC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= ~ADC_CR2_ADON)
|
||||
|
||||
/**
|
||||
* @brief Enable the ADC end of conversion interrupt.
|
||||
* @param __HANDLE__: specifies the ADC Handle.
|
||||
* @param __INTERRUPT__: ADC Interrupt.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) |= (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Disable the ADC end of conversion interrupt.
|
||||
* @param __HANDLE__: specifies the ADC Handle.
|
||||
* @param __INTERRUPT__: ADC interrupt.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) &= ~(__INTERRUPT__))
|
||||
|
||||
/** @brief Check if the specified ADC interrupt source is enabled or disabled.
|
||||
* @param __HANDLE__: specifies the ADC Handle.
|
||||
* @param __INTERRUPT__: specifies the ADC interrupt source to check.
|
||||
* @retval The new state of __IT__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Clear the ADC's pending flags.
|
||||
* @param __HANDLE__: specifies the ADC Handle.
|
||||
* @param __FLAG__: ADC flag.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = ~(__FLAG__))
|
||||
|
||||
/**
|
||||
* @brief Get the selected ADC's flag status.
|
||||
* @param __HANDLE__: specifies the ADC Handle.
|
||||
* @param __FLAG__: ADC flag.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include ADC HAL Extension module */
|
||||
#include "stm32f7xx_hal_adc_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup ADC_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup ADC_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Initialization/de-initialization functions ***********************************/
|
||||
HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc);
|
||||
HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
|
||||
void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc);
|
||||
void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup ADC_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* I/O operation functions ******************************************************/
|
||||
HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc);
|
||||
HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc);
|
||||
HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
|
||||
|
||||
HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout);
|
||||
|
||||
HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc);
|
||||
HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc);
|
||||
|
||||
void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc);
|
||||
|
||||
HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
|
||||
HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc);
|
||||
|
||||
uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc);
|
||||
|
||||
void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc);
|
||||
void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc);
|
||||
void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc);
|
||||
void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup ADC_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral Control functions *************************************************/
|
||||
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig);
|
||||
HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup ADC_Exported_Functions_Group4
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State functions ***************************************************/
|
||||
uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc);
|
||||
uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup ADC_Private_Constants ADC Private Constants
|
||||
* @{
|
||||
*/
|
||||
/* Delay for ADC stabilization time. */
|
||||
/* Maximum delay is 1us (refer to device datasheet, parameter tSTAB). */
|
||||
/* Unit: us */
|
||||
#define ADC_STAB_DELAY_US ((uint32_t) 3U)
|
||||
/* Delay for temperature sensor stabilization time. */
|
||||
/* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */
|
||||
/* Unit: us */
|
||||
#define ADC_TEMPSENSOR_DELAY_US ((uint32_t) 10U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup ADC_Private_Macros ADC Private Macros
|
||||
* @{
|
||||
*/
|
||||
/* Macro reserved for internal HAL driver usage, not intended to be used in
|
||||
code of final user */
|
||||
|
||||
/**
|
||||
* @brief Verification of ADC state: enabled or disabled
|
||||
* @param __HANDLE__: ADC handle
|
||||
* @retval SET (ADC enabled) or RESET (ADC disabled)
|
||||
*/
|
||||
#define ADC_IS_ENABLE(__HANDLE__) \
|
||||
((( ((__HANDLE__)->Instance->SR & ADC_SR_ADONS) == ADC_SR_ADONS ) \
|
||||
) ? SET : RESET)
|
||||
|
||||
/**
|
||||
* @brief Test if conversion trigger of regular group is software start
|
||||
* or external trigger.
|
||||
* @param __HANDLE__: ADC handle
|
||||
* @retval SET (software start) or RESET (external trigger)
|
||||
*/
|
||||
#define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \
|
||||
(((__HANDLE__)->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
|
||||
|
||||
/**
|
||||
* @brief Test if conversion trigger of injected group is software start
|
||||
* or external trigger.
|
||||
* @param __HANDLE__: ADC handle
|
||||
* @retval SET (software start) or RESET (external trigger)
|
||||
*/
|
||||
#define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \
|
||||
(((__HANDLE__)->Instance->CR2 & ADC_CR2_JEXTEN) == RESET)
|
||||
|
||||
/**
|
||||
* @brief Simultaneously clears and sets specific bits of the handle State
|
||||
* @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(),
|
||||
* the first parameter is the ADC handle State, the second parameter is the
|
||||
* bit field to clear, the third and last parameter is the bit field to set.
|
||||
* @retval None
|
||||
*/
|
||||
#define ADC_STATE_CLR_SET MODIFY_REG
|
||||
|
||||
/**
|
||||
* @brief Clear ADC error code (set it to error code: "no error")
|
||||
* @param __HANDLE__: ADC handle
|
||||
* @retval None
|
||||
*/
|
||||
#define ADC_CLEAR_ERRORCODE(__HANDLE__) \
|
||||
((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
|
||||
#define IS_ADC_CLOCKPRESCALER(__ADC_CLOCK__) (((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV2) || \
|
||||
((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV4) || \
|
||||
((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV6) || \
|
||||
((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV8))
|
||||
#define IS_ADC_SAMPLING_DELAY(__DELAY__) (((__DELAY__) == ADC_TWOSAMPLINGDELAY_5CYCLES) || \
|
||||
((__DELAY__) == ADC_TWOSAMPLINGDELAY_6CYCLES) || \
|
||||
((__DELAY__) == ADC_TWOSAMPLINGDELAY_7CYCLES) || \
|
||||
((__DELAY__) == ADC_TWOSAMPLINGDELAY_8CYCLES) || \
|
||||
((__DELAY__) == ADC_TWOSAMPLINGDELAY_9CYCLES) || \
|
||||
((__DELAY__) == ADC_TWOSAMPLINGDELAY_10CYCLES) || \
|
||||
((__DELAY__) == ADC_TWOSAMPLINGDELAY_11CYCLES) || \
|
||||
((__DELAY__) == ADC_TWOSAMPLINGDELAY_12CYCLES) || \
|
||||
((__DELAY__) == ADC_TWOSAMPLINGDELAY_13CYCLES) || \
|
||||
((__DELAY__) == ADC_TWOSAMPLINGDELAY_14CYCLES) || \
|
||||
((__DELAY__) == ADC_TWOSAMPLINGDELAY_15CYCLES) || \
|
||||
((__DELAY__) == ADC_TWOSAMPLINGDELAY_16CYCLES) || \
|
||||
((__DELAY__) == ADC_TWOSAMPLINGDELAY_17CYCLES) || \
|
||||
((__DELAY__) == ADC_TWOSAMPLINGDELAY_18CYCLES) || \
|
||||
((__DELAY__) == ADC_TWOSAMPLINGDELAY_19CYCLES) || \
|
||||
((__DELAY__) == ADC_TWOSAMPLINGDELAY_20CYCLES))
|
||||
#define IS_ADC_RESOLUTION(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_12B) || \
|
||||
((__RESOLUTION__) == ADC_RESOLUTION_10B) || \
|
||||
((__RESOLUTION__) == ADC_RESOLUTION_8B) || \
|
||||
((__RESOLUTION__) == ADC_RESOLUTION_6B))
|
||||
#define IS_ADC_EXT_TRIG_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \
|
||||
((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \
|
||||
((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \
|
||||
((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING))
|
||||
#define IS_ADC_EXT_TRIG(__REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T1_CC1) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T1_CC2) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T1_CC3) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T2_CC2) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T5_TRGO) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T4_CC4) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T3_CC4) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T8_TRGO) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T8_TRGO2) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T1_TRGO) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T1_TRGO2) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T4_TRGO) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T6_TRGO) || \
|
||||
((__REGTRIG__) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \
|
||||
((__REGTRIG__) == ADC_SOFTWARE_START))
|
||||
#define IS_ADC_DATA_ALIGN(__ALIGN__) (((__ALIGN__) == ADC_DATAALIGN_RIGHT) || \
|
||||
((__ALIGN__) == ADC_DATAALIGN_LEFT))
|
||||
|
||||
|
||||
#define IS_ADC_SAMPLE_TIME(__TIME__) (((__TIME__) == ADC_SAMPLETIME_3CYCLES) || \
|
||||
((__TIME__) == ADC_SAMPLETIME_15CYCLES) || \
|
||||
((__TIME__) == ADC_SAMPLETIME_28CYCLES) || \
|
||||
((__TIME__) == ADC_SAMPLETIME_56CYCLES) || \
|
||||
((__TIME__) == ADC_SAMPLETIME_84CYCLES) || \
|
||||
((__TIME__) == ADC_SAMPLETIME_112CYCLES) || \
|
||||
((__TIME__) == ADC_SAMPLETIME_144CYCLES) || \
|
||||
((__TIME__) == ADC_SAMPLETIME_480CYCLES))
|
||||
#define IS_ADC_EOCSelection(__EOCSelection__) (((__EOCSelection__) == ADC_EOC_SINGLE_CONV) || \
|
||||
((__EOCSelection__) == ADC_EOC_SEQ_CONV) || \
|
||||
((__EOCSelection__) == ADC_EOC_SINGLE_SEQ_CONV))
|
||||
#define IS_ADC_EVENT_TYPE(__EVENT__) (((__EVENT__) == ADC_AWD_EVENT) || \
|
||||
((__EVENT__) == ADC_OVR_EVENT))
|
||||
#define IS_ADC_ANALOG_WATCHDOG(__WATCHDOG__) (((__WATCHDOG__) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \
|
||||
((__WATCHDOG__) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \
|
||||
((__WATCHDOG__) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \
|
||||
((__WATCHDOG__) == ADC_ANALOGWATCHDOG_ALL_REG) || \
|
||||
((__WATCHDOG__) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \
|
||||
((__WATCHDOG__) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) || \
|
||||
((__WATCHDOG__) == ADC_ANALOGWATCHDOG_NONE))
|
||||
#define IS_ADC_CHANNELS_TYPE(CHANNEL_TYPE) (((CHANNEL_TYPE) == ADC_ALL_CHANNELS) || \
|
||||
((CHANNEL_TYPE) == ADC_REGULAR_CHANNELS) || \
|
||||
((CHANNEL_TYPE) == ADC_INJECTED_CHANNELS))
|
||||
|
||||
#define IS_ADC_REGULAR_RANK(__RANK__) (((__RANK__) == ADC_REGULAR_RANK_1 ) || \
|
||||
((__RANK__) == ADC_REGULAR_RANK_2 ) || \
|
||||
((__RANK__) == ADC_REGULAR_RANK_3 ) || \
|
||||
((__RANK__) == ADC_REGULAR_RANK_4 ) || \
|
||||
((__RANK__) == ADC_REGULAR_RANK_5 ) || \
|
||||
((__RANK__) == ADC_REGULAR_RANK_6 ) || \
|
||||
((__RANK__) == ADC_REGULAR_RANK_7 ) || \
|
||||
((__RANK__) == ADC_REGULAR_RANK_8 ) || \
|
||||
((__RANK__) == ADC_REGULAR_RANK_9 ) || \
|
||||
((__RANK__) == ADC_REGULAR_RANK_10) || \
|
||||
((__RANK__) == ADC_REGULAR_RANK_11) || \
|
||||
((__RANK__) == ADC_REGULAR_RANK_12) || \
|
||||
((__RANK__) == ADC_REGULAR_RANK_13) || \
|
||||
((__RANK__) == ADC_REGULAR_RANK_14) || \
|
||||
((__RANK__) == ADC_REGULAR_RANK_15) || \
|
||||
((__RANK__) == ADC_REGULAR_RANK_16))
|
||||
|
||||
#define IS_ADC_SCAN_MODE(__SCAN_MODE__) (((__SCAN_MODE__) == ADC_SCAN_DISABLE) || \
|
||||
((__SCAN_MODE__) == ADC_SCAN_ENABLE))
|
||||
|
||||
#define IS_ADC_THRESHOLD(__THRESHOLD__) ((__THRESHOLD__) <= ((uint32_t)0xFFF))
|
||||
#define IS_ADC_REGULAR_LENGTH(__LENGTH__) (((__LENGTH__) >= ((uint32_t)1)) && ((__LENGTH__) <= ((uint32_t)16)))
|
||||
#define IS_ADC_REGULAR_DISC_NUMBER(__NUMBER__) (((__NUMBER__) >= ((uint32_t)1)) && ((__NUMBER__) <= ((uint32_t)8)))
|
||||
#define IS_ADC_RANGE(__RESOLUTION__, __ADC_VALUE__) \
|
||||
((((__RESOLUTION__) == ADC_RESOLUTION_12B) && ((__ADC_VALUE__) <= ((uint32_t)0x0FFF))) || \
|
||||
(((__RESOLUTION__) == ADC_RESOLUTION_10B) && ((__ADC_VALUE__) <= ((uint32_t)0x03FF))) || \
|
||||
(((__RESOLUTION__) == ADC_RESOLUTION_8B) && ((__ADC_VALUE__) <= ((uint32_t)0x00FF))) || \
|
||||
(((__RESOLUTION__) == ADC_RESOLUTION_6B) && ((__ADC_VALUE__) <= ((uint32_t)0x003F))))
|
||||
|
||||
/**
|
||||
* @brief Set ADC Regular channel sequence length.
|
||||
* @param _NbrOfConversion_: Regular channel sequence length.
|
||||
* @retval None
|
||||
*/
|
||||
#define ADC_SQR1(_NbrOfConversion_) (((_NbrOfConversion_) - (uint8_t)1) << 20)
|
||||
|
||||
/**
|
||||
* @brief Set the ADC's sample time for channel numbers between 10 and 18.
|
||||
* @param _SAMPLETIME_: Sample time parameter.
|
||||
* @param _CHANNELNB_: Channel number.
|
||||
* @retval None
|
||||
*/
|
||||
#define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * (((uint32_t)((uint16_t)(_CHANNELNB_))) - 10)))
|
||||
|
||||
/**
|
||||
* @brief Set the ADC's sample time for channel numbers between 0 and 9.
|
||||
* @param _SAMPLETIME_: Sample time parameter.
|
||||
* @param _CHANNELNB_: Channel number.
|
||||
* @retval None
|
||||
*/
|
||||
#define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * ((uint32_t)((uint16_t)(_CHANNELNB_)))))
|
||||
|
||||
/**
|
||||
* @brief Set the selected regular channel rank for rank between 1 and 6.
|
||||
* @param _CHANNELNB_: Channel number.
|
||||
* @param _RANKNB_: Rank number.
|
||||
* @retval None
|
||||
*/
|
||||
#define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * ((_RANKNB_) - 1)))
|
||||
|
||||
/**
|
||||
* @brief Set the selected regular channel rank for rank between 7 and 12.
|
||||
* @param _CHANNELNB_: Channel number.
|
||||
* @param _RANKNB_: Rank number.
|
||||
* @retval None
|
||||
*/
|
||||
#define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * ((_RANKNB_) - 7)))
|
||||
|
||||
/**
|
||||
* @brief Set the selected regular channel rank for rank between 13 and 16.
|
||||
* @param _CHANNELNB_: Channel number.
|
||||
* @param _RANKNB_: Rank number.
|
||||
* @retval None
|
||||
*/
|
||||
#define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * ((_RANKNB_) - 13)))
|
||||
|
||||
/**
|
||||
* @brief Enable ADC continuous conversion mode.
|
||||
* @param _CONTINUOUS_MODE_: Continuous mode.
|
||||
* @retval None
|
||||
*/
|
||||
#define ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 1)
|
||||
|
||||
/**
|
||||
* @brief Configures the number of discontinuous conversions for the regular group channels.
|
||||
* @param _NBR_DISCONTINUOUSCONV_: Number of discontinuous conversions.
|
||||
* @retval None
|
||||
*/
|
||||
#define ADC_CR1_DISCONTINUOUS(_NBR_DISCONTINUOUSCONV_) (((_NBR_DISCONTINUOUSCONV_) - 1) << POSITION_VAL(ADC_CR1_DISCNUM))
|
||||
|
||||
/**
|
||||
* @brief Enable ADC scan mode.
|
||||
* @param _SCANCONV_MODE_: Scan conversion mode.
|
||||
* @retval None
|
||||
*/
|
||||
#define ADC_CR1_SCANCONV(_SCANCONV_MODE_) ((_SCANCONV_MODE_) << 8)
|
||||
|
||||
/**
|
||||
* @brief Enable the ADC end of conversion selection.
|
||||
* @param _EOCSelection_MODE_: End of conversion selection mode.
|
||||
* @retval None
|
||||
*/
|
||||
#define ADC_CR2_EOCSelection(_EOCSelection_MODE_) ((_EOCSelection_MODE_) << 10)
|
||||
|
||||
/**
|
||||
* @brief Enable the ADC DMA continuous request.
|
||||
* @param _DMAContReq_MODE_: DMA continuous request mode.
|
||||
* @retval None
|
||||
*/
|
||||
#define ADC_CR2_DMAContReq(_DMAContReq_MODE_) ((_DMAContReq_MODE_) << 9)
|
||||
|
||||
/**
|
||||
* @brief Return resolution bits in CR1 register.
|
||||
* @param __HANDLE__: ADC handle
|
||||
* @retval None
|
||||
*/
|
||||
#define ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CR1) & ADC_CR1_RES)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup ADC_Private_Functions ADC Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__STM32F7xx_ADC_H */
|
||||
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,376 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_hal_adc.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.2
|
||||
* @date 14-April-2017
|
||||
* @brief Header file of ADC HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F7xx_ADC_EX_H
|
||||
#define __STM32F7xx_ADC_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup ADCEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup ADCEx_Exported_Types ADC Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief ADC Configuration injected Channel structure definition
|
||||
* @note Parameters of this structure are shared within 2 scopes:
|
||||
* - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime, InjectedOffset
|
||||
* - Scope injected group (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode,
|
||||
* AutoInjectedConv, ExternalTrigInjecConvEdge, ExternalTrigInjecConv.
|
||||
* @note The setting of these parameters with function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state.
|
||||
* ADC state can be either:
|
||||
* - For all parameters: ADC disabled
|
||||
* - For all except parameters 'InjectedDiscontinuousConvMode' and 'AutoInjectedConv': ADC enabled without conversion on going on injected group.
|
||||
* - For parameters 'ExternalTrigInjecConv' and 'ExternalTrigInjecConvEdge': ADC enabled, even with conversion on going on injected group.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t InjectedChannel; /*!< Selection of ADC channel to configure
|
||||
This parameter can be a value of @ref ADC_channels
|
||||
Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. */
|
||||
uint32_t InjectedRank; /*!< Rank in the injected group sequencer
|
||||
This parameter must be a value of @ref ADCEx_injected_rank
|
||||
Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */
|
||||
uint32_t InjectedSamplingTime; /*!< Sampling time value to be set for the selected channel.
|
||||
Unit: ADC clock cycles
|
||||
Conversion time is the addition of sampling time and processing time (12 ADC clock cycles at ADC resolution 12 bits, 11 cycles at 10 bits, 9 cycles at 8 bits, 7 cycles at 6 bits).
|
||||
This parameter can be a value of @ref ADC_sampling_times
|
||||
Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
|
||||
If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
|
||||
Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
|
||||
sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
|
||||
Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 4us min). */
|
||||
uint32_t InjectedOffset; /*!< Defines the offset to be subtracted from the raw converted data (for channels set on injected group only).
|
||||
Offset value must be a positive number.
|
||||
Depending of ADC resolution selected (12, 10, 8 or 6 bits),
|
||||
this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */
|
||||
uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the injected group sequencer.
|
||||
To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
|
||||
This parameter must be a number between Min_Data = 1 and Max_Data = 4.
|
||||
Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
|
||||
configure a channel on injected group can impact the configuration of other channels previously set. */
|
||||
uint32_t InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of injected group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
|
||||
Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
|
||||
Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
|
||||
This parameter can be set to ENABLE or DISABLE.
|
||||
Note: For injected group, number of discontinuous ranks increment is fixed to one-by-one.
|
||||
Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
|
||||
configure a channel on injected group can impact the configuration of other channels previously set. */
|
||||
uint32_t AutoInjectedConv; /*!< Enables or disables the selected ADC automatic injected group conversion after regular one
|
||||
This parameter can be set to ENABLE or DISABLE.
|
||||
Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE)
|
||||
Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_SOFTWARE_START)
|
||||
Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete.
|
||||
To maintain JAUTO always enabled, DMA must be configured in circular mode.
|
||||
Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
|
||||
configure a channel on injected group can impact the configuration of other channels previously set. */
|
||||
uint32_t ExternalTrigInjecConv; /*!< Selects the external event used to trigger the conversion start of injected group.
|
||||
If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled.
|
||||
If set to external trigger source, triggering is on event rising edge.
|
||||
This parameter can be a value of @ref ADCEx_External_trigger_Source_Injected
|
||||
Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
|
||||
If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behaviour in case of another parameter update on the fly)
|
||||
Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
|
||||
configure a channel on injected group can impact the configuration of other channels previously set. */
|
||||
uint32_t ExternalTrigInjecConvEdge; /*!< Selects the external trigger edge of injected group.
|
||||
This parameter can be a value of @ref ADCEx_External_trigger_edge_Injected.
|
||||
If trigger is set to ADC_INJECTED_SOFTWARE_START, this parameter is discarded.
|
||||
Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
|
||||
configure a channel on injected group can impact the configuration of other channels previously set. */
|
||||
}ADC_InjectionConfTypeDef;
|
||||
|
||||
/**
|
||||
* @brief ADC Configuration multi-mode structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Mode; /*!< Configures the ADC to operate in independent or multi mode.
|
||||
This parameter can be a value of @ref ADCEx_Common_mode */
|
||||
uint32_t DMAAccessMode; /*!< Configures the Direct memory access mode for multi ADC mode.
|
||||
This parameter can be a value of @ref ADCEx_Direct_memory_access_mode_for_multi_mode */
|
||||
uint32_t TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases.
|
||||
This parameter can be a value of @ref ADC_delay_between_2_sampling_phases */
|
||||
}ADC_MultiModeTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup ADCEx_Exported_Constants ADC Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup ADCEx_Common_mode ADC Common Mode
|
||||
* @{
|
||||
*/
|
||||
#define ADC_MODE_INDEPENDENT ((uint32_t)0x00000000U)
|
||||
#define ADC_DUALMODE_REGSIMULT_INJECSIMULT ((uint32_t)ADC_CCR_MULTI_0)
|
||||
#define ADC_DUALMODE_REGSIMULT_ALTERTRIG ((uint32_t)ADC_CCR_MULTI_1)
|
||||
#define ADC_DUALMODE_INJECSIMULT ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0))
|
||||
#define ADC_DUALMODE_REGSIMULT ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1))
|
||||
#define ADC_DUALMODE_INTERL ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0))
|
||||
#define ADC_DUALMODE_ALTERTRIG ((uint32_t)(ADC_CCR_MULTI_3 | ADC_CCR_MULTI_0))
|
||||
#define ADC_TRIPLEMODE_REGSIMULT_INJECSIMULT ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_0))
|
||||
#define ADC_TRIPLEMODE_REGSIMULT_AlterTrig ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_1))
|
||||
#define ADC_TRIPLEMODE_INJECSIMULT ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0))
|
||||
#define ADC_TRIPLEMODE_REGSIMULT ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1))
|
||||
#define ADC_TRIPLEMODE_INTERL ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0))
|
||||
#define ADC_TRIPLEMODE_ALTERTRIG ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_3 | ADC_CCR_MULTI_0))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADCEx_Direct_memory_access_mode_for_multi_mode ADC Direct Memory Access Mode For Multi Mode
|
||||
* @{
|
||||
*/
|
||||
#define ADC_DMAACCESSMODE_DISABLED ((uint32_t)0x00000000U) /*!< DMA mode disabled */
|
||||
#define ADC_DMAACCESSMODE_1 ((uint32_t)ADC_CCR_DMA_0) /*!< DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3)*/
|
||||
#define ADC_DMAACCESSMODE_2 ((uint32_t)ADC_CCR_DMA_1) /*!< DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)*/
|
||||
#define ADC_DMAACCESSMODE_3 ((uint32_t)ADC_CCR_DMA) /*!< DMA mode 3 enabled (2 / 3 bytes by pairs - 2&1 then 1&3 then 3&2) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADCEx_External_trigger_edge_Injected ADC External Trigger Edge Injected
|
||||
* @{
|
||||
*/
|
||||
#define ADC_EXTERNALTRIGINJECCONVEDGE_NONE ((uint32_t)0x00000000U)
|
||||
#define ADC_EXTERNALTRIGINJECCONVEDGE_RISING ((uint32_t)ADC_CR2_JEXTEN_0)
|
||||
#define ADC_EXTERNALTRIGINJECCONVEDGE_FALLING ((uint32_t)ADC_CR2_JEXTEN_1)
|
||||
#define ADC_EXTERNALTRIGINJECCONVEDGE_RISINGFALLING ((uint32_t)ADC_CR2_JEXTEN)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADCEx_External_trigger_Source_Injected ADC External Trigger Source Injected
|
||||
* @{
|
||||
*/
|
||||
#define ADC_EXTERNALTRIGINJECCONV_T1_TRGO ((uint32_t)0x00000000U)
|
||||
#define ADC_EXTERNALTRIGINJECCONV_T1_CC4 ((uint32_t)ADC_CR2_JEXTSEL_0)
|
||||
#define ADC_EXTERNALTRIGINJECCONV_T2_TRGO ((uint32_t)ADC_CR2_JEXTSEL_1)
|
||||
#define ADC_EXTERNALTRIGINJECCONV_T2_CC1 ((uint32_t)(ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
|
||||
#define ADC_EXTERNALTRIGINJECCONV_T3_CC4 ((uint32_t)ADC_CR2_JEXTSEL_2)
|
||||
#define ADC_EXTERNALTRIGINJECCONV_T4_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0))
|
||||
|
||||
#define ADC_EXTERNALTRIGINJECCONV_T8_CC4 ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
|
||||
#define ADC_EXTERNALTRIGINJECCONV_T1_TRGO2 ((uint32_t)ADC_CR2_JEXTSEL_3)
|
||||
#define ADC_EXTERNALTRIGINJECCONV_T8_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_0))
|
||||
#define ADC_EXTERNALTRIGINJECCONV_T8_TRGO2 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1))
|
||||
#define ADC_EXTERNALTRIGINJECCONV_T3_CC3 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
|
||||
#define ADC_EXTERNALTRIGINJECCONV_T5_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2))
|
||||
#define ADC_EXTERNALTRIGINJECCONV_T3_CC1 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0))
|
||||
#define ADC_EXTERNALTRIGINJECCONV_T6_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1))
|
||||
#define ADC_INJECTED_SOFTWARE_START ((uint32_t)ADC_CR2_JEXTSEL + 1)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADCEx_injected_rank ADC Injected Channel Rank
|
||||
* @{
|
||||
*/
|
||||
#define ADC_INJECTED_RANK_1 ((uint32_t)0x00000001U)
|
||||
#define ADC_INJECTED_RANK_2 ((uint32_t)0x00000002U)
|
||||
#define ADC_INJECTED_RANK_3 ((uint32_t)0x00000003U)
|
||||
#define ADC_INJECTED_RANK_4 ((uint32_t)0x00000004U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADCEx_channels ADC Specific Channels
|
||||
* @{
|
||||
*/
|
||||
#define ADC_CHANNEL_TEMPSENSOR ((uint32_t)ADC_CHANNEL_18 | 0x10000000U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup ADC_Exported_Macros ADC Exported Macros
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup ADCEx_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup ADCEx_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* I/O operation functions ******************************************************/
|
||||
HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc);
|
||||
HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc);
|
||||
HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc);
|
||||
HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc);
|
||||
uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank);
|
||||
HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
|
||||
HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc);
|
||||
uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc);
|
||||
void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc);
|
||||
|
||||
/* Peripheral Control functions *************************************************/
|
||||
HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc,ADC_InjectionConfTypeDef* sConfigInjected);
|
||||
HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* multimode);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup ADCEx_Private_Constants ADC Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup ADCEx_Private_Macros ADC Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) <= ADC_CHANNEL_18) || \
|
||||
((CHANNEL) == ADC_CHANNEL_TEMPSENSOR))
|
||||
|
||||
#define IS_ADC_MODE(__MODE__) (((__MODE__) == ADC_MODE_INDEPENDENT) || \
|
||||
((__MODE__) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \
|
||||
((__MODE__) == ADC_DUALMODE_REGSIMULT_ALTERTRIG) || \
|
||||
((__MODE__) == ADC_DUALMODE_INJECSIMULT) || \
|
||||
((__MODE__) == ADC_DUALMODE_REGSIMULT) || \
|
||||
((__MODE__) == ADC_DUALMODE_INTERL) || \
|
||||
((__MODE__) == ADC_DUALMODE_ALTERTRIG) || \
|
||||
((__MODE__) == ADC_TRIPLEMODE_REGSIMULT_INJECSIMULT) || \
|
||||
((__MODE__) == ADC_TRIPLEMODE_REGSIMULT_AlterTrig) || \
|
||||
((__MODE__) == ADC_TRIPLEMODE_INJECSIMULT) || \
|
||||
((__MODE__) == ADC_TRIPLEMODE_REGSIMULT) || \
|
||||
((__MODE__) == ADC_TRIPLEMODE_INTERL) || \
|
||||
((__MODE__) == ADC_TRIPLEMODE_ALTERTRIG))
|
||||
#define IS_ADC_DMA_ACCESS_MODE(__MODE__) (((__MODE__) == ADC_DMAACCESSMODE_DISABLED) || \
|
||||
((__MODE__) == ADC_DMAACCESSMODE_1) || \
|
||||
((__MODE__) == ADC_DMAACCESSMODE_2) || \
|
||||
((__MODE__) == ADC_DMAACCESSMODE_3))
|
||||
#define IS_ADC_EXT_INJEC_TRIG_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGINJECCONVEDGE_NONE) || \
|
||||
((__EDGE__) == ADC_EXTERNALTRIGINJECCONVEDGE_RISING) || \
|
||||
((__EDGE__) == ADC_EXTERNALTRIGINJECCONVEDGE_FALLING) || \
|
||||
((__EDGE__) == ADC_EXTERNALTRIGINJECCONVEDGE_RISINGFALLING))
|
||||
#define IS_ADC_EXT_INJEC_TRIG(__INJTRIG__) (((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO2) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T8_TRGO) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T8_TRGO2) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T3_CC3) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T5_TRGO) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T3_CC1) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T6_TRGO) || \
|
||||
((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START))
|
||||
#define IS_ADC_INJECTED_RANK(__RANK__) (((__RANK__) == ADC_INJECTED_RANK_1) || \
|
||||
((__RANK__) == ADC_INJECTED_RANK_2) || \
|
||||
((__RANK__) == ADC_INJECTED_RANK_3) || \
|
||||
((__RANK__) == ADC_INJECTED_RANK_4))
|
||||
#define IS_ADC_INJECTED_LENGTH(__LENGTH__) (((__LENGTH__) >= ((uint32_t)1)) && ((__LENGTH__) <= ((uint32_t)4)))
|
||||
|
||||
/**
|
||||
* @brief Set the selected injected Channel rank.
|
||||
* @param _CHANNELNB_: Channel number.
|
||||
* @param _RANKNB_: Rank number.
|
||||
* @param _JSQR_JL_: Sequence length.
|
||||
* @retval None
|
||||
*/
|
||||
#define ADC_JSQR(_CHANNELNB_, _RANKNB_,_JSQR_JL_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * (uint8_t)(((_RANKNB_) + 3) - (_JSQR_JL_))))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup ADCEx_Private_Functions ADC Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__STM32F7xx_ADC_EX_H */
|
||||
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,777 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_hal_can.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.2
|
||||
* @date 14-April-2017
|
||||
* @brief Header file of CAN HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F7xx_HAL_CAN_H
|
||||
#define __STM32F7xx_HAL_CAN_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CAN
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup CAN_Exported_Types CAN Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief HAL State structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_CAN_STATE_RESET = 0x00U, /*!< CAN not yet initialized or disabled */
|
||||
HAL_CAN_STATE_READY = 0x01U, /*!< CAN initialized and ready for use */
|
||||
HAL_CAN_STATE_BUSY = 0x02U, /*!< CAN process is ongoing */
|
||||
HAL_CAN_STATE_BUSY_TX = 0x12U, /*!< CAN process is ongoing */
|
||||
HAL_CAN_STATE_BUSY_RX0 = 0x22U, /*!< CAN process is ongoing */
|
||||
HAL_CAN_STATE_BUSY_RX1 = 0x32U, /*!< CAN process is ongoing */
|
||||
HAL_CAN_STATE_BUSY_TX_RX0 = 0x42U, /*!< CAN process is ongoing */
|
||||
HAL_CAN_STATE_BUSY_TX_RX1 = 0x52U, /*!< CAN process is ongoing */
|
||||
HAL_CAN_STATE_BUSY_RX0_RX1 = 0x62U, /*!< CAN process is ongoing */
|
||||
HAL_CAN_STATE_BUSY_TX_RX0_RX1 = 0x72U, /*!< CAN process is ongoing */
|
||||
HAL_CAN_STATE_TIMEOUT = 0x03U, /*!< CAN in Timeout state */
|
||||
HAL_CAN_STATE_ERROR = 0x04U /*!< CAN error state */
|
||||
|
||||
}HAL_CAN_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief CAN init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Prescaler; /*!< Specifies the length of a time quantum.
|
||||
This parameter must be a number between Min_Data = 1 and Max_Data = 1024 */
|
||||
|
||||
uint32_t Mode; /*!< Specifies the CAN operating mode.
|
||||
This parameter can be a value of @ref CAN_operating_mode */
|
||||
|
||||
uint32_t SJW; /*!< Specifies the maximum number of time quanta
|
||||
the CAN hardware is allowed to lengthen or
|
||||
shorten a bit to perform resynchronization.
|
||||
This parameter can be a value of @ref CAN_synchronisation_jump_width */
|
||||
|
||||
uint32_t BS1; /*!< Specifies the number of time quanta in Bit Segment 1.
|
||||
This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */
|
||||
|
||||
uint32_t BS2; /*!< Specifies the number of time quanta in Bit Segment 2.
|
||||
This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */
|
||||
|
||||
uint32_t TTCM; /*!< Enable or disable the time triggered communication mode.
|
||||
This parameter can be set to ENABLE or DISABLE. */
|
||||
|
||||
uint32_t ABOM; /*!< Enable or disable the automatic bus-off management.
|
||||
This parameter can be set to ENABLE or DISABLE */
|
||||
|
||||
uint32_t AWUM; /*!< Enable or disable the automatic wake-up mode.
|
||||
This parameter can be set to ENABLE or DISABLE */
|
||||
|
||||
uint32_t NART; /*!< Enable or disable the non-automatic retransmission mode.
|
||||
This parameter can be set to ENABLE or DISABLE */
|
||||
|
||||
uint32_t RFLM; /*!< Enable or disable the receive FIFO Locked mode.
|
||||
This parameter can be set to ENABLE or DISABLE */
|
||||
|
||||
uint32_t TXFP; /*!< Enable or disable the transmit FIFO priority.
|
||||
This parameter can be set to ENABLE or DISABLE */
|
||||
}CAN_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief CAN filter configuration structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit
|
||||
configuration, first one for a 16-bit configuration).
|
||||
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
|
||||
|
||||
uint32_t FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit
|
||||
configuration, second one for a 16-bit configuration).
|
||||
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
|
||||
|
||||
uint32_t FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number,
|
||||
according to the mode (MSBs for a 32-bit configuration,
|
||||
first one for a 16-bit configuration).
|
||||
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
|
||||
|
||||
uint32_t FilterMaskIdLow; /*!< Specifies the filter mask number or identification number,
|
||||
according to the mode (LSBs for a 32-bit configuration,
|
||||
second one for a 16-bit configuration).
|
||||
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
|
||||
|
||||
uint32_t FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter.
|
||||
This parameter can be a value of @ref CAN_filter_FIFO */
|
||||
|
||||
uint32_t FilterNumber; /*!< Specifies the filter which will be initialized.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 27 */
|
||||
|
||||
uint32_t FilterMode; /*!< Specifies the filter mode to be initialized.
|
||||
This parameter can be a value of @ref CAN_filter_mode */
|
||||
|
||||
uint32_t FilterScale; /*!< Specifies the filter scale.
|
||||
This parameter can be a value of @ref CAN_filter_scale */
|
||||
|
||||
uint32_t FilterActivation; /*!< Enable or disable the filter.
|
||||
This parameter can be set to ENABLE or DISABLE. */
|
||||
|
||||
uint32_t BankNumber; /*!< Select the start slave bank filter.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 28 */
|
||||
|
||||
}CAN_FilterConfTypeDef;
|
||||
|
||||
/**
|
||||
* @brief CAN Tx message structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t StdId; /*!< Specifies the standard identifier.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */
|
||||
|
||||
uint32_t ExtId; /*!< Specifies the extended identifier.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */
|
||||
|
||||
uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted.
|
||||
This parameter can be a value of @ref CAN_Identifier_Type */
|
||||
|
||||
uint32_t RTR; /*!< Specifies the type of frame for the message that will be transmitted.
|
||||
This parameter can be a value of @ref CAN_remote_transmission_request */
|
||||
|
||||
uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 8 */
|
||||
|
||||
uint8_t Data[8]; /*!< Contains the data to be transmitted.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
|
||||
|
||||
}CanTxMsgTypeDef;
|
||||
|
||||
/**
|
||||
* @brief CAN Rx message structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t StdId; /*!< Specifies the standard identifier.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */
|
||||
|
||||
uint32_t ExtId; /*!< Specifies the extended identifier.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */
|
||||
|
||||
uint32_t IDE; /*!< Specifies the type of identifier for the message that will be received.
|
||||
This parameter can be a value of @ref CAN_Identifier_Type */
|
||||
|
||||
uint32_t RTR; /*!< Specifies the type of frame for the received message.
|
||||
This parameter can be a value of @ref CAN_remote_transmission_request */
|
||||
|
||||
uint32_t DLC; /*!< Specifies the length of the frame that will be received.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 8 */
|
||||
|
||||
uint8_t Data[8]; /*!< Contains the data to be received.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
|
||||
|
||||
uint32_t FMI; /*!< Specifies the index of the filter the message stored in the mailbox passes through.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
|
||||
|
||||
uint32_t FIFONumber; /*!< Specifies the receive FIFO number.
|
||||
This parameter can be CAN_FIFO0 or CAN_FIFO1 */
|
||||
|
||||
}CanRxMsgTypeDef;
|
||||
|
||||
/**
|
||||
* @brief CAN handle Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
CAN_TypeDef *Instance; /*!< Register base address */
|
||||
|
||||
CAN_InitTypeDef Init; /*!< CAN required parameters */
|
||||
|
||||
CanTxMsgTypeDef* pTxMsg; /*!< Pointer to transmit structure */
|
||||
|
||||
CanRxMsgTypeDef* pRxMsg; /*!< Pointer to reception structure for RX FIFO0 msg */
|
||||
|
||||
CanRxMsgTypeDef* pRx1Msg; /*!< Pointer to reception structure for RX FIFO1 msg */
|
||||
|
||||
__IO HAL_CAN_StateTypeDef State; /*!< CAN communication state */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< CAN locking object */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< CAN Error code
|
||||
This parameter can be a value of @ref CAN_Error_Code */
|
||||
}CAN_HandleTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup CAN_Exported_Constants CAN Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_Error_Code CAN Error Code
|
||||
* @{
|
||||
*/
|
||||
#define HAL_CAN_ERROR_NONE 0x00000000U /*!< No error */
|
||||
#define HAL_CAN_ERROR_EWG 0x00000001U /*!< EWG error */
|
||||
#define HAL_CAN_ERROR_EPV 0x00000002U /*!< EPV error */
|
||||
#define HAL_CAN_ERROR_BOF 0x00000004U /*!< BOF error */
|
||||
#define HAL_CAN_ERROR_STF 0x00000008U /*!< Stuff error */
|
||||
#define HAL_CAN_ERROR_FOR 0x00000010U /*!< Form error */
|
||||
#define HAL_CAN_ERROR_ACK 0x00000020U /*!< Acknowledgment error */
|
||||
#define HAL_CAN_ERROR_BR 0x00000040U /*!< Bit recessive */
|
||||
#define HAL_CAN_ERROR_BD 0x00000080U /*!< LEC dominant */
|
||||
#define HAL_CAN_ERROR_CRC 0x00000100U /*!< LEC transfer error */
|
||||
#define HAL_CAN_ERROR_FOV0 0x00000200U /*!< FIFO0 overrun error */
|
||||
#define HAL_CAN_ERROR_FOV1 0x00000400U /*!< FIFO1 overrun error */
|
||||
#define HAL_CAN_ERROR_TXFAIL 0x00000800U /*!< Transmit failure */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_InitStatus CAN InitStatus
|
||||
* @{
|
||||
*/
|
||||
#define CAN_INITSTATUS_FAILED ((uint8_t)0x00U) /*!< CAN initialization failed */
|
||||
#define CAN_INITSTATUS_SUCCESS ((uint8_t)0x01U) /*!< CAN initialization OK */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_operating_mode CAN Operating Mode
|
||||
* @{
|
||||
*/
|
||||
#define CAN_MODE_NORMAL ((uint32_t)0x00000000U) /*!< Normal mode */
|
||||
#define CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM) /*!< Loopback mode */
|
||||
#define CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM) /*!< Silent mode */
|
||||
#define CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM)) /*!< Loopback combined with silent mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_synchronisation_jump_width CAN Synchronisation Jump Width
|
||||
* @{
|
||||
*/
|
||||
#define CAN_SJW_1TQ ((uint32_t)0x00000000U) /*!< 1 time quantum */
|
||||
#define CAN_SJW_2TQ ((uint32_t)CAN_BTR_SJW_0) /*!< 2 time quantum */
|
||||
#define CAN_SJW_3TQ ((uint32_t)CAN_BTR_SJW_1) /*!< 3 time quantum */
|
||||
#define CAN_SJW_4TQ ((uint32_t)CAN_BTR_SJW) /*!< 4 time quantum */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_time_quantum_in_bit_segment_1 CAN Time Quantum in bit segment 1
|
||||
* @{
|
||||
*/
|
||||
#define CAN_BS1_1TQ ((uint32_t)0x00000000U) /*!< 1 time quantum */
|
||||
#define CAN_BS1_2TQ ((uint32_t)CAN_BTR_TS1_0) /*!< 2 time quantum */
|
||||
#define CAN_BS1_3TQ ((uint32_t)CAN_BTR_TS1_1) /*!< 3 time quantum */
|
||||
#define CAN_BS1_4TQ ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 4 time quantum */
|
||||
#define CAN_BS1_5TQ ((uint32_t)CAN_BTR_TS1_2) /*!< 5 time quantum */
|
||||
#define CAN_BS1_6TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 6 time quantum */
|
||||
#define CAN_BS1_7TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 7 time quantum */
|
||||
#define CAN_BS1_8TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 8 time quantum */
|
||||
#define CAN_BS1_9TQ ((uint32_t)CAN_BTR_TS1_3) /*!< 9 time quantum */
|
||||
#define CAN_BS1_10TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_0)) /*!< 10 time quantum */
|
||||
#define CAN_BS1_11TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1)) /*!< 11 time quantum */
|
||||
#define CAN_BS1_12TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 12 time quantum */
|
||||
#define CAN_BS1_13TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2)) /*!< 13 time quantum */
|
||||
#define CAN_BS1_14TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 14 time quantum */
|
||||
#define CAN_BS1_15TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 15 time quantum */
|
||||
#define CAN_BS1_16TQ ((uint32_t)CAN_BTR_TS1) /*!< 16 time quantum */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in bit segment 2
|
||||
* @{
|
||||
*/
|
||||
#define CAN_BS2_1TQ ((uint32_t)0x00000000U) /*!< 1 time quantum */
|
||||
#define CAN_BS2_2TQ ((uint32_t)CAN_BTR_TS2_0) /*!< 2 time quantum */
|
||||
#define CAN_BS2_3TQ ((uint32_t)CAN_BTR_TS2_1) /*!< 3 time quantum */
|
||||
#define CAN_BS2_4TQ ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0)) /*!< 4 time quantum */
|
||||
#define CAN_BS2_5TQ ((uint32_t)CAN_BTR_TS2_2) /*!< 5 time quantum */
|
||||
#define CAN_BS2_6TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_0)) /*!< 6 time quantum */
|
||||
#define CAN_BS2_7TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_1)) /*!< 7 time quantum */
|
||||
#define CAN_BS2_8TQ ((uint32_t)CAN_BTR_TS2) /*!< 8 time quantum */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_filter_mode CAN Filter Mode
|
||||
* @{
|
||||
*/
|
||||
#define CAN_FILTERMODE_IDMASK ((uint8_t)0x00U) /*!< Identifier mask mode */
|
||||
#define CAN_FILTERMODE_IDLIST ((uint8_t)0x01U) /*!< Identifier list mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_filter_scale CAN Filter Scale
|
||||
* @{
|
||||
*/
|
||||
#define CAN_FILTERSCALE_16BIT ((uint8_t)0x00U) /*!< Two 16-bit filters */
|
||||
#define CAN_FILTERSCALE_32BIT ((uint8_t)0x01U) /*!< One 32-bit filter */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_filter_FIFO CAN Filter FIFO
|
||||
* @{
|
||||
*/
|
||||
#define CAN_FILTER_FIFO0 ((uint8_t)0x00U) /*!< Filter FIFO 0 assignment for filter x */
|
||||
#define CAN_FILTER_FIFO1 ((uint8_t)0x01U) /*!< Filter FIFO 1 assignment for filter x */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_Identifier_Type CAN Identifier Type
|
||||
* @{
|
||||
*/
|
||||
#define CAN_ID_STD ((uint32_t)0x00000000U) /*!< Standard Id */
|
||||
#define CAN_ID_EXT ((uint32_t)0x00000004U) /*!< Extended Id */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_remote_transmission_request CAN Remote Transmission Request
|
||||
* @{
|
||||
*/
|
||||
#define CAN_RTR_DATA ((uint32_t)0x00000000U) /*!< Data frame */
|
||||
#define CAN_RTR_REMOTE ((uint32_t)0x00000002U) /*!< Remote frame */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_receive_FIFO_number_constants CAN Receive FIFO Number Constants
|
||||
* @{
|
||||
*/
|
||||
#define CAN_FIFO0 ((uint8_t)0x00U) /*!< CAN FIFO 0 used to receive */
|
||||
#define CAN_FIFO1 ((uint8_t)0x01U) /*!< CAN FIFO 1 used to receive */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_flags CAN Flags
|
||||
* @{
|
||||
*/
|
||||
/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus()
|
||||
and CAN_ClearFlag() functions. */
|
||||
/* If the flag is 0x1XXXXXXX, it means that it can only be used with
|
||||
CAN_GetFlagStatus() function. */
|
||||
|
||||
/* Transmit Flags */
|
||||
#define CAN_FLAG_RQCP0 ((uint32_t)0x00000500U) /*!< Request MailBox0 flag */
|
||||
#define CAN_FLAG_RQCP1 ((uint32_t)0x00000508U) /*!< Request MailBox1 flag */
|
||||
#define CAN_FLAG_RQCP2 ((uint32_t)0x00000510U) /*!< Request MailBox2 flag */
|
||||
#define CAN_FLAG_TXOK0 ((uint32_t)0x00000501U) /*!< Transmission OK MailBox0 flag */
|
||||
#define CAN_FLAG_TXOK1 ((uint32_t)0x00000509U) /*!< Transmission OK MailBox1 flag */
|
||||
#define CAN_FLAG_TXOK2 ((uint32_t)0x00000511U) /*!< Transmission OK MailBox2 flag */
|
||||
#define CAN_FLAG_TME0 ((uint32_t)0x0000051AU) /*!< Transmit mailbox 0 empty flag */
|
||||
#define CAN_FLAG_TME1 ((uint32_t)0x0000051BU) /*!< Transmit mailbox 0 empty flag */
|
||||
#define CAN_FLAG_TME2 ((uint32_t)0x0000051CU) /*!< Transmit mailbox 0 empty flag */
|
||||
|
||||
/* Receive Flags */
|
||||
#define CAN_FLAG_FF0 ((uint32_t)0x00000203U) /*!< FIFO 0 Full flag */
|
||||
#define CAN_FLAG_FOV0 ((uint32_t)0x00000204U) /*!< FIFO 0 Overrun flag */
|
||||
|
||||
#define CAN_FLAG_FF1 ((uint32_t)0x00000403U) /*!< FIFO 1 Full flag */
|
||||
#define CAN_FLAG_FOV1 ((uint32_t)0x00000404U) /*!< FIFO 1 Overrun flag */
|
||||
|
||||
/* Operating Mode Flags */
|
||||
#define CAN_FLAG_INAK ((uint32_t)0x00000100U) /*!< Initialization acknowledge flag */
|
||||
#define CAN_FLAG_SLAK ((uint32_t)0x00000101U) /*!< Sleep acknowledge flag */
|
||||
#define CAN_FLAG_ERRI ((uint32_t)0x00000102U) /*!< Error flag */
|
||||
#define CAN_FLAG_WKU ((uint32_t)0x00000103U) /*!< Wake up flag */
|
||||
#define CAN_FLAG_SLAKI ((uint32_t)0x00000104U) /*!< Sleep acknowledge flag */
|
||||
|
||||
/* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible.
|
||||
In this case the SLAK bit can be polled.*/
|
||||
|
||||
/* Error Flags */
|
||||
#define CAN_FLAG_EWG ((uint32_t)0x00000300U) /*!< Error warning flag */
|
||||
#define CAN_FLAG_EPV ((uint32_t)0x00000301U) /*!< Error passive flag */
|
||||
#define CAN_FLAG_BOF ((uint32_t)0x00000302U) /*!< Bus-Off flag */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_Interrupts CAN Interrupts
|
||||
* @{
|
||||
*/
|
||||
#define CAN_IT_TME ((uint32_t)CAN_IER_TMEIE) /*!< Transmit mailbox empty interrupt */
|
||||
|
||||
/* Receive Interrupts */
|
||||
#define CAN_IT_FMP0 ((uint32_t)CAN_IER_FMPIE0) /*!< FIFO 0 message pending interrupt */
|
||||
#define CAN_IT_FF0 ((uint32_t)CAN_IER_FFIE0) /*!< FIFO 0 full interrupt */
|
||||
#define CAN_IT_FOV0 ((uint32_t)CAN_IER_FOVIE0) /*!< FIFO 0 overrun interrupt */
|
||||
#define CAN_IT_FMP1 ((uint32_t)CAN_IER_FMPIE1) /*!< FIFO 1 message pending interrupt */
|
||||
#define CAN_IT_FF1 ((uint32_t)CAN_IER_FFIE1) /*!< FIFO 1 full interrupt */
|
||||
#define CAN_IT_FOV1 ((uint32_t)CAN_IER_FOVIE1) /*!< FIFO 1 overrun interrupt */
|
||||
|
||||
/* Operating Mode Interrupts */
|
||||
#define CAN_IT_WKU ((uint32_t)CAN_IER_WKUIE) /*!< Wake-up interrupt */
|
||||
#define CAN_IT_SLK ((uint32_t)CAN_IER_SLKIE) /*!< Sleep acknowledge interrupt */
|
||||
|
||||
/* Error Interrupts */
|
||||
#define CAN_IT_EWG ((uint32_t)CAN_IER_EWGIE) /*!< Error warning interrupt */
|
||||
#define CAN_IT_EPV ((uint32_t)CAN_IER_EPVIE) /*!< Error passive interrupt */
|
||||
#define CAN_IT_BOF ((uint32_t)CAN_IER_BOFIE) /*!< Bus-off interrupt */
|
||||
#define CAN_IT_LEC ((uint32_t)CAN_IER_LECIE) /*!< Last error code interrupt */
|
||||
#define CAN_IT_ERR ((uint32_t)CAN_IER_ERRIE) /*!< Error Interrupt */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_Mailboxes_Definition CAN Mailboxes Definition
|
||||
* @{
|
||||
*/
|
||||
#define CAN_TXMAILBOX_0 ((uint8_t)0x00U)
|
||||
#define CAN_TXMAILBOX_1 ((uint8_t)0x01U)
|
||||
#define CAN_TXMAILBOX_2 ((uint8_t)0x02U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup CAN_Exported_Macros CAN Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset CAN handle state
|
||||
* @param __HANDLE__: specifies the CAN Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET)
|
||||
|
||||
/**
|
||||
* @brief Enable the specified CAN interrupts.
|
||||
* @param __HANDLE__: CAN handle
|
||||
* @param __INTERRUPT__: CAN Interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Disable the specified CAN interrupts.
|
||||
* @param __HANDLE__: CAN handle
|
||||
* @param __INTERRUPT__: CAN Interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Return the number of pending received messages.
|
||||
* @param __HANDLE__: CAN handle
|
||||
* @param __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
|
||||
* @retval The number of pending message.
|
||||
*/
|
||||
#define __HAL_CAN_MSG_PENDING(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
|
||||
((uint8_t)((__HANDLE__)->Instance->RF0R&(uint32_t)0x03)) : ((uint8_t)((__HANDLE__)->Instance->RF1R&(uint32_t)0x03)))
|
||||
|
||||
/** @brief Check whether the specified CAN flag is set or not.
|
||||
* @param __HANDLE__: CAN Handle
|
||||
* @param __FLAG__: specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg CAN_TSR_RQCP0: Request MailBox0 Flag
|
||||
* @arg CAN_TSR_RQCP1: Request MailBox1 Flag
|
||||
* @arg CAN_TSR_RQCP2: Request MailBox2 Flag
|
||||
* @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag
|
||||
* @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag
|
||||
* @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag
|
||||
* @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag
|
||||
* @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag
|
||||
* @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag
|
||||
* @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
|
||||
* @arg CAN_FLAG_FF0: FIFO 0 Full Flag
|
||||
* @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
|
||||
* @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
|
||||
* @arg CAN_FLAG_FF1: FIFO 1 Full Flag
|
||||
* @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
|
||||
* @arg CAN_FLAG_WKU: Wake up Flag
|
||||
* @arg CAN_FLAG_SLAK: Sleep acknowledge Flag
|
||||
* @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag
|
||||
* @arg CAN_FLAG_EWG: Error Warning Flag
|
||||
* @arg CAN_FLAG_EPV: Error Passive Flag
|
||||
* @arg CAN_FLAG_BOF: Bus-Off Flag
|
||||
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__) \
|
||||
((((__FLAG__) >> 8) == 5)? ((((__HANDLE__)->Instance->TSR) & (1 << ((__FLAG__) & CAN_FLAG_MASK))) == (1 << ((__FLAG__) & CAN_FLAG_MASK))): \
|
||||
(((__FLAG__) >> 8) == 2)? ((((__HANDLE__)->Instance->RF0R) & (1 << ((__FLAG__) & CAN_FLAG_MASK))) == (1 << ((__FLAG__) & CAN_FLAG_MASK))): \
|
||||
(((__FLAG__) >> 8) == 4)? ((((__HANDLE__)->Instance->RF1R) & (1 << ((__FLAG__) & CAN_FLAG_MASK))) == (1 << ((__FLAG__) & CAN_FLAG_MASK))): \
|
||||
(((__FLAG__) >> 8) == 1)? ((((__HANDLE__)->Instance->MSR) & (1 << ((__FLAG__) & CAN_FLAG_MASK))) == (1 << ((__FLAG__) & CAN_FLAG_MASK))): \
|
||||
((((__HANDLE__)->Instance->ESR) & (1 << ((__FLAG__) & CAN_FLAG_MASK))) == (1 << ((__FLAG__) & CAN_FLAG_MASK))))
|
||||
|
||||
/** @brief Clear the specified CAN pending flag.
|
||||
* @param __HANDLE__: CAN Handle.
|
||||
* @param __FLAG__: specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg CAN_TSR_RQCP0: Request MailBox0 Flag
|
||||
* @arg CAN_TSR_RQCP1: Request MailBox1 Flag
|
||||
* @arg CAN_TSR_RQCP2: Request MailBox2 Flag
|
||||
* @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag
|
||||
* @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag
|
||||
* @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag
|
||||
* @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag
|
||||
* @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag
|
||||
* @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag
|
||||
* @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
|
||||
* @arg CAN_FLAG_FF0: FIFO 0 Full Flag
|
||||
* @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
|
||||
* @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
|
||||
* @arg CAN_FLAG_FF1: FIFO 1 Full Flag
|
||||
* @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
|
||||
* @arg CAN_FLAG_WKU: Wake up Flag
|
||||
* @arg CAN_FLAG_SLAK: Sleep acknowledge Flag
|
||||
* @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag
|
||||
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \
|
||||
((((__FLAG__) >> 8) == 5)? (((__HANDLE__)->Instance->TSR) = ((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK))): \
|
||||
(((__FLAG__) >> 8) == 2)? (((__HANDLE__)->Instance->RF0R) = ((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK))): \
|
||||
(((__FLAG__) >> 8) == 4)? (((__HANDLE__)->Instance->RF1R) = ((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK))): \
|
||||
(((__HANDLE__)->Instance->MSR) = ((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK))))
|
||||
|
||||
/** @brief Check if the specified CAN interrupt source is enabled or disabled.
|
||||
* @param __HANDLE__: CAN Handle
|
||||
* @param __INTERRUPT__: specifies the CAN interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg CAN_IT_TME: Transmit mailbox empty interrupt enable
|
||||
* @arg CAN_IT_FMP0: FIFO0 message pending interrupt enable
|
||||
* @arg CAN_IT_FMP1: FIFO1 message pending interrupt enable
|
||||
* @retval The new state of __IT__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
||||
|
||||
/**
|
||||
* @brief Check the transmission status of a CAN Frame.
|
||||
* @param __HANDLE__: CAN Handle
|
||||
* @param __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission.
|
||||
* @retval The new status of transmission (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_CAN_TRANSMIT_STATUS(__HANDLE__, __TRANSMITMAILBOX__)\
|
||||
(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) == (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) :\
|
||||
((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) == (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) :\
|
||||
((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)) == (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)))
|
||||
|
||||
/**
|
||||
* @brief Release the specified receive FIFO.
|
||||
* @param __HANDLE__: CAN handle
|
||||
* @param __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CAN_FIFO_RELEASE(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
|
||||
((__HANDLE__)->Instance->RF0R = CAN_RF0R_RFOM0) : ((__HANDLE__)->Instance->RF1R = CAN_RF1R_RFOM1))
|
||||
|
||||
/**
|
||||
* @brief Cancel a transmit request.
|
||||
* @param __HANDLE__: CAN Handle
|
||||
* @param __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CAN_CANCEL_TRANSMIT(__HANDLE__, __TRANSMITMAILBOX__)\
|
||||
(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ0) :\
|
||||
((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ1) :\
|
||||
((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ2))
|
||||
|
||||
/**
|
||||
* @brief Enable or disable the DBG Freeze for CAN.
|
||||
* @param __HANDLE__: CAN Handle
|
||||
* @param __NEWSTATE__: new state of the CAN peripheral.
|
||||
* This parameter can be: ENABLE (CAN reception/transmission is frozen
|
||||
* during debug. Reception FIFOs can still be accessed/controlled normally)
|
||||
* or DISABLE (CAN is working during debug).
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CAN_DBG_FREEZE(__HANDLE__, __NEWSTATE__) (((__NEWSTATE__) == ENABLE)? \
|
||||
((__HANDLE__)->Instance->MCR |= CAN_MCR_DBF) : ((__HANDLE__)->Instance->MCR &= ~CAN_MCR_DBF))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup CAN_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CAN_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Initialization/de-initialization functions ***********************************/
|
||||
HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan);
|
||||
HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig);
|
||||
HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan);
|
||||
void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan);
|
||||
void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CAN_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* I/O operation functions ******************************************************/
|
||||
HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef *hcan, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef *hcan);
|
||||
HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef *hcan, uint8_t FIFONumber, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef *hcan, uint8_t FIFONumber);
|
||||
HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef *hcan);
|
||||
HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan);
|
||||
void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan);
|
||||
void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan);
|
||||
void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan);
|
||||
void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CAN_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State functions ***************************************************/
|
||||
uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan);
|
||||
HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/** @defgroup CAN_Private_Types CAN Private Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/** @defgroup CAN_Private_Variables CAN Private Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup CAN_Private_Constants CAN Private Constants
|
||||
* @{
|
||||
*/
|
||||
#define CAN_TXSTATUS_NOMAILBOX ((uint8_t)0x04U) /*!< CAN cell did not provide CAN_TxStatus_NoMailBox */
|
||||
#define CAN_FLAG_MASK ((uint32_t)0x000000FFU)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup CAN_Private_Macros CAN Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \
|
||||
((MODE) == CAN_MODE_LOOPBACK)|| \
|
||||
((MODE) == CAN_MODE_SILENT) || \
|
||||
((MODE) == CAN_MODE_SILENT_LOOPBACK))
|
||||
#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ)|| \
|
||||
((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ))
|
||||
#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16TQ)
|
||||
#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8TQ)
|
||||
#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024))
|
||||
#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27)
|
||||
#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \
|
||||
((MODE) == CAN_FILTERMODE_IDLIST))
|
||||
#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \
|
||||
((SCALE) == CAN_FILTERSCALE_32BIT))
|
||||
#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \
|
||||
((FIFO) == CAN_FILTER_FIFO1))
|
||||
#define IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28)
|
||||
|
||||
#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))
|
||||
#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF))
|
||||
#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF))
|
||||
#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08))
|
||||
|
||||
#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || \
|
||||
((IDTYPE) == CAN_ID_EXT))
|
||||
#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE))
|
||||
#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup CAN_Private_Functions CAN Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F7xx_CAN_H */
|
||||
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,751 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_hal_cec.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.2
|
||||
* @date 14-April-2017
|
||||
* @brief Header file of CEC HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F7xx_HAL_CEC_H
|
||||
#define __STM32F7xx_HAL_CEC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx_hal_def.h"
|
||||
|
||||
#if defined (CEC)
|
||||
|
||||
/** @addtogroup STM32F7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CEC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup CEC_Exported_Types CEC Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief CEC Init Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t SignalFreeTime; /*!< Set SFT field, specifies the Signal Free Time.
|
||||
It can be one of @ref CEC_Signal_Free_Time
|
||||
and belongs to the set {0,...,7} where
|
||||
0x0 is the default configuration
|
||||
else means 0.5 + (SignalFreeTime - 1) nominal data bit periods */
|
||||
|
||||
uint32_t Tolerance; /*!< Set RXTOL bit, specifies the tolerance accepted on the received waveforms,
|
||||
it can be a value of @ref CEC_Tolerance : it is either CEC_STANDARD_TOLERANCE
|
||||
or CEC_EXTENDED_TOLERANCE */
|
||||
|
||||
uint32_t BRERxStop; /*!< Set BRESTP bit @ref CEC_BRERxStop : specifies whether or not a Bit Rising Error stops the reception.
|
||||
CEC_NO_RX_STOP_ON_BRE: reception is not stopped.
|
||||
CEC_RX_STOP_ON_BRE: reception is stopped. */
|
||||
|
||||
uint32_t BREErrorBitGen; /*!< Set BREGEN bit @ref CEC_BREErrorBitGen : specifies whether or not an Error-Bit is generated on the
|
||||
CEC line upon Bit Rising Error detection.
|
||||
CEC_BRE_ERRORBIT_NO_GENERATION: no error-bit generation.
|
||||
CEC_BRE_ERRORBIT_GENERATION: error-bit generation if BRESTP is set. */
|
||||
|
||||
uint32_t LBPEErrorBitGen; /*!< Set LBPEGEN bit @ref CEC_LBPEErrorBitGen : specifies whether or not an Error-Bit is generated on the
|
||||
CEC line upon Long Bit Period Error detection.
|
||||
CEC_LBPE_ERRORBIT_NO_GENERATION: no error-bit generation.
|
||||
CEC_LBPE_ERRORBIT_GENERATION: error-bit generation. */
|
||||
|
||||
uint32_t BroadcastMsgNoErrorBitGen; /*!< Set BRDNOGEN bit @ref CEC_BroadCastMsgErrorBitGen : allows to avoid an Error-Bit generation on the CEC line
|
||||
upon an error detected on a broadcast message.
|
||||
|
||||
It supersedes BREGEN and LBPEGEN bits for a broadcast message error handling. It can take two values:
|
||||
|
||||
1) CEC_BROADCASTERROR_ERRORBIT_GENERATION.
|
||||
a) BRE detection: error-bit generation on the CEC line if BRESTP=CEC_RX_STOP_ON_BRE
|
||||
and BREGEN=CEC_BRE_ERRORBIT_NO_GENERATION.
|
||||
b) LBPE detection: error-bit generation on the CEC line
|
||||
if LBPGEN=CEC_LBPE_ERRORBIT_NO_GENERATION.
|
||||
|
||||
2) CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION.
|
||||
no error-bit generation in case neither a) nor b) are satisfied. Additionally,
|
||||
there is no error-bit generation in case of Short Bit Period Error detection in
|
||||
a broadcast message while LSTN bit is set. */
|
||||
|
||||
uint32_t SignalFreeTimeOption; /*!< Set SFTOP bit @ref CEC_SFT_Option : specifies when SFT timer starts.
|
||||
CEC_SFT_START_ON_TXSOM SFT: timer starts when TXSOM is set by software.
|
||||
CEC_SFT_START_ON_TX_RX_END: SFT timer starts automatically at the end of message transmission/reception. */
|
||||
|
||||
uint32_t ListenMode; /*!< Set LSTN bit @ref CEC_Listening_Mode : specifies device listening mode. It can take two values:
|
||||
|
||||
CEC_REDUCED_LISTENING_MODE: CEC peripheral receives only message addressed to its
|
||||
own address (OAR). Messages addressed to different destination are ignored.
|
||||
Broadcast messages are always received.
|
||||
|
||||
CEC_FULL_LISTENING_MODE: CEC peripheral receives messages addressed to its own
|
||||
address (OAR) with positive acknowledge. Messages addressed to different destination
|
||||
are received, but without interfering with the CEC bus: no acknowledge sent. */
|
||||
|
||||
uint16_t OwnAddress; /*!< Own addresses configuration
|
||||
This parameter can be a value of @ref CEC_OWN_ADDRESS */
|
||||
|
||||
uint8_t *RxBuffer; /*!< CEC Rx buffer pointeur */
|
||||
|
||||
|
||||
}CEC_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL CEC State structures definition
|
||||
* @note HAL CEC State value is a combination of 2 different substates: gState and RxState.
|
||||
* - gState contains CEC state information related to global Handle management
|
||||
* and also information related to Tx operations.
|
||||
* gState value coding follow below described bitmap :
|
||||
* b7 (not used)
|
||||
* x : Should be set to 0
|
||||
* b6 Error information
|
||||
* 0 : No Error
|
||||
* 1 : Error
|
||||
* b5 IP initilisation status
|
||||
* 0 : Reset (IP not initialized)
|
||||
* 1 : Init done (IP initialized. HAL CEC Init function already called)
|
||||
* b4-b3 (not used)
|
||||
* xx : Should be set to 00
|
||||
* b2 Intrinsic process state
|
||||
* 0 : Ready
|
||||
* 1 : Busy (IP busy with some configuration or internal operations)
|
||||
* b1 (not used)
|
||||
* x : Should be set to 0
|
||||
* b0 Tx state
|
||||
* 0 : Ready (no Tx operation ongoing)
|
||||
* 1 : Busy (Tx operation ongoing)
|
||||
* - RxState contains information related to Rx operations.
|
||||
* RxState value coding follow below described bitmap :
|
||||
* b7-b6 (not used)
|
||||
* xx : Should be set to 00
|
||||
* b5 IP initilisation status
|
||||
* 0 : Reset (IP not initialized)
|
||||
* 1 : Init done (IP initialized)
|
||||
* b4-b2 (not used)
|
||||
* xxx : Should be set to 000
|
||||
* b1 Rx state
|
||||
* 0 : Ready (no Rx operation ongoing)
|
||||
* 1 : Busy (Rx operation ongoing)
|
||||
* b0 (not used)
|
||||
* x : Should be set to 0.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_CEC_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized
|
||||
Value is allowed for gState and RxState */
|
||||
HAL_CEC_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use
|
||||
Value is allowed for gState and RxState */
|
||||
HAL_CEC_STATE_BUSY = 0x24U, /*!< an internal process is ongoing
|
||||
Value is allowed for gState only */
|
||||
HAL_CEC_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing
|
||||
Value is allowed for RxState only */
|
||||
HAL_CEC_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing
|
||||
Value is allowed for gState only */
|
||||
HAL_CEC_STATE_BUSY_RX_TX = 0x23U, /*!< an internal process is ongoing
|
||||
Value is allowed for gState only */
|
||||
HAL_CEC_STATE_ERROR = 0x60U /*!< Error Value is allowed for gState only */
|
||||
}HAL_CEC_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief CEC handle Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
CEC_TypeDef *Instance; /*!< CEC registers base address */
|
||||
|
||||
CEC_InitTypeDef Init; /*!< CEC communication parameters */
|
||||
|
||||
uint8_t *pTxBuffPtr; /*!< Pointer to CEC Tx transfer Buffer */
|
||||
|
||||
uint16_t TxXferCount; /*!< CEC Tx Transfer Counter */
|
||||
|
||||
uint16_t RxXferSize; /*!< CEC Rx Transfer size, 0: header received only */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< Locking object */
|
||||
|
||||
HAL_CEC_StateTypeDef gState; /*!< CEC state information related to global Handle management
|
||||
and also related to Tx operations.
|
||||
This parameter can be a value of @ref HAL_CEC_StateTypeDef */
|
||||
|
||||
HAL_CEC_StateTypeDef RxState; /*!< CEC state information related to Rx operations.
|
||||
This parameter can be a value of @ref HAL_CEC_StateTypeDef */
|
||||
|
||||
uint32_t ErrorCode; /*!< For errors handling purposes, copy of ISR register
|
||||
in case error is reported */
|
||||
}CEC_HandleTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup CEC_Exported_Constants CEC Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_Error_Code CEC Error Code
|
||||
* @{
|
||||
*/
|
||||
#define HAL_CEC_ERROR_NONE (uint32_t) 0x0000U /*!< no error */
|
||||
#define HAL_CEC_ERROR_RXOVR CEC_ISR_RXOVR /*!< CEC Rx-Overrun */
|
||||
#define HAL_CEC_ERROR_BRE CEC_ISR_BRE /*!< CEC Rx Bit Rising Error */
|
||||
#define HAL_CEC_ERROR_SBPE CEC_ISR_SBPE /*!< CEC Rx Short Bit period Error */
|
||||
#define HAL_CEC_ERROR_LBPE CEC_ISR_LBPE /*!< CEC Rx Long Bit period Error */
|
||||
#define HAL_CEC_ERROR_RXACKE CEC_ISR_RXACKE /*!< CEC Rx Missing Acknowledge */
|
||||
#define HAL_CEC_ERROR_ARBLST CEC_ISR_ARBLST /*!< CEC Arbitration Lost */
|
||||
#define HAL_CEC_ERROR_TXUDR CEC_ISR_TXUDR /*!< CEC Tx-Buffer Underrun */
|
||||
#define HAL_CEC_ERROR_TXERR CEC_ISR_TXERR /*!< CEC Tx-Error */
|
||||
#define HAL_CEC_ERROR_TXACKE CEC_ISR_TXACKE /*!< CEC Tx Missing Acknowledge */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_Signal_Free_Time CEC Signal Free Time setting parameter
|
||||
* @{
|
||||
*/
|
||||
#define CEC_DEFAULT_SFT ((uint32_t)0x00000000U)
|
||||
#define CEC_0_5_BITPERIOD_SFT ((uint32_t)0x00000001U)
|
||||
#define CEC_1_5_BITPERIOD_SFT ((uint32_t)0x00000002U)
|
||||
#define CEC_2_5_BITPERIOD_SFT ((uint32_t)0x00000003U)
|
||||
#define CEC_3_5_BITPERIOD_SFT ((uint32_t)0x00000004U)
|
||||
#define CEC_4_5_BITPERIOD_SFT ((uint32_t)0x00000005U)
|
||||
#define CEC_5_5_BITPERIOD_SFT ((uint32_t)0x00000006U)
|
||||
#define CEC_6_5_BITPERIOD_SFT ((uint32_t)0x00000007U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_Tolerance CEC Receiver Tolerance
|
||||
* @{
|
||||
*/
|
||||
#define CEC_STANDARD_TOLERANCE ((uint32_t)0x00000000U)
|
||||
#define CEC_EXTENDED_TOLERANCE ((uint32_t)CEC_CFGR_RXTOL)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_BRERxStop CEC Reception Stop on Error
|
||||
* @{
|
||||
*/
|
||||
#define CEC_NO_RX_STOP_ON_BRE ((uint32_t)0x00000000U)
|
||||
#define CEC_RX_STOP_ON_BRE ((uint32_t)CEC_CFGR_BRESTP)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_BREErrorBitGen CEC Error Bit Generation if Bit Rise Error reported
|
||||
* @{
|
||||
*/
|
||||
#define CEC_BRE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000U)
|
||||
#define CEC_BRE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BREGEN)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_LBPEErrorBitGen CEC Error Bit Generation if Long Bit Period Error reported
|
||||
* @{
|
||||
*/
|
||||
#define CEC_LBPE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000U)
|
||||
#define CEC_LBPE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_LBPEGEN)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_BroadCastMsgErrorBitGen CEC Error Bit Generation on Broadcast message
|
||||
* @{
|
||||
*/
|
||||
#define CEC_BROADCASTERROR_ERRORBIT_GENERATION ((uint32_t)0x00000000U)
|
||||
#define CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BRDNOGEN)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_SFT_Option CEC Signal Free Time start option
|
||||
* @{
|
||||
*/
|
||||
#define CEC_SFT_START_ON_TXSOM ((uint32_t)0x00000000U)
|
||||
#define CEC_SFT_START_ON_TX_RX_END ((uint32_t)CEC_CFGR_SFTOPT)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_Listening_Mode CEC Listening mode option
|
||||
* @{
|
||||
*/
|
||||
#define CEC_REDUCED_LISTENING_MODE ((uint32_t)0x00000000U)
|
||||
#define CEC_FULL_LISTENING_MODE ((uint32_t)CEC_CFGR_LSTN)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_OAR_Position CEC Device Own Address position in CEC CFGR register
|
||||
* @{
|
||||
*/
|
||||
#define CEC_CFGR_OAR_LSB_POS ((uint32_t) 16U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_Initiator_Position CEC Initiator logical address position in message header
|
||||
* @{
|
||||
*/
|
||||
#define CEC_INITIATOR_LSB_POS ((uint32_t) 4U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_OWN_ADDRESS CEC Own Address
|
||||
* @{
|
||||
*/
|
||||
#define CEC_OWN_ADDRESS_NONE ((uint16_t) 0x0000U) /* Reset value */
|
||||
#define CEC_OWN_ADDRESS_0 ((uint16_t) 0x0001U) /* Logical Address 0 */
|
||||
#define CEC_OWN_ADDRESS_1 ((uint16_t) 0x0002U) /* Logical Address 1 */
|
||||
#define CEC_OWN_ADDRESS_2 ((uint16_t) 0x0004U) /* Logical Address 2 */
|
||||
#define CEC_OWN_ADDRESS_3 ((uint16_t) 0x0008U) /* Logical Address 3 */
|
||||
#define CEC_OWN_ADDRESS_4 ((uint16_t) 0x0010U) /* Logical Address 4 */
|
||||
#define CEC_OWN_ADDRESS_5 ((uint16_t) 0x0020U) /* Logical Address 5 */
|
||||
#define CEC_OWN_ADDRESS_6 ((uint16_t) 0x0040U) /* Logical Address 6 */
|
||||
#define CEC_OWN_ADDRESS_7 ((uint16_t) 0x0080U) /* Logical Address 7 */
|
||||
#define CEC_OWN_ADDRESS_8 ((uint16_t) 0x0100U) /* Logical Address 9 */
|
||||
#define CEC_OWN_ADDRESS_9 ((uint16_t) 0x0200U) /* Logical Address 10 */
|
||||
#define CEC_OWN_ADDRESS_10 ((uint16_t) 0x0400U) /* Logical Address 11 */
|
||||
#define CEC_OWN_ADDRESS_11 ((uint16_t) 0x0800U) /* Logical Address 12 */
|
||||
#define CEC_OWN_ADDRESS_12 ((uint16_t) 0x1000U) /* Logical Address 13 */
|
||||
#define CEC_OWN_ADDRESS_13 ((uint16_t) 0x2000U) /* Logical Address 14 */
|
||||
#define CEC_OWN_ADDRESS_14 ((uint16_t) 0x4000U) /* Logical Address 15 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_Interrupts_Definitions CEC Interrupts definition
|
||||
* @{
|
||||
*/
|
||||
#define CEC_IT_TXACKE CEC_IER_TXACKEIE
|
||||
#define CEC_IT_TXERR CEC_IER_TXERRIE
|
||||
#define CEC_IT_TXUDR CEC_IER_TXUDRIE
|
||||
#define CEC_IT_TXEND CEC_IER_TXENDIE
|
||||
#define CEC_IT_TXBR CEC_IER_TXBRIE
|
||||
#define CEC_IT_ARBLST CEC_IER_ARBLSTIE
|
||||
#define CEC_IT_RXACKE CEC_IER_RXACKEIE
|
||||
#define CEC_IT_LBPE CEC_IER_LBPEIE
|
||||
#define CEC_IT_SBPE CEC_IER_SBPEIE
|
||||
#define CEC_IT_BRE CEC_IER_BREIE
|
||||
#define CEC_IT_RXOVR CEC_IER_RXOVRIE
|
||||
#define CEC_IT_RXEND CEC_IER_RXENDIE
|
||||
#define CEC_IT_RXBR CEC_IER_RXBRIE
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_Flags_Definitions CEC Flags definition
|
||||
* @{
|
||||
*/
|
||||
#define CEC_FLAG_TXACKE CEC_ISR_TXACKE
|
||||
#define CEC_FLAG_TXERR CEC_ISR_TXERR
|
||||
#define CEC_FLAG_TXUDR CEC_ISR_TXUDR
|
||||
#define CEC_FLAG_TXEND CEC_ISR_TXEND
|
||||
#define CEC_FLAG_TXBR CEC_ISR_TXBR
|
||||
#define CEC_FLAG_ARBLST CEC_ISR_ARBLST
|
||||
#define CEC_FLAG_RXACKE CEC_ISR_RXACKE
|
||||
#define CEC_FLAG_LBPE CEC_ISR_LBPE
|
||||
#define CEC_FLAG_SBPE CEC_ISR_SBPE
|
||||
#define CEC_FLAG_BRE CEC_ISR_BRE
|
||||
#define CEC_FLAG_RXOVR CEC_ISR_RXOVR
|
||||
#define CEC_FLAG_RXEND CEC_ISR_RXEND
|
||||
#define CEC_FLAG_RXBR CEC_ISR_RXBR
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_ALL_ERROR CEC all RX or TX errors flags
|
||||
* @{
|
||||
*/
|
||||
#define CEC_ISR_ALL_ERROR ((uint32_t)CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE|\
|
||||
CEC_ISR_ARBLST|CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_IER_ALL_RX CEC all RX errors interrupts enabling flag
|
||||
* @{
|
||||
*/
|
||||
#define CEC_IER_RX_ALL_ERR ((uint32_t)CEC_IER_RXACKEIE|CEC_IER_LBPEIE|CEC_IER_SBPEIE|CEC_IER_BREIE|CEC_IER_RXOVRIE)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_IER_ALL_TX CEC all TX errors interrupts enabling flag
|
||||
* @{
|
||||
*/
|
||||
#define CEC_IER_TX_ALL_ERR ((uint32_t)CEC_IER_TXACKEIE|CEC_IER_TXERRIE|CEC_IER_TXUDRIE|CEC_IER_ARBLSTIE)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup CEC_Exported_Macros CEC Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset CEC handle gstate & RxState
|
||||
* @param __HANDLE__: CEC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
||||
(__HANDLE__)->gState = HAL_CEC_STATE_RESET; \
|
||||
(__HANDLE__)->RxState = HAL_CEC_STATE_RESET; \
|
||||
} while(0)
|
||||
|
||||
/** @brief Checks whether or not the specified CEC interrupt flag is set.
|
||||
* @param __HANDLE__: specifies the CEC Handle.
|
||||
* @param __FLAG__: specifies the flag to check.
|
||||
* @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error
|
||||
* @arg CEC_FLAG_TXERR: Tx Error.
|
||||
* @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun.
|
||||
* @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte).
|
||||
* @arg CEC_FLAG_TXBR: Tx-Byte Request.
|
||||
* @arg CEC_FLAG_ARBLST: Arbitration Lost
|
||||
* @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge
|
||||
* @arg CEC_FLAG_LBPE: Rx Long period Error
|
||||
* @arg CEC_FLAG_SBPE: Rx Short period Error
|
||||
* @arg CEC_FLAG_BRE: Rx Bit Rising Error
|
||||
* @arg CEC_FLAG_RXOVR: Rx Overrun.
|
||||
* @arg CEC_FLAG_RXEND: End Of Reception.
|
||||
* @arg CEC_FLAG_RXBR: Rx-Byte Received.
|
||||
* @retval ITStatus
|
||||
*/
|
||||
#define __HAL_CEC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
|
||||
|
||||
/** @brief Clears the interrupt or status flag when raised (write at 1)
|
||||
* @param __HANDLE__: specifies the CEC Handle.
|
||||
* @param __FLAG__: specifies the interrupt/status flag to clear.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error
|
||||
* @arg CEC_FLAG_TXERR: Tx Error.
|
||||
* @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun.
|
||||
* @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte).
|
||||
* @arg CEC_FLAG_TXBR: Tx-Byte Request.
|
||||
* @arg CEC_FLAG_ARBLST: Arbitration Lost
|
||||
* @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge
|
||||
* @arg CEC_FLAG_LBPE: Rx Long period Error
|
||||
* @arg CEC_FLAG_SBPE: Rx Short period Error
|
||||
* @arg CEC_FLAG_BRE: Rx Bit Rising Error
|
||||
* @arg CEC_FLAG_RXOVR: Rx Overrun.
|
||||
* @arg CEC_FLAG_RXEND: End Of Reception.
|
||||
* @arg CEC_FLAG_RXBR: Rx-Byte Received.
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_CEC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR |= (__FLAG__))
|
||||
|
||||
/** @brief Enables the specified CEC interrupt.
|
||||
* @param __HANDLE__: specifies the CEC Handle.
|
||||
* @param __INTERRUPT__: specifies the CEC interrupt to enable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
|
||||
* @arg CEC_IT_TXERR: Tx Error IT Enable
|
||||
* @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
|
||||
* @arg CEC_IT_TXEND: End of transmission IT Enable
|
||||
* @arg CEC_IT_TXBR: Tx-Byte Request IT Enable
|
||||
* @arg CEC_IT_ARBLST: Arbitration Lost IT Enable
|
||||
* @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
|
||||
* @arg CEC_IT_LBPE: Rx Long period Error IT Enable
|
||||
* @arg CEC_IT_SBPE: Rx Short period Error IT Enable
|
||||
* @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable
|
||||
* @arg CEC_IT_RXOVR: Rx Overrun IT Enable
|
||||
* @arg CEC_IT_RXEND: End Of Reception IT Enable
|
||||
* @arg CEC_IT_RXBR: Rx-Byte Received IT Enable
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_CEC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
|
||||
|
||||
/** @brief Disables the specified CEC interrupt.
|
||||
* @param __HANDLE__: specifies the CEC Handle.
|
||||
* @param __INTERRUPT__: specifies the CEC interrupt to disable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
|
||||
* @arg CEC_IT_TXERR: Tx Error IT Enable
|
||||
* @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
|
||||
* @arg CEC_IT_TXEND: End of transmission IT Enable
|
||||
* @arg CEC_IT_TXBR: Tx-Byte Request IT Enable
|
||||
* @arg CEC_IT_ARBLST: Arbitration Lost IT Enable
|
||||
* @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
|
||||
* @arg CEC_IT_LBPE: Rx Long period Error IT Enable
|
||||
* @arg CEC_IT_SBPE: Rx Short period Error IT Enable
|
||||
* @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable
|
||||
* @arg CEC_IT_RXOVR: Rx Overrun IT Enable
|
||||
* @arg CEC_IT_RXEND: End Of Reception IT Enable
|
||||
* @arg CEC_IT_RXBR: Rx-Byte Received IT Enable
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_CEC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
|
||||
|
||||
/** @brief Checks whether or not the specified CEC interrupt is enabled.
|
||||
* @param __HANDLE__: specifies the CEC Handle.
|
||||
* @param __INTERRUPT__: specifies the CEC interrupt to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
|
||||
* @arg CEC_IT_TXERR: Tx Error IT Enable
|
||||
* @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
|
||||
* @arg CEC_IT_TXEND: End of transmission IT Enable
|
||||
* @arg CEC_IT_TXBR: Tx-Byte Request IT Enable
|
||||
* @arg CEC_IT_ARBLST: Arbitration Lost IT Enable
|
||||
* @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
|
||||
* @arg CEC_IT_LBPE: Rx Long period Error IT Enable
|
||||
* @arg CEC_IT_SBPE: Rx Short period Error IT Enable
|
||||
* @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable
|
||||
* @arg CEC_IT_RXOVR: Rx Overrun IT Enable
|
||||
* @arg CEC_IT_RXEND: End Of Reception IT Enable
|
||||
* @arg CEC_IT_RXBR: Rx-Byte Received IT Enable
|
||||
* @retval FlagStatus
|
||||
*/
|
||||
#define __HAL_CEC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__))
|
||||
|
||||
/** @brief Enables the CEC device
|
||||
* @param __HANDLE__: specifies the CEC Handle.
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_CEC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_CECEN)
|
||||
|
||||
/** @brief Disables the CEC device
|
||||
* @param __HANDLE__: specifies the CEC Handle.
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_CEC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~CEC_CR_CECEN)
|
||||
|
||||
/** @brief Set Transmission Start flag
|
||||
* @param __HANDLE__: specifies the CEC Handle.
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_CEC_FIRST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXSOM)
|
||||
|
||||
/** @brief Set Transmission End flag
|
||||
* @param __HANDLE__: specifies the CEC Handle.
|
||||
* @retval none
|
||||
* If the CEC message consists of only one byte, TXEOM must be set before of TXSOM.
|
||||
*/
|
||||
#define __HAL_CEC_LAST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXEOM)
|
||||
|
||||
/** @brief Get Transmission Start flag
|
||||
* @param __HANDLE__: specifies the CEC Handle.
|
||||
* @retval FlagStatus
|
||||
*/
|
||||
#define __HAL_CEC_GET_TRANSMISSION_START_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXSOM)
|
||||
|
||||
/** @brief Get Transmission End flag
|
||||
* @param __HANDLE__: specifies the CEC Handle.
|
||||
* @retval FlagStatus
|
||||
*/
|
||||
#define __HAL_CEC_GET_TRANSMISSION_END_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXEOM)
|
||||
|
||||
/** @brief Clear OAR register
|
||||
* @param __HANDLE__: specifies the CEC Handle.
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_CEC_CLEAR_OAR(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CFGR, CEC_CFGR_OAR)
|
||||
|
||||
/** @brief Set OAR register (without resetting previously set address in case of multi-address mode)
|
||||
* To reset OAR, __HAL_CEC_CLEAR_OAR() needs to be called beforehand
|
||||
* @param __HANDLE__: specifies the CEC Handle.
|
||||
* @param __ADDRESS__: Own Address value (CEC logical address is identified by bit position)
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_CEC_SET_OAR(__HANDLE__,__ADDRESS__) SET_BIT((__HANDLE__)->Instance->CFGR, (__ADDRESS__)<< CEC_CFGR_OAR_LSB_POS)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup CEC_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CEC_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Initialization and de-initialization functions ****************************/
|
||||
HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec);
|
||||
HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec);
|
||||
HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress);
|
||||
void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec);
|
||||
void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CEC_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* I/O operation functions ***************************************************/
|
||||
HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress,uint8_t DestinationAddress, uint8_t *pData, uint32_t Size);
|
||||
uint32_t HAL_CEC_GetLastReceivedFrameSize(CEC_HandleTypeDef *hcec);
|
||||
void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t* Rxbuffer);
|
||||
void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec);
|
||||
void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec);
|
||||
void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize);
|
||||
void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CEC_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State functions ************************************************/
|
||||
HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec);
|
||||
uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/** @defgroup CEC_Private_Types CEC Private Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/** @defgroup CEC_Private_Variables CEC Private Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup CEC_Private_Constants CEC Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup CEC_Private_Macros CEC Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_CEC_SIGNALFREETIME(__SFT__) ((__SFT__) <= CEC_CFGR_SFT)
|
||||
|
||||
#define IS_CEC_TOLERANCE(__RXTOL__) (((__RXTOL__) == CEC_STANDARD_TOLERANCE) || \
|
||||
((__RXTOL__) == CEC_EXTENDED_TOLERANCE))
|
||||
|
||||
#define IS_CEC_BRERXSTOP(__BRERXSTOP__) (((__BRERXSTOP__) == CEC_NO_RX_STOP_ON_BRE) || \
|
||||
((__BRERXSTOP__) == CEC_RX_STOP_ON_BRE))
|
||||
|
||||
#define IS_CEC_BREERRORBITGEN(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_NO_GENERATION) || \
|
||||
((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_GENERATION))
|
||||
|
||||
#define IS_CEC_LBPEERRORBITGEN(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_NO_GENERATION) || \
|
||||
((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_GENERATION))
|
||||
|
||||
#define IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_BROADCASTERROR_ERRORBIT_GENERATION) || \
|
||||
((__ERRORBITGEN__) == CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION))
|
||||
|
||||
#define IS_CEC_SFTOP(__SFTOP__) (((__SFTOP__) == CEC_SFT_START_ON_TXSOM) || \
|
||||
((__SFTOP__) == CEC_SFT_START_ON_TX_RX_END))
|
||||
|
||||
#define IS_CEC_LISTENING_MODE(__MODE__) (((__MODE__) == CEC_REDUCED_LISTENING_MODE) || \
|
||||
((__MODE__) == CEC_FULL_LISTENING_MODE))
|
||||
|
||||
/** @brief Check CEC message size.
|
||||
* The message size is the payload size: without counting the header,
|
||||
* it varies from 0 byte (ping operation, one header only, no payload) to
|
||||
* 15 bytes (1 opcode and up to 14 operands following the header).
|
||||
* @param __SIZE__: CEC message size.
|
||||
* @retval Test result (TRUE or FALSE).
|
||||
*/
|
||||
#define IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0x10)
|
||||
|
||||
/** @brief Check CEC device Own Address Register (OAR) setting.
|
||||
* OAR address is written in a 15-bit field within CEC_CFGR register.
|
||||
* @param __ADDRESS__: CEC own address.
|
||||
* @retval Test result (TRUE or FALSE).
|
||||
*/
|
||||
#define IS_CEC_OWN_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x7FFF)
|
||||
|
||||
/** @brief Check CEC initiator or destination logical address setting.
|
||||
* Initiator and destination addresses are coded over 4 bits.
|
||||
* @param __ADDRESS__: CEC initiator or logical address.
|
||||
* @retval Test result (TRUE or FALSE).
|
||||
*/
|
||||
#define IS_CEC_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0xF)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup CEC_Private_Functions CEC Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* CEC */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F7xx_HAL_CEC_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,464 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_hal_conf_template.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.2
|
||||
* @date 14-April-2017
|
||||
* @brief HAL configuration template file.
|
||||
* This file should be copied to the application folder and renamed
|
||||
* to stm32f7xx_hal_conf.h.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F7xx_HAL_CONF_H
|
||||
#define __STM32F7xx_HAL_CONF_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/* ########################## Module Selection ############################## */
|
||||
/**
|
||||
* @brief This is the list of modules to be used in the HAL driver
|
||||
*/
|
||||
#define HAL_MODULE_ENABLED
|
||||
#define HAL_ADC_MODULE_ENABLED
|
||||
#define HAL_CAN_MODULE_ENABLED
|
||||
#define HAL_CEC_MODULE_ENABLED
|
||||
#define HAL_CRC_MODULE_ENABLED
|
||||
#define HAL_CRYP_MODULE_ENABLED
|
||||
#define HAL_DAC_MODULE_ENABLED
|
||||
#define HAL_DCMI_MODULE_ENABLED
|
||||
#define HAL_DMA_MODULE_ENABLED
|
||||
#define HAL_DMA2D_MODULE_ENABLED
|
||||
#define HAL_ETH_MODULE_ENABLED
|
||||
#define HAL_FLASH_MODULE_ENABLED
|
||||
#define HAL_NAND_MODULE_ENABLED
|
||||
#define HAL_NOR_MODULE_ENABLED
|
||||
#define HAL_SRAM_MODULE_ENABLED
|
||||
#define HAL_SDRAM_MODULE_ENABLED
|
||||
#define HAL_HASH_MODULE_ENABLED
|
||||
#define HAL_GPIO_MODULE_ENABLED
|
||||
#define HAL_I2C_MODULE_ENABLED
|
||||
#define HAL_I2S_MODULE_ENABLED
|
||||
#define HAL_IWDG_MODULE_ENABLED
|
||||
#define HAL_LPTIM_MODULE_ENABLED
|
||||
#define HAL_LTDC_MODULE_ENABLED
|
||||
#define HAL_PWR_MODULE_ENABLED
|
||||
#define HAL_QSPI_MODULE_ENABLED
|
||||
#define HAL_RCC_MODULE_ENABLED
|
||||
#define HAL_RNG_MODULE_ENABLED
|
||||
#define HAL_RTC_MODULE_ENABLED
|
||||
#define HAL_SAI_MODULE_ENABLED
|
||||
#define HAL_SD_MODULE_ENABLED
|
||||
#define HAL_SPDIFRX_MODULE_ENABLED
|
||||
#define HAL_SPI_MODULE_ENABLED
|
||||
#define HAL_TIM_MODULE_ENABLED
|
||||
#define HAL_UART_MODULE_ENABLED
|
||||
#define HAL_USART_MODULE_ENABLED
|
||||
#define HAL_IRDA_MODULE_ENABLED
|
||||
#define HAL_SMARTCARD_MODULE_ENABLED
|
||||
#define HAL_WWDG_MODULE_ENABLED
|
||||
#define HAL_CORTEX_MODULE_ENABLED
|
||||
#define HAL_PCD_MODULE_ENABLED
|
||||
#define HAL_HCD_MODULE_ENABLED
|
||||
#define HAL_DFSDM_MODULE_ENABLED
|
||||
#define HAL_DSI_MODULE_ENABLED
|
||||
#define HAL_JPEG_MODULE_ENABLED
|
||||
#define HAL_MDIOS_MODULE_ENABLED
|
||||
#define HAL_SMBUS_MODULE_ENABLED
|
||||
#define HAL_MMC_MODULE_ENABLED
|
||||
|
||||
|
||||
/* ########################## HSE/HSI Values adaptation ##################### */
|
||||
/**
|
||||
* @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
|
||||
* This value is used by the RCC HAL module to compute the system frequency
|
||||
* (when HSE is used as system clock source, directly or through the PLL).
|
||||
*/
|
||||
#if !defined (HSE_VALUE)
|
||||
#define HSE_VALUE 25000000U /*!< Value of the External oscillator in Hz */
|
||||
#endif /* HSE_VALUE */
|
||||
|
||||
#if !defined (HSE_STARTUP_TIMEOUT)
|
||||
#define HSE_STARTUP_TIMEOUT 100U /*!< Time out for HSE start up, in ms */
|
||||
#endif /* HSE_STARTUP_TIMEOUT */
|
||||
|
||||
/**
|
||||
* @brief Internal High Speed oscillator (HSI) value.
|
||||
* This value is used by the RCC HAL module to compute the system frequency
|
||||
* (when HSI is used as system clock source, directly or through the PLL).
|
||||
*/
|
||||
#if !defined (HSI_VALUE)
|
||||
#define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/
|
||||
#endif /* HSI_VALUE */
|
||||
|
||||
/**
|
||||
* @brief Internal Low Speed oscillator (LSI) value.
|
||||
*/
|
||||
#if !defined (LSI_VALUE)
|
||||
#define LSI_VALUE 32000U /*!< LSI Typical Value in Hz*/
|
||||
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
|
||||
The real value may vary depending on the variations
|
||||
in voltage and temperature. */
|
||||
/**
|
||||
* @brief External Low Speed oscillator (LSE) value.
|
||||
*/
|
||||
#if !defined (LSE_VALUE)
|
||||
#define LSE_VALUE 32768U /*!< Value of the External Low Speed oscillator in Hz */
|
||||
#endif /* LSE_VALUE */
|
||||
|
||||
#if !defined (LSE_STARTUP_TIMEOUT)
|
||||
#define LSE_STARTUP_TIMEOUT 5000U /*!< Time out for LSE start up, in ms */
|
||||
#endif /* LSE_STARTUP_TIMEOUT */
|
||||
|
||||
/**
|
||||
* @brief External clock source for I2S peripheral
|
||||
* This value is used by the I2S HAL module to compute the I2S clock source
|
||||
* frequency, this source is inserted directly through I2S_CKIN pad.
|
||||
*/
|
||||
#if !defined (EXTERNAL_CLOCK_VALUE)
|
||||
#define EXTERNAL_CLOCK_VALUE 12288000U /*!< Value of the Internal oscillator in Hz*/
|
||||
#endif /* EXTERNAL_CLOCK_VALUE */
|
||||
|
||||
/* Tip: To avoid modifying this file each time you need to use different HSE,
|
||||
=== you can define the HSE value in your toolchain compiler preprocessor. */
|
||||
|
||||
/* ########################### System Configuration ######################### */
|
||||
/**
|
||||
* @brief This is the HAL system configuration section
|
||||
*/
|
||||
#define VDD_VALUE 3300U /*!< Value of VDD in mv */
|
||||
#define TICK_INT_PRIORITY 0x0FU /*!< tick interrupt priority */
|
||||
#define USE_RTOS 0U
|
||||
#define PREFETCH_ENABLE 1U
|
||||
#define ART_ACCLERATOR_ENABLE 1U /* To enable instruction cache and prefetch */
|
||||
|
||||
/* ########################## Assert Selection ############################## */
|
||||
/**
|
||||
* @brief Uncomment the line below to expanse the "assert_param" macro in the
|
||||
* HAL drivers code
|
||||
*/
|
||||
/* #define USE_FULL_ASSERT 1 */
|
||||
|
||||
/* ################## Ethernet peripheral configuration ##################### */
|
||||
|
||||
/* Section 1 : Ethernet peripheral configuration */
|
||||
|
||||
/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
|
||||
#define MAC_ADDR0 2U
|
||||
#define MAC_ADDR1 0U
|
||||
#define MAC_ADDR2 0U
|
||||
#define MAC_ADDR3 0U
|
||||
#define MAC_ADDR4 0U
|
||||
#define MAC_ADDR5 0U
|
||||
|
||||
/* Definition of the Ethernet driver buffers size and count */
|
||||
#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */
|
||||
#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */
|
||||
#define ETH_RXBUFNB 4U /* 4 Rx buffers of size ETH_RX_BUF_SIZE */
|
||||
#define ETH_TXBUFNB 4U /* 4 Tx buffers of size ETH_TX_BUF_SIZE */
|
||||
|
||||
/* Section 2: PHY configuration section */
|
||||
|
||||
/* DP83848 PHY Address*/
|
||||
#define DP83848_PHY_ADDRESS 0x01U
|
||||
/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
|
||||
#define PHY_RESET_DELAY 0x000000FFU
|
||||
/* PHY Configuration delay */
|
||||
#define PHY_CONFIG_DELAY 0x00000FFFU
|
||||
|
||||
#define PHY_READ_TO 0x0000FFFFU
|
||||
#define PHY_WRITE_TO 0x0000FFFFU
|
||||
|
||||
/* Section 3: Common PHY Registers */
|
||||
|
||||
#define PHY_BCR ((uint16_t)0x00U) /*!< Transceiver Basic Control Register */
|
||||
#define PHY_BSR ((uint16_t)0x01U) /*!< Transceiver Basic Status Register */
|
||||
|
||||
#define PHY_RESET ((uint16_t)0x8000U) /*!< PHY Reset */
|
||||
#define PHY_LOOPBACK ((uint16_t)0x4000U) /*!< Select loop-back mode */
|
||||
#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100U) /*!< Set the full-duplex mode at 100 Mb/s */
|
||||
#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000U) /*!< Set the half-duplex mode at 100 Mb/s */
|
||||
#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100U) /*!< Set the full-duplex mode at 10 Mb/s */
|
||||
#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000U) /*!< Set the half-duplex mode at 10 Mb/s */
|
||||
#define PHY_AUTONEGOTIATION ((uint16_t)0x1000U) /*!< Enable auto-negotiation function */
|
||||
#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200U) /*!< Restart auto-negotiation function */
|
||||
#define PHY_POWERDOWN ((uint16_t)0x0800U) /*!< Select the power down mode */
|
||||
#define PHY_ISOLATE ((uint16_t)0x0400U) /*!< Isolate PHY from MII */
|
||||
|
||||
#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020U) /*!< Auto-Negotiation process completed */
|
||||
#define PHY_LINKED_STATUS ((uint16_t)0x0004U) /*!< Valid link established */
|
||||
#define PHY_JABBER_DETECTION ((uint16_t)0x0002U) /*!< Jabber condition detected */
|
||||
|
||||
/* Section 4: Extended PHY Registers */
|
||||
|
||||
#define PHY_SR ((uint16_t)0x10U) /*!< PHY status register Offset */
|
||||
#define PHY_MICR ((uint16_t)0x11U) /*!< MII Interrupt Control Register */
|
||||
#define PHY_MISR ((uint16_t)0x12U) /*!< MII Interrupt Status and Misc. Control Register */
|
||||
|
||||
#define PHY_LINK_STATUS ((uint16_t)0x0001U) /*!< PHY Link mask */
|
||||
#define PHY_SPEED_STATUS ((uint16_t)0x0002U) /*!< PHY Speed mask */
|
||||
#define PHY_DUPLEX_STATUS ((uint16_t)0x0004U) /*!< PHY Duplex mask */
|
||||
|
||||
#define PHY_MICR_INT_EN ((uint16_t)0x0002U) /*!< PHY Enable interrupts */
|
||||
#define PHY_MICR_INT_OE ((uint16_t)0x0001U) /*!< PHY Enable output interrupt events */
|
||||
|
||||
#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020U) /*!< Enable Interrupt on change of link status */
|
||||
#define PHY_LINK_INTERRUPT ((uint16_t)0x2000U) /*!< PHY link status interrupt mask */
|
||||
|
||||
/* ################## SPI peripheral configuration ########################## */
|
||||
|
||||
/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
|
||||
* Activated: CRC code is present inside driver
|
||||
* Deactivated: CRC code cleaned from driver
|
||||
*/
|
||||
|
||||
#define USE_SPI_CRC 1U
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
/**
|
||||
* @brief Include module's header file
|
||||
*/
|
||||
|
||||
#ifdef HAL_RCC_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_rcc.h"
|
||||
#endif /* HAL_RCC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_GPIO_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_gpio.h"
|
||||
#endif /* HAL_GPIO_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_DMA_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_dma.h"
|
||||
#endif /* HAL_DMA_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_CORTEX_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_cortex.h"
|
||||
#endif /* HAL_CORTEX_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_ADC_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_adc.h"
|
||||
#endif /* HAL_ADC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_CAN_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_can.h"
|
||||
#endif /* HAL_CAN_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_CEC_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_cec.h"
|
||||
#endif /* HAL_CEC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_CRC_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_crc.h"
|
||||
#endif /* HAL_CRC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_CRYP_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_cryp.h"
|
||||
#endif /* HAL_CRYP_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_DMA2D_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_dma2d.h"
|
||||
#endif /* HAL_DMA2D_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_DAC_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_dac.h"
|
||||
#endif /* HAL_DAC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_DCMI_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_dcmi.h"
|
||||
#endif /* HAL_DCMI_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_ETH_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_eth.h"
|
||||
#endif /* HAL_ETH_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_FLASH_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_flash.h"
|
||||
#endif /* HAL_FLASH_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SRAM_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_sram.h"
|
||||
#endif /* HAL_SRAM_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_NOR_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_nor.h"
|
||||
#endif /* HAL_NOR_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_NAND_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_nand.h"
|
||||
#endif /* HAL_NAND_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SDRAM_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_sdram.h"
|
||||
#endif /* HAL_SDRAM_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_HASH_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_hash.h"
|
||||
#endif /* HAL_HASH_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_I2C_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_i2c.h"
|
||||
#endif /* HAL_I2C_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_I2S_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_i2s.h"
|
||||
#endif /* HAL_I2S_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_IWDG_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_iwdg.h"
|
||||
#endif /* HAL_IWDG_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_LPTIM_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_lptim.h"
|
||||
#endif /* HAL_LPTIM_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_LTDC_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_ltdc.h"
|
||||
#endif /* HAL_LTDC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_PWR_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_pwr.h"
|
||||
#endif /* HAL_PWR_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_QSPI_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_qspi.h"
|
||||
#endif /* HAL_QSPI_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_RNG_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_rng.h"
|
||||
#endif /* HAL_RNG_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_RTC_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_rtc.h"
|
||||
#endif /* HAL_RTC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SAI_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_sai.h"
|
||||
#endif /* HAL_SAI_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SD_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_sd.h"
|
||||
#endif /* HAL_SD_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SPDIFRX_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_spdifrx.h"
|
||||
#endif /* HAL_SPDIFRX_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SPI_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_spi.h"
|
||||
#endif /* HAL_SPI_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_TIM_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_tim.h"
|
||||
#endif /* HAL_TIM_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_UART_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_uart.h"
|
||||
#endif /* HAL_UART_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_USART_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_usart.h"
|
||||
#endif /* HAL_USART_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_IRDA_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_irda.h"
|
||||
#endif /* HAL_IRDA_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SMARTCARD_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_smartcard.h"
|
||||
#endif /* HAL_SMARTCARD_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_WWDG_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_wwdg.h"
|
||||
#endif /* HAL_WWDG_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_PCD_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_pcd.h"
|
||||
#endif /* HAL_PCD_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_HCD_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_hcd.h"
|
||||
#endif /* HAL_HCD_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_DFSDM_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_dfsdm.h"
|
||||
#endif /* HAL_DFSDM_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_DSI_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_dsi.h"
|
||||
#endif /* HAL_DSI_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_JPEG_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_jpeg.h"
|
||||
#endif /* HAL_JPEG_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_MDIOS_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_mdios.h"
|
||||
#endif /* HAL_MDIOS_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SMBUS_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_smbus.h"
|
||||
#endif /* HAL_SMBUS_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_MMC_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_mmc.h"
|
||||
#endif /* HAL_MMC_MODULE_ENABLED */
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
#ifdef USE_FULL_ASSERT
|
||||
/**
|
||||
* @brief The assert_param macro is used for function's parameters check.
|
||||
* @param expr: If expr is false, it calls assert_failed function
|
||||
* which reports the name of the source file and the source
|
||||
* line number of the call that failed.
|
||||
* If expr is true, it returns no value.
|
||||
* @retval None
|
||||
*/
|
||||
#define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
void assert_failed(uint8_t* file, uint32_t line);
|
||||
#else
|
||||
#define assert_param(expr) ((void)0)
|
||||
#endif /* USE_FULL_ASSERT */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F7xx_HAL_CONF_H */
|
||||
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,424 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_hal_cortex.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.2
|
||||
* @date 14-April-2017
|
||||
* @brief Header file of CORTEX HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F7xx_HAL_CORTEX_H
|
||||
#define __STM32F7xx_HAL_CORTEX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CORTEX
|
||||
* @{
|
||||
*/
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup CORTEX_Exported_Types Cortex Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if (__MPU_PRESENT == 1)
|
||||
/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
|
||||
* @brief MPU Region initialization structure
|
||||
* @{
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t Enable; /*!< Specifies the status of the region.
|
||||
This parameter can be a value of @ref CORTEX_MPU_Region_Enable */
|
||||
uint8_t Number; /*!< Specifies the number of the region to protect.
|
||||
This parameter can be a value of @ref CORTEX_MPU_Region_Number */
|
||||
uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */
|
||||
uint8_t Size; /*!< Specifies the size of the region to protect.
|
||||
This parameter can be a value of @ref CORTEX_MPU_Region_Size */
|
||||
uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable.
|
||||
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
|
||||
uint8_t TypeExtField; /*!< Specifies the TEX field level.
|
||||
This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */
|
||||
uint8_t AccessPermission; /*!< Specifies the region access permission type.
|
||||
This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */
|
||||
uint8_t DisableExec; /*!< Specifies the instruction access status.
|
||||
This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */
|
||||
uint8_t IsShareable; /*!< Specifies the shareability status of the protected region.
|
||||
This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */
|
||||
uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected.
|
||||
This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */
|
||||
uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region.
|
||||
This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */
|
||||
}MPU_Region_InitTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* __MPU_PRESENT */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
|
||||
* @{
|
||||
*/
|
||||
#define NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007U) /*!< 0 bits for pre-emption priority
|
||||
4 bits for subpriority */
|
||||
#define NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006U) /*!< 1 bits for pre-emption priority
|
||||
3 bits for subpriority */
|
||||
#define NVIC_PRIORITYGROUP_2 ((uint32_t)0x00000005U) /*!< 2 bits for pre-emption priority
|
||||
2 bits for subpriority */
|
||||
#define NVIC_PRIORITYGROUP_3 ((uint32_t)0x00000004U) /*!< 3 bits for pre-emption priority
|
||||
1 bits for subpriority */
|
||||
#define NVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003U) /*!< 4 bits for pre-emption priority
|
||||
0 bits for subpriority */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_SysTick_clock_source CORTEX _SysTick clock source
|
||||
* @{
|
||||
*/
|
||||
#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000U)
|
||||
#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004U)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if (__MPU_PRESENT == 1)
|
||||
/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control
|
||||
* @{
|
||||
*/
|
||||
#define MPU_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000U)
|
||||
#define MPU_HARDFAULT_NMI ((uint32_t)0x00000002U)
|
||||
#define MPU_PRIVILEGED_DEFAULT ((uint32_t)0x00000004U)
|
||||
#define MPU_HFNMI_PRIVDEF ((uint32_t)0x00000006U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
|
||||
* @{
|
||||
*/
|
||||
#define MPU_REGION_ENABLE ((uint8_t)0x01U)
|
||||
#define MPU_REGION_DISABLE ((uint8_t)0x00U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
|
||||
* @{
|
||||
*/
|
||||
#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00U)
|
||||
#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
|
||||
* @{
|
||||
*/
|
||||
#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01U)
|
||||
#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
|
||||
* @{
|
||||
*/
|
||||
#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01U)
|
||||
#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
|
||||
* @{
|
||||
*/
|
||||
#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01U)
|
||||
#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels
|
||||
* @{
|
||||
*/
|
||||
#define MPU_TEX_LEVEL0 ((uint8_t)0x00U)
|
||||
#define MPU_TEX_LEVEL1 ((uint8_t)0x01U)
|
||||
#define MPU_TEX_LEVEL2 ((uint8_t)0x02U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
|
||||
* @{
|
||||
*/
|
||||
#define MPU_REGION_SIZE_32B ((uint8_t)0x04U)
|
||||
#define MPU_REGION_SIZE_64B ((uint8_t)0x05U)
|
||||
#define MPU_REGION_SIZE_128B ((uint8_t)0x06U)
|
||||
#define MPU_REGION_SIZE_256B ((uint8_t)0x07U)
|
||||
#define MPU_REGION_SIZE_512B ((uint8_t)0x08U)
|
||||
#define MPU_REGION_SIZE_1KB ((uint8_t)0x09U)
|
||||
#define MPU_REGION_SIZE_2KB ((uint8_t)0x0AU)
|
||||
#define MPU_REGION_SIZE_4KB ((uint8_t)0x0BU)
|
||||
#define MPU_REGION_SIZE_8KB ((uint8_t)0x0CU)
|
||||
#define MPU_REGION_SIZE_16KB ((uint8_t)0x0DU)
|
||||
#define MPU_REGION_SIZE_32KB ((uint8_t)0x0EU)
|
||||
#define MPU_REGION_SIZE_64KB ((uint8_t)0x0FU)
|
||||
#define MPU_REGION_SIZE_128KB ((uint8_t)0x10U)
|
||||
#define MPU_REGION_SIZE_256KB ((uint8_t)0x11U)
|
||||
#define MPU_REGION_SIZE_512KB ((uint8_t)0x12U)
|
||||
#define MPU_REGION_SIZE_1MB ((uint8_t)0x13U)
|
||||
#define MPU_REGION_SIZE_2MB ((uint8_t)0x14U)
|
||||
#define MPU_REGION_SIZE_4MB ((uint8_t)0x15U)
|
||||
#define MPU_REGION_SIZE_8MB ((uint8_t)0x16U)
|
||||
#define MPU_REGION_SIZE_16MB ((uint8_t)0x17U)
|
||||
#define MPU_REGION_SIZE_32MB ((uint8_t)0x18U)
|
||||
#define MPU_REGION_SIZE_64MB ((uint8_t)0x19U)
|
||||
#define MPU_REGION_SIZE_128MB ((uint8_t)0x1AU)
|
||||
#define MPU_REGION_SIZE_256MB ((uint8_t)0x1BU)
|
||||
#define MPU_REGION_SIZE_512MB ((uint8_t)0x1CU)
|
||||
#define MPU_REGION_SIZE_1GB ((uint8_t)0x1DU)
|
||||
#define MPU_REGION_SIZE_2GB ((uint8_t)0x1EU)
|
||||
#define MPU_REGION_SIZE_4GB ((uint8_t)0x1FU)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
|
||||
* @{
|
||||
*/
|
||||
#define MPU_REGION_NO_ACCESS ((uint8_t)0x00U)
|
||||
#define MPU_REGION_PRIV_RW ((uint8_t)0x01U)
|
||||
#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02U)
|
||||
#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03U)
|
||||
#define MPU_REGION_PRIV_RO ((uint8_t)0x05U)
|
||||
#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
|
||||
* @{
|
||||
*/
|
||||
#define MPU_REGION_NUMBER0 ((uint8_t)0x00U)
|
||||
#define MPU_REGION_NUMBER1 ((uint8_t)0x01U)
|
||||
#define MPU_REGION_NUMBER2 ((uint8_t)0x02U)
|
||||
#define MPU_REGION_NUMBER3 ((uint8_t)0x03U)
|
||||
#define MPU_REGION_NUMBER4 ((uint8_t)0x04U)
|
||||
#define MPU_REGION_NUMBER5 ((uint8_t)0x05U)
|
||||
#define MPU_REGION_NUMBER6 ((uint8_t)0x06U)
|
||||
#define MPU_REGION_NUMBER7 ((uint8_t)0x07U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* __MPU_PRESENT */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Exported Macros -----------------------------------------------------------*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup CORTEX_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CORTEX_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Initialization and de-initialization functions *****************************/
|
||||
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
|
||||
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
|
||||
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
|
||||
void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
|
||||
void HAL_NVIC_SystemReset(void);
|
||||
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CORTEX_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral Control functions ***********************************************/
|
||||
#if (__MPU_PRESENT == 1)
|
||||
void HAL_MPU_Enable(uint32_t MPU_Control);
|
||||
void HAL_MPU_Disable(void);
|
||||
void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
|
||||
#endif /* __MPU_PRESENT */
|
||||
uint32_t HAL_NVIC_GetPriorityGrouping(void);
|
||||
void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
|
||||
uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
|
||||
void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
|
||||
void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
|
||||
uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
|
||||
void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
|
||||
void HAL_SYSTICK_IRQHandler(void);
|
||||
void HAL_SYSTICK_Callback(void);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup CORTEX_Private_Macros CORTEX Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \
|
||||
((GROUP) == NVIC_PRIORITYGROUP_1) || \
|
||||
((GROUP) == NVIC_PRIORITYGROUP_2) || \
|
||||
((GROUP) == NVIC_PRIORITYGROUP_3) || \
|
||||
((GROUP) == NVIC_PRIORITYGROUP_4))
|
||||
|
||||
#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
|
||||
|
||||
#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
|
||||
|
||||
#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x00)
|
||||
|
||||
#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
|
||||
((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
|
||||
|
||||
#if (__MPU_PRESENT == 1)
|
||||
#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \
|
||||
((STATE) == MPU_REGION_DISABLE))
|
||||
|
||||
#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
|
||||
((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
|
||||
|
||||
#define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \
|
||||
((STATE) == MPU_ACCESS_NOT_SHAREABLE))
|
||||
|
||||
#define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \
|
||||
((STATE) == MPU_ACCESS_NOT_CACHEABLE))
|
||||
|
||||
#define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \
|
||||
((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
|
||||
|
||||
#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \
|
||||
((TYPE) == MPU_TEX_LEVEL1) || \
|
||||
((TYPE) == MPU_TEX_LEVEL2))
|
||||
|
||||
#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \
|
||||
((TYPE) == MPU_REGION_PRIV_RW) || \
|
||||
((TYPE) == MPU_REGION_PRIV_RW_URO) || \
|
||||
((TYPE) == MPU_REGION_FULL_ACCESS) || \
|
||||
((TYPE) == MPU_REGION_PRIV_RO) || \
|
||||
((TYPE) == MPU_REGION_PRIV_RO_URO))
|
||||
|
||||
#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER1) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER2) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER3) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER4) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER5) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER6) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER7))
|
||||
|
||||
#define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \
|
||||
((SIZE) == MPU_REGION_SIZE_64B) || \
|
||||
((SIZE) == MPU_REGION_SIZE_128B) || \
|
||||
((SIZE) == MPU_REGION_SIZE_256B) || \
|
||||
((SIZE) == MPU_REGION_SIZE_512B) || \
|
||||
((SIZE) == MPU_REGION_SIZE_1KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_2KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_4KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_8KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_16KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_32KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_64KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_128KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_256KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_512KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_1MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_2MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_4MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_8MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_16MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_32MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_64MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_128MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_256MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_512MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_1GB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_2GB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_4GB))
|
||||
|
||||
#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FFU)
|
||||
#endif /* __MPU_PRESENT */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F7xx_HAL_CORTEX_H */
|
||||
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,422 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_hal_crc.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.2
|
||||
* @date 14-April-2017
|
||||
* @brief Header file of CRC HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F7xx_HAL_CRC_H
|
||||
#define __STM32F7xx_HAL_CRC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CRC CRC
|
||||
* @brief CRC HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup CRC_Exported_Types CRC Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Exported_Types_Group1 CRC State Structure definition
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_CRC_STATE_RESET = 0x00U, /*!< CRC not yet initialized or disabled */
|
||||
HAL_CRC_STATE_READY = 0x01U, /*!< CRC initialized and ready for use */
|
||||
HAL_CRC_STATE_BUSY = 0x02U, /*!< CRC internal process is ongoing */
|
||||
HAL_CRC_STATE_TIMEOUT = 0x03U, /*!< CRC timeout state */
|
||||
HAL_CRC_STATE_ERROR = 0x04U /*!< CRC error state */
|
||||
}HAL_CRC_StateTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Exported_Types_Group2 CRC Init Structure definition
|
||||
* @{
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t DefaultPolynomialUse; /*!< This parameter is a value of @ref CRC_Default_Polynomial and indicates if default polynomial is used.
|
||||
If set to DEFAULT_POLYNOMIAL_ENABLE, resort to default
|
||||
X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2+ X +1.
|
||||
In that case, there is no need to set GeneratingPolynomial field.
|
||||
If otherwise set to DEFAULT_POLYNOMIAL_DISABLE, GeneratingPolynomial and CRCLength fields must be set */
|
||||
|
||||
uint8_t DefaultInitValueUse; /*!< This parameter is a value of @ref CRC_Default_InitValue_Use and indicates if default init value is used.
|
||||
If set to DEFAULT_INIT_VALUE_ENABLE, resort to default
|
||||
0xFFFFFFFF value. In that case, there is no need to set InitValue field.
|
||||
If otherwise set to DEFAULT_INIT_VALUE_DISABLE, InitValue field must be set */
|
||||
|
||||
uint32_t GeneratingPolynomial; /*!< Set CRC generating polynomial. 7, 8, 16 or 32-bit long value for a polynomial degree
|
||||
respectively equal to 7, 8, 16 or 32. This field is written in normal representation,
|
||||
e.g., for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65.
|
||||
No need to specify it if DefaultPolynomialUse is set to DEFAULT_POLYNOMIAL_ENABLE */
|
||||
|
||||
uint32_t CRCLength; /*!< This parameter is a value of @ref CRC_Polynomial_Sizes and indicates CRC length.
|
||||
Value can be either one of
|
||||
CRC_POLYLENGTH_32B (32-bit CRC)
|
||||
CRC_POLYLENGTH_16B (16-bit CRC)
|
||||
CRC_POLYLENGTH_8B (8-bit CRC)
|
||||
CRC_POLYLENGTH_7B (7-bit CRC) */
|
||||
|
||||
uint32_t InitValue; /*!< Init value to initiate CRC computation. No need to specify it if DefaultInitValueUse
|
||||
is set to DEFAULT_INIT_VALUE_ENABLE */
|
||||
|
||||
uint32_t InputDataInversionMode; /*!< This parameter is a value of @ref CRCEx_Input_Data_Inversion and specifies input data inversion mode.
|
||||
Can be either one of the following values
|
||||
CRC_INPUTDATA_INVERSION_NONE no input data inversion
|
||||
CRC_INPUTDATA_INVERSION_BYTE byte-wise inversion, 0x1A2B3C4D becomes 0x58D43CB2
|
||||
CRC_INPUTDATA_INVERSION_HALFWORD halfword-wise inversion, 0x1A2B3C4D becomes 0xD458B23C
|
||||
CRC_INPUTDATA_INVERSION_WORD word-wise inversion, 0x1A2B3C4D becomes 0xB23CD458 */
|
||||
|
||||
uint32_t OutputDataInversionMode; /*!< This parameter is a value of @ref CRCEx_Output_Data_Inversion and specifies output data (i.e. CRC) inversion mode.
|
||||
Can be either
|
||||
CRC_OUTPUTDATA_INVERSION_DISABLE no CRC inversion, or
|
||||
CRC_OUTPUTDATA_INVERSION_ENABLE CRC 0x11223344 is converted into 0x22CC4488 */
|
||||
}CRC_InitTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Exported_Types_Group3 CRC Handle Structure definition
|
||||
* @{
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
CRC_TypeDef *Instance; /*!< Register base address */
|
||||
|
||||
CRC_InitTypeDef Init; /*!< CRC configuration parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< CRC Locking object */
|
||||
|
||||
__IO HAL_CRC_StateTypeDef State; /*!< CRC communication state */
|
||||
|
||||
uint32_t InputDataFormat; /*!< This parameter is a value of @ref CRC_Input_Buffer_Format and specifies input data format.
|
||||
Can be either
|
||||
CRC_INPUTDATA_FORMAT_BYTES input data is a stream of bytes (8-bit data)
|
||||
CRC_INPUTDATA_FORMAT_HALFWORDS input data is a stream of half-words (16-bit data)
|
||||
CRC_INPUTDATA_FORMAT_WORDS input data is a stream of words (32-bits data)
|
||||
Note that constant CRC_INPUT_FORMAT_UNDEFINED is defined but an initialization error
|
||||
must occur if InputBufferFormat is not one of the three values listed above */
|
||||
}CRC_HandleTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup CRC_Exported_Constants CRC exported constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Default_Polynomial_Value Default CRC generating polynomial
|
||||
* @{
|
||||
*/
|
||||
#define DEFAULT_CRC32_POLY 0x04C11DB7U
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Default_InitValue Default CRC computation initialization value
|
||||
* @{
|
||||
*/
|
||||
#define DEFAULT_CRC_INITVALUE 0xFFFFFFFFU
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Default_Polynomial Indicates whether or not default polynomial is used
|
||||
* @{
|
||||
*/
|
||||
#define DEFAULT_POLYNOMIAL_ENABLE ((uint8_t)0x00U)
|
||||
#define DEFAULT_POLYNOMIAL_DISABLE ((uint8_t)0x01U)
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Default_InitValue_Use Indicates whether or not default init value is used
|
||||
* @{
|
||||
*/
|
||||
#define DEFAULT_INIT_VALUE_ENABLE ((uint8_t)0x00U)
|
||||
#define DEFAULT_INIT_VALUE_DISABLE ((uint8_t)0x01U)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Polynomial_Sizes Polynomial sizes to configure the IP
|
||||
* @{
|
||||
*/
|
||||
#define CRC_POLYLENGTH_32B ((uint32_t)0x00000000U)
|
||||
#define CRC_POLYLENGTH_16B ((uint32_t)CRC_CR_POLYSIZE_0)
|
||||
#define CRC_POLYLENGTH_8B ((uint32_t)CRC_CR_POLYSIZE_1)
|
||||
#define CRC_POLYLENGTH_7B ((uint32_t)CRC_CR_POLYSIZE)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Polynomial_Size_Definitions CRC polynomial possible sizes actual definitions
|
||||
* @{
|
||||
*/
|
||||
#define HAL_CRC_LENGTH_32B 32U
|
||||
#define HAL_CRC_LENGTH_16B 16U
|
||||
#define HAL_CRC_LENGTH_8B 8U
|
||||
#define HAL_CRC_LENGTH_7B 7U
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Input_Buffer_Format CRC input buffer format
|
||||
* @{
|
||||
*/
|
||||
/* WARNING: CRC_INPUT_FORMAT_UNDEFINED is created for reference purposes but
|
||||
* an error is triggered in HAL_CRC_Init() if InputDataFormat field is set
|
||||
* to CRC_INPUT_FORMAT_UNDEFINED: the format MUST be defined by the user for
|
||||
* the CRC APIs to provide a correct result */
|
||||
#define CRC_INPUTDATA_FORMAT_UNDEFINED ((uint32_t)0x00000000U)
|
||||
#define CRC_INPUTDATA_FORMAT_BYTES ((uint32_t)0x00000001U)
|
||||
#define CRC_INPUTDATA_FORMAT_HALFWORDS ((uint32_t)0x00000002U)
|
||||
#define CRC_INPUTDATA_FORMAT_WORDS ((uint32_t)0x00000003U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
|
||||
/** @defgroup CRC_Exported_Macros CRC exported macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset CRC handle state
|
||||
* @param __HANDLE__: CRC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET)
|
||||
|
||||
/**
|
||||
* @brief Reset CRC Data Register.
|
||||
* @param __HANDLE__: CRC handle
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET)
|
||||
|
||||
/**
|
||||
* @brief Set CRC INIT non-default value
|
||||
* @param __HANDLE__ : CRC handle
|
||||
* @param __INIT__ : 32-bit initial value
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_CRC_INITIALCRCVALUE_CONFIG(__HANDLE__, __INIT__) ((__HANDLE__)->Instance->INIT = (__INIT__))
|
||||
|
||||
/**
|
||||
* @brief Stores a 8-bit data in the Independent Data(ID) register.
|
||||
* @param __HANDLE__: CRC handle
|
||||
* @param __VALUE__: 8-bit value to be stored in the ID register
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, CRC_IDR_IDR, (__VALUE__)))
|
||||
|
||||
/**
|
||||
* @brief Returns the 8-bit data stored in the Independent Data(ID) register.
|
||||
* @param __HANDLE__: CRC handle
|
||||
* @retval 8-bit value of the ID register
|
||||
*/
|
||||
#define __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include CRC HAL Extension module */
|
||||
#include "stm32f7xx_hal_crc_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup CRC_Exported_Functions CRC Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Exported_Functions_Group1 Initialization/de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
/* Initialization and de-initialization functions ****************************/
|
||||
HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc);
|
||||
HAL_StatusTypeDef HAL_CRC_DeInit (CRC_HandleTypeDef *hcrc);
|
||||
void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc);
|
||||
void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Aliases for inter STM32 series compatibility */
|
||||
#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse
|
||||
#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse
|
||||
|
||||
/** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral Control functions ***********************************************/
|
||||
uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
|
||||
uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State and Error functions ***************************************/
|
||||
HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/** @defgroup CRC_Private_Types CRC Private Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private defines -----------------------------------------------------------*/
|
||||
/** @defgroup CRC_Private_Defines CRC Private Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/** @defgroup CRC_Private_Variables CRC Private Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup CRC_Private_Constants CRC Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup CRC_Private_Macros CRC Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_DEFAULT_POLYNOMIAL(__DEFAULT__) (((__DEFAULT__) == DEFAULT_POLYNOMIAL_ENABLE) || \
|
||||
((__DEFAULT__) == DEFAULT_POLYNOMIAL_DISABLE))
|
||||
#define IS_DEFAULT_INIT_VALUE(__VALUE__) (((__VALUE__) == DEFAULT_INIT_VALUE_ENABLE) || \
|
||||
((__VALUE__) == DEFAULT_INIT_VALUE_DISABLE))
|
||||
#define IS_CRC_POL_LENGTH(__LENGTH__) (((__LENGTH__) == CRC_POLYLENGTH_32B) || \
|
||||
((__LENGTH__) == CRC_POLYLENGTH_16B) || \
|
||||
((__LENGTH__) == CRC_POLYLENGTH_8B) || \
|
||||
((__LENGTH__) == CRC_POLYLENGTH_7B))
|
||||
#define IS_CRC_INPUTDATA_FORMAT(__FORMAT__) (((__FORMAT__) == CRC_INPUTDATA_FORMAT_BYTES) || \
|
||||
((__FORMAT__) == CRC_INPUTDATA_FORMAT_HALFWORDS) || \
|
||||
((__FORMAT__) == CRC_INPUTDATA_FORMAT_WORDS))
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions prototypes ----------------------------------------------*/
|
||||
/** @defgroup CRC_Private_Functions_Prototypes CRC Private Functions Prototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup CRC_Private_Functions CRC Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F7xx_HAL_CRC_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
||||
@@ -0,0 +1,168 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_hal_crc_ex.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.2
|
||||
* @date 14-April-2017
|
||||
* @brief Header file of CRC HAL extension module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F7xx_HAL_CRC_EX_H
|
||||
#define __STM32F7xx_HAL_CRC_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CRCEx CRCEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup CRCEx_Exported_Constants CRC Extended exported constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CRCEx_Input_Data_Inversion CRC Extended input data inversion modes
|
||||
* @{
|
||||
*/
|
||||
#define CRC_INPUTDATA_INVERSION_NONE ((uint32_t)0x00000000U)
|
||||
#define CRC_INPUTDATA_INVERSION_BYTE ((uint32_t)CRC_CR_REV_IN_0)
|
||||
#define CRC_INPUTDATA_INVERSION_HALFWORD ((uint32_t)CRC_CR_REV_IN_1)
|
||||
#define CRC_INPUTDATA_INVERSION_WORD ((uint32_t)CRC_CR_REV_IN)
|
||||
|
||||
#define IS_CRC_INPUTDATA_INVERSION_MODE(__MODE__) (((__MODE__) == CRC_INPUTDATA_INVERSION_NONE) || \
|
||||
((__MODE__) == CRC_INPUTDATA_INVERSION_BYTE) || \
|
||||
((__MODE__) == CRC_INPUTDATA_INVERSION_HALFWORD) || \
|
||||
((__MODE__) == CRC_INPUTDATA_INVERSION_WORD))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRCEx_Output_Data_Inversion CRC Extended output data inversion modes
|
||||
* @{
|
||||
*/
|
||||
#define CRC_OUTPUTDATA_INVERSION_DISABLE ((uint32_t)0x00000000U)
|
||||
#define CRC_OUTPUTDATA_INVERSION_ENABLE ((uint32_t)CRC_CR_REV_OUT)
|
||||
|
||||
#define IS_CRC_OUTPUTDATA_INVERSION_MODE(__MODE__) (((__MODE__) == CRC_OUTPUTDATA_INVERSION_DISABLE) || \
|
||||
((__MODE__) == CRC_OUTPUTDATA_INVERSION_ENABLE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup CRCEx_Exported_Macros CRC Extended exported macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Set CRC output reversal
|
||||
* @param __HANDLE__ : CRC handle
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_CRC_OUTPUTREVERSAL_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_REV_OUT)
|
||||
|
||||
/**
|
||||
* @brief Unset CRC output reversal
|
||||
* @param __HANDLE__ : CRC handle
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_CRC_OUTPUTREVERSAL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(CRC_CR_REV_OUT))
|
||||
|
||||
/**
|
||||
* @brief Set CRC non-default polynomial
|
||||
* @param __HANDLE__ : CRC handle
|
||||
* @param __POLYNOMIAL__: 7, 8, 16 or 32-bit polynomial
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_CRC_POLYNOMIAL_CONFIG(__HANDLE__, __POLYNOMIAL__) ((__HANDLE__)->Instance->POL = (__POLYNOMIAL__))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup CRCEx_Exported_Functions CRC Extended Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CRCEx_Exported_Functions_Group1 Extended CRC features functions
|
||||
* @{
|
||||
*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/* Initialization and de-initialization functions ****************************/
|
||||
HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength);
|
||||
HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode);
|
||||
HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode);
|
||||
|
||||
/* Peripheral Control functions ***********************************************/
|
||||
/* Peripheral State and Error functions ***************************************/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F7xx_HAL_CRC_EX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,293 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_hal_cryp_ex.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.2
|
||||
* @date 14-April-2017
|
||||
* @brief Header file of CRYP HAL Extension module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F7xx_HAL_CRYP_EX_H
|
||||
#define __STM32F7xx_HAL_CRYP_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx_hal_def.h"
|
||||
|
||||
#if defined (CRYP)
|
||||
|
||||
/** @addtogroup STM32F7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CRYPEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup CRYPEx_Exported_Constants CRYPEx Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CRYPEx_Exported_Constants_Group1 CRYP AlgoModeDirection
|
||||
* @{
|
||||
*/
|
||||
#define CRYP_CR_ALGOMODE_AES_GCM_ENCRYPT ((uint32_t)0x00080000U)
|
||||
#define CRYP_CR_ALGOMODE_AES_GCM_DECRYPT ((uint32_t)0x00080004U)
|
||||
#define CRYP_CR_ALGOMODE_AES_CCM_ENCRYPT ((uint32_t)0x00080008U)
|
||||
#define CRYP_CR_ALGOMODE_AES_CCM_DECRYPT ((uint32_t)0x0008000CU)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRYPEx_Exported_Constants_Group3 CRYP PhaseConfig
|
||||
* @brief The phases are relevant only to AES-GCM and AES-CCM
|
||||
* @{
|
||||
*/
|
||||
#define CRYP_PHASE_INIT ((uint32_t)0x00000000U)
|
||||
#define CRYP_PHASE_HEADER CRYP_CR_GCM_CCMPH_0
|
||||
#define CRYP_PHASE_PAYLOAD CRYP_CR_GCM_CCMPH_1
|
||||
#define CRYP_PHASE_FINAL CRYP_CR_GCM_CCMPH
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup CRYPEx_Exported_Macros CRYP Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Set the phase: Init, header, payload, final.
|
||||
* This is relevant only for GCM and CCM modes.
|
||||
* @param __HANDLE__: specifies the CRYP handle.
|
||||
* @param __PHASE__: The phase.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CRYP_SET_PHASE(__HANDLE__, __PHASE__) do{(__HANDLE__)->Instance->CR &= (uint32_t)(~CRYP_CR_GCM_CCMPH);\
|
||||
(__HANDLE__)->Instance->CR |= (uint32_t)(__PHASE__);\
|
||||
}while(0)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup CRYPEx_Exported_Functions CRYPEx Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CRYPEx_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* AES encryption/decryption using polling ***********************************/
|
||||
HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Finish(CRYP_HandleTypeDef *hcryp, uint32_t Size, uint8_t *AuthTag, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Finish(CRYP_HandleTypeDef *hcryp, uint8_t *AuthTag, uint32_t Timeout);
|
||||
|
||||
/* AES encryption/decryption using interrupt *********************************/
|
||||
HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
|
||||
HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
|
||||
HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
|
||||
HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
|
||||
|
||||
/* AES encryption/decryption using DMA ***************************************/
|
||||
HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
|
||||
HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
|
||||
HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
|
||||
HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CRYPEx_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
|
||||
void HAL_CRYPEx_GCMCCM_IRQHandler(CRYP_HandleTypeDef *hcryp);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/** @defgroup CRYPEx_Private_Types CRYPEx Private Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/** @defgroup CRYPEx_Private_Variables CRYPEx Private Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup CRYPEx_Private_Constants CRYPEx Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup CRYPEx_Private_Macros CRYPEx Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup CRYPEx_Private_Functions CRYPEx Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* CRYP */
|
||||
|
||||
#if defined (AES)
|
||||
|
||||
/** @addtogroup CRYPEx_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CRYPEx_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* CallBack functions ********************************************************/
|
||||
void HAL_CRYPEx_ComputationCpltCallback(CRYP_HandleTypeDef *hcryp);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CRYPEx_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* AES encryption/decryption processing functions ****************************/
|
||||
HAL_StatusTypeDef HAL_CRYPEx_AES(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint16_t Size, uint8_t *pOutputData, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_CRYPEx_AES_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint16_t Size, uint8_t *pOutputData);
|
||||
HAL_StatusTypeDef HAL_CRYPEx_AES_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint16_t Size, uint8_t *pOutputData);
|
||||
|
||||
/* AES encryption/decryption/authentication processing functions *************/
|
||||
HAL_StatusTypeDef HAL_CRYPEx_AES_Auth(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint64_t Size, uint8_t *pOutputData, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint64_t Size, uint8_t *pOutputData);
|
||||
HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint64_t Size, uint8_t *pOutputData);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CRYPEx_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* AES suspension/resumption functions ***************************************/
|
||||
void HAL_CRYPEx_Read_IVRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Output);
|
||||
void HAL_CRYPEx_Write_IVRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Input);
|
||||
void HAL_CRYPEx_Read_SuspendRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Output);
|
||||
void HAL_CRYPEx_Write_SuspendRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Input);
|
||||
void HAL_CRYPEx_Read_KeyRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Output, uint32_t KeySize);
|
||||
void HAL_CRYPEx_Write_KeyRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint32_t KeySize);
|
||||
void HAL_CRYPEx_Read_ControlRegister(CRYP_HandleTypeDef *hcryp, uint8_t* Output);
|
||||
void HAL_CRYPEx_Write_ControlRegister(CRYP_HandleTypeDef *hcryp, uint8_t* Input);
|
||||
void HAL_CRYPEx_ProcessSuspend(CRYP_HandleTypeDef *hcryp);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions -----------------------------------------------------------*/
|
||||
/** @addtogroup CRYPEx_Private_Functions CRYPEx Private Functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef CRYP_AES_Auth_IT(CRYP_HandleTypeDef *hcryp);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* AES */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F7xx_HAL_CRYP_EX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,408 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_hal_dac.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.2
|
||||
* @date 14-April-2017
|
||||
* @brief Header file of DAC HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F7xx_HAL_DAC_H
|
||||
#define __STM32F7xx_HAL_DAC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DAC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup DAC_Exported_Types DAC Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief HAL State structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_DAC_STATE_RESET = 0x00U, /*!< DAC not yet initialized or disabled */
|
||||
HAL_DAC_STATE_READY = 0x01U, /*!< DAC initialized and ready for use */
|
||||
HAL_DAC_STATE_BUSY = 0x02U, /*!< DAC internal processing is ongoing */
|
||||
HAL_DAC_STATE_TIMEOUT = 0x03U, /*!< DAC timeout state */
|
||||
HAL_DAC_STATE_ERROR = 0x04U /*!< DAC error state */
|
||||
}HAL_DAC_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief DAC handle Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
DAC_TypeDef *Instance; /*!< Register base address */
|
||||
|
||||
__IO HAL_DAC_StateTypeDef State; /*!< DAC communication state */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< DAC locking object */
|
||||
|
||||
DMA_HandleTypeDef *DMA_Handle1; /*!< Pointer DMA handler for channel 1 */
|
||||
|
||||
DMA_HandleTypeDef *DMA_Handle2; /*!< Pointer DMA handler for channel 2 */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< DAC Error code */
|
||||
|
||||
}DAC_HandleTypeDef;
|
||||
|
||||
/**
|
||||
* @brief DAC Configuration regular Channel structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel.
|
||||
This parameter can be a value of @ref DAC_trigger_selection */
|
||||
|
||||
uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
|
||||
This parameter can be a value of @ref DAC_output_buffer */
|
||||
}DAC_ChannelConfTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup DAC_Exported_Constants DAC Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_Error_Code DAC Error Code
|
||||
* @{
|
||||
*/
|
||||
#define HAL_DAC_ERROR_NONE 0x00U /*!< No error */
|
||||
#define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01U /*!< DAC channel1 DAM underrun error */
|
||||
#define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02U /*!< DAC channel2 DAM underrun error */
|
||||
#define HAL_DAC_ERROR_DMA 0x04U /*!< DMA error */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_trigger_selection DAC Trigger Selection
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DAC_TRIGGER_NONE ((uint32_t)0x00000000U) /*!< Conversion is automatic once the DAC1_DHRxxxx register
|
||||
has been loaded, and not by external trigger */
|
||||
#define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_T4_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_T5_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_T7_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_T8_TRGO ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */
|
||||
|
||||
#define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_output_buffer DAC Output Buffer
|
||||
* @{
|
||||
*/
|
||||
#define DAC_OUTPUTBUFFER_ENABLE ((uint32_t)0x00000000U)
|
||||
#define DAC_OUTPUTBUFFER_DISABLE ((uint32_t)DAC_CR_BOFF1)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_Channel_selection DAC Channel Selection
|
||||
* @{
|
||||
*/
|
||||
#define DAC_CHANNEL_1 ((uint32_t)0x00000000U)
|
||||
#define DAC_CHANNEL_2 ((uint32_t)0x00000010U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_data_alignment DAC Data Alignment
|
||||
* @{
|
||||
*/
|
||||
#define DAC_ALIGN_12B_R ((uint32_t)0x00000000U)
|
||||
#define DAC_ALIGN_12B_L ((uint32_t)0x00000004U)
|
||||
#define DAC_ALIGN_8B_R ((uint32_t)0x00000008U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_flags_definition DAC Flags Definition
|
||||
* @{
|
||||
*/
|
||||
#define DAC_FLAG_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1)
|
||||
#define DAC_FLAG_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_IT_definition DAC IT Definition
|
||||
* @{
|
||||
*/
|
||||
#define DAC_IT_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1)
|
||||
#define DAC_IT_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup DAC_Exported_Macros DAC Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset DAC handle state
|
||||
* @param __HANDLE__: specifies the DAC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET)
|
||||
|
||||
/** @brief Enable the DAC channel
|
||||
* @param __HANDLE__: specifies the DAC handle.
|
||||
* @param __DAC_CHANNEL__: specifies the DAC channel
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DAC_ENABLE(__HANDLE__, __DAC_CHANNEL__) \
|
||||
((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << (__DAC_CHANNEL__)))
|
||||
|
||||
/** @brief Disable the DAC channel
|
||||
* @param __HANDLE__: specifies the DAC handle
|
||||
* @param __DAC_CHANNEL__: specifies the DAC channel.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DAC_DISABLE(__HANDLE__, __DAC_CHANNEL__) \
|
||||
((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << (__DAC_CHANNEL__)))
|
||||
|
||||
|
||||
/** @brief Enable the DAC interrupt
|
||||
* @param __HANDLE__: specifies the DAC handle
|
||||
* @param __INTERRUPT__: specifies the DAC interrupt.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
|
||||
|
||||
/** @brief Disable the DAC interrupt
|
||||
* @param __HANDLE__: specifies the DAC handle
|
||||
* @param __INTERRUPT__: specifies the DAC interrupt.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
|
||||
|
||||
/** @brief Checks if the specified DAC interrupt source is enabled or disabled.
|
||||
* @param __HANDLE__: DAC handle
|
||||
* @param __INTERRUPT__: DAC interrupt source to check
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
|
||||
* @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
|
||||
* @retval State of interruption (SET or RESET)
|
||||
*/
|
||||
#define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))
|
||||
|
||||
/** @brief Get the selected DAC's flag status.
|
||||
* @param __HANDLE__: specifies the DAC handle.
|
||||
* @param __FLAG__: specifies the flag to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DAC_FLAG_DMAUDR1: DMA underrun 1 flag
|
||||
* @arg DAC_FLAG_DMAUDR2: DMA underrun 2 flag
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
|
||||
|
||||
/** @brief Clear the DAC's flag.
|
||||
* @param __HANDLE__: specifies the DAC handle.
|
||||
* @param __FLAG__: specifies the flag to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DAC_FLAG_DMAUDR1: DMA underrun 1 flag
|
||||
* @arg DAC_FLAG_DMAUDR2: DMA underrun 2 flag
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include DAC HAL Extension module */
|
||||
#include "stm32f7xx_hal_dac_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup DAC_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DAC_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Initialization/de-initialization functions *********************************/
|
||||
HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac);
|
||||
HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac);
|
||||
void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac);
|
||||
void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DAC_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* I/O operation functions ****************************************************/
|
||||
HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment);
|
||||
HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel);
|
||||
uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DAC_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral Control functions ***********************************************/
|
||||
HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DAC_Exported_Functions_Group4
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State functions *************************************************/
|
||||
HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac);
|
||||
void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac);
|
||||
uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac);
|
||||
|
||||
void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac);
|
||||
void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac);
|
||||
void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac);
|
||||
void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup DAC_Private_Constants DAC Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup DAC_Private_Macros DAC Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0U)
|
||||
#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \
|
||||
((ALIGN) == DAC_ALIGN_12B_L) || \
|
||||
((ALIGN) == DAC_ALIGN_8B_R))
|
||||
#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \
|
||||
((CHANNEL) == DAC_CHANNEL_2))
|
||||
#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \
|
||||
((STATE) == DAC_OUTPUTBUFFER_DISABLE))
|
||||
|
||||
#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T8_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T5_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
|
||||
((TRIGGER) == DAC_TRIGGER_SOFTWARE))
|
||||
|
||||
/** @brief Set DHR12R1 alignment
|
||||
* @param __ALIGNMENT__: specifies the DAC alignment
|
||||
* @retval None
|
||||
*/
|
||||
#define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000008U) + (__ALIGNMENT__))
|
||||
|
||||
/** @brief Set DHR12R2 alignment
|
||||
* @param __ALIGNMENT__: specifies the DAC alignment
|
||||
* @retval None
|
||||
*/
|
||||
#define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000014U) + (__ALIGNMENT__))
|
||||
|
||||
/** @brief Set DHR12RD alignment
|
||||
* @param __ALIGNMENT__: specifies the DAC alignment
|
||||
* @retval None
|
||||
*/
|
||||
#define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000020U) + (__ALIGNMENT__))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup DAC_Private_Functions DAC Private Functions
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__STM32F7xx_HAL_DAC_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,191 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_hal_dac.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.2
|
||||
* @date 14-April-2017
|
||||
* @brief Header file of DAC HAL Extension module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F7xx_HAL_DAC_EX_H
|
||||
#define __STM32F7xx_HAL_DAC_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DACEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup DACEx_Exported_Constants DAC Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DACEx_lfsrunmask_triangleamplitude DAC LFS Run Mask Triangle Amplitude
|
||||
* @{
|
||||
*/
|
||||
#define DAC_LFSRUNMASK_BIT0 ((uint32_t)0x00000000U) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS1_0 ((uint32_t)DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS2_0 ((uint32_t)DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS3_0 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)/*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS4_0 ((uint32_t)DAC_CR_MAMP1_2) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS5_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS6_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS7_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS8_0 ((uint32_t)DAC_CR_MAMP1_3) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS9_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS10_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS11_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
|
||||
#define DAC_TRIANGLEAMPLITUDE_1 ((uint32_t)0x00000000U) /*!< Select max triangle amplitude of 1 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_3 ((uint32_t)DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_7 ((uint32_t)DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 7 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_15 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_31 ((uint32_t)DAC_CR_MAMP1_2) /*!< Select max triangle amplitude of 31 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_63 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 63 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_127 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 127 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_255 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 255 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_511 ((uint32_t)DAC_CR_MAMP1_3) /*!< Select max triangle amplitude of 511 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_1023 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 1023 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_2047 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 2047 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_4095 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 4095 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup DACEx_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DACEx_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Extension features functions ***********************************************/
|
||||
uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac);
|
||||
HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude);
|
||||
HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude);
|
||||
HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2);
|
||||
|
||||
void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac);
|
||||
void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac);
|
||||
void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef* hdac);
|
||||
void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef* hdac);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup DACEx_Private_Constants DAC Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup DACEx_Private_Macros DAC Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUNMASK_BIT0) || \
|
||||
((VALUE) == DAC_LFSRUNMASK_BITS1_0) || \
|
||||
((VALUE) == DAC_LFSRUNMASK_BITS2_0) || \
|
||||
((VALUE) == DAC_LFSRUNMASK_BITS3_0) || \
|
||||
((VALUE) == DAC_LFSRUNMASK_BITS4_0) || \
|
||||
((VALUE) == DAC_LFSRUNMASK_BITS5_0) || \
|
||||
((VALUE) == DAC_LFSRUNMASK_BITS6_0) || \
|
||||
((VALUE) == DAC_LFSRUNMASK_BITS7_0) || \
|
||||
((VALUE) == DAC_LFSRUNMASK_BITS8_0) || \
|
||||
((VALUE) == DAC_LFSRUNMASK_BITS9_0) || \
|
||||
((VALUE) == DAC_LFSRUNMASK_BITS10_0) || \
|
||||
((VALUE) == DAC_LFSRUNMASK_BITS11_0) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_1) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_3) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_7) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_15) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_31) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_63) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_127) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_255) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_511) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_1023) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_2047) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_4095))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup DACEx_Private_Functions DAC Private Functions
|
||||
* @{
|
||||
*/
|
||||
void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma);
|
||||
void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma);
|
||||
void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__STM32F7xx_HAL_DAC_EX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,628 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_hal_dcmi.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.2
|
||||
* @date 14-April-2017
|
||||
* @brief Header file of DCMI HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F7xx_HAL_DCMI_H
|
||||
#define __STM32F7xx_HAL_DCMI_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx_hal_def.h"
|
||||
|
||||
#if defined (DCMI)
|
||||
|
||||
/** @addtogroup STM32F7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DCMI DCMI
|
||||
* @brief DCMI HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup DCMI_Exported_Types DCMI Exported Types
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief HAL DCMI State structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_DCMI_STATE_RESET = 0x00U, /*!< DCMI not yet initialized or disabled */
|
||||
HAL_DCMI_STATE_READY = 0x01U, /*!< DCMI initialized and ready for use */
|
||||
HAL_DCMI_STATE_BUSY = 0x02U, /*!< DCMI internal processing is ongoing */
|
||||
HAL_DCMI_STATE_TIMEOUT = 0x03U, /*!< DCMI timeout state */
|
||||
HAL_DCMI_STATE_ERROR = 0x04U, /*!< DCMI error state */
|
||||
HAL_DCMI_STATE_SUSPENDED = 0x05U /*!< DCMI suspend state */
|
||||
}HAL_DCMI_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief DCMIEx Embedded Synchronisation CODE Init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t FrameStartCode; /*!< Specifies the code of the frame start delimiter. */
|
||||
uint8_t LineStartCode; /*!< Specifies the code of the line start delimiter. */
|
||||
uint8_t LineEndCode; /*!< Specifies the code of the line end delimiter. */
|
||||
uint8_t FrameEndCode; /*!< Specifies the code of the frame end delimiter. */
|
||||
}DCMI_CodesInitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief DCMI Init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t SynchroMode; /*!< Specifies the Synchronization Mode: Hardware or Embedded.
|
||||
This parameter can be a value of @ref DCMI_Synchronization_Mode */
|
||||
|
||||
uint32_t PCKPolarity; /*!< Specifies the Pixel clock polarity: Falling or Rising.
|
||||
This parameter can be a value of @ref DCMI_PIXCK_Polarity */
|
||||
|
||||
uint32_t VSPolarity; /*!< Specifies the Vertical synchronization polarity: High or Low.
|
||||
This parameter can be a value of @ref DCMI_VSYNC_Polarity */
|
||||
|
||||
uint32_t HSPolarity; /*!< Specifies the Horizontal synchronization polarity: High or Low.
|
||||
This parameter can be a value of @ref DCMI_HSYNC_Polarity */
|
||||
|
||||
uint32_t CaptureRate; /*!< Specifies the frequency of frame capture: All, 1/2 or 1/4.
|
||||
This parameter can be a value of @ref DCMI_Capture_Rate */
|
||||
|
||||
uint32_t ExtendedDataMode; /*!< Specifies the data width: 8-bit, 10-bit, 12-bit or 14-bit.
|
||||
This parameter can be a value of @ref DCMI_Extended_Data_Mode */
|
||||
|
||||
DCMI_CodesInitTypeDef SyncroCode; /*!< Specifies the code of the line/frame start delimiter and the
|
||||
line/frame end delimiter */
|
||||
|
||||
uint32_t JPEGMode; /*!< Enable or Disable the JPEG mode.
|
||||
This parameter can be a value of @ref DCMI_MODE_JPEG */
|
||||
|
||||
uint32_t ByteSelectMode; /*!< Specifies the data to be captured by the interface
|
||||
This parameter can be a value of @ref DCMI_Byte_Select_Mode */
|
||||
|
||||
uint32_t ByteSelectStart; /*!< Specifies if the data to be captured by the interface is even or odd
|
||||
This parameter can be a value of @ref DCMI_Byte_Select_Start */
|
||||
|
||||
uint32_t LineSelectMode; /*!< Specifies the line of data to be captured by the interface
|
||||
This parameter can be a value of @ref DCMI_Line_Select_Mode */
|
||||
|
||||
uint32_t LineSelectStart; /*!< Specifies if the line of data to be captured by the interface is even or odd
|
||||
This parameter can be a value of @ref DCMI_Line_Select_Start */
|
||||
}DCMI_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief DCMI handle Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
DCMI_TypeDef *Instance; /*!< DCMI Register base address */
|
||||
|
||||
DCMI_InitTypeDef Init; /*!< DCMI parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< DCMI locking object */
|
||||
|
||||
__IO HAL_DCMI_StateTypeDef State; /*!< DCMI state */
|
||||
|
||||
__IO uint32_t XferCount; /*!< DMA transfer counter */
|
||||
|
||||
__IO uint32_t XferSize; /*!< DMA transfer size */
|
||||
|
||||
uint32_t XferTransferNumber; /*!< DMA transfer number */
|
||||
|
||||
uint32_t pBuffPtr; /*!< Pointer to DMA output buffer */
|
||||
|
||||
DMA_HandleTypeDef *DMA_Handle; /*!< Pointer to the DMA handler */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< DCMI Error code */
|
||||
|
||||
}DCMI_HandleTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DCMI_Exported_Constants DCMI Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DCMI_Error_Code DCMI Error Code
|
||||
* @{
|
||||
*/
|
||||
#define HAL_DCMI_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
|
||||
#define HAL_DCMI_ERROR_OVR ((uint32_t)0x00000001U) /*!< Overrun error */
|
||||
#define HAL_DCMI_ERROR_SYNC ((uint32_t)0x00000002U) /*!< Synchronization error */
|
||||
#define HAL_DCMI_ERROR_TIMEOUT ((uint32_t)0x00000020U) /*!< Timeout error */
|
||||
#define HAL_DCMI_ERROR_DMA ((uint32_t)0x00000040U) /*!< DMA error */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DCMI_Capture_Mode DCMI Capture Mode
|
||||
* @{
|
||||
*/
|
||||
#define DCMI_MODE_CONTINUOUS ((uint32_t)0x00000000U) /*!< The received data are transferred continuously
|
||||
into the destination memory through the DMA */
|
||||
#define DCMI_MODE_SNAPSHOT ((uint32_t)DCMI_CR_CM) /*!< Once activated, the interface waits for the start of
|
||||
frame and then transfers a single frame through the DMA */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DCMI_Synchronization_Mode DCMI Synchronization Mode
|
||||
* @{
|
||||
*/
|
||||
#define DCMI_SYNCHRO_HARDWARE ((uint32_t)0x00000000U) /*!< Hardware synchronization data capture (frame/line start/stop)
|
||||
is synchronized with the HSYNC/VSYNC signals */
|
||||
#define DCMI_SYNCHRO_EMBEDDED ((uint32_t)DCMI_CR_ESS) /*!< Embedded synchronization data capture is synchronized with
|
||||
synchronization codes embedded in the data flow */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DCMI_PIXCK_Polarity DCMI PIXCK Polarity
|
||||
* @{
|
||||
*/
|
||||
#define DCMI_PCKPOLARITY_FALLING ((uint32_t)0x00000000U) /*!< Pixel clock active on Falling edge */
|
||||
#define DCMI_PCKPOLARITY_RISING ((uint32_t)DCMI_CR_PCKPOL) /*!< Pixel clock active on Rising edge */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DCMI_VSYNC_Polarity DCMI VSYNC Polarity
|
||||
* @{
|
||||
*/
|
||||
#define DCMI_VSPOLARITY_LOW ((uint32_t)0x00000000U) /*!< Vertical synchronization active Low */
|
||||
#define DCMI_VSPOLARITY_HIGH ((uint32_t)DCMI_CR_VSPOL) /*!< Vertical synchronization active High */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DCMI_HSYNC_Polarity DCMI HSYNC Polarity
|
||||
* @{
|
||||
*/
|
||||
#define DCMI_HSPOLARITY_LOW ((uint32_t)0x00000000U) /*!< Horizontal synchronization active Low */
|
||||
#define DCMI_HSPOLARITY_HIGH ((uint32_t)DCMI_CR_HSPOL) /*!< Horizontal synchronization active High */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DCMI_MODE_JPEG DCMI MODE JPEG
|
||||
* @{
|
||||
*/
|
||||
#define DCMI_JPEG_DISABLE ((uint32_t)0x00000000U) /*!< Mode JPEG Disabled */
|
||||
#define DCMI_JPEG_ENABLE ((uint32_t)DCMI_CR_JPEG) /*!< Mode JPEG Enabled */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DCMI_Capture_Rate DCMI Capture Rate
|
||||
* @{
|
||||
*/
|
||||
#define DCMI_CR_ALL_FRAME ((uint32_t)0x00000000U) /*!< All frames are captured */
|
||||
#define DCMI_CR_ALTERNATE_2_FRAME ((uint32_t)DCMI_CR_FCRC_0) /*!< Every alternate frame captured */
|
||||
#define DCMI_CR_ALTERNATE_4_FRAME ((uint32_t)DCMI_CR_FCRC_1) /*!< One frame in 4 frames captured */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DCMI_Extended_Data_Mode DCMI Extended Data Mode
|
||||
* @{
|
||||
*/
|
||||
#define DCMI_EXTEND_DATA_8B ((uint32_t)0x00000000U) /*!< Interface captures 8-bit data on every pixel clock */
|
||||
#define DCMI_EXTEND_DATA_10B ((uint32_t)DCMI_CR_EDM_0) /*!< Interface captures 10-bit data on every pixel clock */
|
||||
#define DCMI_EXTEND_DATA_12B ((uint32_t)DCMI_CR_EDM_1) /*!< Interface captures 12-bit data on every pixel clock */
|
||||
#define DCMI_EXTEND_DATA_14B ((uint32_t)(DCMI_CR_EDM_0 | DCMI_CR_EDM_1)) /*!< Interface captures 14-bit data on every pixel clock */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DCMI_Window_Coordinate DCMI Window Coordinate
|
||||
* @{
|
||||
*/
|
||||
#define DCMI_WINDOW_COORDINATE ((uint32_t)0x3FFFU) /*!< Window coordinate */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DCMI_Window_Height DCMI Window Height
|
||||
* @{
|
||||
*/
|
||||
#define DCMI_WINDOW_HEIGHT ((uint32_t)0x1FFFU) /*!< Window Height */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DCMI_interrupt_sources DCMI interrupt sources
|
||||
* @{
|
||||
*/
|
||||
#define DCMI_IT_FRAME ((uint32_t)DCMI_IER_FRAME_IE) /*!< Capture complete interrupt */
|
||||
#define DCMI_IT_OVR ((uint32_t)DCMI_IER_OVR_IE) /*!< Overrun interrupt */
|
||||
#define DCMI_IT_ERR ((uint32_t)DCMI_IER_ERR_IE) /*!< Synchronization error interrupt */
|
||||
#define DCMI_IT_VSYNC ((uint32_t)DCMI_IER_VSYNC_IE) /*!< VSYNC interrupt */
|
||||
#define DCMI_IT_LINE ((uint32_t)DCMI_IER_LINE_IE) /*!< Line interrupt */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DCMI_Flags DCMI Flags
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief DCMI SR register
|
||||
*/
|
||||
#define DCMI_FLAG_HSYNC ((uint32_t)DCMI_SR_INDEX|DCMI_SR_HSYNC) /*!< HSYNC pin state (active line / synchronization between lines) */
|
||||
#define DCMI_FLAG_VSYNC ((uint32_t)DCMI_SR_INDEX|DCMI_SR_VSYNC) /*!< VSYNC pin state (active frame / synchronization between frames) */
|
||||
#define DCMI_FLAG_FNE ((uint32_t)DCMI_SR_INDEX|DCMI_SR_FNE) /*!< FIFO not empty flag */
|
||||
/**
|
||||
* @brief DCMI RIS register
|
||||
*/
|
||||
#define DCMI_FLAG_FRAMERI ((uint32_t)DCMI_RIS_FRAME_RIS) /*!< Frame capture complete interrupt flag */
|
||||
#define DCMI_FLAG_OVRRI ((uint32_t)DCMI_RIS_OVR_RIS) /*!< Overrun interrupt flag */
|
||||
#define DCMI_FLAG_ERRRI ((uint32_t)DCMI_RIS_ERR_RIS) /*!< Synchronization error interrupt flag */
|
||||
#define DCMI_FLAG_VSYNCRI ((uint32_t)DCMI_RIS_VSYNC_RIS) /*!< VSYNC interrupt flag */
|
||||
#define DCMI_FLAG_LINERI ((uint32_t)DCMI_RIS_LINE_RIS) /*!< Line interrupt flag */
|
||||
/**
|
||||
* @brief DCMI MIS register
|
||||
*/
|
||||
#define DCMI_FLAG_FRAMEMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_FRAME_MIS) /*!< DCMI Frame capture complete masked interrupt status */
|
||||
#define DCMI_FLAG_OVRMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_OVR_MIS ) /*!< DCMI Overrun masked interrupt status */
|
||||
#define DCMI_FLAG_ERRMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_ERR_MIS ) /*!< DCMI Synchronization error masked interrupt status */
|
||||
#define DCMI_FLAG_VSYNCMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_VSYNC_MIS) /*!< DCMI VSYNC masked interrupt status */
|
||||
#define DCMI_FLAG_LINEMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_LINE_MIS ) /*!< DCMI Line masked interrupt status */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DCMI_Byte_Select_Mode DCMI Byte Select Mode
|
||||
* @{
|
||||
*/
|
||||
#define DCMI_BSM_ALL ((uint32_t)0x00000000U) /*!< Interface captures all received data */
|
||||
#define DCMI_BSM_OTHER ((uint32_t)DCMI_CR_BSM_0) /*!< Interface captures every other byte from the received data */
|
||||
#define DCMI_BSM_ALTERNATE_4 ((uint32_t)DCMI_CR_BSM_1) /*!< Interface captures one byte out of four */
|
||||
#define DCMI_BSM_ALTERNATE_2 ((uint32_t)(DCMI_CR_BSM_0 | DCMI_CR_BSM_1)) /*!< Interface captures two bytes out of four */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DCMI_Byte_Select_Start DCMI Byte Select Start
|
||||
* @{
|
||||
*/
|
||||
#define DCMI_OEBS_ODD ((uint32_t)0x00000000U) /*!< Interface captures first data from the frame/line start, second one being dropped */
|
||||
#define DCMI_OEBS_EVEN ((uint32_t)DCMI_CR_OEBS) /*!< Interface captures second data from the frame/line start, first one being dropped */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DCMI_Line_Select_Mode DCMI Line Select Mode
|
||||
* @{
|
||||
*/
|
||||
#define DCMI_LSM_ALL ((uint32_t)0x00000000U) /*!< Interface captures all received lines */
|
||||
#define DCMI_LSM_ALTERNATE_2 ((uint32_t)DCMI_CR_LSM) /*!< Interface captures one line out of two */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DCMI_Line_Select_Start DCMI Line Select Start
|
||||
* @{
|
||||
*/
|
||||
#define DCMI_OELS_ODD ((uint32_t)0x00000000U) /*!< Interface captures first line from the frame start, second one being dropped */
|
||||
#define DCMI_OELS_EVEN ((uint32_t)DCMI_CR_OELS) /*!< Interface captures second line from the frame start, first one being dropped */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup DCMI_Exported_Macros DCMI Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset DCMI handle state
|
||||
* @param __HANDLE__: specifies the DCMI handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DCMI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DCMI_STATE_RESET)
|
||||
|
||||
/**
|
||||
* @brief Enable the DCMI.
|
||||
* @param __HANDLE__: DCMI handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DCMI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DCMI_CR_ENABLE)
|
||||
|
||||
/**
|
||||
* @brief Disable the DCMI.
|
||||
* @param __HANDLE__: DCMI handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DCMI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(DCMI_CR_ENABLE))
|
||||
|
||||
/* Interrupt & Flag management */
|
||||
/**
|
||||
* @brief Get the DCMI pending flag.
|
||||
* @param __HANDLE__: DCMI handle
|
||||
* @param __FLAG__: Get the specified flag.
|
||||
* This parameter can be one of the following values (no combination allowed)
|
||||
* @arg DCMI_FLAG_HSYNC: HSYNC pin state (active line / synchronization between lines)
|
||||
* @arg DCMI_FLAG_VSYNC: VSYNC pin state (active frame / synchronization between frames)
|
||||
* @arg DCMI_FLAG_FNE: FIFO empty flag
|
||||
* @arg DCMI_FLAG_FRAMERI: Frame capture complete flag mask
|
||||
* @arg DCMI_FLAG_OVRRI: Overrun flag mask
|
||||
* @arg DCMI_FLAG_ERRRI: Synchronization error flag mask
|
||||
* @arg DCMI_FLAG_VSYNCRI: VSYNC flag mask
|
||||
* @arg DCMI_FLAG_LINERI: Line flag mask
|
||||
* @arg DCMI_FLAG_FRAMEMI: DCMI Capture complete masked interrupt status
|
||||
* @arg DCMI_FLAG_OVRMI: DCMI Overrun masked interrupt status
|
||||
* @arg DCMI_FLAG_ERRMI: DCMI Synchronization error masked interrupt status
|
||||
* @arg DCMI_FLAG_VSYNCMI: DCMI VSYNC masked interrupt status
|
||||
* @arg DCMI_FLAG_LINEMI: DCMI Line masked interrupt status
|
||||
* @retval The state of FLAG.
|
||||
*/
|
||||
#define __HAL_DCMI_GET_FLAG(__HANDLE__, __FLAG__)\
|
||||
((((__FLAG__) & (DCMI_SR_INDEX|DCMI_MIS_INDEX)) == 0x0)? ((__HANDLE__)->Instance->RIS & (__FLAG__)) :\
|
||||
(((__FLAG__) & DCMI_SR_INDEX) == 0x0)? ((__HANDLE__)->Instance->MIS & (__FLAG__)) : ((__HANDLE__)->Instance->SR & (__FLAG__)))
|
||||
|
||||
/**
|
||||
* @brief Clear the DCMI pending flags.
|
||||
* @param __HANDLE__: DCMI handle
|
||||
* @param __FLAG__: specifies the flag to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DCMI_FLAG_FRAMERI: Frame capture complete flag mask
|
||||
* @arg DCMI_FLAG_OVFRI: Overflow flag mask
|
||||
* @arg DCMI_FLAG_ERRRI: Synchronization error flag mask
|
||||
* @arg DCMI_FLAG_VSYNCRI: VSYNC flag mask
|
||||
* @arg DCMI_FLAG_LINERI: Line flag mask
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DCMI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
|
||||
|
||||
/**
|
||||
* @brief Enable the specified DCMI interrupts.
|
||||
* @param __HANDLE__: DCMI handle
|
||||
* @param __INTERRUPT__: specifies the DCMI interrupt sources to be enabled.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DCMI_IT_FRAME: Frame capture complete interrupt mask
|
||||
* @arg DCMI_IT_OVF: Overflow interrupt mask
|
||||
* @arg DCMI_IT_ERR: Synchronization error interrupt mask
|
||||
* @arg DCMI_IT_VSYNC: VSYNC interrupt mask
|
||||
* @arg DCMI_IT_LINE: Line interrupt mask
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DCMI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Disable the specified DCMI interrupts.
|
||||
* @param __HANDLE__: DCMI handle
|
||||
* @param __INTERRUPT__: specifies the DCMI interrupt sources to be enabled.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DCMI_IT_FRAME: Frame capture complete interrupt mask
|
||||
* @arg DCMI_IT_OVF: Overflow interrupt mask
|
||||
* @arg DCMI_IT_ERR: Synchronization error interrupt mask
|
||||
* @arg DCMI_IT_VSYNC: VSYNC interrupt mask
|
||||
* @arg DCMI_IT_LINE: Line interrupt mask
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DCMI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= ~(__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified DCMI interrupt has occurred or not.
|
||||
* @param __HANDLE__: DCMI handle
|
||||
* @param __INTERRUPT__: specifies the DCMI interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DCMI_IT_FRAME: Frame capture complete interrupt mask
|
||||
* @arg DCMI_IT_OVF: Overflow interrupt mask
|
||||
* @arg DCMI_IT_ERR: Synchronization error interrupt mask
|
||||
* @arg DCMI_IT_VSYNC: VSYNC interrupt mask
|
||||
* @arg DCMI_IT_LINE: Line interrupt mask
|
||||
* @retval The state of INTERRUPT.
|
||||
*/
|
||||
#define __HAL_DCMI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MISR & (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup DCMI_Exported_Functions DCMI Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DCMI_Exported_Functions_Group1 Initialization and Configuration functions
|
||||
* @{
|
||||
*/
|
||||
/* Initialization and de-initialization functions *****************************/
|
||||
HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi);
|
||||
HAL_StatusTypeDef HAL_DCMI_DeInit(DCMI_HandleTypeDef *hdcmi);
|
||||
void HAL_DCMI_MspInit(DCMI_HandleTypeDef* hdcmi);
|
||||
void HAL_DCMI_MspDeInit(DCMI_HandleTypeDef* hdcmi);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DCMI_Exported_Functions_Group2 IO operation functions
|
||||
* @{
|
||||
*/
|
||||
/* IO operation functions *****************************************************/
|
||||
HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length);
|
||||
HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi);
|
||||
HAL_StatusTypeDef HAL_DCMI_Suspend(DCMI_HandleTypeDef* hdcmi);
|
||||
HAL_StatusTypeDef HAL_DCMI_Resume(DCMI_HandleTypeDef* hdcmi);
|
||||
void HAL_DCMI_ErrorCallback(DCMI_HandleTypeDef *hdcmi);
|
||||
void HAL_DCMI_LineEventCallback(DCMI_HandleTypeDef *hdcmi);
|
||||
void HAL_DCMI_FrameEventCallback(DCMI_HandleTypeDef *hdcmi);
|
||||
void HAL_DCMI_VsyncEventCallback(DCMI_HandleTypeDef *hdcmi);
|
||||
void HAL_DCMI_VsyncCallback(DCMI_HandleTypeDef *hdcmi);
|
||||
void HAL_DCMI_HsyncCallback(DCMI_HandleTypeDef *hdcmi);
|
||||
void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DCMI_Exported_Functions_Group3 Peripheral Control functions
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral Control functions ***********************************************/
|
||||
HAL_StatusTypeDef HAL_DCMI_ConfigCrop(DCMI_HandleTypeDef *hdcmi, uint32_t X0, uint32_t Y0, uint32_t XSize, uint32_t YSize);
|
||||
HAL_StatusTypeDef HAL_DCMI_EnableCrop(DCMI_HandleTypeDef *hdcmi);
|
||||
HAL_StatusTypeDef HAL_DCMI_DisableCrop(DCMI_HandleTypeDef *hdcmi);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DCMI_Exported_Functions_Group4 Peripheral State functions
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State functions *************************************************/
|
||||
HAL_DCMI_StateTypeDef HAL_DCMI_GetState(DCMI_HandleTypeDef *hdcmi);
|
||||
uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup DCMI_Private_Constants DCMI Private Constants
|
||||
* @{
|
||||
*/
|
||||
#define DCMI_MIS_INDEX ((uint32_t)0x1000) /*!< DCMI MIS register index */
|
||||
#define DCMI_SR_INDEX ((uint32_t)0x2000) /*!< DCMI SR register index */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/** @defgroup DCMI_Private_Macros DCMI Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_DCMI_CAPTURE_MODE(MODE)(((MODE) == DCMI_MODE_CONTINUOUS) || \
|
||||
((MODE) == DCMI_MODE_SNAPSHOT))
|
||||
|
||||
#define IS_DCMI_SYNCHRO(MODE)(((MODE) == DCMI_SYNCHRO_HARDWARE) || \
|
||||
((MODE) == DCMI_SYNCHRO_EMBEDDED))
|
||||
|
||||
#define IS_DCMI_PCKPOLARITY(POLARITY)(((POLARITY) == DCMI_PCKPOLARITY_FALLING) || \
|
||||
((POLARITY) == DCMI_PCKPOLARITY_RISING))
|
||||
|
||||
#define IS_DCMI_VSPOLARITY(POLARITY)(((POLARITY) == DCMI_VSPOLARITY_LOW) || \
|
||||
((POLARITY) == DCMI_VSPOLARITY_HIGH))
|
||||
|
||||
#define IS_DCMI_HSPOLARITY(POLARITY)(((POLARITY) == DCMI_HSPOLARITY_LOW) || \
|
||||
((POLARITY) == DCMI_HSPOLARITY_HIGH))
|
||||
|
||||
#define IS_DCMI_MODE_JPEG(JPEG_MODE)(((JPEG_MODE) == DCMI_JPEG_DISABLE) || \
|
||||
((JPEG_MODE) == DCMI_JPEG_ENABLE))
|
||||
|
||||
#define IS_DCMI_CAPTURE_RATE(RATE) (((RATE) == DCMI_CR_ALL_FRAME) || \
|
||||
((RATE) == DCMI_CR_ALTERNATE_2_FRAME) || \
|
||||
((RATE) == DCMI_CR_ALTERNATE_4_FRAME))
|
||||
|
||||
#define IS_DCMI_EXTENDED_DATA(DATA)(((DATA) == DCMI_EXTEND_DATA_8B) || \
|
||||
((DATA) == DCMI_EXTEND_DATA_10B) || \
|
||||
((DATA) == DCMI_EXTEND_DATA_12B) || \
|
||||
((DATA) == DCMI_EXTEND_DATA_14B))
|
||||
|
||||
#define IS_DCMI_WINDOW_COORDINATE(COORDINATE) ((COORDINATE) <= DCMI_WINDOW_COORDINATE)
|
||||
|
||||
#define IS_DCMI_WINDOW_HEIGHT(HEIGHT) ((HEIGHT) <= DCMI_WINDOW_HEIGHT)
|
||||
|
||||
#define IS_DCMI_BYTE_SELECT_MODE(MODE)(((MODE) == DCMI_BSM_ALL) || \
|
||||
((MODE) == DCMI_BSM_OTHER) || \
|
||||
((MODE) == DCMI_BSM_ALTERNATE_4) || \
|
||||
((MODE) == DCMI_BSM_ALTERNATE_2))
|
||||
|
||||
#define IS_DCMI_BYTE_SELECT_START(POLARITY)(((POLARITY) == DCMI_OEBS_ODD) || \
|
||||
((POLARITY) == DCMI_OEBS_EVEN))
|
||||
|
||||
#define IS_DCMI_LINE_SELECT_MODE(MODE)(((MODE) == DCMI_LSM_ALL) || \
|
||||
((MODE) == DCMI_LSM_ALTERNATE_2))
|
||||
|
||||
#define IS_DCMI_LINE_SELECT_START(POLARITY)(((POLARITY) == DCMI_OELS_ODD) || \
|
||||
((POLARITY) == DCMI_OELS_EVEN))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @addtogroup DCMI_Private_Functions DCMI Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* DCMI */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F7xx_HAL_DCMI_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,55 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_hal_dcmi_ex.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.2
|
||||
* @date 14-April-2017
|
||||
* @brief Header file of DCMI Extension HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F7xx_HAL_DCMI_EX_H
|
||||
#define __STM32F7xx_HAL_DCMI_EX_H
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
#endif /* __STM32F7xx_HAL_DCMI_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,215 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_hal_def.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.2
|
||||
* @date 14-April-2017
|
||||
* @brief This file contains HAL common defines, enumeration, macros and
|
||||
* structures definitions.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F7xx_HAL_DEF
|
||||
#define __STM32F7xx_HAL_DEF
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx.h"
|
||||
#include "Legacy/stm32_hal_legacy.h"
|
||||
#include <stddef.h>
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief HAL Status structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_OK = 0x00U,
|
||||
HAL_ERROR = 0x01U,
|
||||
HAL_BUSY = 0x02U,
|
||||
HAL_TIMEOUT = 0x03U
|
||||
} HAL_StatusTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL Lock structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_UNLOCKED = 0x00,
|
||||
HAL_LOCKED = 0x01
|
||||
} HAL_LockTypeDef;
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
#define HAL_MAX_DELAY 0xFFFFFFFFU
|
||||
|
||||
#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) != RESET)
|
||||
#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == RESET)
|
||||
|
||||
#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \
|
||||
do{ \
|
||||
(__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \
|
||||
(__DMA_HANDLE__).Parent = (__HANDLE__); \
|
||||
} while(0)
|
||||
|
||||
#ifndef UNUSED
|
||||
#define UNUSED(x) ((void)(x))
|
||||
#endif
|
||||
|
||||
/** @brief Reset the Handle's State field.
|
||||
* @param __HANDLE__: specifies the Peripheral Handle.
|
||||
* @note This macro can be used for the following purpose:
|
||||
* - When the Handle is declared as local variable; before passing it as parameter
|
||||
* to HAL_PPP_Init() for the first time, it is mandatory to use this macro
|
||||
* to set to 0 the Handle's "State" field.
|
||||
* Otherwise, "State" field may have any random value and the first time the function
|
||||
* HAL_PPP_Init() is called, the low level hardware initialization will be missed
|
||||
* (i.e. HAL_PPP_MspInit() will not be executed).
|
||||
* - When there is a need to reconfigure the low level hardware: instead of calling
|
||||
* HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init().
|
||||
* In this later function, when the Handle's "State" field is set to 0, it will execute the function
|
||||
* HAL_PPP_MspInit() which will reconfigure the low level hardware.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U)
|
||||
|
||||
#if (USE_RTOS == 1)
|
||||
/* Reserved for future use */
|
||||
#error "USE_RTOS should be 0 in the current HAL release"
|
||||
#else
|
||||
#define __HAL_LOCK(__HANDLE__) \
|
||||
do{ \
|
||||
if((__HANDLE__)->Lock == HAL_LOCKED) \
|
||||
{ \
|
||||
return HAL_BUSY; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__HANDLE__)->Lock = HAL_LOCKED; \
|
||||
} \
|
||||
}while (0)
|
||||
|
||||
#define __HAL_UNLOCK(__HANDLE__) \
|
||||
do{ \
|
||||
(__HANDLE__)->Lock = HAL_UNLOCKED; \
|
||||
}while (0)
|
||||
#endif /* USE_RTOS */
|
||||
|
||||
#if defined ( __GNUC__ )
|
||||
#ifndef __weak
|
||||
#define __weak __attribute__((weak))
|
||||
#endif /* __weak */
|
||||
#ifndef __packed
|
||||
#define __packed __attribute__((__packed__))
|
||||
#endif /* __packed */
|
||||
#endif /* __GNUC__ */
|
||||
|
||||
|
||||
/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
|
||||
#if defined (__GNUC__) /* GNU Compiler */
|
||||
#ifndef __ALIGN_END
|
||||
#define __ALIGN_END __attribute__ ((aligned (4)))
|
||||
#endif /* __ALIGN_END */
|
||||
#ifndef __ALIGN_BEGIN
|
||||
#define __ALIGN_BEGIN
|
||||
#endif /* __ALIGN_BEGIN */
|
||||
#else
|
||||
#ifndef __ALIGN_END
|
||||
#define __ALIGN_END
|
||||
#endif /* __ALIGN_END */
|
||||
#ifndef __ALIGN_BEGIN
|
||||
#if defined (__CC_ARM) /* ARM Compiler */
|
||||
#define __ALIGN_BEGIN __align(4)
|
||||
#elif defined (__ICCARM__) /* IAR Compiler */
|
||||
#define __ALIGN_BEGIN
|
||||
#endif /* __CC_ARM */
|
||||
#endif /* __ALIGN_BEGIN */
|
||||
#endif /* __GNUC__ */
|
||||
|
||||
|
||||
/**
|
||||
* @brief __RAM_FUNC definition
|
||||
*/
|
||||
#if defined ( __CC_ARM )
|
||||
/* ARM Compiler
|
||||
------------
|
||||
RAM functions are defined using the toolchain options.
|
||||
Functions that are executed in RAM should reside in a separate source module.
|
||||
Using the 'Options for File' dialog you can simply change the 'Code / Const'
|
||||
area of a module to a memory space in physical RAM.
|
||||
Available memory areas are declared in the 'Target' tab of the 'Options for Target'
|
||||
dialog.
|
||||
*/
|
||||
#define __RAM_FUNC HAL_StatusTypeDef
|
||||
|
||||
#elif defined ( __ICCARM__ )
|
||||
/* ICCARM Compiler
|
||||
---------------
|
||||
RAM functions are defined using a specific toolchain keyword "__ramfunc".
|
||||
*/
|
||||
#define __RAM_FUNC __ramfunc HAL_StatusTypeDef
|
||||
|
||||
#elif defined ( __GNUC__ )
|
||||
/* GNU Compiler
|
||||
------------
|
||||
RAM functions are defined using a specific toolchain attribute
|
||||
"__attribute__((section(".RamFunc")))".
|
||||
*/
|
||||
#define __RAM_FUNC HAL_StatusTypeDef __attribute__((section(".RamFunc")))
|
||||
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief __NOINLINE definition
|
||||
*/
|
||||
#if defined ( __CC_ARM ) || defined ( __GNUC__ )
|
||||
/* ARM & GNUCompiler
|
||||
----------------
|
||||
*/
|
||||
#define __NOINLINE __attribute__ ( (noinline) )
|
||||
|
||||
#elif defined ( __ICCARM__ )
|
||||
/* ICCARM Compiler
|
||||
---------------
|
||||
*/
|
||||
#define __NOINLINE _Pragma("optimize = no_inline")
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ___STM32F7xx_HAL_DEF */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,710 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_hal_dfsdm.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.2
|
||||
* @date 14-April-2017
|
||||
* @brief Header file of DFSDM HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F7xx_HAL_DFSDM_H
|
||||
#define __STM32F7xx_HAL_DFSDM_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DFSDM
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup DFSDM_Exported_Types DFSDM Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief HAL DFSDM Channel states definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_DFSDM_CHANNEL_STATE_RESET = 0x00U, /*!< DFSDM channel not initialized */
|
||||
HAL_DFSDM_CHANNEL_STATE_READY = 0x01U, /*!< DFSDM channel initialized and ready for use */
|
||||
HAL_DFSDM_CHANNEL_STATE_ERROR = 0xFFU /*!< DFSDM channel state error */
|
||||
}HAL_DFSDM_Channel_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief DFSDM channel output clock structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
FunctionalState Activation; /*!< Output clock enable/disable */
|
||||
uint32_t Selection; /*!< Output clock is system clock or audio clock.
|
||||
This parameter can be a value of @ref DFSDM_Channel_OuputClock */
|
||||
uint32_t Divider; /*!< Output clock divider.
|
||||
This parameter must be a number between Min_Data = 2 and Max_Data = 256 */
|
||||
}DFSDM_Channel_OutputClockTypeDef;
|
||||
|
||||
/**
|
||||
* @brief DFSDM channel input structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Multiplexer; /*!< Input is external serial inputs or internal register.
|
||||
This parameter can be a value of @ref DFSDM_Channel_InputMultiplexer */
|
||||
uint32_t DataPacking; /*!< Standard, interleaved or dual mode for internal register.
|
||||
This parameter can be a value of @ref DFSDM_Channel_DataPacking */
|
||||
uint32_t Pins; /*!< Input pins are taken from same or following channel.
|
||||
This parameter can be a value of @ref DFSDM_Channel_InputPins */
|
||||
}DFSDM_Channel_InputTypeDef;
|
||||
|
||||
/**
|
||||
* @brief DFSDM channel serial interface structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Type; /*!< SPI or Manchester modes.
|
||||
This parameter can be a value of @ref DFSDM_Channel_SerialInterfaceType */
|
||||
uint32_t SpiClock; /*!< SPI clock select (external or internal with different sampling point).
|
||||
This parameter can be a value of @ref DFSDM_Channel_SpiClock */
|
||||
}DFSDM_Channel_SerialInterfaceTypeDef;
|
||||
|
||||
/**
|
||||
* @brief DFSDM channel analog watchdog structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t FilterOrder; /*!< Analog watchdog Sinc filter order.
|
||||
This parameter can be a value of @ref DFSDM_Channel_AwdFilterOrder */
|
||||
uint32_t Oversampling; /*!< Analog watchdog filter oversampling ratio.
|
||||
This parameter must be a number between Min_Data = 1 and Max_Data = 32 */
|
||||
}DFSDM_Channel_AwdTypeDef;
|
||||
|
||||
/**
|
||||
* @brief DFSDM channel init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
DFSDM_Channel_OutputClockTypeDef OutputClock; /*!< DFSDM channel output clock parameters */
|
||||
DFSDM_Channel_InputTypeDef Input; /*!< DFSDM channel input parameters */
|
||||
DFSDM_Channel_SerialInterfaceTypeDef SerialInterface; /*!< DFSDM channel serial interface parameters */
|
||||
DFSDM_Channel_AwdTypeDef Awd; /*!< DFSDM channel analog watchdog parameters */
|
||||
int32_t Offset; /*!< DFSDM channel offset.
|
||||
This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */
|
||||
uint32_t RightBitShift; /*!< DFSDM channel right bit shift.
|
||||
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
|
||||
}DFSDM_Channel_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief DFSDM channel handle structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
DFSDM_Channel_TypeDef *Instance; /*!< DFSDM channel instance */
|
||||
DFSDM_Channel_InitTypeDef Init; /*!< DFSDM channel init parameters */
|
||||
HAL_DFSDM_Channel_StateTypeDef State; /*!< DFSDM channel state */
|
||||
}DFSDM_Channel_HandleTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL DFSDM Filter states definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_DFSDM_FILTER_STATE_RESET = 0x00U, /*!< DFSDM filter not initialized */
|
||||
HAL_DFSDM_FILTER_STATE_READY = 0x01U, /*!< DFSDM filter initialized and ready for use */
|
||||
HAL_DFSDM_FILTER_STATE_REG = 0x02U, /*!< DFSDM filter regular conversion in progress */
|
||||
HAL_DFSDM_FILTER_STATE_INJ = 0x03U, /*!< DFSDM filter injected conversion in progress */
|
||||
HAL_DFSDM_FILTER_STATE_REG_INJ = 0x04U, /*!< DFSDM filter regular and injected conversions in progress */
|
||||
HAL_DFSDM_FILTER_STATE_ERROR = 0xFFU /*!< DFSDM filter state error */
|
||||
}HAL_DFSDM_Filter_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief DFSDM filter regular conversion parameters structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Trigger; /*!< Trigger used to start regular conversion: software or synchronous.
|
||||
This parameter can be a value of @ref DFSDM_Filter_Trigger */
|
||||
FunctionalState FastMode; /*!< Enable/disable fast mode for regular conversion */
|
||||
FunctionalState DmaMode; /*!< Enable/disable DMA for regular conversion */
|
||||
}DFSDM_Filter_RegularParamTypeDef;
|
||||
|
||||
/**
|
||||
* @brief DFSDM filter injected conversion parameters structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Trigger; /*!< Trigger used to start injected conversion: software, external or synchronous.
|
||||
This parameter can be a value of @ref DFSDM_Filter_Trigger */
|
||||
FunctionalState ScanMode; /*!< Enable/disable scanning mode for injected conversion */
|
||||
FunctionalState DmaMode; /*!< Enable/disable DMA for injected conversion */
|
||||
uint32_t ExtTrigger; /*!< External trigger.
|
||||
This parameter can be a value of @ref DFSDM_Filter_ExtTrigger */
|
||||
uint32_t ExtTriggerEdge; /*!< External trigger edge: rising, falling or both.
|
||||
This parameter can be a value of @ref DFSDM_Filter_ExtTriggerEdge */
|
||||
}DFSDM_Filter_InjectedParamTypeDef;
|
||||
|
||||
/**
|
||||
* @brief DFSDM filter parameters structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t SincOrder; /*!< Sinc filter order.
|
||||
This parameter can be a value of @ref DFSDM_Filter_SincOrder */
|
||||
uint32_t Oversampling; /*!< Filter oversampling ratio.
|
||||
This parameter must be a number between Min_Data = 1 and Max_Data = 1024 */
|
||||
uint32_t IntOversampling; /*!< Integrator oversampling ratio.
|
||||
This parameter must be a number between Min_Data = 1 and Max_Data = 256 */
|
||||
}DFSDM_Filter_FilterParamTypeDef;
|
||||
|
||||
/**
|
||||
* @brief DFSDM filter init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
DFSDM_Filter_RegularParamTypeDef RegularParam; /*!< DFSDM regular conversion parameters */
|
||||
DFSDM_Filter_InjectedParamTypeDef InjectedParam; /*!< DFSDM injected conversion parameters */
|
||||
DFSDM_Filter_FilterParamTypeDef FilterParam; /*!< DFSDM filter parameters */
|
||||
}DFSDM_Filter_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief DFSDM filter handle structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
DFSDM_Filter_TypeDef *Instance; /*!< DFSDM filter instance */
|
||||
DFSDM_Filter_InitTypeDef Init; /*!< DFSDM filter init parameters */
|
||||
DMA_HandleTypeDef *hdmaReg; /*!< Pointer on DMA handler for regular conversions */
|
||||
DMA_HandleTypeDef *hdmaInj; /*!< Pointer on DMA handler for injected conversions */
|
||||
uint32_t RegularContMode; /*!< Regular conversion continuous mode */
|
||||
uint32_t RegularTrigger; /*!< Trigger used for regular conversion */
|
||||
uint32_t InjectedTrigger; /*!< Trigger used for injected conversion */
|
||||
uint32_t ExtTriggerEdge; /*!< Rising, falling or both edges selected */
|
||||
FunctionalState InjectedScanMode; /*!< Injected scanning mode */
|
||||
uint32_t InjectedChannelsNbr; /*!< Number of channels in injected sequence */
|
||||
uint32_t InjConvRemaining; /*!< Injected conversions remaining */
|
||||
HAL_DFSDM_Filter_StateTypeDef State; /*!< DFSDM filter state */
|
||||
uint32_t ErrorCode; /*!< DFSDM filter error code */
|
||||
}DFSDM_Filter_HandleTypeDef;
|
||||
|
||||
/**
|
||||
* @brief DFSDM filter analog watchdog parameters structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t DataSource; /*!< Values from digital filter or from channel watchdog filter.
|
||||
This parameter can be a value of @ref DFSDM_Filter_AwdDataSource */
|
||||
uint32_t Channel; /*!< Analog watchdog channel selection.
|
||||
This parameter can be a values combination of @ref DFSDM_Channel_Selection */
|
||||
int32_t HighThreshold; /*!< High threshold for the analog watchdog.
|
||||
This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */
|
||||
int32_t LowThreshold; /*!< Low threshold for the analog watchdog.
|
||||
This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */
|
||||
uint32_t HighBreakSignal; /*!< Break signal assigned to analog watchdog high threshold event.
|
||||
This parameter can be a values combination of @ref DFSDM_BreakSignals */
|
||||
uint32_t LowBreakSignal; /*!< Break signal assigned to analog watchdog low threshold event.
|
||||
This parameter can be a values combination of @ref DFSDM_BreakSignals */
|
||||
}DFSDM_Filter_AwdParamTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* End of exported types -----------------------------------------------------*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup DFSDM_Exported_Constants DFSDM Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DFSDM_Channel_OuputClock DFSDM channel output clock selection
|
||||
* @{
|
||||
*/
|
||||
#define DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM ((uint32_t)0x00000000U) /*!< Source for ouput clock is system clock */
|
||||
#define DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO DFSDM_CHCFGR1_CKOUTSRC /*!< Source for ouput clock is audio clock */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DFSDM_Channel_InputMultiplexer DFSDM channel input multiplexer
|
||||
* @{
|
||||
*/
|
||||
#define DFSDM_CHANNEL_EXTERNAL_INPUTS ((uint32_t)0x00000000U) /*!< Data are taken from external inputs */
|
||||
#define DFSDM_CHANNEL_INTERNAL_REGISTER DFSDM_CHCFGR1_DATMPX_1 /*!< Data are taken from internal register */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DFSDM_Channel_DataPacking DFSDM channel input data packing
|
||||
* @{
|
||||
*/
|
||||
#define DFSDM_CHANNEL_STANDARD_MODE ((uint32_t)0x00000000U) /*!< Standard data packing mode */
|
||||
#define DFSDM_CHANNEL_INTERLEAVED_MODE DFSDM_CHCFGR1_DATPACK_0 /*!< Interleaved data packing mode */
|
||||
#define DFSDM_CHANNEL_DUAL_MODE DFSDM_CHCFGR1_DATPACK_1 /*!< Dual data packing mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DFSDM_Channel_InputPins DFSDM channel input pins
|
||||
* @{
|
||||
*/
|
||||
#define DFSDM_CHANNEL_SAME_CHANNEL_PINS ((uint32_t)0x00000000U) /*!< Input from pins on same channel */
|
||||
#define DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS DFSDM_CHCFGR1_CHINSEL /*!< Input from pins on following channel */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DFSDM_Channel_SerialInterfaceType DFSDM channel serial interface type
|
||||
* @{
|
||||
*/
|
||||
#define DFSDM_CHANNEL_SPI_RISING ((uint32_t)0x00000000U) /*!< SPI with rising edge */
|
||||
#define DFSDM_CHANNEL_SPI_FALLING DFSDM_CHCFGR1_SITP_0 /*!< SPI with falling edge */
|
||||
#define DFSDM_CHANNEL_MANCHESTER_RISING DFSDM_CHCFGR1_SITP_1 /*!< Manchester with rising edge */
|
||||
#define DFSDM_CHANNEL_MANCHESTER_FALLING DFSDM_CHCFGR1_SITP /*!< Manchester with falling edge */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DFSDM_Channel_SpiClock DFSDM channel SPI clock selection
|
||||
* @{
|
||||
*/
|
||||
#define DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL ((uint32_t)0x00000000U) /*!< External SPI clock */
|
||||
#define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL DFSDM_CHCFGR1_SPICKSEL_0 /*!< Internal SPI clock */
|
||||
#define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING DFSDM_CHCFGR1_SPICKSEL_1 /*!< Internal SPI clock divided by 2, falling edge */
|
||||
#define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING DFSDM_CHCFGR1_SPICKSEL /*!< Internal SPI clock divided by 2, rising edge */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DFSDM_Channel_AwdFilterOrder DFSDM channel analog watchdog filter order
|
||||
* @{
|
||||
*/
|
||||
#define DFSDM_CHANNEL_FASTSINC_ORDER ((uint32_t)0x00000000U) /*!< FastSinc filter type */
|
||||
#define DFSDM_CHANNEL_SINC1_ORDER DFSDM_CHAWSCDR_AWFORD_0 /*!< Sinc 1 filter type */
|
||||
#define DFSDM_CHANNEL_SINC2_ORDER DFSDM_CHAWSCDR_AWFORD_1 /*!< Sinc 2 filter type */
|
||||
#define DFSDM_CHANNEL_SINC3_ORDER DFSDM_CHAWSCDR_AWFORD /*!< Sinc 3 filter type */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DFSDM_Filter_Trigger DFSDM filter conversion trigger
|
||||
* @{
|
||||
*/
|
||||
#define DFSDM_FILTER_SW_TRIGGER ((uint32_t)0x00000000U) /*!< Software trigger */
|
||||
#define DFSDM_FILTER_SYNC_TRIGGER ((uint32_t)0x00000001U) /*!< Synchronous with DFSDM_FLT0 */
|
||||
#define DFSDM_FILTER_EXT_TRIGGER ((uint32_t)0x00000002U) /*!< External trigger (only for injected conversion) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DFSDM_Filter_ExtTrigger DFSDM filter external trigger
|
||||
* @{
|
||||
*/
|
||||
#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO ((uint32_t)0x00000000U) /*!< For DFSDM filter 0, 1, 2 and 3 */
|
||||
#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2 DFSDM_FLTCR1_JEXTSEL_0 /*!< For DFSDM filter 0, 1, 2 and 3 */
|
||||
#define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO DFSDM_FLTCR1_JEXTSEL_1 /*!< For DFSDM filter 0, 1, 2 and 3 */
|
||||
#define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For DFSDM filter 0, 1, 2 and 3 */
|
||||
#define DFSDM_FILTER_EXT_TRIG_TIM3_TRGO DFSDM_FLTCR1_JEXTSEL_2 /*!< For DFSDM filter 0, 1, 2 and 3 */
|
||||
#define DFSDM_FILTER_EXT_TRIG_TIM4_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 0, 1, 2 and 3 */
|
||||
#define DFSDM_FILTER_EXT_TRIG_TIM10_OC1 (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 0, 1, 2 and 3 */
|
||||
#define DFSDM_FILTER_EXT_TRIG_TIM6_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1 | \
|
||||
DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 0, 1, 2 and 3 */
|
||||
#define DFSDM_FILTER_EXT_TRIG_TIM7_TRGO DFSDM_FLTCR1_JEXTSEL_3 /*!< For DFSDM filter 0, 1, 2 and 3 */
|
||||
#define DFSDM_FILTER_EXT_TRIG_EXTI11 (DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_4) /*!< For DFSDM filter 0, 1, 2 and 3 */
|
||||
#define DFSDM_FILTER_EXT_TRIG_EXTI15 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_3 | \
|
||||
DFSDM_FLTCR1_JEXTSEL_4) /*!< For DFSDM filter 0, 1, 2 and 3 */
|
||||
#define DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_3 | \
|
||||
DFSDM_FLTCR1_JEXTSEL_4) /*!< For DFSDM filter 0, 1, 2 and 3 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DFSDM_Filter_ExtTriggerEdge DFSDM filter external trigger edge
|
||||
* @{
|
||||
*/
|
||||
#define DFSDM_FILTER_EXT_TRIG_RISING_EDGE DFSDM_FLTCR1_JEXTEN_0 /*!< External rising edge */
|
||||
#define DFSDM_FILTER_EXT_TRIG_FALLING_EDGE DFSDM_FLTCR1_JEXTEN_1 /*!< External falling edge */
|
||||
#define DFSDM_FILTER_EXT_TRIG_BOTH_EDGES DFSDM_FLTCR1_JEXTEN /*!< External rising and falling edges */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DFSDM_Filter_SincOrder DFSDM filter sinc order
|
||||
* @{
|
||||
*/
|
||||
#define DFSDM_FILTER_FASTSINC_ORDER ((uint32_t)0x00000000U) /*!< FastSinc filter type */
|
||||
#define DFSDM_FILTER_SINC1_ORDER DFSDM_FLTFCR_FORD_0 /*!< Sinc 1 filter type */
|
||||
#define DFSDM_FILTER_SINC2_ORDER DFSDM_FLTFCR_FORD_1 /*!< Sinc 2 filter type */
|
||||
#define DFSDM_FILTER_SINC3_ORDER (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_1) /*!< Sinc 3 filter type */
|
||||
#define DFSDM_FILTER_SINC4_ORDER DFSDM_FLTFCR_FORD_2 /*!< Sinc 4 filter type */
|
||||
#define DFSDM_FILTER_SINC5_ORDER (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_2) /*!< Sinc 5 filter type */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DFSDM_Filter_AwdDataSource DFSDM filter analog watchdog data source
|
||||
* @{
|
||||
*/
|
||||
#define DFSDM_FILTER_AWD_FILTER_DATA ((uint32_t)0x00000000U) /*!< From digital filter */
|
||||
#define DFSDM_FILTER_AWD_CHANNEL_DATA DFSDM_FLTCR1_AWFSEL /*!< From analog watchdog channel */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DFSDM_Filter_ErrorCode DFSDM filter error code
|
||||
* @{
|
||||
*/
|
||||
#define DFSDM_FILTER_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
|
||||
#define DFSDM_FILTER_ERROR_REGULAR_OVERRUN ((uint32_t)0x00000001U) /*!< Overrun occurs during regular conversion */
|
||||
#define DFSDM_FILTER_ERROR_INJECTED_OVERRUN ((uint32_t)0x00000002U) /*!< Overrun occurs during injected conversion */
|
||||
#define DFSDM_FILTER_ERROR_DMA ((uint32_t)0x00000003U) /*!< DMA error occurs */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DFSDM_BreakSignals DFSDM break signals
|
||||
* @{
|
||||
*/
|
||||
#define DFSDM_NO_BREAK_SIGNAL ((uint32_t)0x00000000U) /*!< No break signal */
|
||||
#define DFSDM_BREAK_SIGNAL_0 ((uint32_t)0x00000001U) /*!< Break signal 0 */
|
||||
#define DFSDM_BREAK_SIGNAL_1 ((uint32_t)0x00000002U) /*!< Break signal 1 */
|
||||
#define DFSDM_BREAK_SIGNAL_2 ((uint32_t)0x00000004U) /*!< Break signal 2 */
|
||||
#define DFSDM_BREAK_SIGNAL_3 ((uint32_t)0x00000008U) /*!< Break signal 3 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DFSDM_Channel_Selection DFSDM Channel Selection
|
||||
* @{
|
||||
*/
|
||||
/* DFSDM Channels ------------------------------------------------------------*/
|
||||
/* The DFSDM channels are defined as follows:
|
||||
- in 16-bit LSB the channel mask is set
|
||||
- in 16-bit MSB the channel number is set
|
||||
e.g. for channel 5 definition:
|
||||
- the channel mask is 0x00000020 (bit 5 is set)
|
||||
- the channel number 5 is 0x00050000
|
||||
--> Consequently, channel 5 definition is 0x00000020 | 0x00050000 = 0x00050020 */
|
||||
#define DFSDM_CHANNEL_0 ((uint32_t)0x00000001U)
|
||||
#define DFSDM_CHANNEL_1 ((uint32_t)0x00010002U)
|
||||
#define DFSDM_CHANNEL_2 ((uint32_t)0x00020004U)
|
||||
#define DFSDM_CHANNEL_3 ((uint32_t)0x00030008U)
|
||||
#define DFSDM_CHANNEL_4 ((uint32_t)0x00040010U)
|
||||
#define DFSDM_CHANNEL_5 ((uint32_t)0x00050020U)
|
||||
#define DFSDM_CHANNEL_6 ((uint32_t)0x00060040U)
|
||||
#define DFSDM_CHANNEL_7 ((uint32_t)0x00070080U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DFSDM_ContinuousMode DFSDM Continuous Mode
|
||||
* @{
|
||||
*/
|
||||
#define DFSDM_CONTINUOUS_CONV_OFF ((uint32_t)0x00000000U) /*!< Conversion are not continuous */
|
||||
#define DFSDM_CONTINUOUS_CONV_ON ((uint32_t)0x00000001U) /*!< Conversion are continuous */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DFSDM_AwdThreshold DFSDM analog watchdog threshold
|
||||
* @{
|
||||
*/
|
||||
#define DFSDM_AWD_HIGH_THRESHOLD ((uint32_t)0x00000000U) /*!< Analog watchdog high threshold */
|
||||
#define DFSDM_AWD_LOW_THRESHOLD ((uint32_t)0x00000001U) /*!< Analog watchdog low threshold */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* End of exported constants -------------------------------------------------*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup DFSDM_Exported_Macros DFSDM Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset DFSDM channel handle state.
|
||||
* @param __HANDLE__: DFSDM channel handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_CHANNEL_STATE_RESET)
|
||||
|
||||
/** @brief Reset DFSDM filter handle state.
|
||||
* @param __HANDLE__: DFSDM filter handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DFSDM_FILTER_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_FILTER_STATE_RESET)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* End of exported macros ----------------------------------------------------*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup DFSDM_Exported_Functions DFSDM Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DFSDM_Exported_Functions_Group1_Channel Channel initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
/* Channel initialization and de-initialization functions *********************/
|
||||
HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
|
||||
HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
|
||||
void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
|
||||
void HAL_DFSDM_ChannelMspDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DFSDM_Exported_Functions_Group2_Channel Channel operation functions
|
||||
* @{
|
||||
*/
|
||||
/* Channel operation functions ************************************************/
|
||||
HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
|
||||
HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
|
||||
HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
|
||||
HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
|
||||
|
||||
HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal);
|
||||
HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal);
|
||||
HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
|
||||
HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
|
||||
|
||||
int16_t HAL_DFSDM_ChannelGetAwdValue(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
|
||||
HAL_StatusTypeDef HAL_DFSDM_ChannelModifyOffset(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, int32_t Offset);
|
||||
|
||||
HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout);
|
||||
|
||||
void HAL_DFSDM_ChannelCkabCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
|
||||
void HAL_DFSDM_ChannelScdCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DFSDM_Exported_Functions_Group3_Channel Channel state function
|
||||
* @{
|
||||
*/
|
||||
/* Channel state function *****************************************************/
|
||||
HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DFSDM_Exported_Functions_Group1_Filter Filter initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
/* Filter initialization and de-initialization functions *********************/
|
||||
HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
|
||||
HAL_StatusTypeDef HAL_DFSDM_FilterDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
|
||||
void HAL_DFSDM_FilterMspInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
|
||||
void HAL_DFSDM_FilterMspDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DFSDM_Exported_Functions_Group2_Filter Filter control functions
|
||||
* @{
|
||||
*/
|
||||
/* Filter control functions *********************/
|
||||
HAL_StatusTypeDef HAL_DFSDM_FilterConfigRegChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
|
||||
uint32_t Channel,
|
||||
uint32_t ContinuousMode);
|
||||
HAL_StatusTypeDef HAL_DFSDM_FilterConfigInjChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
|
||||
uint32_t Channel);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DFSDM_Exported_Functions_Group3_Filter Filter operation functions
|
||||
* @{
|
||||
*/
|
||||
/* Filter operation functions *********************/
|
||||
HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
|
||||
HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
|
||||
HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length);
|
||||
HAL_StatusTypeDef HAL_DFSDM_FilterRegularMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length);
|
||||
HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
|
||||
HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
|
||||
HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
|
||||
HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
|
||||
HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
|
||||
HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length);
|
||||
HAL_StatusTypeDef HAL_DFSDM_FilterInjectedMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length);
|
||||
HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
|
||||
HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
|
||||
HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
|
||||
HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
|
||||
DFSDM_Filter_AwdParamTypeDef* awdParam);
|
||||
HAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
|
||||
HAL_StatusTypeDef HAL_DFSDM_FilterExdStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
|
||||
|
||||
int32_t HAL_DFSDM_FilterGetRegularValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);
|
||||
int32_t HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);
|
||||
int32_t HAL_DFSDM_FilterGetExdMaxValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);
|
||||
int32_t HAL_DFSDM_FilterGetExdMinValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);
|
||||
uint32_t HAL_DFSDM_FilterGetConvTimeValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
|
||||
|
||||
void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
|
||||
|
||||
HAL_StatusTypeDef HAL_DFSDM_FilterPollForRegConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_DFSDM_FilterPollForInjConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout);
|
||||
|
||||
void HAL_DFSDM_FilterRegConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
|
||||
void HAL_DFSDM_FilterRegConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
|
||||
void HAL_DFSDM_FilterInjConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
|
||||
void HAL_DFSDM_FilterInjConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
|
||||
void HAL_DFSDM_FilterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel, uint32_t Threshold);
|
||||
void HAL_DFSDM_FilterErrorCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DFSDM_Exported_Functions_Group4_Filter Filter state functions
|
||||
* @{
|
||||
*/
|
||||
/* Filter state functions *****************************************************/
|
||||
HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
|
||||
uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* End of exported functions -------------------------------------------------*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup DFSDM_Private_Macros DFSDM Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_DFSDM_CHANNEL_OUTPUT_CLOCK(CLOCK) (((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM) || \
|
||||
((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO))
|
||||
#define IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(DIVIDER) ((2 <= (DIVIDER)) && ((DIVIDER) <= 256))
|
||||
#define IS_DFSDM_CHANNEL_INPUT(INPUT) (((INPUT) == DFSDM_CHANNEL_EXTERNAL_INPUTS) || \
|
||||
((INPUT) == DFSDM_CHANNEL_INTERNAL_REGISTER))
|
||||
#define IS_DFSDM_CHANNEL_DATA_PACKING(MODE) (((MODE) == DFSDM_CHANNEL_STANDARD_MODE) || \
|
||||
((MODE) == DFSDM_CHANNEL_INTERLEAVED_MODE) || \
|
||||
((MODE) == DFSDM_CHANNEL_DUAL_MODE))
|
||||
#define IS_DFSDM_CHANNEL_INPUT_PINS(PINS) (((PINS) == DFSDM_CHANNEL_SAME_CHANNEL_PINS) || \
|
||||
((PINS) == DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS))
|
||||
#define IS_DFSDM_CHANNEL_SERIAL_INTERFACE_TYPE(MODE) (((MODE) == DFSDM_CHANNEL_SPI_RISING) || \
|
||||
((MODE) == DFSDM_CHANNEL_SPI_FALLING) || \
|
||||
((MODE) == DFSDM_CHANNEL_MANCHESTER_RISING) || \
|
||||
((MODE) == DFSDM_CHANNEL_MANCHESTER_FALLING))
|
||||
#define IS_DFSDM_CHANNEL_SPI_CLOCK(TYPE) (((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL) || \
|
||||
((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL) || \
|
||||
((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING) || \
|
||||
((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING))
|
||||
#define IS_DFSDM_CHANNEL_FILTER_ORDER(ORDER) (((ORDER) == DFSDM_CHANNEL_FASTSINC_ORDER) || \
|
||||
((ORDER) == DFSDM_CHANNEL_SINC1_ORDER) || \
|
||||
((ORDER) == DFSDM_CHANNEL_SINC2_ORDER) || \
|
||||
((ORDER) == DFSDM_CHANNEL_SINC3_ORDER))
|
||||
#define IS_DFSDM_CHANNEL_FILTER_OVS_RATIO(RATIO) ((1 <= (RATIO)) && ((RATIO) <= 32))
|
||||
#define IS_DFSDM_CHANNEL_OFFSET(VALUE) ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607))
|
||||
#define IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT(VALUE) ((VALUE) <= 0x1F)
|
||||
#define IS_DFSDM_CHANNEL_SCD_THRESHOLD(VALUE) ((VALUE) <= 0xFF)
|
||||
#define IS_DFSDM_FILTER_REG_TRIGGER(TRIG) (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \
|
||||
((TRIG) == DFSDM_FILTER_SYNC_TRIGGER))
|
||||
#define IS_DFSDM_FILTER_INJ_TRIGGER(TRIG) (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \
|
||||
((TRIG) == DFSDM_FILTER_SYNC_TRIGGER) || \
|
||||
((TRIG) == DFSDM_FILTER_EXT_TRIGGER))
|
||||
#define IS_DFSDM_FILTER_EXT_TRIG(TRIG) (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) || \
|
||||
((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2)|| \
|
||||
((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO) || \
|
||||
((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2)|| \
|
||||
((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM3_TRGO) || \
|
||||
((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM4_TRGO) || \
|
||||
((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM10_OC1) || \
|
||||
((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM6_TRGO) || \
|
||||
((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM7_TRGO) || \
|
||||
((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11) || \
|
||||
((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15) ||\
|
||||
((TRIG) == DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT))
|
||||
#define IS_DFSDM_FILTER_EXT_TRIG_EDGE(EDGE) (((EDGE) == DFSDM_FILTER_EXT_TRIG_RISING_EDGE) || \
|
||||
((EDGE) == DFSDM_FILTER_EXT_TRIG_FALLING_EDGE) || \
|
||||
((EDGE) == DFSDM_FILTER_EXT_TRIG_BOTH_EDGES))
|
||||
#define IS_DFSDM_FILTER_SINC_ORDER(ORDER) (((ORDER) == DFSDM_FILTER_FASTSINC_ORDER) || \
|
||||
((ORDER) == DFSDM_FILTER_SINC1_ORDER) || \
|
||||
((ORDER) == DFSDM_FILTER_SINC2_ORDER) || \
|
||||
((ORDER) == DFSDM_FILTER_SINC3_ORDER) || \
|
||||
((ORDER) == DFSDM_FILTER_SINC4_ORDER) || \
|
||||
((ORDER) == DFSDM_FILTER_SINC5_ORDER))
|
||||
#define IS_DFSDM_FILTER_OVS_RATIO(RATIO) ((1 <= (RATIO)) && ((RATIO) <= 1024))
|
||||
#define IS_DFSDM_FILTER_INTEGRATOR_OVS_RATIO(RATIO) ((1 <= (RATIO)) && ((RATIO) <= 256))
|
||||
#define IS_DFSDM_FILTER_AWD_DATA_SOURCE(DATA) (((DATA) == DFSDM_FILTER_AWD_FILTER_DATA) || \
|
||||
((DATA) == DFSDM_FILTER_AWD_CHANNEL_DATA))
|
||||
#define IS_DFSDM_FILTER_AWD_THRESHOLD(VALUE) ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607))
|
||||
#define IS_DFSDM_BREAK_SIGNALS(VALUE) ((VALUE) <= 0xFU)
|
||||
#define IS_DFSDM_REGULAR_CHANNEL(CHANNEL) (((CHANNEL) == DFSDM_CHANNEL_0) || \
|
||||
((CHANNEL) == DFSDM_CHANNEL_1) || \
|
||||
((CHANNEL) == DFSDM_CHANNEL_2) || \
|
||||
((CHANNEL) == DFSDM_CHANNEL_3) || \
|
||||
((CHANNEL) == DFSDM_CHANNEL_4) || \
|
||||
((CHANNEL) == DFSDM_CHANNEL_5) || \
|
||||
((CHANNEL) == DFSDM_CHANNEL_6) || \
|
||||
((CHANNEL) == DFSDM_CHANNEL_7))
|
||||
#define IS_DFSDM_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) != 0) && ((CHANNEL) <= 0x000F00FFU))
|
||||
#define IS_DFSDM_CONTINUOUS_MODE(MODE) (((MODE) == DFSDM_CONTINUOUS_CONV_OFF) || \
|
||||
((MODE) == DFSDM_CONTINUOUS_CONV_ON))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* End of private macros -----------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F7xx_HAL_DFSDM_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,768 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_hal_dma.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.2
|
||||
* @date 14-April-2017
|
||||
* @brief Header file of DMA HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F7xx_HAL_DMA_H
|
||||
#define __STM32F7xx_HAL_DMA_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DMA
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DMA_Exported_Types DMA Exported Types
|
||||
* @brief DMA Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief DMA Configuration Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Channel; /*!< Specifies the channel used for the specified stream.
|
||||
This parameter can be a value of @ref DMAEx_Channel_selection */
|
||||
|
||||
uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
|
||||
from memory to memory or from peripheral to memory.
|
||||
This parameter can be a value of @ref DMA_Data_transfer_direction */
|
||||
|
||||
uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
|
||||
This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
|
||||
|
||||
uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
|
||||
This parameter can be a value of @ref DMA_Memory_incremented_mode */
|
||||
|
||||
uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
|
||||
This parameter can be a value of @ref DMA_Peripheral_data_size */
|
||||
|
||||
uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
|
||||
This parameter can be a value of @ref DMA_Memory_data_size */
|
||||
|
||||
uint32_t Mode; /*!< Specifies the operation mode of the DMAy Streamx.
|
||||
This parameter can be a value of @ref DMA_mode
|
||||
@note The circular buffer mode cannot be used if the memory-to-memory
|
||||
data transfer is configured on the selected Stream */
|
||||
|
||||
uint32_t Priority; /*!< Specifies the software priority for the DMAy Streamx.
|
||||
This parameter can be a value of @ref DMA_Priority_level */
|
||||
|
||||
uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.
|
||||
This parameter can be a value of @ref DMA_FIFO_direct_mode
|
||||
@note The Direct mode (FIFO mode disabled) cannot be used if the
|
||||
memory-to-memory data transfer is configured on the selected stream */
|
||||
|
||||
uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level.
|
||||
This parameter can be a value of @ref DMA_FIFO_threshold_level */
|
||||
|
||||
uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers.
|
||||
It specifies the amount of data to be transferred in a single non interruptible
|
||||
transaction.
|
||||
This parameter can be a value of @ref DMA_Memory_burst
|
||||
@note The burst mode is possible only if the address Increment mode is enabled. */
|
||||
|
||||
uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers.
|
||||
It specifies the amount of data to be transferred in a single non interruptible
|
||||
transaction.
|
||||
This parameter can be a value of @ref DMA_Peripheral_burst
|
||||
@note The burst mode is possible only if the address Increment mode is enabled. */
|
||||
}DMA_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL DMA State structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */
|
||||
HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */
|
||||
HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */
|
||||
HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */
|
||||
HAL_DMA_STATE_ERROR = 0x04U, /*!< DMA error state */
|
||||
HAL_DMA_STATE_ABORT = 0x05U, /*!< DMA Abort state */
|
||||
}HAL_DMA_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL DMA Error Code structure definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */
|
||||
HAL_DMA_HALF_TRANSFER = 0x01U, /*!< Half Transfer */
|
||||
}HAL_DMA_LevelCompleteTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL DMA Error Code structure definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */
|
||||
HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half Transfer */
|
||||
HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U, /*!< M1 Full Transfer */
|
||||
HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U, /*!< M1 Half Transfer */
|
||||
HAL_DMA_XFER_ERROR_CB_ID = 0x04U, /*!< Error */
|
||||
HAL_DMA_XFER_ABORT_CB_ID = 0x05U, /*!< Abort */
|
||||
HAL_DMA_XFER_ALL_CB_ID = 0x06U /*!< All */
|
||||
}HAL_DMA_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief DMA handle Structure definition
|
||||
*/
|
||||
typedef struct __DMA_HandleTypeDef
|
||||
{
|
||||
DMA_Stream_TypeDef *Instance; /*!< Register base address */
|
||||
|
||||
DMA_InitTypeDef Init; /*!< DMA communication parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< DMA locking object */
|
||||
|
||||
__IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
|
||||
|
||||
void *Parent; /*!< Parent object state */
|
||||
|
||||
void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */
|
||||
|
||||
void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */
|
||||
|
||||
void (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete Memory1 callback */
|
||||
|
||||
void (* XferM1HalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Half complete Memory1 callback */
|
||||
|
||||
void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
|
||||
|
||||
void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Abort callback */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< DMA Error code */
|
||||
|
||||
uint32_t StreamBaseAddress; /*!< DMA Stream Base Address */
|
||||
|
||||
uint32_t StreamIndex; /*!< DMA Stream Index */
|
||||
|
||||
}DMA_HandleTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DMA_Exported_Constants DMA Exported Constants
|
||||
* @brief DMA Exported constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Error_Code DMA Error Code
|
||||
* @brief DMA Error Code
|
||||
* @{
|
||||
*/
|
||||
#define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
|
||||
#define HAL_DMA_ERROR_TE ((uint32_t)0x00000001U) /*!< Transfer error */
|
||||
#define HAL_DMA_ERROR_FE ((uint32_t)0x00000002U) /*!< FIFO error */
|
||||
#define HAL_DMA_ERROR_DME ((uint32_t)0x00000004U) /*!< Direct Mode error */
|
||||
#define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020U) /*!< Timeout error */
|
||||
#define HAL_DMA_ERROR_PARAM ((uint32_t)0x00000040U) /*!< Parameter error */
|
||||
#define HAL_DMA_ERROR_NO_XFER ((uint32_t)0x00000080U) /*!< Abort requested with no Xfer ongoing */
|
||||
#define HAL_DMA_ERROR_NOT_SUPPORTED ((uint32_t)0x00000100U) /*!< Not supported mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
|
||||
* @brief DMA data transfer direction
|
||||
* @{
|
||||
*/
|
||||
#define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000U) /*!< Peripheral to memory direction */
|
||||
#define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_SxCR_DIR_0) /*!< Memory to peripheral direction */
|
||||
#define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_SxCR_DIR_1) /*!< Memory to memory direction */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
|
||||
* @brief DMA peripheral incremented mode
|
||||
* @{
|
||||
*/
|
||||
#define DMA_PINC_ENABLE ((uint32_t)DMA_SxCR_PINC) /*!< Peripheral increment mode enable */
|
||||
#define DMA_PINC_DISABLE ((uint32_t)0x00000000U) /*!< Peripheral increment mode disable */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
|
||||
* @brief DMA memory incremented mode
|
||||
* @{
|
||||
*/
|
||||
#define DMA_MINC_ENABLE ((uint32_t)DMA_SxCR_MINC) /*!< Memory increment mode enable */
|
||||
#define DMA_MINC_DISABLE ((uint32_t)0x00000000U) /*!< Memory increment mode disable */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
|
||||
* @brief DMA peripheral data size
|
||||
* @{
|
||||
*/
|
||||
#define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000U) /*!< Peripheral data alignment: Byte */
|
||||
#define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */
|
||||
#define DMA_PDATAALIGN_WORD ((uint32_t)DMA_SxCR_PSIZE_1) /*!< Peripheral data alignment: Word */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Memory_data_size DMA Memory data size
|
||||
* @brief DMA memory data size
|
||||
* @{
|
||||
*/
|
||||
#define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000U) /*!< Memory data alignment: Byte */
|
||||
#define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_MSIZE_0) /*!< Memory data alignment: HalfWord */
|
||||
#define DMA_MDATAALIGN_WORD ((uint32_t)DMA_SxCR_MSIZE_1) /*!< Memory data alignment: Word */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_mode DMA mode
|
||||
* @brief DMA mode
|
||||
* @{
|
||||
*/
|
||||
#define DMA_NORMAL ((uint32_t)0x00000000U) /*!< Normal mode */
|
||||
#define DMA_CIRCULAR ((uint32_t)DMA_SxCR_CIRC) /*!< Circular mode */
|
||||
#define DMA_PFCTRL ((uint32_t)DMA_SxCR_PFCTRL) /*!< Peripheral flow control mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Priority_level DMA Priority level
|
||||
* @brief DMA priority levels
|
||||
* @{
|
||||
*/
|
||||
#define DMA_PRIORITY_LOW ((uint32_t)0x00000000U) /*!< Priority level: Low */
|
||||
#define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_SxCR_PL_0) /*!< Priority level: Medium */
|
||||
#define DMA_PRIORITY_HIGH ((uint32_t)DMA_SxCR_PL_1) /*!< Priority level: High */
|
||||
#define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_SxCR_PL) /*!< Priority level: Very High */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_FIFO_direct_mode DMA FIFO direct mode
|
||||
* @brief DMA FIFO direct mode
|
||||
* @{
|
||||
*/
|
||||
#define DMA_FIFOMODE_DISABLE ((uint32_t)0x00000000U) /*!< FIFO mode disable */
|
||||
#define DMA_FIFOMODE_ENABLE ((uint32_t)DMA_SxFCR_DMDIS) /*!< FIFO mode enable */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_FIFO_threshold_level DMA FIFO threshold level
|
||||
* @brief DMA FIFO level
|
||||
* @{
|
||||
*/
|
||||
#define DMA_FIFO_THRESHOLD_1QUARTERFULL ((uint32_t)0x00000000U) /*!< FIFO threshold 1 quart full configuration */
|
||||
#define DMA_FIFO_THRESHOLD_HALFFULL ((uint32_t)DMA_SxFCR_FTH_0) /*!< FIFO threshold half full configuration */
|
||||
#define DMA_FIFO_THRESHOLD_3QUARTERSFULL ((uint32_t)DMA_SxFCR_FTH_1) /*!< FIFO threshold 3 quarts full configuration */
|
||||
#define DMA_FIFO_THRESHOLD_FULL ((uint32_t)DMA_SxFCR_FTH) /*!< FIFO threshold full configuration */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Memory_burst DMA Memory burst
|
||||
* @brief DMA memory burst
|
||||
* @{
|
||||
*/
|
||||
#define DMA_MBURST_SINGLE ((uint32_t)0x00000000U)
|
||||
#define DMA_MBURST_INC4 ((uint32_t)DMA_SxCR_MBURST_0)
|
||||
#define DMA_MBURST_INC8 ((uint32_t)DMA_SxCR_MBURST_1)
|
||||
#define DMA_MBURST_INC16 ((uint32_t)DMA_SxCR_MBURST)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Peripheral_burst DMA Peripheral burst
|
||||
* @brief DMA peripheral burst
|
||||
* @{
|
||||
*/
|
||||
#define DMA_PBURST_SINGLE ((uint32_t)0x00000000U)
|
||||
#define DMA_PBURST_INC4 ((uint32_t)DMA_SxCR_PBURST_0)
|
||||
#define DMA_PBURST_INC8 ((uint32_t)DMA_SxCR_PBURST_1)
|
||||
#define DMA_PBURST_INC16 ((uint32_t)DMA_SxCR_PBURST)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
|
||||
* @brief DMA interrupts definition
|
||||
* @{
|
||||
*/
|
||||
#define DMA_IT_TC ((uint32_t)DMA_SxCR_TCIE)
|
||||
#define DMA_IT_HT ((uint32_t)DMA_SxCR_HTIE)
|
||||
#define DMA_IT_TE ((uint32_t)DMA_SxCR_TEIE)
|
||||
#define DMA_IT_DME ((uint32_t)DMA_SxCR_DMEIE)
|
||||
#define DMA_IT_FE ((uint32_t)0x00000080U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_flag_definitions DMA flag definitions
|
||||
* @brief DMA flag definitions
|
||||
* @{
|
||||
*/
|
||||
#define DMA_FLAG_FEIF0_4 ((uint32_t)0x00800001U)
|
||||
#define DMA_FLAG_DMEIF0_4 ((uint32_t)0x00800004U)
|
||||
#define DMA_FLAG_TEIF0_4 ((uint32_t)0x00000008U)
|
||||
#define DMA_FLAG_HTIF0_4 ((uint32_t)0x00000010U)
|
||||
#define DMA_FLAG_TCIF0_4 ((uint32_t)0x00000020U)
|
||||
#define DMA_FLAG_FEIF1_5 ((uint32_t)0x00000040U)
|
||||
#define DMA_FLAG_DMEIF1_5 ((uint32_t)0x00000100U)
|
||||
#define DMA_FLAG_TEIF1_5 ((uint32_t)0x00000200U)
|
||||
#define DMA_FLAG_HTIF1_5 ((uint32_t)0x00000400U)
|
||||
#define DMA_FLAG_TCIF1_5 ((uint32_t)0x00000800U)
|
||||
#define DMA_FLAG_FEIF2_6 ((uint32_t)0x00010000U)
|
||||
#define DMA_FLAG_DMEIF2_6 ((uint32_t)0x00040000U)
|
||||
#define DMA_FLAG_TEIF2_6 ((uint32_t)0x00080000U)
|
||||
#define DMA_FLAG_HTIF2_6 ((uint32_t)0x00100000U)
|
||||
#define DMA_FLAG_TCIF2_6 ((uint32_t)0x00200000U)
|
||||
#define DMA_FLAG_FEIF3_7 ((uint32_t)0x00400000U)
|
||||
#define DMA_FLAG_DMEIF3_7 ((uint32_t)0x01000000U)
|
||||
#define DMA_FLAG_TEIF3_7 ((uint32_t)0x02000000U)
|
||||
#define DMA_FLAG_HTIF3_7 ((uint32_t)0x04000000U)
|
||||
#define DMA_FLAG_TCIF3_7 ((uint32_t)0x08000000U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
|
||||
/** @brief Reset DMA handle state
|
||||
* @param __HANDLE__: specifies the DMA handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
|
||||
|
||||
/**
|
||||
* @brief Return the current DMA Stream FIFO filled level.
|
||||
* @param __HANDLE__: DMA handle
|
||||
* @retval The FIFO filling state.
|
||||
* - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full
|
||||
* and not empty.
|
||||
* - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full.
|
||||
* - DMA_FIFOStatus_HalfFull: if more than 1 half-full.
|
||||
* - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full.
|
||||
* - DMA_FIFOStatus_Empty: when FIFO is empty
|
||||
* - DMA_FIFOStatus_Full: when FIFO is full
|
||||
*/
|
||||
#define __HAL_DMA_GET_FS(__HANDLE__) (((__HANDLE__)->Instance->FCR & (DMA_SxFCR_FS)))
|
||||
|
||||
/**
|
||||
* @brief Enable the specified DMA Stream.
|
||||
* @param __HANDLE__: DMA handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA_SxCR_EN)
|
||||
|
||||
/**
|
||||
* @brief Disable the specified DMA Stream.
|
||||
* @param __HANDLE__: DMA handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DMA_SxCR_EN)
|
||||
|
||||
/* Interrupt & Flag management */
|
||||
|
||||
/**
|
||||
* @brief Return the current DMA Stream transfer complete flag.
|
||||
* @param __HANDLE__: DMA handle
|
||||
* @retval The specified transfer complete flag index.
|
||||
*/
|
||||
#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
|
||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\
|
||||
DMA_FLAG_TCIF3_7)
|
||||
|
||||
/**
|
||||
* @brief Return the current DMA Stream half transfer complete flag.
|
||||
* @param __HANDLE__: DMA handle
|
||||
* @retval The specified half transfer complete flag index.
|
||||
*/
|
||||
#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
|
||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\
|
||||
DMA_FLAG_HTIF3_7)
|
||||
|
||||
/**
|
||||
* @brief Return the current DMA Stream transfer error flag.
|
||||
* @param __HANDLE__: DMA handle
|
||||
* @retval The specified transfer error flag index.
|
||||
*/
|
||||
#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
|
||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\
|
||||
DMA_FLAG_TEIF3_7)
|
||||
|
||||
/**
|
||||
* @brief Return the current DMA Stream FIFO error flag.
|
||||
* @param __HANDLE__: DMA handle
|
||||
* @retval The specified FIFO error flag index.
|
||||
*/
|
||||
#define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\
|
||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\
|
||||
DMA_FLAG_FEIF3_7)
|
||||
|
||||
/**
|
||||
* @brief Return the current DMA Stream direct mode error flag.
|
||||
* @param __HANDLE__: DMA handle
|
||||
* @retval The specified direct mode error flag index.
|
||||
*/
|
||||
#define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\
|
||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\
|
||||
DMA_FLAG_DMEIF3_7)
|
||||
|
||||
/**
|
||||
* @brief Get the DMA Stream pending flags.
|
||||
* @param __HANDLE__: DMA handle
|
||||
* @param __FLAG__: Get the specified flag.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DMA_FLAG_TCIFx: Transfer complete flag.
|
||||
* @arg DMA_FLAG_HTIFx: Half transfer complete flag.
|
||||
* @arg DMA_FLAG_TEIFx: Transfer error flag.
|
||||
* @arg DMA_FLAG_DMEIFx: Direct mode error flag.
|
||||
* @arg DMA_FLAG_FEIFx: FIFO error flag.
|
||||
* Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
|
||||
* @retval The state of FLAG (SET or RESET).
|
||||
*/
|
||||
#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
|
||||
(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\
|
||||
((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\
|
||||
((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__)))
|
||||
|
||||
/**
|
||||
* @brief Clear the DMA Stream pending flags.
|
||||
* @param __HANDLE__: DMA handle
|
||||
* @param __FLAG__: specifies the flag to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DMA_FLAG_TCIFx: Transfer complete flag.
|
||||
* @arg DMA_FLAG_HTIFx: Half transfer complete flag.
|
||||
* @arg DMA_FLAG_TEIFx: Transfer error flag.
|
||||
* @arg DMA_FLAG_DMEIFx: Direct mode error flag.
|
||||
* @arg DMA_FLAG_FEIFx: FIFO error flag.
|
||||
* Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
|
||||
(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\
|
||||
((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\
|
||||
((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__)))
|
||||
|
||||
/**
|
||||
* @brief Enable the specified DMA Stream interrupts.
|
||||
* @param __HANDLE__: DMA handle
|
||||
* @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DMA_IT_TC: Transfer complete interrupt mask.
|
||||
* @arg DMA_IT_HT: Half transfer complete interrupt mask.
|
||||
* @arg DMA_IT_TE: Transfer error interrupt mask.
|
||||
* @arg DMA_IT_FE: FIFO error interrupt mask.
|
||||
* @arg DMA_IT_DME: Direct mode error interrupt.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
|
||||
((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR |= (__INTERRUPT__)))
|
||||
|
||||
/**
|
||||
* @brief Disable the specified DMA Stream interrupts.
|
||||
* @param __HANDLE__: DMA handle
|
||||
* @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DMA_IT_TC: Transfer complete interrupt mask.
|
||||
* @arg DMA_IT_HT: Half transfer complete interrupt mask.
|
||||
* @arg DMA_IT_TE: Transfer error interrupt mask.
|
||||
* @arg DMA_IT_FE: FIFO error interrupt mask.
|
||||
* @arg DMA_IT_DME: Direct mode error interrupt.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
|
||||
((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR &= ~(__INTERRUPT__)))
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified DMA Stream interrupt is enabled or not.
|
||||
* @param __HANDLE__: DMA handle
|
||||
* @param __INTERRUPT__: specifies the DMA interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DMA_IT_TC: Transfer complete interrupt mask.
|
||||
* @arg DMA_IT_HT: Half transfer complete interrupt mask.
|
||||
* @arg DMA_IT_TE: Transfer error interrupt mask.
|
||||
* @arg DMA_IT_FE: FIFO error interrupt mask.
|
||||
* @arg DMA_IT_DME: Direct mode error interrupt.
|
||||
* @retval The state of DMA_IT.
|
||||
*/
|
||||
#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
|
||||
((__HANDLE__)->Instance->CR & (__INTERRUPT__)) : \
|
||||
((__HANDLE__)->Instance->FCR & (__INTERRUPT__)))
|
||||
|
||||
/**
|
||||
* @brief Writes the number of data units to be transferred on the DMA Stream.
|
||||
* @param __HANDLE__: DMA handle
|
||||
* @param __COUNTER__: Number of data units to be transferred (from 0 to 65535)
|
||||
* Number of data items depends only on the Peripheral data format.
|
||||
*
|
||||
* @note If Peripheral data format is Bytes: number of data units is equal
|
||||
* to total number of bytes to be transferred.
|
||||
*
|
||||
* @note If Peripheral data format is Half-Word: number of data units is
|
||||
* equal to total number of bytes to be transferred / 2.
|
||||
*
|
||||
* @note If Peripheral data format is Word: number of data units is equal
|
||||
* to total number of bytes to be transferred / 4.
|
||||
*
|
||||
* @retval The number of remaining data units in the current DMAy Streamx transfer.
|
||||
*/
|
||||
#define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->NDTR = (uint16_t)(__COUNTER__))
|
||||
|
||||
/**
|
||||
* @brief Returns the number of remaining data units in the current DMAy Streamx transfer.
|
||||
* @param __HANDLE__: DMA handle
|
||||
*
|
||||
* @retval The number of remaining data units in the current DMA Stream transfer.
|
||||
*/
|
||||
#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->NDTR)
|
||||
|
||||
|
||||
/* Include DMA HAL Extension module */
|
||||
#include "stm32f7xx_hal_dma_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DMA_Exported_Functions DMA Exported Functions
|
||||
* @brief DMA Exported functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @brief Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
|
||||
HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Exported_Functions_Group2 I/O operation functions
|
||||
* @brief I/O operation functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
|
||||
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
|
||||
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
|
||||
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
|
||||
HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout);
|
||||
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
|
||||
HAL_StatusTypeDef HAL_DMA_CleanCallbacks(DMA_HandleTypeDef *hdma);
|
||||
HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma));
|
||||
HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions
|
||||
* @brief Peripheral State functions
|
||||
* @{
|
||||
*/
|
||||
HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
|
||||
uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private Constants -------------------------------------------------------------*/
|
||||
/** @defgroup DMA_Private_Constants DMA Private Constants
|
||||
* @brief DMA private defines and constants
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup DMA_Private_Macros DMA Private Macros
|
||||
* @brief DMA private macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
|
||||
((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
|
||||
((DIRECTION) == DMA_MEMORY_TO_MEMORY))
|
||||
|
||||
#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x01U) && ((SIZE) < 0x10000U))
|
||||
|
||||
#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
|
||||
((STATE) == DMA_PINC_DISABLE))
|
||||
|
||||
#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
|
||||
((STATE) == DMA_MINC_DISABLE))
|
||||
|
||||
#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
|
||||
((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
|
||||
((SIZE) == DMA_PDATAALIGN_WORD))
|
||||
|
||||
#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
|
||||
((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
|
||||
((SIZE) == DMA_MDATAALIGN_WORD ))
|
||||
|
||||
#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
|
||||
((MODE) == DMA_CIRCULAR) || \
|
||||
((MODE) == DMA_PFCTRL))
|
||||
|
||||
#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
|
||||
((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
|
||||
((PRIORITY) == DMA_PRIORITY_HIGH) || \
|
||||
((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
|
||||
|
||||
#define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \
|
||||
((STATE) == DMA_FIFOMODE_ENABLE))
|
||||
|
||||
#define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \
|
||||
((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL) || \
|
||||
((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \
|
||||
((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL))
|
||||
|
||||
#define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || \
|
||||
((BURST) == DMA_MBURST_INC4) || \
|
||||
((BURST) == DMA_MBURST_INC8) || \
|
||||
((BURST) == DMA_MBURST_INC16))
|
||||
|
||||
#define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || \
|
||||
((BURST) == DMA_PBURST_INC4) || \
|
||||
((BURST) == DMA_PBURST_INC8) || \
|
||||
((BURST) == DMA_PBURST_INC16))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup DMA_Private_Functions DMA Private Functions
|
||||
* @brief DMA private functions
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F7xx_HAL_DMA_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,638 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_hal_dma2d.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.2
|
||||
* @date 14-April-2017
|
||||
* @brief Header file of DMA2D HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F7xx_HAL_DMA2D_H
|
||||
#define __STM32F7xx_HAL_DMA2D_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx_hal_def.h"
|
||||
|
||||
#if defined (DMA2D)
|
||||
|
||||
/** @addtogroup STM32F7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DMA2D DMA2D
|
||||
* @brief DMA2D HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup DMA2D_Exported_Types DMA2D Exported Types
|
||||
* @{
|
||||
*/
|
||||
#define MAX_DMA2D_LAYER 2
|
||||
|
||||
/**
|
||||
* @brief DMA2D color Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Blue; /*!< Configures the blue value.
|
||||
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
|
||||
|
||||
uint32_t Green; /*!< Configures the green value.
|
||||
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
|
||||
|
||||
uint32_t Red; /*!< Configures the red value.
|
||||
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
|
||||
} DMA2D_ColorTypeDef;
|
||||
|
||||
/**
|
||||
* @brief DMA2D CLUT Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t *pCLUT; /*!< Configures the DMA2D CLUT memory address.*/
|
||||
|
||||
uint32_t CLUTColorMode; /*!< Configures the DMA2D CLUT color mode.
|
||||
This parameter can be one value of @ref DMA2D_CLUT_CM. */
|
||||
|
||||
uint32_t Size; /*!< Configures the DMA2D CLUT size.
|
||||
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.*/
|
||||
} DMA2D_CLUTCfgTypeDef;
|
||||
|
||||
/**
|
||||
* @brief DMA2D Init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Mode; /*!< Configures the DMA2D transfer mode.
|
||||
This parameter can be one value of @ref DMA2D_Mode. */
|
||||
|
||||
uint32_t ColorMode; /*!< Configures the color format of the output image.
|
||||
This parameter can be one value of @ref DMA2D_Output_Color_Mode. */
|
||||
|
||||
uint32_t OutputOffset; /*!< Specifies the Offset value.
|
||||
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */
|
||||
#if defined (DMA2D_OPFCCR_AI)
|
||||
uint32_t AlphaInverted; /*!< Select regular or inverted alpha value for the output pixel format converter.
|
||||
This parameter can be one value of @ref DMA2D_Alpha_Inverted. */
|
||||
#endif /* DMA2D_OPFCCR_AI */
|
||||
|
||||
#if defined (DMA2D_OPFCCR_RBS)
|
||||
uint32_t RedBlueSwap; /*!< Select regular mode (RGB or ARGB) or swap mode (BGR or ABGR)
|
||||
for the output pixel format converter.
|
||||
This parameter can be one value of @ref DMA2D_RB_Swap. */
|
||||
#endif /* DMA2D_OPFCCR_RBS */
|
||||
|
||||
} DMA2D_InitTypeDef;
|
||||
|
||||
|
||||
/**
|
||||
* @brief DMA2D Layer structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t InputOffset; /*!< Configures the DMA2D foreground or background offset.
|
||||
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */
|
||||
|
||||
uint32_t InputColorMode; /*!< Configures the DMA2D foreground or background color mode.
|
||||
This parameter can be one value of @ref DMA2D_Input_Color_Mode. */
|
||||
|
||||
uint32_t AlphaMode; /*!< Configures the DMA2D foreground or background alpha mode.
|
||||
This parameter can be one value of @ref DMA2D_Alpha_Mode. */
|
||||
|
||||
uint32_t InputAlpha; /*!< Specifies the DMA2D foreground or background alpha value and color value in case of A8 or A4 color mode.
|
||||
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF except for the color modes detailed below.
|
||||
@note In case of A8 or A4 color mode (ARGB), this parameter must be a number between
|
||||
Min_Data = 0x00000000 and Max_Data = 0xFFFFFFFF where
|
||||
- InputAlpha[24:31] is the alpha value ALPHA[0:7]
|
||||
- InputAlpha[16:23] is the red value RED[0:7]
|
||||
- InputAlpha[8:15] is the green value GREEN[0:7]
|
||||
- InputAlpha[0:7] is the blue value BLUE[0:7]. */
|
||||
|
||||
#if defined (DMA2D_FGPFCCR_AI) && defined (DMA2D_BGPFCCR_AI)
|
||||
uint32_t AlphaInverted; /*!< Select regular or inverted alpha value.
|
||||
This parameter can be one value of @ref DMA2D_Alpha_Inverted.
|
||||
This feature is only available on devices :
|
||||
STM32F756xx, STM32F767xx, STM32F769xx, STM32F777xx and STM32F779xx.*/
|
||||
|
||||
#endif /* (DMA2D_FGPFCCR_AI) && (DMA2D_BGPFCCR_AI) */
|
||||
|
||||
#if defined (DMA2D_FGPFCCR_RBS) && defined (DMA2D_BGPFCCR_RBS)
|
||||
uint32_t RedBlueSwap; /*!< Select regular mode (RGB or ARGB) or swap mode (BGR or ABGR).
|
||||
This parameter can be one value of @ref DMA2D_RB_Swap
|
||||
This feature is only available on devices :
|
||||
STM32F756xx, STM32F767xx, STM32F769xx, STM32F777xx and STM32F779xx.*/
|
||||
|
||||
#endif /* (DMA2D_FGPFCCR_RBS) && (DMA2D_BGPFCCR_RBS) */
|
||||
|
||||
} DMA2D_LayerCfgTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL DMA2D State structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_DMA2D_STATE_RESET = 0x00U, /*!< DMA2D not yet initialized or disabled */
|
||||
HAL_DMA2D_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
|
||||
HAL_DMA2D_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */
|
||||
HAL_DMA2D_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
|
||||
HAL_DMA2D_STATE_ERROR = 0x04U, /*!< DMA2D state error */
|
||||
HAL_DMA2D_STATE_SUSPEND = 0x05U /*!< DMA2D process is suspended */
|
||||
}HAL_DMA2D_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief DMA2D handle Structure definition
|
||||
*/
|
||||
typedef struct __DMA2D_HandleTypeDef
|
||||
{
|
||||
DMA2D_TypeDef *Instance; /*!< DMA2D register base address. */
|
||||
|
||||
DMA2D_InitTypeDef Init; /*!< DMA2D communication parameters. */
|
||||
|
||||
void (* XferCpltCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer complete callback. */
|
||||
|
||||
void (* XferErrorCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer error callback. */
|
||||
|
||||
DMA2D_LayerCfgTypeDef LayerCfg[MAX_DMA2D_LAYER]; /*!< DMA2D Layers parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< DMA2D lock. */
|
||||
|
||||
__IO HAL_DMA2D_StateTypeDef State; /*!< DMA2D transfer state. */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< DMA2D error code. */
|
||||
} DMA2D_HandleTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup DMA2D_Exported_Constants DMA2D Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DMA2D_Error_Code DMA2D Error Code
|
||||
* @{
|
||||
*/
|
||||
#define HAL_DMA2D_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
|
||||
#define HAL_DMA2D_ERROR_TE ((uint32_t)0x00000001U) /*!< Transfer error */
|
||||
#define HAL_DMA2D_ERROR_CE ((uint32_t)0x00000002U) /*!< Configuration error */
|
||||
#define HAL_DMA2D_ERROR_CAE ((uint32_t)0x00000004U) /*!< CLUT access error */
|
||||
#define HAL_DMA2D_ERROR_TIMEOUT ((uint32_t)0x00000020U) /*!< Timeout error */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA2D_Mode DMA2D Mode
|
||||
* @{
|
||||
*/
|
||||
#define DMA2D_M2M ((uint32_t)0x00000000U) /*!< DMA2D memory to memory transfer mode */
|
||||
#define DMA2D_M2M_PFC DMA2D_CR_MODE_0 /*!< DMA2D memory to memory with pixel format conversion transfer mode */
|
||||
#define DMA2D_M2M_BLEND DMA2D_CR_MODE_1 /*!< DMA2D memory to memory with blending transfer mode */
|
||||
#define DMA2D_R2M DMA2D_CR_MODE /*!< DMA2D register to memory transfer mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA2D_Output_Color_Mode DMA2D Output Color Mode
|
||||
* @{
|
||||
*/
|
||||
#define DMA2D_OUTPUT_ARGB8888 ((uint32_t)0x00000000U) /*!< ARGB8888 DMA2D color mode */
|
||||
#define DMA2D_OUTPUT_RGB888 DMA2D_OPFCCR_CM_0 /*!< RGB888 DMA2D color mode */
|
||||
#define DMA2D_OUTPUT_RGB565 DMA2D_OPFCCR_CM_1 /*!< RGB565 DMA2D color mode */
|
||||
#define DMA2D_OUTPUT_ARGB1555 (DMA2D_OPFCCR_CM_0|DMA2D_OPFCCR_CM_1) /*!< ARGB1555 DMA2D color mode */
|
||||
#define DMA2D_OUTPUT_ARGB4444 DMA2D_OPFCCR_CM_2 /*!< ARGB4444 DMA2D color mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA2D_Input_Color_Mode DMA2D Input Color Mode
|
||||
* @{
|
||||
*/
|
||||
#define DMA2D_INPUT_ARGB8888 ((uint32_t)0x00000000U) /*!< ARGB8888 color mode */
|
||||
#define DMA2D_INPUT_RGB888 ((uint32_t)0x00000001U) /*!< RGB888 color mode */
|
||||
#define DMA2D_INPUT_RGB565 ((uint32_t)0x00000002U) /*!< RGB565 color mode */
|
||||
#define DMA2D_INPUT_ARGB1555 ((uint32_t)0x00000003U) /*!< ARGB1555 color mode */
|
||||
#define DMA2D_INPUT_ARGB4444 ((uint32_t)0x00000004U) /*!< ARGB4444 color mode */
|
||||
#define DMA2D_INPUT_L8 ((uint32_t)0x00000005U) /*!< L8 color mode */
|
||||
#define DMA2D_INPUT_AL44 ((uint32_t)0x00000006U) /*!< AL44 color mode */
|
||||
#define DMA2D_INPUT_AL88 ((uint32_t)0x00000007U) /*!< AL88 color mode */
|
||||
#define DMA2D_INPUT_L4 ((uint32_t)0x00000008U) /*!< L4 color mode */
|
||||
#define DMA2D_INPUT_A8 ((uint32_t)0x00000009U) /*!< A8 color mode */
|
||||
#define DMA2D_INPUT_A4 ((uint32_t)0x0000000AU) /*!< A4 color mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA2D_Alpha_Mode DMA2D Alpha Mode
|
||||
* @{
|
||||
*/
|
||||
#define DMA2D_NO_MODIF_ALPHA ((uint32_t)0x00000000U) /*!< No modification of the alpha channel value */
|
||||
#define DMA2D_REPLACE_ALPHA ((uint32_t)0x00000001U) /*!< Replace original alpha channel value by programmed alpha value */
|
||||
#define DMA2D_COMBINE_ALPHA ((uint32_t)0x00000002U) /*!< Replace original alpha channel value by programmed alpha value
|
||||
with original alpha channel value */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined (DMA2D_FGPFCCR_AI) && defined (DMA2D_BGPFCCR_AI)
|
||||
/** @defgroup DMA2D_Alpha_Inverted DMA2D ALPHA Inversion
|
||||
* @{
|
||||
*/
|
||||
#define DMA2D_REGULAR_ALPHA ((uint32_t)0x00000000U) /*!< No modification of the alpha channel value */
|
||||
#define DMA2D_INVERTED_ALPHA ((uint32_t)0x00000001U) /*!< Invert the alpha channel value */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* (DMA2D_FGPFCCR_AI) && (DMA2D_BGPFCCR_AI) */
|
||||
|
||||
#if defined (DMA2D_FGPFCCR_RBS) && defined (DMA2D_BGPFCCR_RBS)
|
||||
/** @defgroup DMA2D_RB_Swap DMA2D Red and Blue Swap
|
||||
* @{
|
||||
*/
|
||||
#define DMA2D_RB_REGULAR ((uint32_t)0x00000000U) /*!< Select regular mode (RGB or ARGB) */
|
||||
#define DMA2D_RB_SWAP ((uint32_t)0x00000001U) /*!< Select swap mode (BGR or ABGR) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* (DMA2D_FGPFCCR_RBS) && (DMA2D_BGPFCCR_RBS) */
|
||||
|
||||
/** @defgroup DMA2D_CLUT_CM DMA2D CLUT Color Mode
|
||||
* @{
|
||||
*/
|
||||
#define DMA2D_CCM_ARGB8888 ((uint32_t)0x00000000U) /*!< ARGB8888 DMA2D CLUT color mode */
|
||||
#define DMA2D_CCM_RGB888 ((uint32_t)0x00000001U) /*!< RGB888 DMA2D CLUT color mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup DMA2D_Interrupts DMA2D Interrupts
|
||||
* @{
|
||||
*/
|
||||
#define DMA2D_IT_CE DMA2D_CR_CEIE /*!< Configuration Error Interrupt */
|
||||
#define DMA2D_IT_CTC DMA2D_CR_CTCIE /*!< CLUT Transfer Complete Interrupt */
|
||||
#define DMA2D_IT_CAE DMA2D_CR_CAEIE /*!< CLUT Access Error Interrupt */
|
||||
#define DMA2D_IT_TW DMA2D_CR_TWIE /*!< Transfer Watermark Interrupt */
|
||||
#define DMA2D_IT_TC DMA2D_CR_TCIE /*!< Transfer Complete Interrupt */
|
||||
#define DMA2D_IT_TE DMA2D_CR_TEIE /*!< Transfer Error Interrupt */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA2D_Flags DMA2D Flags
|
||||
* @{
|
||||
*/
|
||||
#define DMA2D_FLAG_CE DMA2D_ISR_CEIF /*!< Configuration Error Interrupt Flag */
|
||||
#define DMA2D_FLAG_CTC DMA2D_ISR_CTCIF /*!< CLUT Transfer Complete Interrupt Flag */
|
||||
#define DMA2D_FLAG_CAE DMA2D_ISR_CAEIF /*!< CLUT Access Error Interrupt Flag */
|
||||
#define DMA2D_FLAG_TW DMA2D_ISR_TWIF /*!< Transfer Watermark Interrupt Flag */
|
||||
#define DMA2D_FLAG_TC DMA2D_ISR_TCIF /*!< Transfer Complete Interrupt Flag */
|
||||
#define DMA2D_FLAG_TE DMA2D_ISR_TEIF /*!< Transfer Error Interrupt Flag */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA2D_Aliases DMA2D API Aliases
|
||||
* @{
|
||||
*/
|
||||
#define HAL_DMA2D_DisableCLUT HAL_DMA2D_CLUTLoading_Abort /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort for compatibility with legacy code */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported macros ------------------------------------------------------------*/
|
||||
/** @defgroup DMA2D_Exported_Macros DMA2D Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset DMA2D handle state
|
||||
* @param __HANDLE__: specifies the DMA2D handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA2D_STATE_RESET)
|
||||
|
||||
/**
|
||||
* @brief Enable the DMA2D.
|
||||
* @param __HANDLE__: DMA2D handle
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_DMA2D_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA2D_CR_START)
|
||||
|
||||
|
||||
/* Interrupt & Flag management */
|
||||
/**
|
||||
* @brief Get the DMA2D pending flags.
|
||||
* @param __HANDLE__: DMA2D handle
|
||||
* @param __FLAG__: flag to check.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DMA2D_FLAG_CE: Configuration error flag
|
||||
* @arg DMA2D_FLAG_CTC: CLUT transfer complete flag
|
||||
* @arg DMA2D_FLAG_CAE: CLUT access error flag
|
||||
* @arg DMA2D_FLAG_TW: Transfer Watermark flag
|
||||
* @arg DMA2D_FLAG_TC: Transfer complete flag
|
||||
* @arg DMA2D_FLAG_TE: Transfer error flag
|
||||
* @retval The state of FLAG.
|
||||
*/
|
||||
#define __HAL_DMA2D_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
|
||||
|
||||
/**
|
||||
* @brief Clear the DMA2D pending flags.
|
||||
* @param __HANDLE__: DMA2D handle
|
||||
* @param __FLAG__: specifies the flag to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DMA2D_FLAG_CE: Configuration error flag
|
||||
* @arg DMA2D_FLAG_CTC: CLUT transfer complete flag
|
||||
* @arg DMA2D_FLAG_CAE: CLUT access error flag
|
||||
* @arg DMA2D_FLAG_TW: Transfer Watermark flag
|
||||
* @arg DMA2D_FLAG_TC: Transfer complete flag
|
||||
* @arg DMA2D_FLAG_TE: Transfer error flag
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DMA2D_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->IFCR = (__FLAG__))
|
||||
|
||||
/**
|
||||
* @brief Enable the specified DMA2D interrupts.
|
||||
* @param __HANDLE__: DMA2D handle
|
||||
* @param __INTERRUPT__: specifies the DMA2D interrupt sources to be enabled.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DMA2D_IT_CE: Configuration error interrupt mask
|
||||
* @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask
|
||||
* @arg DMA2D_IT_CAE: CLUT access error interrupt mask
|
||||
* @arg DMA2D_IT_TW: Transfer Watermark interrupt mask
|
||||
* @arg DMA2D_IT_TC: Transfer complete interrupt mask
|
||||
* @arg DMA2D_IT_TE: Transfer error interrupt mask
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DMA2D_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Disable the specified DMA2D interrupts.
|
||||
* @param __HANDLE__: DMA2D handle
|
||||
* @param __INTERRUPT__: specifies the DMA2D interrupt sources to be disabled.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DMA2D_IT_CE: Configuration error interrupt mask
|
||||
* @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask
|
||||
* @arg DMA2D_IT_CAE: CLUT access error interrupt mask
|
||||
* @arg DMA2D_IT_TW: Transfer Watermark interrupt mask
|
||||
* @arg DMA2D_IT_TC: Transfer complete interrupt mask
|
||||
* @arg DMA2D_IT_TE: Transfer error interrupt mask
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DMA2D_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified DMA2D interrupt source is enabled or not.
|
||||
* @param __HANDLE__: DMA2D handle
|
||||
* @param __INTERRUPT__: specifies the DMA2D interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DMA2D_IT_CE: Configuration error interrupt mask
|
||||
* @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask
|
||||
* @arg DMA2D_IT_CAE: CLUT access error interrupt mask
|
||||
* @arg DMA2D_IT_TW: Transfer Watermark interrupt mask
|
||||
* @arg DMA2D_IT_TC: Transfer complete interrupt mask
|
||||
* @arg DMA2D_IT_TE: Transfer error interrupt mask
|
||||
* @retval The state of INTERRUPT source.
|
||||
*/
|
||||
#define __HAL_DMA2D_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup DMA2D_Exported_Functions DMA2D Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DMA2D_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Initialization and de-initialization functions *******************************/
|
||||
HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d);
|
||||
HAL_StatusTypeDef HAL_DMA2D_DeInit (DMA2D_HandleTypeDef *hdma2d);
|
||||
void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d);
|
||||
void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup DMA2D_Exported_Functions_Group2 IO operation functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* IO operation functions *******************************************************/
|
||||
HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height);
|
||||
HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height);
|
||||
HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height);
|
||||
HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height);
|
||||
HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d);
|
||||
HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d);
|
||||
HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d);
|
||||
HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
|
||||
HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
|
||||
HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
|
||||
HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
|
||||
HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
|
||||
HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
|
||||
HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout);
|
||||
void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d);
|
||||
void HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d);
|
||||
void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DMA2D_Exported_Functions_Group3 Peripheral Control functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Peripheral Control functions *************************************************/
|
||||
HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
|
||||
HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
|
||||
HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line);
|
||||
HAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d);
|
||||
HAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d);
|
||||
HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DMA2D_Exported_Functions_Group4 Peripheral State and Error functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Peripheral State functions ***************************************************/
|
||||
HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d);
|
||||
uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
|
||||
/** @addtogroup DMA2D_Private_Constants DMA2D Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DMA2D_Maximum_Line_WaterMark DMA2D Maximum Line Watermark
|
||||
* @{
|
||||
*/
|
||||
#define DMA2D_LINE_WATERMARK_MAX DMA2D_LWR_LW /*!< DMA2D maximum line watermark */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA2D_Color_Value DMA2D Color Value
|
||||
* @{
|
||||
*/
|
||||
#define DMA2D_COLOR_VALUE ((uint32_t)0x000000FFU) /*!< Color value mask */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA2D_Max_Layer DMA2D Maximum Number of Layers
|
||||
* @{
|
||||
*/
|
||||
#define DMA2D_MAX_LAYER 2 /*!< DMA2D maximum number of layers */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA2D_Offset DMA2D Offset
|
||||
* @{
|
||||
*/
|
||||
#define DMA2D_OFFSET DMA2D_FGOR_LO /*!< Line Offset */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA2D_Size DMA2D Size
|
||||
* @{
|
||||
*/
|
||||
#define DMA2D_PIXEL (DMA2D_NLR_PL >> 16U) /*!< DMA2D number of pixels per line */
|
||||
#define DMA2D_LINE DMA2D_NLR_NL /*!< DMA2D number of lines */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA2D_CLUT_Size DMA2D CLUT Size
|
||||
* @{
|
||||
*/
|
||||
#define DMA2D_CLUT_SIZE (DMA2D_FGPFCCR_CS >> 8) /*!< DMA2D CLUT size */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup DMA2D_Private_Macros DMA2D Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_DMA2D_LAYER(LAYER) ((LAYER) <= DMA2D_MAX_LAYER)
|
||||
#define IS_DMA2D_MODE(MODE) (((MODE) == DMA2D_M2M) || ((MODE) == DMA2D_M2M_PFC) || \
|
||||
((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M))
|
||||
#define IS_DMA2D_CMODE(MODE_ARGB) (((MODE_ARGB) == DMA2D_OUTPUT_ARGB8888) || ((MODE_ARGB) == DMA2D_OUTPUT_RGB888) || \
|
||||
((MODE_ARGB) == DMA2D_OUTPUT_RGB565) || ((MODE_ARGB) == DMA2D_OUTPUT_ARGB1555) || \
|
||||
((MODE_ARGB) == DMA2D_OUTPUT_ARGB4444))
|
||||
#define IS_DMA2D_COLOR(COLOR) ((COLOR) <= DMA2D_COLOR_VALUE)
|
||||
#define IS_DMA2D_LINE(LINE) ((LINE) <= DMA2D_LINE)
|
||||
#define IS_DMA2D_PIXEL(PIXEL) ((PIXEL) <= DMA2D_PIXEL)
|
||||
#define IS_DMA2D_OFFSET(OOFFSET) ((OOFFSET) <= DMA2D_OFFSET)
|
||||
#define IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM) (((INPUT_CM) == DMA2D_INPUT_ARGB8888) || ((INPUT_CM) == DMA2D_INPUT_RGB888) || \
|
||||
((INPUT_CM) == DMA2D_INPUT_RGB565) || ((INPUT_CM) == DMA2D_INPUT_ARGB1555) || \
|
||||
((INPUT_CM) == DMA2D_INPUT_ARGB4444) || ((INPUT_CM) == DMA2D_INPUT_L8) || \
|
||||
((INPUT_CM) == DMA2D_INPUT_AL44) || ((INPUT_CM) == DMA2D_INPUT_AL88) || \
|
||||
((INPUT_CM) == DMA2D_INPUT_L4) || ((INPUT_CM) == DMA2D_INPUT_A8) || \
|
||||
((INPUT_CM) == DMA2D_INPUT_A4))
|
||||
#define IS_DMA2D_ALPHA_MODE(AlphaMode) (((AlphaMode) == DMA2D_NO_MODIF_ALPHA) || \
|
||||
((AlphaMode) == DMA2D_REPLACE_ALPHA) || \
|
||||
((AlphaMode) == DMA2D_COMBINE_ALPHA))
|
||||
|
||||
#define IS_DMA2D_ALPHA_INVERTED(Alpha_Inverted) (((Alpha_Inverted) == DMA2D_REGULAR_ALPHA) || \
|
||||
((Alpha_Inverted) == DMA2D_INVERTED_ALPHA))
|
||||
|
||||
#define IS_DMA2D_RB_SWAP(RB_Swap) (((RB_Swap) == DMA2D_RB_REGULAR) || \
|
||||
((RB_Swap) == DMA2D_RB_SWAP))
|
||||
|
||||
#define IS_DMA2D_CLUT_CM(CLUT_CM) (((CLUT_CM) == DMA2D_CCM_ARGB8888) || ((CLUT_CM) == DMA2D_CCM_RGB888))
|
||||
#define IS_DMA2D_CLUT_SIZE(CLUT_SIZE) ((CLUT_SIZE) <= DMA2D_CLUT_SIZE)
|
||||
#define IS_DMA2D_LINEWATERMARK(LineWatermark) ((LineWatermark) <= DMA2D_LINE_WATERMARK_MAX)
|
||||
#define IS_DMA2D_IT(IT) (((IT) == DMA2D_IT_CTC) || ((IT) == DMA2D_IT_CAE) || \
|
||||
((IT) == DMA2D_IT_TW) || ((IT) == DMA2D_IT_TC) || \
|
||||
((IT) == DMA2D_IT_TE) || ((IT) == DMA2D_IT_CE))
|
||||
#define IS_DMA2D_GET_FLAG(FLAG) (((FLAG) == DMA2D_FLAG_CTC) || ((FLAG) == DMA2D_FLAG_CAE) || \
|
||||
((FLAG) == DMA2D_FLAG_TW) || ((FLAG) == DMA2D_FLAG_TC) || \
|
||||
((FLAG) == DMA2D_FLAG_TE) || ((FLAG) == DMA2D_FLAG_CE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* DMA2D */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F7xx_HAL_DMA2D_H */
|
||||
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,203 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_hal_dma_ex.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.2
|
||||
* @date 14-April-2017
|
||||
* @brief Header file of DMA HAL extension module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F7xx_HAL_DMA_EX_H
|
||||
#define __STM32F7xx_HAL_DMA_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DMAEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup DMAEx_Exported_Types DMAEx Exported Types
|
||||
* @brief DMAEx Exported types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief HAL DMA Memory definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
MEMORY0 = 0x00U, /*!< Memory 0 */
|
||||
MEMORY1 = 0x01U, /*!< Memory 1 */
|
||||
|
||||
}HAL_DMA_MemoryTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DMA_Exported_Constants DMA Exported Constants
|
||||
* @brief DMA Exported constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DMAEx_Channel_selection DMA Channel selection
|
||||
* @brief DMAEx channel selection
|
||||
* @{
|
||||
*/
|
||||
#define DMA_CHANNEL_0 ((uint32_t)0x00000000U) /*!< DMA Channel 0 */
|
||||
#define DMA_CHANNEL_1 ((uint32_t)0x02000000U) /*!< DMA Channel 1 */
|
||||
#define DMA_CHANNEL_2 ((uint32_t)0x04000000U) /*!< DMA Channel 2 */
|
||||
#define DMA_CHANNEL_3 ((uint32_t)0x06000000U) /*!< DMA Channel 3 */
|
||||
#define DMA_CHANNEL_4 ((uint32_t)0x08000000U) /*!< DMA Channel 4 */
|
||||
#define DMA_CHANNEL_5 ((uint32_t)0x0A000000U) /*!< DMA Channel 5 */
|
||||
#define DMA_CHANNEL_6 ((uint32_t)0x0C000000U) /*!< DMA Channel 6 */
|
||||
#define DMA_CHANNEL_7 ((uint32_t)0x0E000000U) /*!< DMA Channel 7 */
|
||||
#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\
|
||||
defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\
|
||||
defined (STM32F779xx)
|
||||
#define DMA_CHANNEL_8 ((uint32_t)0x10000000U) /*!< DMA Channel 8 */
|
||||
#define DMA_CHANNEL_9 ((uint32_t)0x12000000U) /*!< DMA Channel 9 */
|
||||
#define DMA_CHANNEL_10 ((uint32_t)0x14000000U) /*!< DMA Channel 10*/
|
||||
#define DMA_CHANNEL_11 ((uint32_t)0x16000000U) /*!< DMA Channel 11*/
|
||||
#define DMA_CHANNEL_12 ((uint32_t)0x18000000U) /*!< DMA Channel 12*/
|
||||
#define DMA_CHANNEL_13 ((uint32_t)0x1A000000U) /*!< DMA Channel 13*/
|
||||
#define DMA_CHANNEL_14 ((uint32_t)0x1C000000U) /*!< DMA Channel 14*/
|
||||
#define DMA_CHANNEL_15 ((uint32_t)0x1E000000U) /*!< DMA Channel 15*/
|
||||
#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx ||
|
||||
STM32F769xx || STM32F777xx || STM32F779xx */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup DMAEx_Exported_Functions DMAEx Exported Functions
|
||||
* @brief DMAEx Exported functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DMAEx_Exported_Functions_Group1 Extended features functions
|
||||
* @brief Extended features functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* IO operation functions *******************************************************/
|
||||
HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength);
|
||||
HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength);
|
||||
HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup DMAEx_Private_Macros DMA Private Macros
|
||||
* @brief DMAEx private macros
|
||||
* @{
|
||||
*/
|
||||
#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\
|
||||
defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\
|
||||
defined (STM32F779xx)
|
||||
#define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \
|
||||
((CHANNEL) == DMA_CHANNEL_1) || \
|
||||
((CHANNEL) == DMA_CHANNEL_2) || \
|
||||
((CHANNEL) == DMA_CHANNEL_3) || \
|
||||
((CHANNEL) == DMA_CHANNEL_4) || \
|
||||
((CHANNEL) == DMA_CHANNEL_5) || \
|
||||
((CHANNEL) == DMA_CHANNEL_6) || \
|
||||
((CHANNEL) == DMA_CHANNEL_7) || \
|
||||
((CHANNEL) == DMA_CHANNEL_8) || \
|
||||
((CHANNEL) == DMA_CHANNEL_9) || \
|
||||
((CHANNEL) == DMA_CHANNEL_10) || \
|
||||
((CHANNEL) == DMA_CHANNEL_11) || \
|
||||
((CHANNEL) == DMA_CHANNEL_12) || \
|
||||
((CHANNEL) == DMA_CHANNEL_13) || \
|
||||
((CHANNEL) == DMA_CHANNEL_14) || \
|
||||
((CHANNEL) == DMA_CHANNEL_15))
|
||||
#else
|
||||
#define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \
|
||||
((CHANNEL) == DMA_CHANNEL_1) || \
|
||||
((CHANNEL) == DMA_CHANNEL_2) || \
|
||||
((CHANNEL) == DMA_CHANNEL_3) || \
|
||||
((CHANNEL) == DMA_CHANNEL_4) || \
|
||||
((CHANNEL) == DMA_CHANNEL_5) || \
|
||||
((CHANNEL) == DMA_CHANNEL_6) || \
|
||||
((CHANNEL) == DMA_CHANNEL_7))
|
||||
#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx ||
|
||||
STM32F769xx || STM32F777xx || STM32F779xx */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup DMAEx_Private_Functions DMAEx Private Functions
|
||||
* @brief DMAEx Private functions
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F7xx_HAL_DMA_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,426 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_hal_flash.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.2
|
||||
* @date 14-April-2017
|
||||
* @brief Header file of FLASH HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F7xx_HAL_FLASH_H
|
||||
#define __STM32F7xx_HAL_FLASH_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASH
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup FLASH_Exported_Types FLASH Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief FLASH Procedure structure definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
FLASH_PROC_NONE = 0U,
|
||||
FLASH_PROC_SECTERASE,
|
||||
FLASH_PROC_MASSERASE,
|
||||
FLASH_PROC_PROGRAM
|
||||
} FLASH_ProcedureTypeDef;
|
||||
|
||||
|
||||
/**
|
||||
* @brief FLASH handle Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IO FLASH_ProcedureTypeDef ProcedureOnGoing; /* Internal variable to indicate which procedure is ongoing or not in IT context */
|
||||
|
||||
__IO uint32_t NbSectorsToErase; /* Internal variable to save the remaining sectors to erase in IT context */
|
||||
|
||||
__IO uint8_t VoltageForErase; /* Internal variable to provide voltage range selected by user in IT context */
|
||||
|
||||
__IO uint32_t Sector; /* Internal variable to define the current sector which is erasing */
|
||||
|
||||
__IO uint32_t Address; /* Internal variable to save address selected for program */
|
||||
|
||||
HAL_LockTypeDef Lock; /* FLASH locking object */
|
||||
|
||||
__IO uint32_t ErrorCode; /* FLASH error code */
|
||||
|
||||
}FLASH_ProcessTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup FLASH_Exported_Constants FLASH Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Error_Code FLASH Error Code
|
||||
* @brief FLASH Error Code
|
||||
* @{
|
||||
*/
|
||||
#define HAL_FLASH_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
|
||||
#define HAL_FLASH_ERROR_ERS ((uint32_t)0x00000002U) /*!< Programming Sequence error */
|
||||
#define HAL_FLASH_ERROR_PGP ((uint32_t)0x00000004U) /*!< Programming Parallelism error */
|
||||
#define HAL_FLASH_ERROR_PGA ((uint32_t)0x00000008U) /*!< Programming Alignment error */
|
||||
#define HAL_FLASH_ERROR_WRP ((uint32_t)0x00000010U) /*!< Write protection error */
|
||||
#define HAL_FLASH_ERROR_OPERATION ((uint32_t)0x00000020U) /*!< Operation Error */
|
||||
#define HAL_FLASH_ERROR_RD ((uint32_t)0x00000040U) /*!< Read Protection Error */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Type_Program FLASH Type Program
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_TYPEPROGRAM_BYTE ((uint32_t)0x00U) /*!< Program byte (8-bit) at a specified address */
|
||||
#define FLASH_TYPEPROGRAM_HALFWORD ((uint32_t)0x01U) /*!< Program a half-word (16-bit) at a specified address */
|
||||
#define FLASH_TYPEPROGRAM_WORD ((uint32_t)0x02U) /*!< Program a word (32-bit) at a specified address */
|
||||
#define FLASH_TYPEPROGRAM_DOUBLEWORD ((uint32_t)0x03U) /*!< Program a double word (64-bit) at a specified address */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Flag_definition FLASH Flag definition
|
||||
* @brief Flag definition
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of Operation flag */
|
||||
#define FLASH_FLAG_OPERR FLASH_SR_OPERR /*!< FLASH operation Error flag */
|
||||
#define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< FLASH Write protected error flag */
|
||||
#define FLASH_FLAG_PGAERR FLASH_SR_PGAERR /*!< FLASH Programming Alignment error flag */
|
||||
#define FLASH_FLAG_PGPERR FLASH_SR_PGPERR /*!< FLASH Programming Parallelism error flag */
|
||||
#define FLASH_FLAG_ERSERR FLASH_SR_ERSERR /*!< FLASH Erasing Sequence error flag */
|
||||
#define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */
|
||||
|
||||
#if defined (FLASH_OPTCR2_PCROP)
|
||||
#define FLASH_FLAG_RDERR FLASH_SR_RDERR /*!< FLASH Read protection error flag */
|
||||
#define FLASH_FLAG_ALL_ERRORS (FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \
|
||||
FLASH_FLAG_PGPERR | FLASH_FLAG_ERSERR | FLASH_FLAG_RDERR)
|
||||
#else
|
||||
#define FLASH_FLAG_ALL_ERRORS (FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \
|
||||
FLASH_FLAG_PGPERR | FLASH_FLAG_ERSERR)
|
||||
#endif /* FLASH_OPTCR2_PCROP */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Interrupt_definition FLASH Interrupt definition
|
||||
* @brief FLASH Interrupt definition
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_IT_EOP FLASH_CR_EOPIE /*!< End of FLASH Operation Interrupt source */
|
||||
#define FLASH_IT_ERR ((uint32_t)0x02000000U) /*!< Error Interrupt source */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Program_Parallelism FLASH Program Parallelism
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_PSIZE_BYTE ((uint32_t)0x00000000U)
|
||||
#define FLASH_PSIZE_HALF_WORD ((uint32_t)FLASH_CR_PSIZE_0)
|
||||
#define FLASH_PSIZE_WORD ((uint32_t)FLASH_CR_PSIZE_1)
|
||||
#define FLASH_PSIZE_DOUBLE_WORD ((uint32_t)FLASH_CR_PSIZE)
|
||||
#define CR_PSIZE_MASK ((uint32_t)0xFFFFFCFFU)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Keys FLASH Keys
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_KEY1 ((uint32_t)0x45670123U)
|
||||
#define FLASH_KEY2 ((uint32_t)0xCDEF89ABU)
|
||||
#define FLASH_OPT_KEY1 ((uint32_t)0x08192A3BU)
|
||||
#define FLASH_OPT_KEY2 ((uint32_t)0x4C5D6E7FU)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Sectors FLASH Sectors
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_SECTOR_0 ((uint32_t)0U) /*!< Sector Number 0 */
|
||||
#define FLASH_SECTOR_1 ((uint32_t)1U) /*!< Sector Number 1 */
|
||||
#define FLASH_SECTOR_2 ((uint32_t)2U) /*!< Sector Number 2 */
|
||||
#define FLASH_SECTOR_3 ((uint32_t)3U) /*!< Sector Number 3 */
|
||||
#define FLASH_SECTOR_4 ((uint32_t)4U) /*!< Sector Number 4 */
|
||||
#define FLASH_SECTOR_5 ((uint32_t)5U) /*!< Sector Number 5 */
|
||||
#define FLASH_SECTOR_6 ((uint32_t)6U) /*!< Sector Number 6 */
|
||||
#define FLASH_SECTOR_7 ((uint32_t)7U) /*!< Sector Number 7 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup FLASH_Exported_Macros FLASH Exported Macros
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Set the FLASH Latency.
|
||||
* @param __LATENCY__: FLASH Latency
|
||||
* The value of this parameter depend on device used within the same series
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_FLASH_SET_LATENCY(__LATENCY__) \
|
||||
MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(__LATENCY__))
|
||||
|
||||
/**
|
||||
* @brief Get the FLASH Latency.
|
||||
* @retval FLASH Latency
|
||||
* The value of this parameter depend on device used within the same series
|
||||
*/
|
||||
#define __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))
|
||||
|
||||
/**
|
||||
* @brief Enable the FLASH prefetch buffer.
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() (FLASH->ACR |= FLASH_ACR_PRFTEN)
|
||||
|
||||
/**
|
||||
* @brief Disable the FLASH prefetch buffer.
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() (FLASH->ACR &= (~FLASH_ACR_PRFTEN))
|
||||
|
||||
/**
|
||||
* @brief Enable the FLASH Adaptive Real-Time memory accelerator.
|
||||
* @note The ART accelerator is available only for flash access on ITCM interface.
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_FLASH_ART_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_ARTEN)
|
||||
|
||||
/**
|
||||
* @brief Disable the FLASH Adaptive Real-Time memory accelerator.
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_FLASH_ART_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_ARTEN)
|
||||
|
||||
/**
|
||||
* @brief Resets the FLASH Adaptive Real-Time memory accelerator.
|
||||
* @note This function must be used only when the Adaptive Real-Time memory accelerator
|
||||
* is disabled.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_FLASH_ART_RESET() (FLASH->ACR |= FLASH_ACR_ARTRST)
|
||||
|
||||
/**
|
||||
* @brief Enable the specified FLASH interrupt.
|
||||
* @param __INTERRUPT__ : FLASH interrupt
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg FLASH_IT_EOP: End of FLASH Operation Interrupt
|
||||
* @arg FLASH_IT_ERR: Error Interrupt
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) (FLASH->CR |= (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Disable the specified FLASH interrupt.
|
||||
* @param __INTERRUPT__ : FLASH interrupt
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg FLASH_IT_EOP: End of FLASH Operation Interrupt
|
||||
* @arg FLASH_IT_ERR: Error Interrupt
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) (FLASH->CR &= ~(uint32_t)(__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Get the specified FLASH flag status.
|
||||
* @param __FLAG__: specifies the FLASH flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg FLASH_FLAG_EOP : FLASH End of Operation flag
|
||||
* @arg FLASH_FLAG_OPERR : FLASH operation Error flag
|
||||
* @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag
|
||||
* @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag
|
||||
* @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag
|
||||
* @arg FLASH_FLAG_ERSERR : FLASH Erasing Sequence error flag
|
||||
* @arg FLASH_FLAG_BSY : FLASH Busy flag
|
||||
* @retval The new state of __FLAG__ (SET or RESET).
|
||||
*/
|
||||
#define __HAL_FLASH_GET_FLAG(__FLAG__) ((FLASH->SR & (__FLAG__)))
|
||||
|
||||
/**
|
||||
* @brief Clear the specified FLASH flag.
|
||||
* @param __FLAG__: specifies the FLASH flags to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg FLASH_FLAG_EOP : FLASH End of Operation flag
|
||||
* @arg FLASH_FLAG_OPERR : FLASH operation Error flag
|
||||
* @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag
|
||||
* @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag
|
||||
* @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag
|
||||
* @arg FLASH_FLAG_ERSERR : FLASH Erasing Sequence error flag
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) (FLASH->SR = (__FLAG__))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include FLASH HAL Extension module */
|
||||
#include "stm32f7xx_hal_flash_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup FLASH_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
/** @addtogroup FLASH_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Program operation functions ***********************************************/
|
||||
HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
|
||||
HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
|
||||
/* FLASH IRQ handler method */
|
||||
void HAL_FLASH_IRQHandler(void);
|
||||
/* Callbacks in non blocking modes */
|
||||
void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);
|
||||
void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASH_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral Control functions **********************************************/
|
||||
HAL_StatusTypeDef HAL_FLASH_Unlock(void);
|
||||
HAL_StatusTypeDef HAL_FLASH_Lock(void);
|
||||
HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void);
|
||||
HAL_StatusTypeDef HAL_FLASH_OB_Lock(void);
|
||||
/* Option bytes control */
|
||||
HAL_StatusTypeDef HAL_FLASH_OB_Launch(void);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASH_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State functions ************************************************/
|
||||
uint32_t HAL_FLASH_GetError(void);
|
||||
HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/** @defgroup FLASH_Private_Variables FLASH Private Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup FLASH_Private_Constants FLASH Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief OPTCR register byte 1 (Bits[15:8]) base address
|
||||
*/
|
||||
#define OPTCR_BYTE1_ADDRESS ((uint32_t)0x40023C15)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup FLASH_Private_Macros FLASH Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_IS_FLASH_Definitions FLASH Private macros to check input parameters
|
||||
* @{
|
||||
*/
|
||||
#define IS_FLASH_TYPEPROGRAM(VALUE)(((VALUE) == FLASH_TYPEPROGRAM_BYTE) || \
|
||||
((VALUE) == FLASH_TYPEPROGRAM_HALFWORD) || \
|
||||
((VALUE) == FLASH_TYPEPROGRAM_WORD) || \
|
||||
((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup FLASH_Private_Functions FLASH Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F7xx_HAL_FLASH_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,663 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_hal_flash_ex.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.2
|
||||
* @date 14-April-2017
|
||||
* @brief Header file of FLASH HAL Extension module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F7xx_HAL_FLASH_EX_H
|
||||
#define __STM32F7xx_HAL_FLASH_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASHEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup FLASHEx_Exported_Types FLASH Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief FLASH Erase structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t TypeErase; /*!< Mass erase or sector Erase.
|
||||
This parameter can be a value of @ref FLASHEx_Type_Erase */
|
||||
|
||||
#if defined (FLASH_OPTCR_nDBANK)
|
||||
uint32_t Banks; /*!< Select banks to erase when Mass erase is enabled.
|
||||
This parameter must be a value of @ref FLASHEx_Banks */
|
||||
#endif /* FLASH_OPTCR_nDBANK */
|
||||
|
||||
uint32_t Sector; /*!< Initial FLASH sector to erase when Mass erase is disabled
|
||||
This parameter must be a value of @ref FLASHEx_Sectors */
|
||||
|
||||
uint32_t NbSectors; /*!< Number of sectors to be erased.
|
||||
This parameter must be a value between 1 and (max number of sectors - value of Initial sector)*/
|
||||
|
||||
uint32_t VoltageRange;/*!< The device voltage range which defines the erase parallelism
|
||||
This parameter must be a value of @ref FLASHEx_Voltage_Range */
|
||||
|
||||
} FLASH_EraseInitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief FLASH Option Bytes Program structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t OptionType; /*!< Option byte to be configured.
|
||||
This parameter can be a value of @ref FLASHEx_Option_Type */
|
||||
|
||||
uint32_t WRPState; /*!< Write protection activation or deactivation.
|
||||
This parameter can be a value of @ref FLASHEx_WRP_State */
|
||||
|
||||
uint32_t WRPSector; /*!< Specifies the sector(s) to be write protected.
|
||||
The value of this parameter depend on device used within the same series */
|
||||
|
||||
uint32_t RDPLevel; /*!< Set the read protection level.
|
||||
This parameter can be a value of @ref FLASHEx_Option_Bytes_Read_Protection */
|
||||
|
||||
uint32_t BORLevel; /*!< Set the BOR Level.
|
||||
This parameter can be a value of @ref FLASHEx_BOR_Reset_Level */
|
||||
|
||||
uint32_t USERConfig; /*!< Program the FLASH User Option Byte: WWDG_SW / IWDG_SW / RST_STOP / RST_STDBY /
|
||||
IWDG_FREEZE_STOP / IWDG_FREEZE_SANDBY / nDBANK / nDBOOT.
|
||||
nDBANK / nDBOOT are only available for STM32F76xxx/STM32F77xxx devices */
|
||||
|
||||
uint32_t BootAddr0; /*!< Boot base address when Boot pin = 0.
|
||||
This parameter can be a value of @ref FLASHEx_Boot_Address */
|
||||
|
||||
uint32_t BootAddr1; /*!< Boot base address when Boot pin = 1.
|
||||
This parameter can be a value of @ref FLASHEx_Boot_Address */
|
||||
|
||||
#if defined (FLASH_OPTCR2_PCROP)
|
||||
uint32_t PCROPSector; /*!< Set the PCROP sector.
|
||||
This parameter can be a value of @ref FLASHEx_Option_Bytes_PCROP_Sectors */
|
||||
|
||||
uint32_t PCROPRdp; /*!< Set the PCROP_RDP option.
|
||||
This parameter can be a value of @ref FLASHEx_Option_Bytes_PCROP_RDP */
|
||||
#endif /* FLASH_OPTCR2_PCROP */
|
||||
|
||||
} FLASH_OBProgramInitTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup FLASHEx_Exported_Constants FLASH Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_Type_Erase FLASH Type Erase
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_TYPEERASE_SECTORS ((uint32_t)0x00U) /*!< Sectors erase only */
|
||||
#define FLASH_TYPEERASE_MASSERASE ((uint32_t)0x01U) /*!< Flash Mass erase activation */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_Voltage_Range FLASH Voltage Range
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_VOLTAGE_RANGE_1 ((uint32_t)0x00U) /*!< Device operating range: 1.8V to 2.1V */
|
||||
#define FLASH_VOLTAGE_RANGE_2 ((uint32_t)0x01U) /*!< Device operating range: 2.1V to 2.7V */
|
||||
#define FLASH_VOLTAGE_RANGE_3 ((uint32_t)0x02U) /*!< Device operating range: 2.7V to 3.6V */
|
||||
#define FLASH_VOLTAGE_RANGE_4 ((uint32_t)0x03U) /*!< Device operating range: 2.7V to 3.6V + External Vpp */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_WRP_State FLASH WRP State
|
||||
* @{
|
||||
*/
|
||||
#define OB_WRPSTATE_DISABLE ((uint32_t)0x00U) /*!< Disable the write protection of the desired bank 1 sectors */
|
||||
#define OB_WRPSTATE_ENABLE ((uint32_t)0x01U) /*!< Enable the write protection of the desired bank 1 sectors */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_Option_Type FLASH Option Type
|
||||
* @{
|
||||
*/
|
||||
#define OPTIONBYTE_WRP ((uint32_t)0x01U) /*!< WRP option byte configuration */
|
||||
#define OPTIONBYTE_RDP ((uint32_t)0x02U) /*!< RDP option byte configuration */
|
||||
#define OPTIONBYTE_USER ((uint32_t)0x04U) /*!< USER option byte configuration */
|
||||
#define OPTIONBYTE_BOR ((uint32_t)0x08U) /*!< BOR option byte configuration */
|
||||
#define OPTIONBYTE_BOOTADDR_0 ((uint32_t)0x10U) /*!< Boot 0 Address configuration */
|
||||
#define OPTIONBYTE_BOOTADDR_1 ((uint32_t)0x20U) /*!< Boot 1 Address configuration */
|
||||
#if defined (FLASH_OPTCR2_PCROP)
|
||||
#define OPTIONBYTE_PCROP ((uint32_t)0x40U) /*!< PCROP configuration */
|
||||
#define OPTIONBYTE_PCROP_RDP ((uint32_t)0x80U) /*!< PCROP_RDP configuration */
|
||||
#endif /* FLASH_OPTCR2_PCROP */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_Option_Bytes_Read_Protection FLASH Option Bytes Read Protection
|
||||
* @{
|
||||
*/
|
||||
#define OB_RDP_LEVEL_0 ((uint8_t)0xAAU)
|
||||
#define OB_RDP_LEVEL_1 ((uint8_t)0x55U)
|
||||
#define OB_RDP_LEVEL_2 ((uint8_t)0xCCU) /*!< Warning: When enabling read protection level 2
|
||||
it s no more possible to go back to level 1 or 0 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_Option_Bytes_WWatchdog FLASH Option Bytes WWatchdog
|
||||
* @{
|
||||
*/
|
||||
#define OB_WWDG_SW ((uint32_t)0x10U) /*!< Software WWDG selected */
|
||||
#define OB_WWDG_HW ((uint32_t)0x00U) /*!< Hardware WWDG selected */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup FLASHEx_Option_Bytes_IWatchdog FLASH Option Bytes IWatchdog
|
||||
* @{
|
||||
*/
|
||||
#define OB_IWDG_SW ((uint32_t)0x20U) /*!< Software IWDG selected */
|
||||
#define OB_IWDG_HW ((uint32_t)0x00U) /*!< Hardware IWDG selected */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_Option_Bytes_nRST_STOP FLASH Option Bytes nRST_STOP
|
||||
* @{
|
||||
*/
|
||||
#define OB_STOP_NO_RST ((uint32_t)0x40U) /*!< No reset generated when entering in STOP */
|
||||
#define OB_STOP_RST ((uint32_t)0x00U) /*!< Reset generated when entering in STOP */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_Option_Bytes_nRST_STDBY FLASH Option Bytes nRST_STDBY
|
||||
* @{
|
||||
*/
|
||||
#define OB_STDBY_NO_RST ((uint32_t)0x80U) /*!< No reset generated when entering in STANDBY */
|
||||
#define OB_STDBY_RST ((uint32_t)0x00U) /*!< Reset generated when entering in STANDBY */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_Option_Bytes_IWDG_FREEZE_STOP FLASH IWDG Counter Freeze in STOP
|
||||
* @{
|
||||
*/
|
||||
#define OB_IWDG_STOP_FREEZE ((uint32_t)0x00000000U) /*!< Freeze IWDG counter in STOP mode */
|
||||
#define OB_IWDG_STOP_ACTIVE ((uint32_t)0x80000000U) /*!< IWDG counter active in STOP mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_Option_Bytes_IWDG_FREEZE_SANDBY FLASH IWDG Counter Freeze in STANDBY
|
||||
* @{
|
||||
*/
|
||||
#define OB_IWDG_STDBY_FREEZE ((uint32_t)0x00000000U) /*!< Freeze IWDG counter in STANDBY mode */
|
||||
#define OB_IWDG_STDBY_ACTIVE ((uint32_t)0x40000000U) /*!< IWDG counter active in STANDBY mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_BOR_Reset_Level FLASH BOR Reset Level
|
||||
* @{
|
||||
*/
|
||||
#define OB_BOR_LEVEL3 ((uint32_t)0x00U) /*!< Supply voltage ranges from 2.70 to 3.60 V */
|
||||
#define OB_BOR_LEVEL2 ((uint32_t)0x04U) /*!< Supply voltage ranges from 2.40 to 2.70 V */
|
||||
#define OB_BOR_LEVEL1 ((uint32_t)0x08U) /*!< Supply voltage ranges from 2.10 to 2.40 V */
|
||||
#define OB_BOR_OFF ((uint32_t)0x0CU) /*!< Supply voltage ranges from 1.62 to 2.10 V */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined (FLASH_OPTCR_nDBOOT)
|
||||
/** @defgroup FLASHEx_Option_Bytes_nDBOOT FLASH Option Bytes nDBOOT
|
||||
* @{
|
||||
*/
|
||||
#define OB_DUAL_BOOT_DISABLE ((uint32_t)0x10000000U) /* !< Dual Boot disable. Boot according to boot address option */
|
||||
#define OB_DUAL_BOOT_ENABLE ((uint32_t)0x00000000U) /* !< Dual Boot enable. Boot always from system memory if boot address in flash
|
||||
(Dual bank Boot mode), or RAM if Boot address option in RAM */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* FLASH_OPTCR_nDBOOT */
|
||||
|
||||
#if defined (FLASH_OPTCR_nDBANK)
|
||||
/** @defgroup FLASHEx_Option_Bytes_nDBank FLASH Single Bank or Dual Bank
|
||||
* @{
|
||||
*/
|
||||
#define OB_NDBANK_SINGLE_BANK ((uint32_t)0x20000000U) /*!< NDBANK bit is set : Single Bank mode */
|
||||
#define OB_NDBANK_DUAL_BANK ((uint32_t)0x00000000U) /*!< NDBANK bit is reset : Dual Bank mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* FLASH_OPTCR_nDBANK */
|
||||
|
||||
/** @defgroup FLASHEx_Boot_Address FLASH Boot Address
|
||||
* @{
|
||||
*/
|
||||
#define OB_BOOTADDR_ITCM_RAM ((uint32_t)0x0000U) /*!< Boot from ITCM RAM (0x00000000) */
|
||||
#define OB_BOOTADDR_SYSTEM ((uint32_t)0x0040U) /*!< Boot from System memory bootloader (0x00100000) */
|
||||
#define OB_BOOTADDR_ITCM_FLASH ((uint32_t)0x0080U) /*!< Boot from Flash on ITCM interface (0x00200000) */
|
||||
#define OB_BOOTADDR_AXIM_FLASH ((uint32_t)0x2000U) /*!< Boot from Flash on AXIM interface (0x08000000) */
|
||||
#define OB_BOOTADDR_DTCM_RAM ((uint32_t)0x8000U) /*!< Boot from DTCM RAM (0x20000000) */
|
||||
#define OB_BOOTADDR_SRAM1 ((uint32_t)0x8004U) /*!< Boot from SRAM1 (0x20010000) */
|
||||
#if (SRAM2_BASE == 0x2003C000U)
|
||||
#define OB_BOOTADDR_SRAM2 ((uint32_t)0x800FU) /*!< Boot from SRAM2 (0x2003C000) */
|
||||
#else
|
||||
#define OB_BOOTADDR_SRAM2 ((uint32_t)0x8013U) /*!< Boot from SRAM2 (0x2004C000) */
|
||||
#endif /* SRAM2_BASE == 0x2003C000U */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Latency FLASH Latency
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero Latency cycle */
|
||||
#define FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One Latency cycle */
|
||||
#define FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two Latency cycles */
|
||||
#define FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three Latency cycles */
|
||||
#define FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH Four Latency cycles */
|
||||
#define FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH Five Latency cycles */
|
||||
#define FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH Six Latency cycles */
|
||||
#define FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH Seven Latency cycles */
|
||||
#define FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS /*!< FLASH Eight Latency cycles */
|
||||
#define FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS /*!< FLASH Nine Latency cycles */
|
||||
#define FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS /*!< FLASH Ten Latency cycles */
|
||||
#define FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS /*!< FLASH Eleven Latency cycles */
|
||||
#define FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS /*!< FLASH Twelve Latency cycles */
|
||||
#define FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS /*!< FLASH Thirteen Latency cycles */
|
||||
#define FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS /*!< FLASH Fourteen Latency cycles */
|
||||
#define FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS /*!< FLASH Fifteen Latency cycles */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined (FLASH_OPTCR_nDBANK)
|
||||
/** @defgroup FLASHEx_Banks FLASH Banks
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_BANK_1 ((uint32_t)0x01U) /*!< Bank 1 */
|
||||
#define FLASH_BANK_2 ((uint32_t)0x02U) /*!< Bank 2 */
|
||||
#define FLASH_BANK_BOTH ((uint32_t)(FLASH_BANK_1 | FLASH_BANK_2)) /*!< Bank1 and Bank2 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* FLASH_OPTCR_nDBANK */
|
||||
|
||||
/** @defgroup FLASHEx_MassErase_bit FLASH Mass Erase bit
|
||||
* @{
|
||||
*/
|
||||
#if defined (FLASH_OPTCR_nDBANK)
|
||||
#define FLASH_MER_BIT (FLASH_CR_MER1 | FLASH_CR_MER2) /*!< 2 MER bits */
|
||||
#else
|
||||
#define FLASH_MER_BIT (FLASH_CR_MER) /*!< only 1 MER bit */
|
||||
#endif /* FLASH_OPTCR_nDBANK */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_Sectors FLASH Sectors
|
||||
* @{
|
||||
*/
|
||||
#if (FLASH_SECTOR_TOTAL == 24)
|
||||
#define FLASH_SECTOR_8 ((uint32_t)8U) /*!< Sector Number 8 */
|
||||
#define FLASH_SECTOR_9 ((uint32_t)9U) /*!< Sector Number 9 */
|
||||
#define FLASH_SECTOR_10 ((uint32_t)10U) /*!< Sector Number 10 */
|
||||
#define FLASH_SECTOR_11 ((uint32_t)11U) /*!< Sector Number 11 */
|
||||
#define FLASH_SECTOR_12 ((uint32_t)12U) /*!< Sector Number 12 */
|
||||
#define FLASH_SECTOR_13 ((uint32_t)13U) /*!< Sector Number 13 */
|
||||
#define FLASH_SECTOR_14 ((uint32_t)14U) /*!< Sector Number 14 */
|
||||
#define FLASH_SECTOR_15 ((uint32_t)15U) /*!< Sector Number 15 */
|
||||
#define FLASH_SECTOR_16 ((uint32_t)16U) /*!< Sector Number 16 */
|
||||
#define FLASH_SECTOR_17 ((uint32_t)17U) /*!< Sector Number 17 */
|
||||
#define FLASH_SECTOR_18 ((uint32_t)18U) /*!< Sector Number 18 */
|
||||
#define FLASH_SECTOR_19 ((uint32_t)19U) /*!< Sector Number 19 */
|
||||
#define FLASH_SECTOR_20 ((uint32_t)20U) /*!< Sector Number 20 */
|
||||
#define FLASH_SECTOR_21 ((uint32_t)21U) /*!< Sector Number 21 */
|
||||
#define FLASH_SECTOR_22 ((uint32_t)22U) /*!< Sector Number 22 */
|
||||
#define FLASH_SECTOR_23 ((uint32_t)23U) /*!< Sector Number 23 */
|
||||
#endif /* FLASH_SECTOR_TOTAL == 24 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if (FLASH_SECTOR_TOTAL == 24)
|
||||
/** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection
|
||||
* @note For Single Bank mode, use OB_WRP_SECTOR_x defines: In fact, in FLASH_OPTCR register,
|
||||
* nWRP[11:0] bits contain the value of the write-protection option bytes for sectors 0 to 11.
|
||||
* For Dual Bank mode, use OB_WRP_DB_SECTOR_x defines: In fact, in FLASH_OPTCR register,
|
||||
* nWRP[11:0] bits are divided on two groups, one group dedicated for bank 1 and
|
||||
* a second one dedicated for bank 2 (nWRP[i] activates Write protection on sector 2*i and 2*i+1).
|
||||
* This behavior is applicable only for STM32F76xxx / STM32F77xxx devices.
|
||||
* @{
|
||||
*/
|
||||
/* Single Bank Sectors */
|
||||
#define OB_WRP_SECTOR_0 ((uint32_t)0x00010000U) /*!< Write protection of Single Bank Sector0 */
|
||||
#define OB_WRP_SECTOR_1 ((uint32_t)0x00020000U) /*!< Write protection of Single Bank Sector1 */
|
||||
#define OB_WRP_SECTOR_2 ((uint32_t)0x00040000U) /*!< Write protection of Single Bank Sector2 */
|
||||
#define OB_WRP_SECTOR_3 ((uint32_t)0x00080000U) /*!< Write protection of Single Bank Sector3 */
|
||||
#define OB_WRP_SECTOR_4 ((uint32_t)0x00100000U) /*!< Write protection of Single Bank Sector4 */
|
||||
#define OB_WRP_SECTOR_5 ((uint32_t)0x00200000U) /*!< Write protection of Single Bank Sector5 */
|
||||
#define OB_WRP_SECTOR_6 ((uint32_t)0x00400000U) /*!< Write protection of Single Bank Sector6 */
|
||||
#define OB_WRP_SECTOR_7 ((uint32_t)0x00800000U) /*!< Write protection of Single Bank Sector7 */
|
||||
#define OB_WRP_SECTOR_8 ((uint32_t)0x01000000U) /*!< Write protection of Single Bank Sector8 */
|
||||
#define OB_WRP_SECTOR_9 ((uint32_t)0x02000000U) /*!< Write protection of Single Bank Sector9 */
|
||||
#define OB_WRP_SECTOR_10 ((uint32_t)0x04000000U) /*!< Write protection of Single Bank Sector10 */
|
||||
#define OB_WRP_SECTOR_11 ((uint32_t)0x08000000U) /*!< Write protection of Single Bank Sector11 */
|
||||
#define OB_WRP_SECTOR_All ((uint32_t)0x0FFF0000U) /*!< Write protection of all Sectors for Single Bank Flash */
|
||||
|
||||
/* Dual Bank Sectors */
|
||||
#define OB_WRP_DB_SECTOR_0 ((uint32_t)0x00010000U) /*!< Write protection of Dual Bank Sector0 */
|
||||
#define OB_WRP_DB_SECTOR_1 ((uint32_t)0x00010000U) /*!< Write protection of Dual Bank Sector1 */
|
||||
#define OB_WRP_DB_SECTOR_2 ((uint32_t)0x00020000U) /*!< Write protection of Dual Bank Sector2 */
|
||||
#define OB_WRP_DB_SECTOR_3 ((uint32_t)0x00020000U) /*!< Write protection of Dual Bank Sector3 */
|
||||
#define OB_WRP_DB_SECTOR_4 ((uint32_t)0x00040000U) /*!< Write protection of Dual Bank Sector4 */
|
||||
#define OB_WRP_DB_SECTOR_5 ((uint32_t)0x00040000U) /*!< Write protection of Dual Bank Sector5 */
|
||||
#define OB_WRP_DB_SECTOR_6 ((uint32_t)0x00080000U) /*!< Write protection of Dual Bank Sector6 */
|
||||
#define OB_WRP_DB_SECTOR_7 ((uint32_t)0x00080000U) /*!< Write protection of Dual Bank Sector7 */
|
||||
#define OB_WRP_DB_SECTOR_8 ((uint32_t)0x00100000U) /*!< Write protection of Dual Bank Sector8 */
|
||||
#define OB_WRP_DB_SECTOR_9 ((uint32_t)0x00100000U) /*!< Write protection of Dual Bank Sector9 */
|
||||
#define OB_WRP_DB_SECTOR_10 ((uint32_t)0x00200000U) /*!< Write protection of Dual Bank Sector10 */
|
||||
#define OB_WRP_DB_SECTOR_11 ((uint32_t)0x00200000U) /*!< Write protection of Dual Bank Sector11 */
|
||||
#define OB_WRP_DB_SECTOR_12 ((uint32_t)0x00400000U) /*!< Write protection of Dual Bank Sector12 */
|
||||
#define OB_WRP_DB_SECTOR_13 ((uint32_t)0x00400000U) /*!< Write protection of Dual Bank Sector13 */
|
||||
#define OB_WRP_DB_SECTOR_14 ((uint32_t)0x00800000U) /*!< Write protection of Dual Bank Sector14 */
|
||||
#define OB_WRP_DB_SECTOR_15 ((uint32_t)0x00800000U) /*!< Write protection of Dual Bank Sector15 */
|
||||
#define OB_WRP_DB_SECTOR_16 ((uint32_t)0x01000000U) /*!< Write protection of Dual Bank Sector16 */
|
||||
#define OB_WRP_DB_SECTOR_17 ((uint32_t)0x01000000U) /*!< Write protection of Dual Bank Sector17 */
|
||||
#define OB_WRP_DB_SECTOR_18 ((uint32_t)0x02000000U) /*!< Write protection of Dual Bank Sector18 */
|
||||
#define OB_WRP_DB_SECTOR_19 ((uint32_t)0x02000000U) /*!< Write protection of Dual Bank Sector19 */
|
||||
#define OB_WRP_DB_SECTOR_20 ((uint32_t)0x04000000U) /*!< Write protection of Dual Bank Sector20 */
|
||||
#define OB_WRP_DB_SECTOR_21 ((uint32_t)0x04000000U) /*!< Write protection of Dual Bank Sector21 */
|
||||
#define OB_WRP_DB_SECTOR_22 ((uint32_t)0x08000000U) /*!< Write protection of Dual Bank Sector22 */
|
||||
#define OB_WRP_DB_SECTOR_23 ((uint32_t)0x08000000U) /*!< Write protection of Dual Bank Sector23 */
|
||||
#define OB_WRP_DB_SECTOR_All ((uint32_t)0x0FFF0000U) /*!< Write protection of all Sectors for Dual Bank Flash */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* FLASH_SECTOR_TOTAL == 24 */
|
||||
|
||||
#if (FLASH_SECTOR_TOTAL == 8)
|
||||
/** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection
|
||||
* @{
|
||||
*/
|
||||
#define OB_WRP_SECTOR_0 ((uint32_t)0x00010000U) /*!< Write protection of Sector0 */
|
||||
#define OB_WRP_SECTOR_1 ((uint32_t)0x00020000U) /*!< Write protection of Sector1 */
|
||||
#define OB_WRP_SECTOR_2 ((uint32_t)0x00040000U) /*!< Write protection of Sector2 */
|
||||
#define OB_WRP_SECTOR_3 ((uint32_t)0x00080000U) /*!< Write protection of Sector3 */
|
||||
#define OB_WRP_SECTOR_4 ((uint32_t)0x00100000U) /*!< Write protection of Sector4 */
|
||||
#define OB_WRP_SECTOR_5 ((uint32_t)0x00200000U) /*!< Write protection of Sector5 */
|
||||
#define OB_WRP_SECTOR_6 ((uint32_t)0x00400000U) /*!< Write protection of Sector6 */
|
||||
#define OB_WRP_SECTOR_7 ((uint32_t)0x00800000U) /*!< Write protection of Sector7 */
|
||||
#define OB_WRP_SECTOR_All ((uint32_t)0x00FF0000U) /*!< Write protection of all Sectors */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* FLASH_SECTOR_TOTAL == 8 */
|
||||
|
||||
#if defined (FLASH_OPTCR2_PCROP)
|
||||
/** @defgroup FLASHEx_Option_Bytes_PCROP_Sectors FLASH Option Bytes PCROP Sectors
|
||||
* @{
|
||||
*/
|
||||
#define OB_PCROP_SECTOR_0 ((uint32_t)0x00000001U) /*!< PC Readout protection of Sector0 */
|
||||
#define OB_PCROP_SECTOR_1 ((uint32_t)0x00000002U) /*!< PC Readout protection of Sector1 */
|
||||
#define OB_PCROP_SECTOR_2 ((uint32_t)0x00000004U) /*!< PC Readout protection of Sector2 */
|
||||
#define OB_PCROP_SECTOR_3 ((uint32_t)0x00000008U) /*!< PC Readout protection of Sector3 */
|
||||
#define OB_PCROP_SECTOR_4 ((uint32_t)0x00000010U) /*!< PC Readout protection of Sector4 */
|
||||
#define OB_PCROP_SECTOR_5 ((uint32_t)0x00000020U) /*!< PC Readout protection of Sector5 */
|
||||
#define OB_PCROP_SECTOR_6 ((uint32_t)0x00000040U) /*!< PC Readout protection of Sector6 */
|
||||
#define OB_PCROP_SECTOR_7 ((uint32_t)0x00000080U) /*!< PC Readout protection of Sector7 */
|
||||
#define OB_PCROP_SECTOR_All ((uint32_t)0x000000FFU) /*!< PC Readout protection of all Sectors */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_Option_Bytes_PCROP_RDP FLASH Option Bytes PCROP_RDP Bit
|
||||
* @{
|
||||
*/
|
||||
#define OB_PCROP_RDP_ENABLE ((uint32_t)0x80000000U) /*!< PCROP_RDP Enable */
|
||||
#define OB_PCROP_RDP_DISABLE ((uint32_t)0x00000000U) /*!< PCROP_RDP Disable */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* FLASH_OPTCR2_PCROP */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup FLASH_Exported_Macros FLASH Exported Macros
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Calculate the FLASH Boot Base Adress (BOOT_ADD0 or BOOT_ADD1)
|
||||
* @note Returned value BOOT_ADDx[15:0] corresponds to boot address [29:14].
|
||||
* @param __ADDRESS__: FLASH Boot Address (in the range 0x0000 0000 to 0x2004 FFFF with a granularity of 16KB)
|
||||
* @retval The FLASH Boot Base Adress
|
||||
*/
|
||||
#define __HAL_FLASH_CALC_BOOT_BASE_ADR(__ADDRESS__) ((__ADDRESS__) >> 14)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup FLASHEx_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASHEx_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Extension Program operation functions *************************************/
|
||||
HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError);
|
||||
HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);
|
||||
HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
|
||||
void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup FLASHEx_Private_Macros FLASH Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_IS_FLASH_Definitions FLASH Private macros to check input parameters
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_FLASH_TYPEERASE(VALUE)(((VALUE) == FLASH_TYPEERASE_SECTORS) || \
|
||||
((VALUE) == FLASH_TYPEERASE_MASSERASE))
|
||||
|
||||
#define IS_VOLTAGERANGE(RANGE)(((RANGE) == FLASH_VOLTAGE_RANGE_1) || \
|
||||
((RANGE) == FLASH_VOLTAGE_RANGE_2) || \
|
||||
((RANGE) == FLASH_VOLTAGE_RANGE_3) || \
|
||||
((RANGE) == FLASH_VOLTAGE_RANGE_4))
|
||||
|
||||
#define IS_WRPSTATE(VALUE)(((VALUE) == OB_WRPSTATE_DISABLE) || \
|
||||
((VALUE) == OB_WRPSTATE_ENABLE))
|
||||
|
||||
#if defined (FLASH_OPTCR2_PCROP)
|
||||
#define IS_OPTIONBYTE(VALUE)(((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\
|
||||
OPTIONBYTE_BOR | OPTIONBYTE_BOOTADDR_0 | OPTIONBYTE_BOOTADDR_1 |\
|
||||
OPTIONBYTE_PCROP | OPTIONBYTE_PCROP_RDP)))
|
||||
#else
|
||||
#define IS_OPTIONBYTE(VALUE)(((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\
|
||||
OPTIONBYTE_BOR | OPTIONBYTE_BOOTADDR_0 | OPTIONBYTE_BOOTADDR_1)))
|
||||
#endif /* FLASH_OPTCR2_PCROP */
|
||||
|
||||
#define IS_OB_BOOT_ADDRESS(ADDRESS) ((ADDRESS) <= 0x8013)
|
||||
|
||||
#define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\
|
||||
((LEVEL) == OB_RDP_LEVEL_1) ||\
|
||||
((LEVEL) == OB_RDP_LEVEL_2))
|
||||
|
||||
#define IS_OB_WWDG_SOURCE(SOURCE) (((SOURCE) == OB_WWDG_SW) || ((SOURCE) == OB_WWDG_HW))
|
||||
|
||||
#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
|
||||
|
||||
#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST))
|
||||
|
||||
#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST))
|
||||
|
||||
#define IS_OB_IWDG_STOP_FREEZE(FREEZE) (((FREEZE) == OB_IWDG_STOP_FREEZE) || ((FREEZE) == OB_IWDG_STOP_ACTIVE))
|
||||
|
||||
#define IS_OB_IWDG_STDBY_FREEZE(FREEZE) (((FREEZE) == OB_IWDG_STDBY_FREEZE) || ((FREEZE) == OB_IWDG_STDBY_ACTIVE))
|
||||
|
||||
#define IS_OB_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL1) || ((LEVEL) == OB_BOR_LEVEL2) ||\
|
||||
((LEVEL) == OB_BOR_LEVEL3) || ((LEVEL) == OB_BOR_OFF))
|
||||
|
||||
#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || \
|
||||
((LATENCY) == FLASH_LATENCY_1) || \
|
||||
((LATENCY) == FLASH_LATENCY_2) || \
|
||||
((LATENCY) == FLASH_LATENCY_3) || \
|
||||
((LATENCY) == FLASH_LATENCY_4) || \
|
||||
((LATENCY) == FLASH_LATENCY_5) || \
|
||||
((LATENCY) == FLASH_LATENCY_6) || \
|
||||
((LATENCY) == FLASH_LATENCY_7) || \
|
||||
((LATENCY) == FLASH_LATENCY_8) || \
|
||||
((LATENCY) == FLASH_LATENCY_9) || \
|
||||
((LATENCY) == FLASH_LATENCY_10) || \
|
||||
((LATENCY) == FLASH_LATENCY_11) || \
|
||||
((LATENCY) == FLASH_LATENCY_12) || \
|
||||
((LATENCY) == FLASH_LATENCY_13) || \
|
||||
((LATENCY) == FLASH_LATENCY_14) || \
|
||||
((LATENCY) == FLASH_LATENCY_15))
|
||||
|
||||
#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= FLASH_BASE) && ((ADDRESS) <= FLASH_END)) || \
|
||||
(((ADDRESS) >= FLASH_OTP_BASE) && ((ADDRESS) <= FLASH_OTP_END)))
|
||||
#define IS_FLASH_NBSECTORS(NBSECTORS) (((NBSECTORS) != 0U) && ((NBSECTORS) <= FLASH_SECTOR_TOTAL))
|
||||
|
||||
#if (FLASH_SECTOR_TOTAL == 8)
|
||||
#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0) || ((SECTOR) == FLASH_SECTOR_1) ||\
|
||||
((SECTOR) == FLASH_SECTOR_2) || ((SECTOR) == FLASH_SECTOR_3) ||\
|
||||
((SECTOR) == FLASH_SECTOR_4) || ((SECTOR) == FLASH_SECTOR_5) ||\
|
||||
((SECTOR) == FLASH_SECTOR_6) || ((SECTOR) == FLASH_SECTOR_7))
|
||||
|
||||
#define IS_OB_WRP_SECTOR(SECTOR) ((((SECTOR) & 0xFF00FFFFU) == 0x00000000U) && ((SECTOR) != 0x00000000U))
|
||||
#endif /* FLASH_SECTOR_TOTAL == 8 */
|
||||
|
||||
#if (FLASH_SECTOR_TOTAL == 24)
|
||||
#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0) || ((SECTOR) == FLASH_SECTOR_1) ||\
|
||||
((SECTOR) == FLASH_SECTOR_2) || ((SECTOR) == FLASH_SECTOR_3) ||\
|
||||
((SECTOR) == FLASH_SECTOR_4) || ((SECTOR) == FLASH_SECTOR_5) ||\
|
||||
((SECTOR) == FLASH_SECTOR_6) || ((SECTOR) == FLASH_SECTOR_7) ||\
|
||||
((SECTOR) == FLASH_SECTOR_8) || ((SECTOR) == FLASH_SECTOR_9) ||\
|
||||
((SECTOR) == FLASH_SECTOR_10) || ((SECTOR) == FLASH_SECTOR_11) ||\
|
||||
((SECTOR) == FLASH_SECTOR_12) || ((SECTOR) == FLASH_SECTOR_13) ||\
|
||||
((SECTOR) == FLASH_SECTOR_14) || ((SECTOR) == FLASH_SECTOR_15) ||\
|
||||
((SECTOR) == FLASH_SECTOR_16) || ((SECTOR) == FLASH_SECTOR_17) ||\
|
||||
((SECTOR) == FLASH_SECTOR_18) || ((SECTOR) == FLASH_SECTOR_19) ||\
|
||||
((SECTOR) == FLASH_SECTOR_20) || ((SECTOR) == FLASH_SECTOR_21) ||\
|
||||
((SECTOR) == FLASH_SECTOR_22) || ((SECTOR) == FLASH_SECTOR_23))
|
||||
|
||||
#define IS_OB_WRP_SECTOR(SECTOR) ((((SECTOR) & 0xF000FFFFU) == 0x00000000U) && ((SECTOR) != 0x00000000U))
|
||||
#endif /* FLASH_SECTOR_TOTAL == 24 */
|
||||
|
||||
#if defined (FLASH_OPTCR_nDBANK)
|
||||
#define IS_OB_NDBANK(VALUE) (((VALUE) == OB_NDBANK_SINGLE_BANK) || \
|
||||
((VALUE) == OB_NDBANK_DUAL_BANK))
|
||||
|
||||
#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) || \
|
||||
((BANK) == FLASH_BANK_2) || \
|
||||
((BANK) == FLASH_BANK_BOTH))
|
||||
#endif /* FLASH_OPTCR_nDBANK */
|
||||
|
||||
#if defined (FLASH_OPTCR_nDBOOT)
|
||||
#define IS_OB_NDBOOT(VALUE) (((VALUE) == OB_DUAL_BOOT_DISABLE) || \
|
||||
((VALUE) == OB_DUAL_BOOT_ENABLE))
|
||||
#endif /* FLASH_OPTCR_nDBOOT */
|
||||
|
||||
#if defined (FLASH_OPTCR2_PCROP)
|
||||
#define IS_OB_PCROP_SECTOR(SECTOR) (((SECTOR) & (uint32_t)0xFFFFFF00U) == 0x00000000U)
|
||||
#define IS_OB_PCROP_RDP_VALUE(VALUE) (((VALUE) == OB_PCROP_RDP_DISABLE) || \
|
||||
((VALUE) == OB_PCROP_RDP_ENABLE))
|
||||
#endif /* FLASH_OPTCR2_PCROP */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup FLASHEx_Private_Functions FLASH Private Functions
|
||||
* @{
|
||||
*/
|
||||
void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F7xx_HAL_FLASH_EX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,327 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_hal_gpio.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.2
|
||||
* @date 14-April-2017
|
||||
* @brief Header file of GPIO HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F7xx_HAL_GPIO_H
|
||||
#define __STM32F7xx_HAL_GPIO_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup GPIO
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup GPIO_Exported_Types GPIO Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief GPIO Init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Pin; /*!< Specifies the GPIO pins to be configured.
|
||||
This parameter can be any value of @ref GPIO_pins_define */
|
||||
|
||||
uint32_t Mode; /*!< Specifies the operating mode for the selected pins.
|
||||
This parameter can be a value of @ref GPIO_mode_define */
|
||||
|
||||
uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.
|
||||
This parameter can be a value of @ref GPIO_pull_define */
|
||||
|
||||
uint32_t Speed; /*!< Specifies the speed for the selected pins.
|
||||
This parameter can be a value of @ref GPIO_speed_define */
|
||||
|
||||
uint32_t Alternate; /*!< Peripheral to be connected to the selected pins.
|
||||
This parameter can be a value of @ref GPIO_Alternate_function_selection */
|
||||
}GPIO_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief GPIO Bit SET and Bit RESET enumeration
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
GPIO_PIN_RESET = 0,
|
||||
GPIO_PIN_SET
|
||||
}GPIO_PinState;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup GPIO_Exported_Constants GPIO Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_pins_define GPIO pins define
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_PIN_0 ((uint16_t)0x0001U) /* Pin 0 selected */
|
||||
#define GPIO_PIN_1 ((uint16_t)0x0002U) /* Pin 1 selected */
|
||||
#define GPIO_PIN_2 ((uint16_t)0x0004U) /* Pin 2 selected */
|
||||
#define GPIO_PIN_3 ((uint16_t)0x0008U) /* Pin 3 selected */
|
||||
#define GPIO_PIN_4 ((uint16_t)0x0010U) /* Pin 4 selected */
|
||||
#define GPIO_PIN_5 ((uint16_t)0x0020U) /* Pin 5 selected */
|
||||
#define GPIO_PIN_6 ((uint16_t)0x0040U) /* Pin 6 selected */
|
||||
#define GPIO_PIN_7 ((uint16_t)0x0080U) /* Pin 7 selected */
|
||||
#define GPIO_PIN_8 ((uint16_t)0x0100U) /* Pin 8 selected */
|
||||
#define GPIO_PIN_9 ((uint16_t)0x0200U) /* Pin 9 selected */
|
||||
#define GPIO_PIN_10 ((uint16_t)0x0400U) /* Pin 10 selected */
|
||||
#define GPIO_PIN_11 ((uint16_t)0x0800U) /* Pin 11 selected */
|
||||
#define GPIO_PIN_12 ((uint16_t)0x1000U) /* Pin 12 selected */
|
||||
#define GPIO_PIN_13 ((uint16_t)0x2000U) /* Pin 13 selected */
|
||||
#define GPIO_PIN_14 ((uint16_t)0x4000U) /* Pin 14 selected */
|
||||
#define GPIO_PIN_15 ((uint16_t)0x8000U) /* Pin 15 selected */
|
||||
#define GPIO_PIN_All ((uint16_t)0xFFFFU) /* All pins selected */
|
||||
|
||||
#define GPIO_PIN_MASK ((uint32_t)0x0000FFFFU) /* PIN mask for assert test */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_mode_define GPIO mode define
|
||||
* @brief GPIO Configuration Mode
|
||||
* Elements values convention: 0xX0yz00YZ
|
||||
* - X : GPIO mode or EXTI Mode
|
||||
* - y : External IT or Event trigger detection
|
||||
* - z : IO configuration on External IT or Event
|
||||
* - Y : Output type (Push Pull or Open Drain)
|
||||
* - Z : IO Direction mode (Input, Output, Alternate or Analog)
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_MODE_INPUT ((uint32_t)0x00000000U) /*!< Input Floating Mode */
|
||||
#define GPIO_MODE_OUTPUT_PP ((uint32_t)0x00000001U) /*!< Output Push Pull Mode */
|
||||
#define GPIO_MODE_OUTPUT_OD ((uint32_t)0x00000011U) /*!< Output Open Drain Mode */
|
||||
#define GPIO_MODE_AF_PP ((uint32_t)0x00000002U) /*!< Alternate Function Push Pull Mode */
|
||||
#define GPIO_MODE_AF_OD ((uint32_t)0x00000012U) /*!< Alternate Function Open Drain Mode */
|
||||
|
||||
#define GPIO_MODE_ANALOG ((uint32_t)0x00000003U) /*!< Analog Mode */
|
||||
|
||||
#define GPIO_MODE_IT_RISING ((uint32_t)0x10110000U) /*!< External Interrupt Mode with Rising edge trigger detection */
|
||||
#define GPIO_MODE_IT_FALLING ((uint32_t)0x10210000U) /*!< External Interrupt Mode with Falling edge trigger detection */
|
||||
#define GPIO_MODE_IT_RISING_FALLING ((uint32_t)0x10310000U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
|
||||
|
||||
#define GPIO_MODE_EVT_RISING ((uint32_t)0x10120000U) /*!< External Event Mode with Rising edge trigger detection */
|
||||
#define GPIO_MODE_EVT_FALLING ((uint32_t)0x10220000U) /*!< External Event Mode with Falling edge trigger detection */
|
||||
#define GPIO_MODE_EVT_RISING_FALLING ((uint32_t)0x10320000U) /*!< External Event Mode with Rising/Falling edge trigger detection */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_speed_define GPIO speed define
|
||||
* @brief GPIO Output Maximum frequency
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_SPEED_FREQ_LOW ((uint32_t)0x00000000U) /*!< Low speed */
|
||||
#define GPIO_SPEED_FREQ_MEDIUM ((uint32_t)0x00000001U) /*!< Medium speed */
|
||||
#define GPIO_SPEED_FREQ_HIGH ((uint32_t)0x00000002U) /*!< Fast speed */
|
||||
#define GPIO_SPEED_FREQ_VERY_HIGH ((uint32_t)0x00000003U) /*!< High speed */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_pull_define GPIO pull define
|
||||
* @brief GPIO Pull-Up or Pull-Down Activation
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_NOPULL ((uint32_t)0x00000000U) /*!< No Pull-up or Pull-down activation */
|
||||
#define GPIO_PULLUP ((uint32_t)0x00000001U) /*!< Pull-up activation */
|
||||
#define GPIO_PULLDOWN ((uint32_t)0x00000002U) /*!< Pull-down activation */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup GPIO_Exported_Macros GPIO Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified EXTI line flag is set or not.
|
||||
* @param __EXTI_LINE__: specifies the EXTI line flag to check.
|
||||
* This parameter can be GPIO_PIN_x where x can be(0..15)
|
||||
* @retval The new state of __EXTI_LINE__ (SET or RESET).
|
||||
*/
|
||||
#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
|
||||
|
||||
/**
|
||||
* @brief Clears the EXTI's line pending flags.
|
||||
* @param __EXTI_LINE__: specifies the EXTI lines flags to clear.
|
||||
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified EXTI line is asserted or not.
|
||||
* @param __EXTI_LINE__: specifies the EXTI line to check.
|
||||
* This parameter can be GPIO_PIN_x where x can be(0..15)
|
||||
* @retval The new state of __EXTI_LINE__ (SET or RESET).
|
||||
*/
|
||||
#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
|
||||
|
||||
/**
|
||||
* @brief Clears the EXTI's line pending bits.
|
||||
* @param __EXTI_LINE__: specifies the EXTI lines to clear.
|
||||
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
|
||||
|
||||
/**
|
||||
* @brief Generates a Software interrupt on selected EXTI line.
|
||||
* @param __EXTI_LINE__: specifies the EXTI line to check.
|
||||
* This parameter can be GPIO_PIN_x where x can be(0..15)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include GPIO HAL Extension module */
|
||||
#include "stm32f7xx_hal_gpio_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup GPIO_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup GPIO_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Initialization and de-initialization functions *****************************/
|
||||
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init);
|
||||
void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup GPIO_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* IO operation functions *****************************************************/
|
||||
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||
void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
|
||||
void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||
HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||
void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);
|
||||
void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup GPIO_Private_Constants GPIO Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup GPIO_Private_Macros GPIO Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
|
||||
#define IS_GPIO_PIN(__PIN__) ((((__PIN__) & GPIO_PIN_MASK) != (uint32_t)0x00))
|
||||
#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT) ||\
|
||||
((MODE) == GPIO_MODE_OUTPUT_PP) ||\
|
||||
((MODE) == GPIO_MODE_OUTPUT_OD) ||\
|
||||
((MODE) == GPIO_MODE_AF_PP) ||\
|
||||
((MODE) == GPIO_MODE_AF_OD) ||\
|
||||
((MODE) == GPIO_MODE_IT_RISING) ||\
|
||||
((MODE) == GPIO_MODE_IT_FALLING) ||\
|
||||
((MODE) == GPIO_MODE_IT_RISING_FALLING) ||\
|
||||
((MODE) == GPIO_MODE_EVT_RISING) ||\
|
||||
((MODE) == GPIO_MODE_EVT_FALLING) ||\
|
||||
((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\
|
||||
((MODE) == GPIO_MODE_ANALOG))
|
||||
#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_LOW) || ((SPEED) == GPIO_SPEED_MEDIUM) || \
|
||||
((SPEED) == GPIO_SPEED_FAST) || ((SPEED) == GPIO_SPEED_HIGH))
|
||||
#define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \
|
||||
((PULL) == GPIO_PULLDOWN))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup GPIO_Private_Functions GPIO Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F7xx_HAL_GPIO_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,675 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_hal_gpio_ex.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.2
|
||||
* @date 14-April-2017
|
||||
* @brief Header file of GPIO HAL Extension module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F7xx_HAL_GPIO_EX_H
|
||||
#define __STM32F7xx_HAL_GPIO_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIOEx GPIOEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup GPIOEx_Exported_Constants GPIO Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Alternate_function_selection GPIO Alternate Function Selection
|
||||
* @{
|
||||
*/
|
||||
/*--------------- STM32F74xxx/STM32F75xxx/STM32F76xxx/STM32F77xxx -------------*/
|
||||
#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || defined (STM32F767xx) ||\
|
||||
defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
|
||||
/**
|
||||
* @brief AF 0 selection
|
||||
*/
|
||||
#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00U) /* RTC_50Hz Alternate Function mapping */
|
||||
#define GPIO_AF0_MCO ((uint8_t)0x00U) /* MCO (MCO1 and MCO2) Alternate Function mapping */
|
||||
#define GPIO_AF0_SWJ ((uint8_t)0x00U) /* SWJ (SWD and JTAG) Alternate Function mapping */
|
||||
#define GPIO_AF0_TRACE ((uint8_t)0x00U) /* TRACE Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 1 selection
|
||||
*/
|
||||
#define GPIO_AF1_TIM1 ((uint8_t)0x01U) /* TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF1_TIM2 ((uint8_t)0x01U) /* TIM2 Alternate Function mapping */
|
||||
#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)
|
||||
#define GPIO_AF1_UART5 ((uint8_t)0x01U) /* UART5 Alternate Function mapping */
|
||||
#define GPIO_AF1_I2C4 ((uint8_t)0x01U) /* I2C4 Alternate Function mapping */
|
||||
#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
|
||||
|
||||
/**
|
||||
* @brief AF 2 selection
|
||||
*/
|
||||
#define GPIO_AF2_TIM3 ((uint8_t)0x02U) /* TIM3 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM4 ((uint8_t)0x02U) /* TIM4 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM5 ((uint8_t)0x02U) /* TIM5 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 3 selection
|
||||
*/
|
||||
#define GPIO_AF3_TIM8 ((uint8_t)0x03U) /* TIM8 Alternate Function mapping */
|
||||
#define GPIO_AF3_TIM9 ((uint8_t)0x03U) /* TIM9 Alternate Function mapping */
|
||||
#define GPIO_AF3_TIM10 ((uint8_t)0x03U) /* TIM10 Alternate Function mapping */
|
||||
#define GPIO_AF3_TIM11 ((uint8_t)0x03U) /* TIM11 Alternate Function mapping */
|
||||
#define GPIO_AF3_LPTIM1 ((uint8_t)0x03U) /* LPTIM1 Alternate Function mapping */
|
||||
#define GPIO_AF3_CEC ((uint8_t)0x03U) /* CEC Alternate Function mapping */
|
||||
#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)
|
||||
#define GPIO_AF3_DFSDM1 ((uint8_t)0x03U) /* DFSDM1 Alternate Function mapping */
|
||||
#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
|
||||
/**
|
||||
* @brief AF 4 selection
|
||||
*/
|
||||
#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /* I2C1 Alternate Function mapping */
|
||||
#define GPIO_AF4_I2C2 ((uint8_t)0x04U) /* I2C2 Alternate Function mapping */
|
||||
#define GPIO_AF4_I2C3 ((uint8_t)0x04U) /* I2C3 Alternate Function mapping */
|
||||
#define GPIO_AF4_I2C4 ((uint8_t)0x04U) /* I2C4 Alternate Function mapping */
|
||||
#define GPIO_AF4_CEC ((uint8_t)0x04U) /* CEC Alternate Function mapping */
|
||||
#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)
|
||||
#define GPIO_AF4_USART1 ((uint8_t)0x04) /* USART1 Alternate Function mapping */
|
||||
#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
|
||||
|
||||
/**
|
||||
* @brief AF 5 selection
|
||||
*/
|
||||
#define GPIO_AF5_SPI1 ((uint8_t)0x05U) /* SPI1 Alternate Function mapping */
|
||||
#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /* SPI2/I2S2 Alternate Function mapping */
|
||||
#define GPIO_AF5_SPI3 ((uint8_t)0x05U) /* SPI3/I2S3 Alternate Function mapping */
|
||||
#define GPIO_AF5_SPI4 ((uint8_t)0x05U) /* SPI4 Alternate Function mapping */
|
||||
#define GPIO_AF5_SPI5 ((uint8_t)0x05U) /* SPI5 Alternate Function mapping */
|
||||
#define GPIO_AF5_SPI6 ((uint8_t)0x05U) /* SPI6 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 6 selection
|
||||
*/
|
||||
#define GPIO_AF6_SPI3 ((uint8_t)0x06U) /* SPI3/I2S3 Alternate Function mapping */
|
||||
#define GPIO_AF6_SAI1 ((uint8_t)0x06U) /* SAI1 Alternate Function mapping */
|
||||
#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)
|
||||
#define GPIO_AF6_UART4 ((uint8_t)0x06U) /* UART4 Alternate Function mapping */
|
||||
#define GPIO_AF6_DFSDM1 ((uint8_t)0x06U) /* DFSDM1 Alternate Function mapping */
|
||||
#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
|
||||
|
||||
/**
|
||||
* @brief AF 7 selection
|
||||
*/
|
||||
#define GPIO_AF7_USART1 ((uint8_t)0x07U) /* USART1 Alternate Function mapping */
|
||||
#define GPIO_AF7_USART2 ((uint8_t)0x07U) /* USART2 Alternate Function mapping */
|
||||
#define GPIO_AF7_USART3 ((uint8_t)0x07U) /* USART3 Alternate Function mapping */
|
||||
#define GPIO_AF7_UART5 ((uint8_t)0x07U) /* UART5 Alternate Function mapping */
|
||||
#define GPIO_AF7_SPDIFRX ((uint8_t)0x07U) /* SPDIF-RX Alternate Function mapping */
|
||||
#define GPIO_AF7_SPI2 ((uint8_t)0x07U) /* SPI2 Alternate Function mapping */
|
||||
#define GPIO_AF7_SPI3 ((uint8_t)0x07U) /* SPI3 Alternate Function mapping */
|
||||
#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)
|
||||
#define GPIO_AF7_SPI6 ((uint8_t)0x07U) /* SPI6 Alternate Function mapping */
|
||||
#define GPIO_AF7_DFSDM1 ((uint8_t)0x07U) /* DFSDM1 Alternate Function mapping */
|
||||
#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
|
||||
|
||||
/**
|
||||
* @brief AF 8 selection
|
||||
*/
|
||||
#define GPIO_AF8_UART4 ((uint8_t)0x08U) /* UART4 Alternate Function mapping */
|
||||
#define GPIO_AF8_UART5 ((uint8_t)0x08U) /* UART5 Alternate Function mapping */
|
||||
#define GPIO_AF8_USART6 ((uint8_t)0x08U) /* USART6 Alternate Function mapping */
|
||||
#define GPIO_AF8_UART7 ((uint8_t)0x08U) /* UART7 Alternate Function mapping */
|
||||
#define GPIO_AF8_UART8 ((uint8_t)0x08U) /* UART8 Alternate Function mapping */
|
||||
#define GPIO_AF8_SPDIFRX ((uint8_t)0x08U) /* SPIDIF-RX Alternate Function mapping */
|
||||
#define GPIO_AF8_SAI2 ((uint8_t)0x08U) /* SAI2 Alternate Function mapping */
|
||||
#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)
|
||||
#define GPIO_AF8_SPI6 ((uint8_t)0x08U) /* SPI6 Alternate Function mapping */
|
||||
#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
|
||||
|
||||
|
||||
/**
|
||||
* @brief AF 9 selection
|
||||
*/
|
||||
#define GPIO_AF9_CAN1 ((uint8_t)0x09U) /* CAN1 Alternate Function mapping */
|
||||
#define GPIO_AF9_CAN2 ((uint8_t)0x09U) /* CAN2 Alternate Function mapping */
|
||||
#define GPIO_AF9_TIM12 ((uint8_t)0x09U) /* TIM12 Alternate Function mapping */
|
||||
#define GPIO_AF9_TIM13 ((uint8_t)0x09U) /* TIM13 Alternate Function mapping */
|
||||
#define GPIO_AF9_TIM14 ((uint8_t)0x09U) /* TIM14 Alternate Function mapping */
|
||||
#define GPIO_AF9_QUADSPI ((uint8_t)0x09U) /* QUADSPI Alternate Function mapping */
|
||||
#if defined(STM32F746xx) || defined(STM32F756xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)
|
||||
#define GPIO_AF9_LTDC ((uint8_t)0x09U) /* LCD-TFT Alternate Function mapping */
|
||||
#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
|
||||
#if defined(STM32F746xx) || defined(STM32F756xx) || defined(STM32F765xx) || defined(STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)
|
||||
#define GPIO_AF9_FMC ((uint8_t)0x09U) /* FMC Alternate Function mapping */
|
||||
#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
|
||||
/**
|
||||
* @brief AF 10 selection
|
||||
*/
|
||||
#define GPIO_AF10_OTG_FS ((uint8_t)0xAU) /* OTG_FS Alternate Function mapping */
|
||||
#define GPIO_AF10_OTG_HS ((uint8_t)0xAU) /* OTG_HS Alternate Function mapping */
|
||||
#define GPIO_AF10_QUADSPI ((uint8_t)0xAU) /* QUADSPI Alternate Function mapping */
|
||||
#define GPIO_AF10_SAI2 ((uint8_t)0xAU) /* SAI2 Alternate Function mapping */
|
||||
#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)
|
||||
#define GPIO_AF10_DFSDM1 ((uint8_t)0x0AU) /* DFSDM1 Alternate Function mapping */
|
||||
#define GPIO_AF10_SDMMC2 ((uint8_t)0x0AU) /* SDMMC2 Alternate Function mapping */
|
||||
#define GPIO_AF10_LTDC ((uint8_t)0x0AU) /* LCD-TFT Alternate Function mapping */
|
||||
#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
|
||||
|
||||
/**
|
||||
* @brief AF 11 selection
|
||||
*/
|
||||
#define GPIO_AF11_ETH ((uint8_t)0x0BU) /* ETHERNET Alternate Function mapping */
|
||||
#if defined(STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
|
||||
#define GPIO_AF11_CAN3 ((uint8_t)0x0BU) /* CAN3 Alternate Function mapping */
|
||||
#define GPIO_AF11_SDMMC2 ((uint8_t)0x0BU) /* SDMMC2 Alternate Function mapping */
|
||||
#define GPIO_AF11_I2C4 ((uint8_t)0x0BU) /* I2C4 Alternate Function mapping */
|
||||
#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
|
||||
|
||||
/**
|
||||
* @brief AF 12 selection
|
||||
*/
|
||||
#define GPIO_AF12_FMC ((uint8_t)0xCU) /* FMC Alternate Function mapping */
|
||||
#define GPIO_AF12_OTG_HS_FS ((uint8_t)0xCU) /* OTG HS configured in FS, Alternate Function mapping */
|
||||
#define GPIO_AF12_SDMMC1 ((uint8_t)0xCU) /* SDMMC1 Alternate Function mapping */
|
||||
#if defined(STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
|
||||
#define GPIO_AF12_MDIOS ((uint8_t)0xCU) /* SDMMC1 Alternate Function mapping */
|
||||
#define GPIO_AF12_UART7 ((uint8_t)0xCU) /* UART7 Alternate Function mapping */
|
||||
#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
|
||||
|
||||
/**
|
||||
* @brief AF 13 selection
|
||||
*/
|
||||
#define GPIO_AF13_DCMI ((uint8_t)0x0DU) /* DCMI Alternate Function mapping */
|
||||
#if defined (STM32F769xx) || defined (STM32F779xx)
|
||||
#define GPIO_AF13_DSI ((uint8_t)0x0DU) /* DSI Alternate Function mapping */
|
||||
#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
|
||||
#if defined(STM32F746xx) || defined(STM32F756xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)
|
||||
#define GPIO_AF13_LTDC ((uint8_t)0x0DU) /* LTDC Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 14 selection
|
||||
*/
|
||||
#define GPIO_AF14_LTDC ((uint8_t)0x0EU) /* LCD-TFT Alternate Function mapping */
|
||||
#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
|
||||
/**
|
||||
* @brief AF 15 selection
|
||||
*/
|
||||
#define GPIO_AF15_EVENTOUT ((uint8_t)0x0FU) /* EVENTOUT Alternate Function mapping */
|
||||
#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
|
||||
/*----------------------------------------------------------------------------*/
|
||||
|
||||
/*---------------------------- STM32F72xxx/STM32F73xxx -----------------------*/
|
||||
#if defined(STM32F722xx) || defined(STM32F723xx) || defined(STM32F732xx) || defined(STM32F733xx)
|
||||
/**
|
||||
* @brief AF 0 selection
|
||||
*/
|
||||
#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00U) /* RTC_50Hz Alternate Function mapping */
|
||||
#define GPIO_AF0_MCO ((uint8_t)0x00U) /* MCO (MCO1 and MCO2) Alternate Function mapping */
|
||||
#define GPIO_AF0_SWJ ((uint8_t)0x00U) /* SWJ (SWD and JTAG) Alternate Function mapping */
|
||||
#define GPIO_AF0_TRACE ((uint8_t)0x00U) /* TRACE Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 1 selection
|
||||
*/
|
||||
#define GPIO_AF1_TIM1 ((uint8_t)0x01U) /* TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF1_TIM2 ((uint8_t)0x01U) /* TIM2 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 2 selection
|
||||
*/
|
||||
#define GPIO_AF2_TIM3 ((uint8_t)0x02U) /* TIM3 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM4 ((uint8_t)0x02U) /* TIM4 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM5 ((uint8_t)0x02U) /* TIM5 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 3 selection
|
||||
*/
|
||||
#define GPIO_AF3_TIM8 ((uint8_t)0x03U) /* TIM8 Alternate Function mapping */
|
||||
#define GPIO_AF3_TIM9 ((uint8_t)0x03U) /* TIM9 Alternate Function mapping */
|
||||
#define GPIO_AF3_TIM10 ((uint8_t)0x03U) /* TIM10 Alternate Function mapping */
|
||||
#define GPIO_AF3_TIM11 ((uint8_t)0x03U) /* TIM11 Alternate Function mapping */
|
||||
#define GPIO_AF3_LPTIM1 ((uint8_t)0x03U) /* LPTIM1 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 4 selection
|
||||
*/
|
||||
#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /* I2C1 Alternate Function mapping */
|
||||
#define GPIO_AF4_I2C2 ((uint8_t)0x04U) /* I2C2 Alternate Function mapping */
|
||||
#define GPIO_AF4_I2C3 ((uint8_t)0x04U) /* I2C3 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 5 selection
|
||||
*/
|
||||
#define GPIO_AF5_SPI1 ((uint8_t)0x05U) /* SPI1 Alternate Function mapping */
|
||||
#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /* SPI2/I2S2 Alternate Function mapping */
|
||||
#define GPIO_AF5_SPI3 ((uint8_t)0x05U) /* SPI3/I2S3 Alternate Function mapping */
|
||||
#define GPIO_AF5_SPI4 ((uint8_t)0x05U) /* SPI4 Alternate Function mapping */
|
||||
#define GPIO_AF5_SPI5 ((uint8_t)0x05U) /* SPI5 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 6 selection
|
||||
*/
|
||||
#define GPIO_AF6_SPI3 ((uint8_t)0x06U) /* SPI3/I2S3 Alternate Function mapping */
|
||||
#define GPIO_AF6_SAI1 ((uint8_t)0x06U) /* SAI1 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 7 selection
|
||||
*/
|
||||
#define GPIO_AF7_USART1 ((uint8_t)0x07U) /* USART1 Alternate Function mapping */
|
||||
#define GPIO_AF7_USART2 ((uint8_t)0x07U) /* USART2 Alternate Function mapping */
|
||||
#define GPIO_AF7_USART3 ((uint8_t)0x07U) /* USART3 Alternate Function mapping */
|
||||
#define GPIO_AF7_UART5 ((uint8_t)0x07U) /* UART5 Alternate Function mapping */
|
||||
#define GPIO_AF7_SPI2 ((uint8_t)0x07U) /* SPI2 Alternate Function mapping */
|
||||
#define GPIO_AF7_SPI3 ((uint8_t)0x07U) /* SPI3 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 8 selection
|
||||
*/
|
||||
#define GPIO_AF8_UART4 ((uint8_t)0x08U) /* UART4 Alternate Function mapping */
|
||||
#define GPIO_AF8_UART5 ((uint8_t)0x08U) /* UART5 Alternate Function mapping */
|
||||
#define GPIO_AF8_USART6 ((uint8_t)0x08U) /* USART6 Alternate Function mapping */
|
||||
#define GPIO_AF8_UART7 ((uint8_t)0x08U) /* UART7 Alternate Function mapping */
|
||||
#define GPIO_AF8_UART8 ((uint8_t)0x08U) /* UART8 Alternate Function mapping */
|
||||
#define GPIO_AF8_SAI2 ((uint8_t)0x08U) /* SAI2 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 9 selection
|
||||
*/
|
||||
#define GPIO_AF9_CAN1 ((uint8_t)0x09U) /* CAN1 Alternate Function mapping */
|
||||
#define GPIO_AF9_TIM12 ((uint8_t)0x09U) /* TIM12 Alternate Function mapping */
|
||||
#define GPIO_AF9_TIM13 ((uint8_t)0x09U) /* TIM13 Alternate Function mapping */
|
||||
#define GPIO_AF9_TIM14 ((uint8_t)0x09U) /* TIM14 Alternate Function mapping */
|
||||
#define GPIO_AF9_QUADSPI ((uint8_t)0x09U) /* QUADSPI Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 10 selection
|
||||
*/
|
||||
#define GPIO_AF10_OTG_FS ((uint8_t)0xAU) /* OTG_FS Alternate Function mapping */
|
||||
#define GPIO_AF10_OTG_HS ((uint8_t)0xAU) /* OTG_HS Alternate Function mapping */
|
||||
#define GPIO_AF10_QUADSPI ((uint8_t)0xAU) /* QUADSPI Alternate Function mapping */
|
||||
#define GPIO_AF10_SAI2 ((uint8_t)0xAU) /* SAI2 Alternate Function mapping */
|
||||
#define GPIO_AF10_SDMMC2 ((uint8_t)0x0AU) /* SDMMC2 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 11 selection
|
||||
*/
|
||||
#define GPIO_AF11_SDMMC2 ((uint8_t)0x0BU) /* SDMMC2 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 12 selection
|
||||
*/
|
||||
#define GPIO_AF12_FMC ((uint8_t)0xCU) /* FMC Alternate Function mapping */
|
||||
#define GPIO_AF12_OTG_HS_FS ((uint8_t)0xCU) /* OTG HS configured in FS, Alternate Function mapping */
|
||||
#define GPIO_AF12_SDMMC1 ((uint8_t)0xCU) /* SDMMC1 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 13 selection
|
||||
*/
|
||||
#define GPIO_AF13_RNG ((uint8_t)0x0DU) /* RNG Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 15 selection
|
||||
*/
|
||||
#define GPIO_AF15_EVENTOUT ((uint8_t)0x0FU) /* EVENTOUT Alternate Function mapping */
|
||||
#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx */
|
||||
/*----------------------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup GPIOEx_Exported_Macros GPIO Exported Macros
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup GPIOEx_Exported_Functions GPIO Exported Functions
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup GPIOEx_Private_Constants GPIO Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief GPIO pin available on the platform
|
||||
*/
|
||||
/* Defines the available pins per GPIOs */
|
||||
#define GPIOA_PIN_AVAILABLE GPIO_PIN_All
|
||||
#define GPIOB_PIN_AVAILABLE GPIO_PIN_All
|
||||
#define GPIOC_PIN_AVAILABLE GPIO_PIN_All
|
||||
#define GPIOD_PIN_AVAILABLE GPIO_PIN_All
|
||||
#define GPIOE_PIN_AVAILABLE GPIO_PIN_All
|
||||
#define GPIOF_PIN_AVAILABLE GPIO_PIN_All
|
||||
#define GPIOG_PIN_AVAILABLE GPIO_PIN_All
|
||||
#define GPIOI_PIN_AVAILABLE GPIO_PIN_All
|
||||
#define GPIOJ_PIN_AVAILABLE GPIO_PIN_All
|
||||
#define GPIOH_PIN_AVAILABLE GPIO_PIN_All
|
||||
#define GPIOK_PIN_AVAILABLE (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_3 | GPIO_PIN_4 | \
|
||||
GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup GPIOEx_Private_Macros GPIO Private Macros
|
||||
* @{
|
||||
*/
|
||||
/** @defgroup GPIOEx_Get_Port_Index GPIO Get Port Index
|
||||
* @{
|
||||
*/
|
||||
#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
|
||||
defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
|
||||
#define GPIO_GET_INDEX(__GPIOx__) (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\
|
||||
((__GPIOx__) == (GPIOB))? 1U :\
|
||||
((__GPIOx__) == (GPIOC))? 2U :\
|
||||
((__GPIOx__) == (GPIOD))? 3U :\
|
||||
((__GPIOx__) == (GPIOE))? 4U :\
|
||||
((__GPIOx__) == (GPIOF))? 5U :\
|
||||
((__GPIOx__) == (GPIOG))? 6U :\
|
||||
((__GPIOx__) == (GPIOH))? 7U :\
|
||||
((__GPIOx__) == (GPIOI))? 8U :\
|
||||
((__GPIOx__) == (GPIOJ))? 9U : 10U)
|
||||
#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
|
||||
|
||||
#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx)
|
||||
#define GPIO_GET_INDEX(__GPIOx__) (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\
|
||||
((__GPIOx__) == (GPIOB))? 1U :\
|
||||
((__GPIOx__) == (GPIOC))? 2U :\
|
||||
((__GPIOx__) == (GPIOD))? 3U :\
|
||||
((__GPIOx__) == (GPIOE))? 4U :\
|
||||
((__GPIOx__) == (GPIOF))? 5U :\
|
||||
((__GPIOx__) == (GPIOG))? 6U :\
|
||||
((__GPIOx__) == (GPIOH))? 7U : 8U)
|
||||
#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#define IS_GPIO_PIN_AVAILABLE(__INSTANCE__,__PIN__) \
|
||||
((((__INSTANCE__) == GPIOA) && (((__PIN__) & (GPIOA_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOA_PIN_AVAILABLE)) == (GPIOA_PIN_AVAILABLE))) || \
|
||||
(((__INSTANCE__) == GPIOB) && (((__PIN__) & (GPIOB_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOB_PIN_AVAILABLE)) == (GPIOB_PIN_AVAILABLE))) || \
|
||||
(((__INSTANCE__) == GPIOC) && (((__PIN__) & (GPIOC_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOC_PIN_AVAILABLE)) == (GPIOC_PIN_AVAILABLE))) || \
|
||||
(((__INSTANCE__) == GPIOD) && (((__PIN__) & (GPIOD_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOD_PIN_AVAILABLE)) == (GPIOD_PIN_AVAILABLE))) || \
|
||||
(((__INSTANCE__) == GPIOE) && (((__PIN__) & (GPIOE_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOE_PIN_AVAILABLE)) == (GPIOE_PIN_AVAILABLE))) || \
|
||||
(((__INSTANCE__) == GPIOF) && (((__PIN__) & (GPIOF_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOF_PIN_AVAILABLE)) == (GPIOF_PIN_AVAILABLE))) || \
|
||||
(((__INSTANCE__) == GPIOG) && (((__PIN__) & (GPIOG_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOG_PIN_AVAILABLE)) == (GPIOG_PIN_AVAILABLE))) || \
|
||||
(((__INSTANCE__) == GPIOI) && (((__PIN__) & (GPIOI_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOI_PIN_AVAILABLE)) == (GPIOI_PIN_AVAILABLE))) || \
|
||||
(((__INSTANCE__) == GPIOJ) && (((__PIN__) & (GPIOJ_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOJ_PIN_AVAILABLE)) == (GPIOJ_PIN_AVAILABLE))) || \
|
||||
(((__INSTANCE__) == GPIOK) && (((__PIN__) & (GPIOK_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOK_PIN_AVAILABLE)) == (GPIOK_PIN_AVAILABLE))) || \
|
||||
(((__INSTANCE__) == GPIOH) && (((__PIN__) & (GPIOH_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOH_PIN_AVAILABLE)) == (GPIOH_PIN_AVAILABLE))))
|
||||
/** @defgroup GPIOEx_IS_Alternat_function_selection GPIO Check Alternate Function
|
||||
* @{
|
||||
*/
|
||||
#if defined(STM32F756xx) || defined(STM32F746xx)
|
||||
#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF1_TIM1) || \
|
||||
((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \
|
||||
((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF1_TIM2) || \
|
||||
((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \
|
||||
((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \
|
||||
((AF) == GPIO_AF3_TIM9) || ((AF) == GPIO_AF3_TIM10) || \
|
||||
((AF) == GPIO_AF3_TIM11) || ((AF) == GPIO_AF3_LPTIM1) || \
|
||||
((AF) == GPIO_AF3_CEC) || ((AF) == GPIO_AF4_CEC) || \
|
||||
((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \
|
||||
((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF4_I2C4) || \
|
||||
((AF) == GPIO_AF5_SPI1) || ((AF) == GPIO_AF5_SPI2) || \
|
||||
((AF) == GPIO_AF5_SPI3) || ((AF) == GPIO_AF5_SPI4) || \
|
||||
((AF) == GPIO_AF5_SPI5) || ((AF) == GPIO_AF5_SPI6) || \
|
||||
((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF6_SAI1) || \
|
||||
((AF) == GPIO_AF7_SPI3) || ((AF) == GPIO_AF7_SPI2) || \
|
||||
((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \
|
||||
((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF7_UART5) || \
|
||||
((AF) == GPIO_AF7_SPDIFRX) || ((AF) == GPIO_AF8_SPDIFRX) || \
|
||||
((AF) == GPIO_AF8_SAI2) || ((AF) == GPIO_AF8_USART6) || \
|
||||
((AF) == GPIO_AF8_UART4) || ((AF) == GPIO_AF8_UART5) || \
|
||||
((AF) == GPIO_AF8_UART7) || ((AF) == GPIO_AF8_UART8) || \
|
||||
((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \
|
||||
((AF) == GPIO_AF9_TIM12) || ((AF) == GPIO_AF9_TIM12) || \
|
||||
((AF) == GPIO_AF9_TIM14) || ((AF) == GPIO_AF9_QUADSPI) || \
|
||||
((AF) == GPIO_AF9_LTDC) || ((AF) == GPIO_AF10_OTG_FS) || \
|
||||
((AF) == GPIO_AF10_OTG_HS) || ((AF) == GPIO_AF10_SAI2) || \
|
||||
((AF) == GPIO_AF10_QUADSPI) || ((AF) == GPIO_AF11_ETH) || \
|
||||
((AF) == GPIO_AF12_OTG_HS_FS) || ((AF) == GPIO_AF12_SDMMC1) || \
|
||||
((AF) == GPIO_AF12_FMC) || ((AF) == GPIO_AF15_EVENTOUT) || \
|
||||
((AF) == GPIO_AF13_DCMI) || ((AF) == GPIO_AF14_LTDC))
|
||||
#elif defined(STM32F745xx)
|
||||
#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF1_TIM1) || \
|
||||
((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \
|
||||
((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF1_TIM2) || \
|
||||
((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \
|
||||
((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \
|
||||
((AF) == GPIO_AF3_TIM9) || ((AF) == GPIO_AF3_TIM10) || \
|
||||
((AF) == GPIO_AF3_TIM11) || ((AF) == GPIO_AF3_LPTIM1) || \
|
||||
((AF) == GPIO_AF3_CEC) || ((AF) == GPIO_AF4_CEC) || \
|
||||
((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \
|
||||
((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF4_I2C4) || \
|
||||
((AF) == GPIO_AF5_SPI1) || ((AF) == GPIO_AF5_SPI2) || \
|
||||
((AF) == GPIO_AF5_SPI3) || ((AF) == GPIO_AF5_SPI4) || \
|
||||
((AF) == GPIO_AF5_SPI5) || ((AF) == GPIO_AF5_SPI6) || \
|
||||
((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF6_SAI1) || \
|
||||
((AF) == GPIO_AF7_SPI3) || ((AF) == GPIO_AF7_SPI2) || \
|
||||
((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \
|
||||
((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF7_UART5) || \
|
||||
((AF) == GPIO_AF7_SPDIFRX) || ((AF) == GPIO_AF8_SPDIFRX) || \
|
||||
((AF) == GPIO_AF8_SAI2) || ((AF) == GPIO_AF8_USART6) || \
|
||||
((AF) == GPIO_AF8_UART4) || ((AF) == GPIO_AF8_UART5) || \
|
||||
((AF) == GPIO_AF8_UART7) || ((AF) == GPIO_AF8_UART8) || \
|
||||
((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \
|
||||
((AF) == GPIO_AF9_TIM12) || ((AF) == GPIO_AF9_TIM12) || \
|
||||
((AF) == GPIO_AF9_TIM14) || ((AF) == GPIO_AF9_QUADSPI) || \
|
||||
((AF) == GPIO_AF13_DCMI) || ((AF) == GPIO_AF10_OTG_FS) || \
|
||||
((AF) == GPIO_AF10_OTG_HS) || ((AF) == GPIO_AF10_SAI2) || \
|
||||
((AF) == GPIO_AF10_QUADSPI) || ((AF) == GPIO_AF11_ETH) || \
|
||||
((AF) == GPIO_AF12_OTG_HS_FS) || ((AF) == GPIO_AF12_SDMMC1) || \
|
||||
((AF) == GPIO_AF12_FMC) || ((AF) == GPIO_AF15_EVENTOUT))
|
||||
#elif defined(STM32F767xx) || defined(STM32F777xx)
|
||||
#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF1_TIM1) || \
|
||||
((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \
|
||||
((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF1_TIM2) || \
|
||||
((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \
|
||||
((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \
|
||||
((AF) == GPIO_AF3_TIM9) || ((AF) == GPIO_AF3_TIM10) || \
|
||||
((AF) == GPIO_AF3_TIM11) || ((AF) == GPIO_AF3_LPTIM1) || \
|
||||
((AF) == GPIO_AF3_CEC) || ((AF) == GPIO_AF4_CEC) || \
|
||||
((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \
|
||||
((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF4_I2C4) || \
|
||||
((AF) == GPIO_AF5_SPI1) || ((AF) == GPIO_AF5_SPI2) || \
|
||||
((AF) == GPIO_AF5_SPI3) || ((AF) == GPIO_AF5_SPI4) || \
|
||||
((AF) == GPIO_AF5_SPI5) || ((AF) == GPIO_AF5_SPI6) || \
|
||||
((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF6_SAI1) || \
|
||||
((AF) == GPIO_AF7_SPI3) || ((AF) == GPIO_AF7_SPI2) || \
|
||||
((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \
|
||||
((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF7_UART5) || \
|
||||
((AF) == GPIO_AF7_SPDIFRX) || ((AF) == GPIO_AF8_SPDIFRX) || \
|
||||
((AF) == GPIO_AF8_SAI2) || ((AF) == GPIO_AF8_USART6) || \
|
||||
((AF) == GPIO_AF8_UART4) || ((AF) == GPIO_AF8_UART5) || \
|
||||
((AF) == GPIO_AF8_UART7) || ((AF) == GPIO_AF8_UART8) || \
|
||||
((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \
|
||||
((AF) == GPIO_AF9_TIM12) || ((AF) == GPIO_AF9_TIM12) || \
|
||||
((AF) == GPIO_AF9_TIM14) || ((AF) == GPIO_AF9_QUADSPI) || \
|
||||
((AF) == GPIO_AF10_OTG_FS) || ((AF) == GPIO_AF9_LTDC) || \
|
||||
((AF) == GPIO_AF10_OTG_HS) || ((AF) == GPIO_AF10_SAI2) || \
|
||||
((AF) == GPIO_AF10_QUADSPI) || ((AF) == GPIO_AF11_ETH) || \
|
||||
((AF) == GPIO_AF10_SDMMC2) || ((AF) == GPIO_AF11_SDMMC2) || \
|
||||
((AF) == GPIO_AF11_CAN3) || ((AF) == GPIO_AF12_OTG_HS_FS) || \
|
||||
((AF) == GPIO_AF12_SDMMC1) || ((AF) == GPIO_AF12_FMC) || \
|
||||
((AF) == GPIO_AF15_EVENTOUT) || ((AF) == GPIO_AF13_DCMI) || \
|
||||
((AF) == GPIO_AF14_LTDC))
|
||||
#elif defined(STM32F769xx) || defined(STM32F779xx)
|
||||
#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF1_TIM1) || \
|
||||
((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \
|
||||
((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF1_TIM2) || \
|
||||
((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \
|
||||
((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \
|
||||
((AF) == GPIO_AF3_TIM9) || ((AF) == GPIO_AF3_TIM10) || \
|
||||
((AF) == GPIO_AF3_TIM11) || ((AF) == GPIO_AF3_LPTIM1) || \
|
||||
((AF) == GPIO_AF3_CEC) || ((AF) == GPIO_AF4_CEC) || \
|
||||
((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \
|
||||
((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF4_I2C4) || \
|
||||
((AF) == GPIO_AF5_SPI1) || ((AF) == GPIO_AF5_SPI2) || \
|
||||
((AF) == GPIO_AF5_SPI3) || ((AF) == GPIO_AF5_SPI4) || \
|
||||
((AF) == GPIO_AF5_SPI5) || ((AF) == GPIO_AF5_SPI6) || \
|
||||
((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF6_SAI1) || \
|
||||
((AF) == GPIO_AF7_SPI3) || ((AF) == GPIO_AF7_SPI2) || \
|
||||
((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \
|
||||
((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF7_UART5) || \
|
||||
((AF) == GPIO_AF7_SPDIFRX) || ((AF) == GPIO_AF8_SPDIFRX) || \
|
||||
((AF) == GPIO_AF8_SAI2) || ((AF) == GPIO_AF8_USART6) || \
|
||||
((AF) == GPIO_AF8_UART4) || ((AF) == GPIO_AF8_UART5) || \
|
||||
((AF) == GPIO_AF8_UART7) || ((AF) == GPIO_AF8_UART8) || \
|
||||
((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \
|
||||
((AF) == GPIO_AF9_TIM12) || ((AF) == GPIO_AF9_TIM12) || \
|
||||
((AF) == GPIO_AF9_TIM14) || ((AF) == GPIO_AF9_QUADSPI) || \
|
||||
((AF) == GPIO_AF9_LTDC) || ((AF) == GPIO_AF10_OTG_FS) || \
|
||||
((AF) == GPIO_AF10_OTG_HS) || ((AF) == GPIO_AF10_SAI2) || \
|
||||
((AF) == GPIO_AF10_QUADSPI) || ((AF) == GPIO_AF11_ETH) || \
|
||||
((AF) == GPIO_AF10_SDMMC2) || ((AF) == GPIO_AF11_SDMMC2) || \
|
||||
((AF) == GPIO_AF11_CAN3) || ((AF) == GPIO_AF12_OTG_HS_FS) || \
|
||||
((AF) == GPIO_AF12_SDMMC1) || ((AF) == GPIO_AF12_FMC) || \
|
||||
((AF) == GPIO_AF15_EVENTOUT) || ((AF) == GPIO_AF13_DCMI) || \
|
||||
((AF) == GPIO_AF14_LTDC) || ((AF) == GPIO_AF13_DSI))
|
||||
#elif defined(STM32F765xx)
|
||||
#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF1_TIM1) || \
|
||||
((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \
|
||||
((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF1_TIM2) || \
|
||||
((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \
|
||||
((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \
|
||||
((AF) == GPIO_AF3_TIM9) || ((AF) == GPIO_AF3_TIM10) || \
|
||||
((AF) == GPIO_AF3_TIM11) || ((AF) == GPIO_AF3_LPTIM1) || \
|
||||
((AF) == GPIO_AF3_CEC) || ((AF) == GPIO_AF4_CEC) || \
|
||||
((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \
|
||||
((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF4_I2C4) || \
|
||||
((AF) == GPIO_AF5_SPI1) || ((AF) == GPIO_AF5_SPI2) || \
|
||||
((AF) == GPIO_AF5_SPI3) || ((AF) == GPIO_AF5_SPI4) || \
|
||||
((AF) == GPIO_AF5_SPI5) || ((AF) == GPIO_AF5_SPI6) || \
|
||||
((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF6_SAI1) || \
|
||||
((AF) == GPIO_AF7_SPI3) || ((AF) == GPIO_AF7_SPI2) || \
|
||||
((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \
|
||||
((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF7_UART5) || \
|
||||
((AF) == GPIO_AF7_SPDIFRX) || ((AF) == GPIO_AF8_SPDIFRX) || \
|
||||
((AF) == GPIO_AF8_SAI2) || ((AF) == GPIO_AF8_USART6) || \
|
||||
((AF) == GPIO_AF8_UART4) || ((AF) == GPIO_AF8_UART5) || \
|
||||
((AF) == GPIO_AF8_UART7) || ((AF) == GPIO_AF8_UART8) || \
|
||||
((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \
|
||||
((AF) == GPIO_AF9_TIM12) || ((AF) == GPIO_AF9_TIM12) || \
|
||||
((AF) == GPIO_AF9_TIM14) || ((AF) == GPIO_AF9_QUADSPI) || \
|
||||
((AF) == GPIO_AF10_OTG_HS) || ((AF) == GPIO_AF10_SAI2) || \
|
||||
((AF) == GPIO_AF10_QUADSPI) || ((AF) == GPIO_AF11_ETH) || \
|
||||
((AF) == GPIO_AF10_SDMMC2) || ((AF) == GPIO_AF11_SDMMC2) || \
|
||||
((AF) == GPIO_AF11_CAN3) || ((AF) == GPIO_AF12_OTG_HS_FS) || \
|
||||
((AF) == GPIO_AF12_SDMMC1) || ((AF) == GPIO_AF12_FMC) || \
|
||||
((AF) == GPIO_AF15_EVENTOUT) || ((AF) == GPIO_AF13_DCMI) || \
|
||||
((AF) == GPIO_AF10_OTG_FS))
|
||||
#elif defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx)
|
||||
#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF1_TIM1) || \
|
||||
((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \
|
||||
((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF1_TIM2) || \
|
||||
((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \
|
||||
((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \
|
||||
((AF) == GPIO_AF3_TIM9) || ((AF) == GPIO_AF3_TIM10) || \
|
||||
((AF) == GPIO_AF3_TIM11) || ((AF) == GPIO_AF3_LPTIM1) || \
|
||||
((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \
|
||||
((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF5_SPI1) || \
|
||||
((AF) == GPIO_AF5_SPI2) || ((AF) == GPIO_AF5_SPI3) || \
|
||||
((AF) == GPIO_AF5_SPI4) || ((AF) == GPIO_AF5_SPI5) || \
|
||||
((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF6_SAI1) || \
|
||||
((AF) == GPIO_AF7_SPI3) || ((AF) == GPIO_AF7_SPI2) || \
|
||||
((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \
|
||||
((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF7_UART5) || \
|
||||
((AF) == GPIO_AF8_SAI2) || ((AF) == GPIO_AF8_USART6) || \
|
||||
((AF) == GPIO_AF8_UART4) || ((AF) == GPIO_AF8_UART5) || \
|
||||
((AF) == GPIO_AF8_UART7) || ((AF) == GPIO_AF8_UART8) || \
|
||||
((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_TIM12) || \
|
||||
((AF) == GPIO_AF9_TIM12) || ((AF) == GPIO_AF9_TIM14) || \
|
||||
((AF) == GPIO_AF9_QUADSPI) || ((AF) == GPIO_AF10_OTG_HS) || \
|
||||
((AF) == GPIO_AF10_SAI2) || ((AF) == GPIO_AF10_QUADSPI) || \
|
||||
((AF) == GPIO_AF10_SDMMC2) || ((AF) == GPIO_AF11_SDMMC2) || \
|
||||
((AF) == GPIO_AF12_OTG_HS_FS) || ((AF) == GPIO_AF12_SDMMC1) || \
|
||||
((AF) == GPIO_AF12_FMC) || ((AF) == GPIO_AF15_EVENTOUT) || \
|
||||
((AF) == GPIO_AF10_OTG_FS))
|
||||
#endif /* STM32F756xx || STM32F746xx */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup GPIOEx_Private_Functions GPIO Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F7xx_HAL_GPIO_EX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,450 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_hal_hash.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.2
|
||||
* @date 14-April-2017
|
||||
* @brief Header file of HASH HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F7xx_HAL_HASH_H
|
||||
#define __STM32F7xx_HAL_HASH_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if defined (STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx)
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup HASH
|
||||
* @brief HASH HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup HASH_Exported_Types HASH Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup HASH_Exported_Types_Group1 HASH Configuration Structure definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t DataType; /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string.
|
||||
This parameter can be a value of @ref HASH_Data_Type */
|
||||
|
||||
uint32_t KeySize; /*!< The key size is used only in HMAC operation */
|
||||
|
||||
uint8_t* pKey; /*!< The key is used only in HMAC operation */
|
||||
}HASH_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HASH_Exported_Types_Group2 HASH State structures definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
typedef enum
|
||||
{
|
||||
HAL_HASH_STATE_RESET = 0x00U, /*!< HASH not yet initialized or disabled */
|
||||
HAL_HASH_STATE_READY = 0x01U, /*!< HASH initialized and ready for use */
|
||||
HAL_HASH_STATE_BUSY = 0x02U, /*!< HASH internal process is ongoing */
|
||||
HAL_HASH_STATE_TIMEOUT = 0x03U, /*!< HASH timeout state */
|
||||
HAL_HASH_STATE_ERROR = 0x04U /*!< HASH error state */
|
||||
}HAL_HASH_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HASH_Exported_Types_Group3 HASH phase structures definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
typedef enum
|
||||
{
|
||||
HAL_HASH_PHASE_READY = 0x01U, /*!< HASH peripheral is ready for initialization */
|
||||
HAL_HASH_PHASE_PROCESS = 0x02U, /*!< HASH peripheral is in processing phase */
|
||||
}HAL_HASHPhaseTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HASH_Exported_Types_Group4 HASH Handle structures definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
HASH_InitTypeDef Init; /*!< HASH required parameters */
|
||||
|
||||
uint8_t *pHashInBuffPtr; /*!< Pointer to input buffer */
|
||||
|
||||
uint8_t *pHashOutBuffPtr; /*!< Pointer to input buffer */
|
||||
|
||||
__IO uint32_t HashBuffSize; /*!< Size of buffer to be processed */
|
||||
|
||||
__IO uint32_t HashInCount; /*!< Counter of inputed data */
|
||||
|
||||
__IO uint32_t HashITCounter; /*!< Counter of issued interrupts */
|
||||
|
||||
HAL_StatusTypeDef Status; /*!< HASH peripheral status */
|
||||
|
||||
HAL_HASH_PhaseTypeDef Phase; /*!< HASH peripheral phase */
|
||||
|
||||
DMA_HandleTypeDef *hdmain; /*!< HASH In DMA handle parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< HASH locking object */
|
||||
|
||||
__IO HAL_HASH_StateTypeDef State; /*!< HASH peripheral state */
|
||||
} HASH_HandleTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup HASH_Exported_Constants HASH Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup HASH_Exported_Constants_Group1 HASH Algorithm Selection
|
||||
* @{
|
||||
*/
|
||||
#define HASH_ALGOSELECTION_SHA1 ((uint32_t)0x0000U) /*!< HASH function is SHA1 */
|
||||
#define HASH_ALGOSELECTION_SHA224 HASH_CR_ALGO_1 /*!< HASH function is SHA224 */
|
||||
#define HASH_ALGOSELECTION_SHA256 HASH_CR_ALGO /*!< HASH function is SHA256 */
|
||||
#define HASH_ALGOSELECTION_MD5 HASH_CR_ALGO_0 /*!< HASH function is MD5 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HASH_Exported_Constants_Group2 HASH Algorithm Mode
|
||||
* @{
|
||||
*/
|
||||
#define HASH_ALGOMODE_HASH ((uint32_t)0x00000000U) /*!< Algorithm is HASH */
|
||||
#define HASH_ALGOMODE_HMAC HASH_CR_MODE /*!< Algorithm is HMAC */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HASH_Data_Type HASH Data Type
|
||||
* @{
|
||||
*/
|
||||
#define HASH_DATATYPE_32B ((uint32_t)0x0000U) /*!< 32-bit data. No swapping */
|
||||
#define HASH_DATATYPE_16B HASH_CR_DATATYPE_0 /*!< 16-bit data. Each half word is swapped */
|
||||
#define HASH_DATATYPE_8B HASH_CR_DATATYPE_1 /*!< 8-bit data. All bytes are swapped */
|
||||
#define HASH_DATATYPE_1B HASH_CR_DATATYPE /*!< 1-bit data. In the word all bits are swapped */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HASH_Exported_Constants_Group4 HASH HMAC Long key
|
||||
* @brief HASH HMAC Long key used only for HMAC mode
|
||||
* @{
|
||||
*/
|
||||
#define HASH_HMAC_KEYTYPE_SHORTKEY ((uint32_t)0x00000000U) /*!< HMAC Key is <= 64 bytes */
|
||||
#define HASH_HMAC_KEYTYPE_LONGKEY HASH_CR_LKEY /*!< HMAC Key is > 64 bytes */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HASH_Exported_Constants_Group5 HASH Flags definition
|
||||
* @{
|
||||
*/
|
||||
#define HASH_FLAG_DINIS HASH_SR_DINIS /*!< 16 locations are free in the DIN : A new block can be entered into the input buffer */
|
||||
#define HASH_FLAG_DCIS HASH_SR_DCIS /*!< Digest calculation complete */
|
||||
#define HASH_FLAG_DMAS HASH_SR_DMAS /*!< DMA interface is enabled (DMAE=1) or a transfer is ongoing */
|
||||
#define HASH_FLAG_BUSY HASH_SR_BUSY /*!< The hash core is Busy : processing a block of data */
|
||||
#define HASH_FLAG_DINNE HASH_CR_DINNE /*!< DIN not empty : The input buffer contains at least one word of data */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HASH_Exported_Constants_Group6 HASH Interrupts definition
|
||||
* @{
|
||||
*/
|
||||
#define HASH_IT_DINI HASH_IMR_DINIE /*!< A new block can be entered into the input buffer (DIN) */
|
||||
#define HASH_IT_DCI HASH_IMR_DCIE /*!< Digest calculation complete */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup HASH_Exported_Macros HASH Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset HASH handle state
|
||||
* @param __HANDLE__: specifies the HASH handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_HASH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_HASH_STATE_RESET)
|
||||
|
||||
/** @brief Check whether the specified HASH flag is set or not.
|
||||
* @param __FLAG__: specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg HASH_FLAG_DINIS: A new block can be entered into the input buffer.
|
||||
* @arg HASH_FLAG_DCIS: Digest calculation complete
|
||||
* @arg HASH_FLAG_DMAS: DMA interface is enabled (DMAE=1) or a transfer is ongoing
|
||||
* @arg HASH_FLAG_BUSY: The hash core is Busy : processing a block of data
|
||||
* @arg HASH_FLAG_DINNE: DIN not empty : The input buffer contains at least one word of data
|
||||
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_HASH_GET_FLAG(__FLAG__) (((__FLAG__) > 8U) ? ((HASH->CR & (__FLAG__)) == (__FLAG__)) :\
|
||||
((HASH->SR & (__FLAG__)) == (__FLAG__)))
|
||||
|
||||
/**
|
||||
* @brief Enable the multiple DMA mode.
|
||||
* This feature is available only in STM32F429x and STM32F439x devices.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_HASH_SET_MDMAT() HASH->CR |= HASH_CR_MDMAT
|
||||
|
||||
/**
|
||||
* @brief Disable the multiple DMA mode.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_HASH_RESET_MDMAT() HASH->CR &= (uint32_t)(~HASH_CR_MDMAT)
|
||||
|
||||
/**
|
||||
* @brief Start the digest computation
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_HASH_START_DIGEST() HASH->STR |= HASH_STR_DCAL
|
||||
|
||||
/**
|
||||
* @brief Set the number of valid bits in last word written in Data register
|
||||
* @param SIZE: size in byte of last data written in Data register.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_HASH_SET_NBVALIDBITS(SIZE) do{HASH->STR &= ~(HASH_STR_NBW);\
|
||||
HASH->STR |= 8 * ((SIZE) % 4);\
|
||||
}while(0)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include HASH HAL Extension module */
|
||||
#include "stm32f7xx_hal_hash_ex.h"
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup HASH_Exported_Functions HASH Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup HASH_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash);
|
||||
HAL_StatusTypeDef HAL_HASH_DeInit(HASH_HandleTypeDef *hhash);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup HASH_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HASH_MD5_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HASH_SHA1_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup HASH_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup HASH_Exported_Functions_Group4
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
|
||||
HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup HASH_Exported_Functions_Group5
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup HASH_Exported_Functions_Group6
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup HASH_Exported_Functions_Group7
|
||||
* @{
|
||||
*/
|
||||
void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup HASH_Exported_Functions_Group8
|
||||
* @{
|
||||
*/
|
||||
HAL_HASH_StateTypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash);
|
||||
void HAL_HASH_MspInit(HASH_HandleTypeDef *hhash);
|
||||
void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash);
|
||||
void HAL_HASH_InCpltCallback(HASH_HandleTypeDef *hhash);
|
||||
void HAL_HASH_DgstCpltCallback(HASH_HandleTypeDef *hhash);
|
||||
void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/** @defgroup HASH_Private_Types HASH Private Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/** @defgroup HASH_Private_Variables HASH Private Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup HASH_Private_Constants HASH Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup HASH_Private_Macros HASH Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_HASH_ALGOSELECTION(__ALGOSELECTION__) (((__ALGOSELECTION__) == HASH_ALGOSELECTION_SHA1) || \
|
||||
((__ALGOSELECTION__) == HASH_ALGOSELECTION_SHA224) || \
|
||||
((__ALGOSELECTION__) == HASH_ALGOSELECTION_SHA256) || \
|
||||
((__ALGOSELECTION__) == HASH_ALGOSELECTION_MD5))
|
||||
|
||||
|
||||
#define IS_HASH_ALGOMODE(__ALGOMODE__) (((__ALGOMODE__) == HASH_ALGOMODE_HASH) || \
|
||||
((__ALGOMODE__) == HASH_ALGOMODE_HMAC))
|
||||
|
||||
|
||||
#define IS_HASH_DATATYPE(__DATATYPE__) (((__DATATYPE__) == HASH_DATATYPE_32B)|| \
|
||||
((__DATATYPE__) == HASH_DATATYPE_16B)|| \
|
||||
((__DATATYPE__) == HASH_DATATYPE_8B) || \
|
||||
((__DATATYPE__) == HASH_DATATYPE_1B))
|
||||
|
||||
|
||||
#define IS_HASH_HMAC_KEYTYPE(__KEYTYPE__) (((__KEYTYPE__) == HASH_HMAC_KEYTYPE_SHORTKEY) || \
|
||||
((__KEYTYPE__) == HASH_HMAC_KEYTYPE_LONGKEY))
|
||||
|
||||
#define IS_HASH_SHA1_BUFFER_SIZE(__SIZE__) ((((__SIZE__)%4) != 0)? 0U: 1U)
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup HASH_Private_Functions HASH Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* STM32F756xx || STM32F777xx || STM32F779xx */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* __STM32F7xx_HAL_HASH_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,199 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_hal_hash_ex.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.2
|
||||
* @date 14-April-2017
|
||||
* @brief Header file of HASH HAL Extension module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F7xx_HAL_HASH_EX_H
|
||||
#define __STM32F7xx_HAL_HASH_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if defined (STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx)
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup HASHEx
|
||||
* @brief HASHEx HAL Extension module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup HASHEx_Exported_Functions HASHEx Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup HASHEx_Exported_Functions_Group1 HASHEx processing using polling functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HASHEx_Exported_Functions_Group2 HMAC processing using polling functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HASHEx_Exported_Functions_Group3 HASHEx processing using functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HASHEx_Exported_Functions_Group4 HASHEx processing using DMA
|
||||
* @{
|
||||
*/
|
||||
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HASHEx_Exported_Functions_Group5 HMAC processing using DMA
|
||||
* @{
|
||||
*/
|
||||
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HASHEx_Exported_Functions_Group6 HASHEx processing functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void HAL_HASHEx_IRQHandler(HASH_HandleTypeDef *hhash);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/** @defgroup HASHEx_Private_Types HASHEx Private Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/** @defgroup HASHEx_Private_Variables HASHEx Private Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup HASHEx_Private_Constants HASHEx Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup HASHEx_Private_Macros HASHEx Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup HASHEx_Private_Functions HASHEx Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* STM32F756xx || STM32F777xx || STM32F779xx */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F7xx_HAL_HASH_EX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,281 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_hal_hcd.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.2
|
||||
* @date 14-April-2017
|
||||
* @brief Header file of HCD HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F7xx_HAL_HCD_H
|
||||
#define __STM32F7xx_HAL_HCD_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx_ll_usb.h"
|
||||
|
||||
/** @addtogroup STM32F7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup HCD HCD
|
||||
* @brief HCD HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup HCD_Exported_Types HCD Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup HCD_Exported_Types_Group1 HCD State Structure definition
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_HCD_STATE_RESET = 0x00U,
|
||||
HAL_HCD_STATE_READY = 0x01U,
|
||||
HAL_HCD_STATE_ERROR = 0x02U,
|
||||
HAL_HCD_STATE_BUSY = 0x03U,
|
||||
HAL_HCD_STATE_TIMEOUT = 0x04U
|
||||
} HCD_StateTypeDef;
|
||||
|
||||
typedef USB_OTG_GlobalTypeDef HCD_TypeDef;
|
||||
typedef USB_OTG_CfgTypeDef HCD_InitTypeDef;
|
||||
typedef USB_OTG_HCTypeDef HCD_HCTypeDef ;
|
||||
typedef USB_OTG_URBStateTypeDef HCD_URBStateTypeDef ;
|
||||
typedef USB_OTG_HCStateTypeDef HCD_HCStateTypeDef ;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HCD_Exported_Types_Group2 HCD Handle Structure definition
|
||||
* @{
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
HCD_TypeDef *Instance; /*!< Register base address */
|
||||
HCD_InitTypeDef Init; /*!< HCD required parameters */
|
||||
HCD_HCTypeDef hc[15]; /*!< Host channels parameters */
|
||||
HAL_LockTypeDef Lock; /*!< HCD peripheral status */
|
||||
__IO HCD_StateTypeDef State; /*!< HCD communication state */
|
||||
void *pData; /*!< Pointer Stack Handler */
|
||||
} HCD_HandleTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup HCD_Exported_Constants HCD Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup HCD_Speed HCD Speed
|
||||
* @{
|
||||
*/
|
||||
#define HCD_SPEED_HIGH 0U
|
||||
#define HCD_SPEED_LOW 2U
|
||||
#define HCD_SPEED_FULL 3U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HCD_PHY_Module HCD PHY Module
|
||||
* @{
|
||||
*/
|
||||
#define HCD_PHY_ULPI 1U
|
||||
#define HCD_PHY_EMBEDDED 2U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup HCD_Exported_Macros HCD Exported Macros
|
||||
* @brief macros to handle interrupts and specific clock configurations
|
||||
* @{
|
||||
*/
|
||||
#define __HAL_HCD_ENABLE(__HANDLE__) USB_EnableGlobalInt ((__HANDLE__)->Instance)
|
||||
#define __HAL_HCD_DISABLE(__HANDLE__) USB_DisableGlobalInt ((__HANDLE__)->Instance)
|
||||
|
||||
#define __HAL_HCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
|
||||
#define __HAL_HCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__))
|
||||
#define __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U)
|
||||
|
||||
#define __HAL_HCD_CLEAR_HC_INT(chnum, __INTERRUPT__) (USBx_HC(chnum)->HCINT = (__INTERRUPT__))
|
||||
#define __HAL_HCD_MASK_HALT_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_CHHM)
|
||||
#define __HAL_HCD_UNMASK_HALT_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_CHHM)
|
||||
#define __HAL_HCD_MASK_ACK_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_ACKM)
|
||||
#define __HAL_HCD_UNMASK_ACK_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_ACKM)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup HCD_Exported_Functions HCD Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd);
|
||||
HAL_StatusTypeDef HAL_HCD_DeInit (HCD_HandleTypeDef *hhcd);
|
||||
HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd,
|
||||
uint8_t ch_num,
|
||||
uint8_t epnum,
|
||||
uint8_t dev_address,
|
||||
uint8_t speed,
|
||||
uint8_t ep_type,
|
||||
uint16_t mps);
|
||||
|
||||
HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num);
|
||||
void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd);
|
||||
void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* I/O operation functions ***************************************************/
|
||||
/** @addtogroup HCD_Exported_Functions_Group2 Input and Output operation functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,
|
||||
uint8_t pipe,
|
||||
uint8_t direction ,
|
||||
uint8_t ep_type,
|
||||
uint8_t token,
|
||||
uint8_t* pbuff,
|
||||
uint16_t length,
|
||||
uint8_t do_ping);
|
||||
|
||||
/* Non-Blocking mode: Interrupt */
|
||||
void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd);
|
||||
void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd);
|
||||
void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd);
|
||||
void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd);
|
||||
void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd,
|
||||
uint8_t chnum,
|
||||
HCD_URBStateTypeDef urb_state);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Peripheral Control functions **********************************************/
|
||||
/** @addtogroup HCD_Exported_Functions_Group3 Peripheral Control functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd);
|
||||
HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd);
|
||||
HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Peripheral State functions ************************************************/
|
||||
/** @addtogroup HCD_Exported_Functions_Group4 Peripheral State functions
|
||||
* @{
|
||||
*/
|
||||
HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef *hhcd);
|
||||
HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnum);
|
||||
uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum);
|
||||
HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum);
|
||||
uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd);
|
||||
uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup HCD_Private_Macros HCD Private Macros
|
||||
* @{
|
||||
*/
|
||||
/** @defgroup HCD_Instance_definition HCD Instance definition
|
||||
* @{
|
||||
*/
|
||||
#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
|
||||
((INSTANCE) == USB_OTG_HS))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions prototypes ----------------------------------------------*/
|
||||
/** @defgroup HCD_Private_Functions_Prototypes HCD Private Functions Prototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup HCD_Private_Functions HCD Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F7xx_HAL_HCD_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,710 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_hal_i2c.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.2
|
||||
* @date 14-April-2017
|
||||
* @brief Header file of I2C HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F7xx_HAL_I2C_H
|
||||
#define __STM32F7xx_HAL_I2C_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup I2C_Exported_Types I2C Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition
|
||||
* @brief I2C Configuration Structure definition
|
||||
* @{
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Timing; /*!< Specifies the I2C_TIMINGR_register value.
|
||||
This parameter calculated by referring to I2C initialization
|
||||
section in Reference manual */
|
||||
|
||||
uint32_t OwnAddress1; /*!< Specifies the first device own address.
|
||||
This parameter can be a 7-bit or 10-bit address. */
|
||||
|
||||
uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected.
|
||||
This parameter can be a value of @ref I2C_ADDRESSING_MODE */
|
||||
|
||||
uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected.
|
||||
This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */
|
||||
|
||||
uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected
|
||||
This parameter can be a 7-bit address. */
|
||||
|
||||
uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing mode is selected
|
||||
This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */
|
||||
|
||||
uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
|
||||
This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */
|
||||
|
||||
uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
|
||||
This parameter can be a value of @ref I2C_NOSTRETCH_MODE */
|
||||
|
||||
}I2C_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_state_structure_definition HAL state structure definition
|
||||
* @brief HAL State structure definition
|
||||
* @note HAL I2C State value coding follow below described bitmap :\n
|
||||
* b7-b6 Error information\n
|
||||
* 00 : No Error\n
|
||||
* 01 : Abort (Abort user request on going)\n
|
||||
* 10 : Timeout\n
|
||||
* 11 : Error\n
|
||||
* b5 IP initilisation status\n
|
||||
* 0 : Reset (IP not initialized)\n
|
||||
* 1 : Init done (IP initialized and ready to use. HAL I2C Init function called)\n
|
||||
* b4 (not used)\n
|
||||
* x : Should be set to 0\n
|
||||
* b3\n
|
||||
* 0 : Ready or Busy (No Listen mode ongoing)\n
|
||||
* 1 : Listen (IP in Address Listen Mode)\n
|
||||
* b2 Intrinsic process state\n
|
||||
* 0 : Ready\n
|
||||
* 1 : Busy (IP busy with some configuration or internal operations)\n
|
||||
* b1 Rx state\n
|
||||
* 0 : Ready (no Rx operation ongoing)\n
|
||||
* 1 : Busy (Rx operation ongoing)\n
|
||||
* b0 Tx state\n
|
||||
* 0 : Ready (no Tx operation ongoing)\n
|
||||
* 1 : Busy (Tx operation ongoing)
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_I2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */
|
||||
HAL_I2C_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use */
|
||||
HAL_I2C_STATE_BUSY = 0x24U, /*!< An internal process is ongoing */
|
||||
HAL_I2C_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing */
|
||||
HAL_I2C_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */
|
||||
HAL_I2C_STATE_LISTEN = 0x28U, /*!< Address Listen Mode is ongoing */
|
||||
HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, /*!< Address Listen Mode and Data Transmission
|
||||
process is ongoing */
|
||||
HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception
|
||||
process is ongoing */
|
||||
HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */
|
||||
HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */
|
||||
HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */
|
||||
|
||||
}HAL_I2C_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_mode_structure_definition HAL mode structure definition
|
||||
* @brief HAL Mode structure definition
|
||||
* @note HAL I2C Mode value coding follow below described bitmap :\n
|
||||
* b7 (not used)\n
|
||||
* x : Should be set to 0\n
|
||||
* b6\n
|
||||
* 0 : None\n
|
||||
* 1 : Memory (HAL I2C communication is in Memory Mode)\n
|
||||
* b5\n
|
||||
* 0 : None\n
|
||||
* 1 : Slave (HAL I2C communication is in Slave Mode)\n
|
||||
* b4\n
|
||||
* 0 : None\n
|
||||
* 1 : Master (HAL I2C communication is in Master Mode)\n
|
||||
* b3-b2-b1-b0 (not used)\n
|
||||
* xxxx : Should be set to 0000
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_I2C_MODE_NONE = 0x00U, /*!< No I2C communication on going */
|
||||
HAL_I2C_MODE_MASTER = 0x10U, /*!< I2C communication is in Master Mode */
|
||||
HAL_I2C_MODE_SLAVE = 0x20U, /*!< I2C communication is in Slave Mode */
|
||||
HAL_I2C_MODE_MEM = 0x40U /*!< I2C communication is in Memory Mode */
|
||||
|
||||
}HAL_I2C_ModeTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_Error_Code_definition I2C Error Code definition
|
||||
* @brief I2C Error Code definition
|
||||
* @{
|
||||
*/
|
||||
#define HAL_I2C_ERROR_NONE (0x00000000U) /*!< No error */
|
||||
#define HAL_I2C_ERROR_BERR (0x00000001U) /*!< BERR error */
|
||||
#define HAL_I2C_ERROR_ARLO (0x00000002U) /*!< ARLO error */
|
||||
#define HAL_I2C_ERROR_AF (0x00000004U) /*!< ACKF error */
|
||||
#define HAL_I2C_ERROR_OVR (0x00000008U) /*!< OVR error */
|
||||
#define HAL_I2C_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
|
||||
#define HAL_I2C_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */
|
||||
#define HAL_I2C_ERROR_SIZE (0x00000040U) /*!< Size Management error */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition
|
||||
* @brief I2C handle Structure definition
|
||||
* @{
|
||||
*/
|
||||
typedef struct __I2C_HandleTypeDef
|
||||
{
|
||||
I2C_TypeDef *Instance; /*!< I2C registers base address */
|
||||
|
||||
I2C_InitTypeDef Init; /*!< I2C communication parameters */
|
||||
|
||||
uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */
|
||||
|
||||
uint16_t XferSize; /*!< I2C transfer size */
|
||||
|
||||
__IO uint16_t XferCount; /*!< I2C transfer counter */
|
||||
|
||||
__IO uint32_t XferOptions; /*!< I2C sequantial transfer options, this parameter can
|
||||
be a value of @ref I2C_XFEROPTIONS */
|
||||
|
||||
__IO uint32_t PreviousState; /*!< I2C communication Previous state */
|
||||
|
||||
HAL_StatusTypeDef (*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); /*!< I2C transfer IRQ handler function pointer */
|
||||
|
||||
DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */
|
||||
|
||||
DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< I2C locking object */
|
||||
|
||||
__IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */
|
||||
|
||||
__IO HAL_I2C_ModeTypeDef Mode; /*!< I2C communication mode */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< I2C Error code */
|
||||
|
||||
__IO uint32_t AddrEventCount; /*!< I2C Address Event counter */
|
||||
}I2C_HandleTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup I2C_Exported_Constants I2C Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_XFEROPTIONS I2C Sequential Transfer Options
|
||||
* @{
|
||||
*/
|
||||
#define I2C_FIRST_FRAME ((uint32_t)I2C_SOFTEND_MODE)
|
||||
#define I2C_FIRST_AND_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
|
||||
#define I2C_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
|
||||
#define I2C_FIRST_AND_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)
|
||||
#define I2C_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_ADDRESSING_MODE I2C Addressing Mode
|
||||
* @{
|
||||
*/
|
||||
#define I2C_ADDRESSINGMODE_7BIT (0x00000001U)
|
||||
#define I2C_ADDRESSINGMODE_10BIT (0x00000002U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_DUAL_ADDRESSING_MODE I2C Dual Addressing Mode
|
||||
* @{
|
||||
*/
|
||||
#define I2C_DUALADDRESS_DISABLE (0x00000000U)
|
||||
#define I2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_OWN_ADDRESS2_MASKS I2C Own Address2 Masks
|
||||
* @{
|
||||
*/
|
||||
#define I2C_OA2_NOMASK ((uint8_t)0x00U)
|
||||
#define I2C_OA2_MASK01 ((uint8_t)0x01U)
|
||||
#define I2C_OA2_MASK02 ((uint8_t)0x02U)
|
||||
#define I2C_OA2_MASK03 ((uint8_t)0x03U)
|
||||
#define I2C_OA2_MASK04 ((uint8_t)0x04U)
|
||||
#define I2C_OA2_MASK05 ((uint8_t)0x05U)
|
||||
#define I2C_OA2_MASK06 ((uint8_t)0x06U)
|
||||
#define I2C_OA2_MASK07 ((uint8_t)0x07U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_GENERAL_CALL_ADDRESSING_MODE I2C General Call Addressing Mode
|
||||
* @{
|
||||
*/
|
||||
#define I2C_GENERALCALL_DISABLE (0x00000000U)
|
||||
#define I2C_GENERALCALL_ENABLE I2C_CR1_GCEN
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_NOSTRETCH_MODE I2C No-Stretch Mode
|
||||
* @{
|
||||
*/
|
||||
#define I2C_NOSTRETCH_DISABLE (0x00000000U)
|
||||
#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_MEMORY_ADDRESS_SIZE I2C Memory Address Size
|
||||
* @{
|
||||
*/
|
||||
#define I2C_MEMADD_SIZE_8BIT (0x00000001U)
|
||||
#define I2C_MEMADD_SIZE_16BIT (0x00000002U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_XFERDIRECTION I2C Transfer Direction Master Point of View
|
||||
* @{
|
||||
*/
|
||||
#define I2C_DIRECTION_TRANSMIT (0x00000000U)
|
||||
#define I2C_DIRECTION_RECEIVE (0x00000001U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_RELOAD_END_MODE I2C Reload End Mode
|
||||
* @{
|
||||
*/
|
||||
#define I2C_RELOAD_MODE I2C_CR2_RELOAD
|
||||
#define I2C_AUTOEND_MODE I2C_CR2_AUTOEND
|
||||
#define I2C_SOFTEND_MODE (0x00000000U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_START_STOP_MODE I2C Start or Stop Mode
|
||||
* @{
|
||||
*/
|
||||
#define I2C_NO_STARTSTOP (0x00000000U)
|
||||
#define I2C_GENERATE_STOP I2C_CR2_STOP
|
||||
#define I2C_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)
|
||||
#define I2C_GENERATE_START_WRITE I2C_CR2_START
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition
|
||||
* @brief I2C Interrupt definition
|
||||
* Elements values convention: 0xXXXXXXXX
|
||||
* - XXXXXXXX : Interrupt control mask
|
||||
* @{
|
||||
*/
|
||||
#define I2C_IT_ERRI I2C_CR1_ERRIE
|
||||
#define I2C_IT_TCI I2C_CR1_TCIE
|
||||
#define I2C_IT_STOPI I2C_CR1_STOPIE
|
||||
#define I2C_IT_NACKI I2C_CR1_NACKIE
|
||||
#define I2C_IT_ADDRI I2C_CR1_ADDRIE
|
||||
#define I2C_IT_RXI I2C_CR1_RXIE
|
||||
#define I2C_IT_TXI I2C_CR1_TXIE
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_Flag_definition I2C Flag definition
|
||||
* @{
|
||||
*/
|
||||
#define I2C_FLAG_TXE I2C_ISR_TXE
|
||||
#define I2C_FLAG_TXIS I2C_ISR_TXIS
|
||||
#define I2C_FLAG_RXNE I2C_ISR_RXNE
|
||||
#define I2C_FLAG_ADDR I2C_ISR_ADDR
|
||||
#define I2C_FLAG_AF I2C_ISR_NACKF
|
||||
#define I2C_FLAG_STOPF I2C_ISR_STOPF
|
||||
#define I2C_FLAG_TC I2C_ISR_TC
|
||||
#define I2C_FLAG_TCR I2C_ISR_TCR
|
||||
#define I2C_FLAG_BERR I2C_ISR_BERR
|
||||
#define I2C_FLAG_ARLO I2C_ISR_ARLO
|
||||
#define I2C_FLAG_OVR I2C_ISR_OVR
|
||||
#define I2C_FLAG_PECERR I2C_ISR_PECERR
|
||||
#define I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT
|
||||
#define I2C_FLAG_ALERT I2C_ISR_ALERT
|
||||
#define I2C_FLAG_BUSY I2C_ISR_BUSY
|
||||
#define I2C_FLAG_DIR I2C_ISR_DIR
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
|
||||
/** @defgroup I2C_Exported_Macros I2C Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset I2C handle state.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
|
||||
|
||||
/** @brief Enable the specified I2C interrupt.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @param __INTERRUPT__ specifies the interrupt source to enable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref I2C_IT_ERRI Errors interrupt enable
|
||||
* @arg @ref I2C_IT_TCI Transfer complete interrupt enable
|
||||
* @arg @ref I2C_IT_STOPI STOP detection interrupt enable
|
||||
* @arg @ref I2C_IT_NACKI NACK received interrupt enable
|
||||
* @arg @ref I2C_IT_ADDRI Address match interrupt enable
|
||||
* @arg @ref I2C_IT_RXI RX interrupt enable
|
||||
* @arg @ref I2C_IT_TXI TX interrupt enable
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
|
||||
|
||||
/** @brief Disable the specified I2C interrupt.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @param __INTERRUPT__ specifies the interrupt source to disable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref I2C_IT_ERRI Errors interrupt enable
|
||||
* @arg @ref I2C_IT_TCI Transfer complete interrupt enable
|
||||
* @arg @ref I2C_IT_STOPI STOP detection interrupt enable
|
||||
* @arg @ref I2C_IT_NACKI NACK received interrupt enable
|
||||
* @arg @ref I2C_IT_ADDRI Address match interrupt enable
|
||||
* @arg @ref I2C_IT_RXI RX interrupt enable
|
||||
* @arg @ref I2C_IT_TXI TX interrupt enable
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
|
||||
|
||||
/** @brief Check whether the specified I2C interrupt source is enabled or not.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @param __INTERRUPT__ specifies the I2C interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref I2C_IT_ERRI Errors interrupt enable
|
||||
* @arg @ref I2C_IT_TCI Transfer complete interrupt enable
|
||||
* @arg @ref I2C_IT_STOPI STOP detection interrupt enable
|
||||
* @arg @ref I2C_IT_NACKI NACK received interrupt enable
|
||||
* @arg @ref I2C_IT_ADDRI Address match interrupt enable
|
||||
* @arg @ref I2C_IT_RXI RX interrupt enable
|
||||
* @arg @ref I2C_IT_TXI TX interrupt enable
|
||||
*
|
||||
* @retval The new state of __INTERRUPT__ (SET or RESET).
|
||||
*/
|
||||
#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
||||
|
||||
/** @brief Check whether the specified I2C flag is set or not.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref I2C_FLAG_TXE Transmit data register empty
|
||||
* @arg @ref I2C_FLAG_TXIS Transmit interrupt status
|
||||
* @arg @ref I2C_FLAG_RXNE Receive data register not empty
|
||||
* @arg @ref I2C_FLAG_ADDR Address matched (slave mode)
|
||||
* @arg @ref I2C_FLAG_AF Acknowledge failure received flag
|
||||
* @arg @ref I2C_FLAG_STOPF STOP detection flag
|
||||
* @arg @ref I2C_FLAG_TC Transfer complete (master mode)
|
||||
* @arg @ref I2C_FLAG_TCR Transfer complete reload
|
||||
* @arg @ref I2C_FLAG_BERR Bus error
|
||||
* @arg @ref I2C_FLAG_ARLO Arbitration lost
|
||||
* @arg @ref I2C_FLAG_OVR Overrun/Underrun
|
||||
* @arg @ref I2C_FLAG_PECERR PEC error in reception
|
||||
* @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
|
||||
* @arg @ref I2C_FLAG_ALERT SMBus alert
|
||||
* @arg @ref I2C_FLAG_BUSY Bus busy
|
||||
* @arg @ref I2C_FLAG_DIR Transfer direction (slave mode)
|
||||
*
|
||||
* @retval The new state of __FLAG__ (SET or RESET).
|
||||
*/
|
||||
#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
|
||||
|
||||
/** @brief Clear the I2C pending flags which are cleared by writing 1 in a specific bit.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @param __FLAG__ specifies the flag to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg @ref I2C_FLAG_TXE Transmit data register empty
|
||||
* @arg @ref I2C_FLAG_ADDR Address matched (slave mode)
|
||||
* @arg @ref I2C_FLAG_AF Acknowledge failure received flag
|
||||
* @arg @ref I2C_FLAG_STOPF STOP detection flag
|
||||
* @arg @ref I2C_FLAG_BERR Bus error
|
||||
* @arg @ref I2C_FLAG_ARLO Arbitration lost
|
||||
* @arg @ref I2C_FLAG_OVR Overrun/Underrun
|
||||
* @arg @ref I2C_FLAG_PECERR PEC error in reception
|
||||
* @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
|
||||
* @arg @ref I2C_FLAG_ALERT SMBus alert
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? ((__HANDLE__)->Instance->ISR |= (__FLAG__)) \
|
||||
: ((__HANDLE__)->Instance->ICR = (__FLAG__)))
|
||||
|
||||
/** @brief Enable the specified I2C peripheral.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
|
||||
|
||||
/** @brief Disable the specified I2C peripheral.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
|
||||
|
||||
/** @brief Generate a Non-Acknowledge I2C peripheral in Slave mode.
|
||||
* @param __HANDLE__: specifies the I2C Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include I2C HAL Extended module */
|
||||
#include "stm32f7xx_hal_i2c_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup I2C_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
/* Initialization and de-initialization functions******************************/
|
||||
HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);
|
||||
HAL_StatusTypeDef HAL_I2C_DeInit (I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions
|
||||
* @{
|
||||
*/
|
||||
/* IO operation functions ****************************************************/
|
||||
/******* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
|
||||
|
||||
/******* Non-Blocking mode: Interrupt */
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
|
||||
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c);
|
||||
HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress);
|
||||
|
||||
/******* Non-Blocking mode: DMA */
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
|
||||
* @{
|
||||
*/
|
||||
/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
|
||||
void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
|
||||
void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State, Mode and Error functions *********************************/
|
||||
HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c);
|
||||
HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c);
|
||||
uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup I2C_Private_Constants I2C Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup I2C_Private_Macro I2C Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_I2C_ADDRESSING_MODE(MODE) (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \
|
||||
((MODE) == I2C_ADDRESSINGMODE_10BIT))
|
||||
|
||||
#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \
|
||||
((ADDRESS) == I2C_DUALADDRESS_ENABLE))
|
||||
|
||||
#define IS_I2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == I2C_OA2_NOMASK) || \
|
||||
((MASK) == I2C_OA2_MASK01) || \
|
||||
((MASK) == I2C_OA2_MASK02) || \
|
||||
((MASK) == I2C_OA2_MASK03) || \
|
||||
((MASK) == I2C_OA2_MASK04) || \
|
||||
((MASK) == I2C_OA2_MASK05) || \
|
||||
((MASK) == I2C_OA2_MASK06) || \
|
||||
((MASK) == I2C_OA2_MASK07))
|
||||
|
||||
#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \
|
||||
((CALL) == I2C_GENERALCALL_ENABLE))
|
||||
|
||||
#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \
|
||||
((STRETCH) == I2C_NOSTRETCH_ENABLE))
|
||||
|
||||
#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
|
||||
((SIZE) == I2C_MEMADD_SIZE_16BIT))
|
||||
|
||||
#define IS_TRANSFER_MODE(MODE) (((MODE) == I2C_RELOAD_MODE) || \
|
||||
((MODE) == I2C_AUTOEND_MODE) || \
|
||||
((MODE) == I2C_SOFTEND_MODE))
|
||||
|
||||
#define IS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == I2C_GENERATE_STOP) || \
|
||||
((REQUEST) == I2C_GENERATE_START_READ) || \
|
||||
((REQUEST) == I2C_GENERATE_START_WRITE) || \
|
||||
((REQUEST) == I2C_NO_STARTSTOP))
|
||||
|
||||
#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || \
|
||||
((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \
|
||||
((REQUEST) == I2C_NEXT_FRAME) || \
|
||||
((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \
|
||||
((REQUEST) == I2C_LAST_FRAME))
|
||||
|
||||
#define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
|
||||
|
||||
#define I2C_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16U)
|
||||
#define I2C_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U)
|
||||
#define I2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
|
||||
#define I2C_GET_OWN_ADDRESS1(__HANDLE__) ((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1)
|
||||
#define I2C_GET_OWN_ADDRESS2(__HANDLE__) ((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2)
|
||||
|
||||
#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)
|
||||
#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU)
|
||||
|
||||
#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8U)))
|
||||
#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
|
||||
|
||||
#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \
|
||||
(uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private Functions ---------------------------------------------------------*/
|
||||
/** @defgroup I2C_Private_Functions I2C Private Functions
|
||||
* @{
|
||||
*/
|
||||
/* Private functions are defined in stm32f7xx_hal_i2c.c file */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* __STM32F7xx_HAL_I2C_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,223 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_hal_i2c_ex.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.2
|
||||
* @date 14-April-2017
|
||||
* @brief Header file of I2C HAL Extended module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F7xx_HAL_I2C_EX_H
|
||||
#define __STM32F7xx_HAL_I2C_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup I2CEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup I2CEx_Exported_Constants I2C Extended Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup I2CEx_Analog_Filter I2C Extended Analog Filter
|
||||
* @{
|
||||
*/
|
||||
#define I2C_ANALOGFILTER_ENABLE 0x00000000U
|
||||
#define I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus
|
||||
* @{
|
||||
*/
|
||||
#define I2C_FMP_NOT_SUPPORTED 0xAAAA0000U /*!< Fast Mode Plus not supported */
|
||||
#if defined(SYSCFG_PMC_I2C_PB6_FMP)
|
||||
#define I2C_FASTMODEPLUS_PB6 SYSCFG_PMC_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */
|
||||
#define I2C_FASTMODEPLUS_PB7 SYSCFG_PMC_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */
|
||||
#else
|
||||
#define I2C_FASTMODEPLUS_PB6 (uint32_t)(0x00000004U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus PB6 not supported */
|
||||
#define I2C_FASTMODEPLUS_PB7 (uint32_t)(0x00000008U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus PB7 not supported */
|
||||
#endif
|
||||
#if defined(SYSCFG_PMC_I2C_PB8_FMP)
|
||||
#define I2C_FASTMODEPLUS_PB8 SYSCFG_PMC_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */
|
||||
#define I2C_FASTMODEPLUS_PB9 SYSCFG_PMC_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */
|
||||
#else
|
||||
#define I2C_FASTMODEPLUS_PB8 (uint32_t)(0x00000010U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus PB8 not supported */
|
||||
#define I2C_FASTMODEPLUS_PB9 (uint32_t)(0x00000012U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus PB9 not supported */
|
||||
#endif
|
||||
#if defined(SYSCFG_PMC_I2C1_FMP)
|
||||
#define I2C_FASTMODEPLUS_I2C1 SYSCFG_PMC_I2C1_FMP /*!< Enable Fast Mode Plus on I2C1 pins */
|
||||
#else
|
||||
#define I2C_FASTMODEPLUS_I2C1 (uint32_t)(0x00000100U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C1 not supported */
|
||||
#endif
|
||||
#if defined(SYSCFG_PMC_I2C2_FMP)
|
||||
#define I2C_FASTMODEPLUS_I2C2 SYSCFG_PMC_I2C2_FMP /*!< Enable Fast Mode Plus on I2C2 pins */
|
||||
#else
|
||||
#define I2C_FASTMODEPLUS_I2C2 (uint32_t)(0x00000200U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C2 not supported */
|
||||
#endif
|
||||
#if defined(SYSCFG_PMC_I2C3_FMP)
|
||||
#define I2C_FASTMODEPLUS_I2C3 SYSCFG_PMC_I2C3_FMP /*!< Enable Fast Mode Plus on I2C3 pins */
|
||||
#else
|
||||
#define I2C_FASTMODEPLUS_I2C3 (uint32_t)(0x00000400U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C3 not supported */
|
||||
#endif
|
||||
#if defined(SYSCFG_PMC_I2C4_FMP)
|
||||
#define I2C_FASTMODEPLUS_I2C4 SYSCFG_PMC_I2C4_FMP /*!< Enable Fast Mode Plus on I2C4 pins */
|
||||
#else
|
||||
#define I2C_FASTMODEPLUS_I2C4 (uint32_t)(0x00000800U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C4 not supported */
|
||||
#endif
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @addtogroup I2CEx_Exported_Functions I2C Extended Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup I2CEx_Exported_Functions_Group1 Extended features functions
|
||||
* @brief Extended features functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Peripheral Control functions ************************************************/
|
||||
HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter);
|
||||
HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter);
|
||||
#if defined(SYSCFG_PMC_I2C1_FMP)
|
||||
void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus);
|
||||
void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
|
||||
#endif /* SYSCFG_PMC_I2C1_FMP */
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup I2CEx_Private_Constants I2C Extended Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup I2CEx_Private_Macro I2C Extended Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \
|
||||
((FILTER) == I2C_ANALOGFILTER_DISABLE))
|
||||
|
||||
#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU)
|
||||
|
||||
#if defined(SYSCFG_PMC_I2C1_FMP) && defined(SYSCFG_PMC_I2C2_FMP) && defined(SYSCFG_PMC_I2C3_FMP) && defined(SYSCFG_PMC_I2C4_FMP)
|
||||
#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6) == I2C_FASTMODEPLUS_PB6) || \
|
||||
(((__CONFIG__) & I2C_FASTMODEPLUS_PB7) == I2C_FASTMODEPLUS_PB7) || \
|
||||
(((__CONFIG__) & I2C_FASTMODEPLUS_PB8) == I2C_FASTMODEPLUS_PB8) || \
|
||||
(((__CONFIG__) & I2C_FASTMODEPLUS_PB9) == I2C_FASTMODEPLUS_PB9) || \
|
||||
(((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || \
|
||||
(((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2) || \
|
||||
(((__CONFIG__) & I2C_FASTMODEPLUS_I2C3) == I2C_FASTMODEPLUS_I2C3) || \
|
||||
(((__CONFIG__) & I2C_FASTMODEPLUS_I2C4) == I2C_FASTMODEPLUS_I2C4))
|
||||
#elif defined(SYSCFG_PMC_I2C1_FMP) && defined(SYSCFG_PMC_I2C2_FMP) && defined(SYSCFG_PMC_I2C3_FMP)
|
||||
#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6) == I2C_FASTMODEPLUS_PB6) || \
|
||||
(((__CONFIG__) & I2C_FASTMODEPLUS_PB7) == I2C_FASTMODEPLUS_PB7) || \
|
||||
(((__CONFIG__) & I2C_FASTMODEPLUS_PB8) == I2C_FASTMODEPLUS_PB8) || \
|
||||
(((__CONFIG__) & I2C_FASTMODEPLUS_PB9) == I2C_FASTMODEPLUS_PB9) || \
|
||||
(((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || \
|
||||
(((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2) || \
|
||||
(((__CONFIG__) & I2C_FASTMODEPLUS_I2C3) == I2C_FASTMODEPLUS_I2C3))
|
||||
#elif defined(SYSCFG_PMC_I2C1_FMP) && defined(SYSCFG_PMC_I2C2_FMP)
|
||||
#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6) == I2C_FASTMODEPLUS_PB6) || \
|
||||
(((__CONFIG__) & I2C_FASTMODEPLUS_PB7) == I2C_FASTMODEPLUS_PB7) || \
|
||||
(((__CONFIG__) & I2C_FASTMODEPLUS_PB8) == I2C_FASTMODEPLUS_PB8) || \
|
||||
(((__CONFIG__) & I2C_FASTMODEPLUS_PB9) == I2C_FASTMODEPLUS_PB9) || \
|
||||
(((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || \
|
||||
(((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2))
|
||||
#elif defined(SYSCFG_PMC_I2C1_FMP)
|
||||
#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6) == I2C_FASTMODEPLUS_PB6) || \
|
||||
(((__CONFIG__) & I2C_FASTMODEPLUS_PB7) == I2C_FASTMODEPLUS_PB7) || \
|
||||
(((__CONFIG__) & I2C_FASTMODEPLUS_PB8) == I2C_FASTMODEPLUS_PB8) || \
|
||||
(((__CONFIG__) & I2C_FASTMODEPLUS_PB9) == I2C_FASTMODEPLUS_PB9) || \
|
||||
(((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1))
|
||||
#endif /* SYSCFG_PMC_I2C1_FMP && SYSCFG_PMC_I2C2_FMP && SYSCFG_PMC_I2C3_FMP && SYSCFG_PMC_I2C4_FMP */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private Functions ---------------------------------------------------------*/
|
||||
/** @defgroup I2CEx_Private_Functions I2C Extended Private Functions
|
||||
* @{
|
||||
*/
|
||||
/* Private functions are defined in stm32f7xx_hal_i2c_ex.c file */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F7xx_HAL_I2C_EX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,483 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_hal_i2s.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.2
|
||||
* @date 14-April-2017
|
||||
* @brief Header file of I2S HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F7xx_HAL_I2S_H
|
||||
#define __STM32F7xx_HAL_I2S_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup I2S
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup I2S_Exported_Types I2S Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief I2S Init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Mode; /*!< Specifies the I2S operating mode.
|
||||
This parameter can be a value of @ref I2S_Mode */
|
||||
|
||||
uint32_t Standard; /*!< Specifies the standard used for the I2S communication.
|
||||
This parameter can be a value of @ref I2S_Standard */
|
||||
|
||||
uint32_t DataFormat; /*!< Specifies the data format for the I2S communication.
|
||||
This parameter can be a value of @ref I2S_Data_Format */
|
||||
|
||||
uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
|
||||
This parameter can be a value of @ref I2S_MCLK_Output */
|
||||
|
||||
uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
|
||||
This parameter can be a value of @ref I2S_Audio_Frequency */
|
||||
|
||||
uint32_t CPOL; /*!< Specifies the idle state of the I2S clock.
|
||||
This parameter can be a value of @ref I2S_Clock_Polarity */
|
||||
|
||||
uint32_t ClockSource; /*!< Specifies the I2S Clock Source.
|
||||
This parameter can be a value of @ref I2S_Clock_Source */
|
||||
}I2S_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL State structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_I2S_STATE_RESET = 0x00U, /*!< I2S not yet initialized or disabled */
|
||||
HAL_I2S_STATE_READY = 0x01U, /*!< I2S initialized and ready for use */
|
||||
HAL_I2S_STATE_BUSY = 0x02U, /*!< I2S internal process is ongoing */
|
||||
HAL_I2S_STATE_BUSY_TX = 0x03U, /*!< Data Transmission process is ongoing */
|
||||
HAL_I2S_STATE_BUSY_RX = 0x04U, /*!< Data Reception process is ongoing */
|
||||
HAL_I2S_STATE_BUSY_TX_RX = 0x05U, /*!< Data Transmission and Reception process is ongoing */
|
||||
HAL_I2S_STATE_TIMEOUT = 0x06U, /*!< I2S timeout state */
|
||||
HAL_I2S_STATE_ERROR = 0x07U /*!< I2S error state */
|
||||
|
||||
}HAL_I2S_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief I2S handle Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
SPI_TypeDef *Instance; /* I2S registers base address */
|
||||
|
||||
I2S_InitTypeDef Init; /* I2S communication parameters */
|
||||
|
||||
uint16_t *pTxBuffPtr; /* Pointer to I2S Tx transfer buffer */
|
||||
|
||||
__IO uint16_t TxXferSize; /* I2S Tx transfer size */
|
||||
|
||||
__IO uint16_t TxXferCount; /* I2S Tx transfer Counter */
|
||||
|
||||
uint16_t *pRxBuffPtr; /* Pointer to I2S Rx transfer buffer */
|
||||
|
||||
__IO uint16_t RxXferSize; /* I2S Rx transfer size */
|
||||
|
||||
__IO uint16_t RxXferCount; /* I2S Rx transfer counter
|
||||
(This field is initialized at the
|
||||
same value as transfer size at the
|
||||
beginning of the transfer and
|
||||
decremented when a sample is received.
|
||||
NbSamplesReceived = RxBufferSize-RxBufferCount) */
|
||||
|
||||
DMA_HandleTypeDef *hdmatx; /* I2S Tx DMA handle parameters */
|
||||
|
||||
DMA_HandleTypeDef *hdmarx; /* I2S Rx DMA handle parameters */
|
||||
|
||||
__IO HAL_LockTypeDef Lock; /* I2S locking object */
|
||||
|
||||
__IO HAL_I2S_StateTypeDef State; /* I2S communication state */
|
||||
|
||||
__IO uint32_t ErrorCode; /* I2S Error code */
|
||||
|
||||
}I2S_HandleTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup I2S_Exported_Constants I2S Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_Error_Defintion I2S_Error_Defintion
|
||||
*@brief I2S Error Code
|
||||
* @{
|
||||
*/
|
||||
#define HAL_I2S_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
|
||||
#define HAL_I2S_ERROR_TIMEOUT ((uint32_t)0x00000001U) /*!< Timeout error */
|
||||
#define HAL_I2S_ERROR_OVR ((uint32_t)0x00000002U) /*!< OVR error */
|
||||
#define HAL_I2S_ERROR_UDR ((uint32_t)0x00000004U) /*!< UDR error */
|
||||
#define HAL_I2S_ERROR_DMA ((uint32_t)0x00000008U) /*!< DMA transfer error */
|
||||
#define HAL_I2S_ERROR_UNKNOW ((uint32_t)0x00000010U) /*!< Unknow Error error */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/** @defgroup I2S_Clock_Source I2S Clock Source
|
||||
* @{
|
||||
*/
|
||||
#define I2S_CLOCK_EXTERNAL ((uint32_t)0x00000001U)
|
||||
#define I2S_CLOCK_PLL ((uint32_t)0x00000002U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_Mode I2S Mode
|
||||
* @{
|
||||
*/
|
||||
#define I2S_MODE_SLAVE_TX ((uint32_t)0x00000000U)
|
||||
#define I2S_MODE_SLAVE_RX ((uint32_t)0x00000100U)
|
||||
#define I2S_MODE_MASTER_TX ((uint32_t)0x00000200U)
|
||||
#define I2S_MODE_MASTER_RX ((uint32_t)0x00000300U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_Standard I2S Standard
|
||||
* @{
|
||||
*/
|
||||
#define I2S_STANDARD_PHILIPS ((uint32_t)0x00000000U)
|
||||
#define I2S_STANDARD_MSB ((uint32_t)0x00000010U)
|
||||
#define I2S_STANDARD_LSB ((uint32_t)0x00000020U)
|
||||
#define I2S_STANDARD_PCM_SHORT ((uint32_t)0x00000030U)
|
||||
#define I2S_STANDARD_PCM_LONG ((uint32_t)0x000000B0U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_Data_Format I2S Data Format
|
||||
* @{
|
||||
*/
|
||||
#define I2S_DATAFORMAT_16B ((uint32_t)0x00000000U)
|
||||
#define I2S_DATAFORMAT_16B_EXTENDED ((uint32_t)0x00000001U)
|
||||
#define I2S_DATAFORMAT_24B ((uint32_t)0x00000003U)
|
||||
#define I2S_DATAFORMAT_32B ((uint32_t)0x00000005U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_MCLK_Output I2S Mclk Output
|
||||
* @{
|
||||
*/
|
||||
#define I2S_MCLKOUTPUT_ENABLE ((uint32_t)SPI_I2SPR_MCKOE)
|
||||
#define I2S_MCLKOUTPUT_DISABLE ((uint32_t)0x00000000U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_Audio_Frequency I2S Audio Frequency
|
||||
* @{
|
||||
*/
|
||||
#define I2S_AUDIOFREQ_192K ((uint32_t)192000U)
|
||||
#define I2S_AUDIOFREQ_96K ((uint32_t)96000U)
|
||||
#define I2S_AUDIOFREQ_48K ((uint32_t)48000U)
|
||||
#define I2S_AUDIOFREQ_44K ((uint32_t)44100U)
|
||||
#define I2S_AUDIOFREQ_32K ((uint32_t)32000U)
|
||||
#define I2S_AUDIOFREQ_22K ((uint32_t)22050U)
|
||||
#define I2S_AUDIOFREQ_16K ((uint32_t)16000U)
|
||||
#define I2S_AUDIOFREQ_11K ((uint32_t)11025U)
|
||||
#define I2S_AUDIOFREQ_8K ((uint32_t)8000U)
|
||||
#define I2S_AUDIOFREQ_DEFAULT ((uint32_t)2U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup I2S_Clock_Polarity I2S Clock Polarity
|
||||
* @{
|
||||
*/
|
||||
#define I2S_CPOL_LOW ((uint32_t)0x00000000U)
|
||||
#define I2S_CPOL_HIGH ((uint32_t)SPI_I2SCFGR_CKPOL)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_Interrupts_Definition I2S Interrupts Definition
|
||||
* @{
|
||||
*/
|
||||
#define I2S_IT_TXE SPI_CR2_TXEIE
|
||||
#define I2S_IT_RXNE SPI_CR2_RXNEIE
|
||||
#define I2S_IT_ERR SPI_CR2_ERRIE
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_Flags_Definition I2S Flags Definition
|
||||
* @{
|
||||
*/
|
||||
#define I2S_FLAG_TXE SPI_SR_TXE
|
||||
#define I2S_FLAG_RXNE SPI_SR_RXNE
|
||||
|
||||
#define I2S_FLAG_UDR SPI_SR_UDR
|
||||
#define I2S_FLAG_OVR SPI_SR_OVR
|
||||
#define I2S_FLAG_FRE SPI_SR_FRE
|
||||
|
||||
#define I2S_FLAG_CHSIDE SPI_SR_CHSIDE
|
||||
#define I2S_FLAG_BSY SPI_SR_BSY
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup I2S_Exported_Macros I2S Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset I2S handle state
|
||||
* @param __HANDLE__: specifies the I2S handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET)
|
||||
|
||||
/** @brief Enable or disable the specified SPI peripheral (in I2S mode).
|
||||
* @param __HANDLE__: specifies the I2S Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2S_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->I2SCFGR |= SPI_I2SCFGR_I2SE)
|
||||
#define __HAL_I2S_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->I2SCFGR &= ~SPI_I2SCFGR_I2SE)
|
||||
|
||||
/** @brief Enable or disable the specified I2S interrupts.
|
||||
* @param __HANDLE__: specifies the I2S Handle.
|
||||
* @param __INTERRUPT__: specifies the interrupt source to enable or disable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg I2S_IT_TXE: Tx buffer empty interrupt enable
|
||||
* @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
|
||||
* @arg I2S_IT_ERR: Error interrupt enable
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
|
||||
#define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= ~(__INTERRUPT__))
|
||||
|
||||
/** @brief Checks if the specified I2S interrupt source is enabled or disabled.
|
||||
* @param __HANDLE__: specifies the I2S Handle.
|
||||
* This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral.
|
||||
* @param __INTERRUPT__: specifies the I2S interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg I2S_IT_TXE: Tx buffer empty interrupt enable
|
||||
* @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
|
||||
* @arg I2S_IT_ERR: Error interrupt enable
|
||||
* @retval The new state of __IT__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
||||
|
||||
/** @brief Checks whether the specified I2S flag is set or not.
|
||||
* @param __HANDLE__: specifies the I2S Handle.
|
||||
* @param __FLAG__: specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg I2S_FLAG_RXNE: Receive buffer not empty flag
|
||||
* @arg I2S_FLAG_TXE: Transmit buffer empty flag
|
||||
* @arg I2S_FLAG_UDR: Underrun flag
|
||||
* @arg I2S_FLAG_OVR: Overrun flag
|
||||
* @arg I2S_FLAG_FRE: Frame error flag
|
||||
* @arg I2S_FLAG_CHSIDE: Channel Side flag
|
||||
* @arg I2S_FLAG_BSY: Busy flag
|
||||
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
|
||||
|
||||
/** @brief Clears the I2S OVR pending flag.
|
||||
* @param __HANDLE__: specifies the I2S Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) \
|
||||
do{ \
|
||||
__IO uint32_t tmpreg; \
|
||||
tmpreg = (__HANDLE__)->Instance->DR; \
|
||||
tmpreg = (__HANDLE__)->Instance->SR; \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
|
||||
/** @brief Clears the I2S UDR pending flag.
|
||||
* @param __HANDLE__: specifies the I2S Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__) \
|
||||
do{ \
|
||||
__IO uint32_t tmpreg; \
|
||||
tmpreg = (__HANDLE__)->Instance->SR; \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup I2S_Exported_Functions I2S Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup I2S_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Initialization and de-initialization functions *****************************/
|
||||
HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s);
|
||||
HAL_StatusTypeDef HAL_I2S_DeInit (I2S_HandleTypeDef *hi2s);
|
||||
void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s);
|
||||
void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup I2S_Exported_Functions_Group2 Input and Output operation functions
|
||||
* @{
|
||||
*/
|
||||
/* I/O operation functions ***************************************************/
|
||||
/* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
|
||||
/* Non-Blocking mode: Interrupt */
|
||||
HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
|
||||
void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s);
|
||||
|
||||
/* Non-Blocking mode: DMA */
|
||||
HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
|
||||
|
||||
HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s);
|
||||
HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s);
|
||||
HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s);
|
||||
|
||||
/* Callbacks used in non blocking modes (Interrupt and DMA) *******************/
|
||||
void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
|
||||
void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s);
|
||||
void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
|
||||
void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s);
|
||||
void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup I2S_Exported_Functions_Group3 Peripheral State and Errors functions
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral Control and State functions ************************************/
|
||||
HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s);
|
||||
uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup I2S_Private_Constants I2S Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup I2S_Private_Macros I2S Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_I2S_CLOCKSOURCE(CLOCK) (((CLOCK) == I2S_CLOCK_EXTERNAL) || \
|
||||
((CLOCK) == I2S_CLOCK_PLL))
|
||||
|
||||
#define IS_I2S_MODE(MODE) (((MODE) == I2S_MODE_SLAVE_TX) || \
|
||||
((MODE) == I2S_MODE_SLAVE_RX) || \
|
||||
((MODE) == I2S_MODE_MASTER_TX)|| \
|
||||
((MODE) == I2S_MODE_MASTER_RX))
|
||||
|
||||
#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_STANDARD_PHILIPS) || \
|
||||
((STANDARD) == I2S_STANDARD_MSB) || \
|
||||
((STANDARD) == I2S_STANDARD_LSB) || \
|
||||
((STANDARD) == I2S_STANDARD_PCM_SHORT) || \
|
||||
((STANDARD) == I2S_STANDARD_PCM_LONG))
|
||||
|
||||
#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DATAFORMAT_16B) || \
|
||||
((FORMAT) == I2S_DATAFORMAT_16B_EXTENDED) || \
|
||||
((FORMAT) == I2S_DATAFORMAT_24B) || \
|
||||
((FORMAT) == I2S_DATAFORMAT_32B))
|
||||
|
||||
#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOUTPUT_ENABLE) || \
|
||||
((OUTPUT) == I2S_MCLKOUTPUT_DISABLE))
|
||||
|
||||
#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AUDIOFREQ_8K) && \
|
||||
((FREQ) <= I2S_AUDIOFREQ_192K)) || \
|
||||
((FREQ) == I2S_AUDIOFREQ_DEFAULT))
|
||||
|
||||
#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_LOW) || \
|
||||
((CPOL) == I2S_CPOL_HIGH))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* __STM32F7xx_HAL_I2S_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,760 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_hal_irda.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.2
|
||||
* @date 14-April-2017
|
||||
* @brief Header file of IRDA HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F7xx_HAL_IRDA_H
|
||||
#define __STM32F7xx_HAL_IRDA_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup IRDA
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup IRDA_Exported_Types IRDA Exported Types
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief IRDA Init Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t BaudRate; /*!< This member configures the IRDA communication baud rate.
|
||||
The baud rate register is computed using the following formula:
|
||||
Baud Rate Register = ((PCLKx) / ((hirda->Init.BaudRate))) */
|
||||
|
||||
uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
|
||||
This parameter can be a value of @ref IRDAEx_Word_Length */
|
||||
|
||||
uint32_t Parity; /*!< Specifies the parity mode.
|
||||
This parameter can be a value of @ref IRDA_Parity
|
||||
@note When parity is enabled, the computed parity is inserted
|
||||
at the MSB position of the transmitted data (9th bit when
|
||||
the word length is set to 9 data bits; 8th bit when the
|
||||
word length is set to 8 data bits). */
|
||||
|
||||
uint16_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
|
||||
This parameter can be a value of @ref IRDA_Transfer_Mode */
|
||||
|
||||
uint8_t Prescaler; /*!< Specifies the Prescaler value for dividing the UART/USART source clock
|
||||
to achieve low-power frequency.
|
||||
@note Prescaler value 0 is forbidden */
|
||||
|
||||
uint16_t PowerMode; /*!< Specifies the IRDA power mode.
|
||||
This parameter can be a value of @ref IRDA_Low_Power */
|
||||
}IRDA_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL IRDA State structures definition
|
||||
* @note HAL IRDA State value is a combination of 2 different substates: gState and RxState.
|
||||
* - gState contains IRDA state information related to global Handle management
|
||||
* and also information related to Tx operations.
|
||||
* gState value coding follow below described bitmap :
|
||||
* b7-b6 Error information
|
||||
* 00 : No Error
|
||||
* 01 : (Not Used)
|
||||
* 10 : Timeout
|
||||
* 11 : Error
|
||||
* b5 IP initilisation status
|
||||
* 0 : Reset (IP not initialized)
|
||||
* 1 : Init done (IP not initialized. HAL IRDA Init function already called)
|
||||
* b4-b3 (not used)
|
||||
* xx : Should be set to 00
|
||||
* b2 Intrinsic process state
|
||||
* 0 : Ready
|
||||
* 1 : Busy (IP busy with some configuration or internal operations)
|
||||
* b1 (not used)
|
||||
* x : Should be set to 0
|
||||
* b0 Tx state
|
||||
* 0 : Ready (no Tx operation ongoing)
|
||||
* 1 : Busy (Tx operation ongoing)
|
||||
* - RxState contains information related to Rx operations.
|
||||
* RxState value coding follow below described bitmap :
|
||||
* b7-b6 (not used)
|
||||
* xx : Should be set to 00
|
||||
* b5 IP initilisation status
|
||||
* 0 : Reset (IP not initialized)
|
||||
* 1 : Init done (IP not initialized)
|
||||
* b4-b2 (not used)
|
||||
* xxx : Should be set to 000
|
||||
* b1 Rx state
|
||||
* 0 : Ready (no Rx operation ongoing)
|
||||
* 1 : Busy (Rx operation ongoing)
|
||||
* b0 (not used)
|
||||
* x : Should be set to 0.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_IRDA_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized
|
||||
Value is allowed for gState and RxState */
|
||||
HAL_IRDA_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use
|
||||
Value is allowed for gState and RxState */
|
||||
HAL_IRDA_STATE_BUSY = 0x24U, /*!< An internal process is ongoing
|
||||
Value is allowed for gState only */
|
||||
HAL_IRDA_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing
|
||||
Value is allowed for gState only */
|
||||
HAL_IRDA_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing
|
||||
Value is allowed for RxState only */
|
||||
HAL_IRDA_STATE_BUSY_TX_RX = 0x23U, /*!< Data Transmission and Reception process is ongoing
|
||||
Not to be used for neither gState nor RxState.
|
||||
Value is result of combination (Or) between gState and RxState values */
|
||||
HAL_IRDA_STATE_TIMEOUT = 0xA0U, /*!< Timeout state
|
||||
Value is allowed for gState only */
|
||||
HAL_IRDA_STATE_ERROR = 0xE0U /*!< Error
|
||||
Value is allowed for gState only */
|
||||
}HAL_IRDA_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief IRDA clock sources definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
IRDA_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */
|
||||
IRDA_CLOCKSOURCE_PCLK2 = 0x01U, /*!< PCLK2 clock source */
|
||||
IRDA_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */
|
||||
IRDA_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */
|
||||
IRDA_CLOCKSOURCE_LSE = 0x08U, /*!< LSE clock source */
|
||||
IRDA_CLOCKSOURCE_UNDEFINED = 0x10 /*!< Undefined clock source */
|
||||
}IRDA_ClockSourceTypeDef;
|
||||
|
||||
/**
|
||||
* @brief IRDA handle Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
USART_TypeDef *Instance; /* IRDA registers base address */
|
||||
|
||||
IRDA_InitTypeDef Init; /* IRDA communication parameters */
|
||||
|
||||
uint8_t *pTxBuffPtr; /* Pointer to IRDA Tx transfer Buffer */
|
||||
|
||||
uint16_t TxXferSize; /* IRDA Tx Transfer size */
|
||||
|
||||
__IO uint16_t TxXferCount; /* IRDA Tx Transfer Counter */
|
||||
|
||||
uint8_t *pRxBuffPtr; /* Pointer to IRDA Rx transfer Buffer */
|
||||
|
||||
uint16_t RxXferSize; /* IRDA Rx Transfer size */
|
||||
|
||||
__IO uint16_t RxXferCount; /* IRDA Rx Transfer Counter */
|
||||
|
||||
uint16_t Mask; /* IRDA RX RDR register mask */
|
||||
|
||||
DMA_HandleTypeDef *hdmatx; /* IRDA Tx DMA Handle parameters */
|
||||
|
||||
DMA_HandleTypeDef *hdmarx; /* IRDA Rx DMA Handle parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /* Locking object */
|
||||
|
||||
__IO HAL_IRDA_StateTypeDef gState; /* IRDA state information related to global Handle management
|
||||
and also related to Tx operations.
|
||||
This parameter can be a value of @ref HAL_IRDA_StateTypeDef */
|
||||
|
||||
__IO HAL_IRDA_StateTypeDef RxState; /* IRDA state information related to Rx operations.
|
||||
This parameter can be a value of @ref HAL_IRDA_StateTypeDef */
|
||||
|
||||
__IO uint32_t ErrorCode; /* IRDA Error code */
|
||||
|
||||
}IRDA_HandleTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief IRDA Configuration enumeration values definition
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup IRDA_Exported_Constants IRDA Exported constants
|
||||
* @{
|
||||
*/
|
||||
/** @defgroup IRDA_Error_Code IRDA Error Code
|
||||
* @brief IRDA Error Code
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define HAL_IRDA_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
|
||||
#define HAL_IRDA_ERROR_PE ((uint32_t)0x00000001U) /*!< Parity error */
|
||||
#define HAL_IRDA_ERROR_NE ((uint32_t)0x00000002U) /*!< Noise error */
|
||||
#define HAL_IRDA_ERROR_FE ((uint32_t)0x00000004U) /*!< frame error */
|
||||
#define HAL_IRDA_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */
|
||||
#define HAL_IRDA_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_Parity IRDA Parity
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_PARITY_NONE ((uint32_t)0x0000U)
|
||||
#define IRDA_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
|
||||
#define IRDA_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup IRDA_Transfer_Mode IRDA Transfer Mode
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_MODE_RX ((uint32_t)USART_CR1_RE)
|
||||
#define IRDA_MODE_TX ((uint32_t)USART_CR1_TE)
|
||||
#define IRDA_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_Low_Power IRDA Low Power
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_POWERMODE_NORMAL ((uint32_t)0x0000U)
|
||||
#define IRDA_POWERMODE_LOWPOWER ((uint32_t)USART_CR3_IRLP)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_State IRDA State
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_STATE_DISABLE ((uint32_t)0x0000U)
|
||||
#define IRDA_STATE_ENABLE ((uint32_t)USART_CR1_UE)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_Mode IRDA Mode
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_MODE_DISABLE ((uint32_t)0x0000U)
|
||||
#define IRDA_MODE_ENABLE ((uint32_t)USART_CR3_IREN)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_One_Bit IRDA One Bit
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_ONE_BIT_SAMPLE_DISABLE ((uint32_t)0x00000000U)
|
||||
#define IRDA_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_DMA_Tx IRDA DMA Tx
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_DMA_TX_DISABLE ((uint32_t)0x00000000U)
|
||||
#define IRDA_DMA_TX_ENABLE ((uint32_t)USART_CR3_DMAT)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_DMA_Rx IRDA DMA Rx
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_DMA_RX_DISABLE ((uint32_t)0x0000U)
|
||||
#define IRDA_DMA_RX_ENABLE ((uint32_t)USART_CR3_DMAR)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_Flags IRDA Flags
|
||||
* Elements values convention: 0xXXXX
|
||||
* - 0xXXXX : Flag mask in the ISR register
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_FLAG_REACK ((uint32_t)0x00400000U)
|
||||
#define IRDA_FLAG_TEACK ((uint32_t)0x00200000U)
|
||||
#define IRDA_FLAG_BUSY ((uint32_t)0x00010000U)
|
||||
#define IRDA_FLAG_ABRF ((uint32_t)0x00008000U)
|
||||
#define IRDA_FLAG_ABRE ((uint32_t)0x00004000U)
|
||||
#define IRDA_FLAG_TXE ((uint32_t)0x00000080U)
|
||||
#define IRDA_FLAG_TC ((uint32_t)0x00000040U)
|
||||
#define IRDA_FLAG_RXNE ((uint32_t)0x00000020U)
|
||||
#define IRDA_FLAG_ORE ((uint32_t)0x00000008U)
|
||||
#define IRDA_FLAG_NE ((uint32_t)0x00000004U)
|
||||
#define IRDA_FLAG_FE ((uint32_t)0x00000002U)
|
||||
#define IRDA_FLAG_PE ((uint32_t)0x00000001U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_Interrupt_definition IRDA Interrupt definition
|
||||
* Elements values convention: 0000ZZZZ0XXYYYYYb
|
||||
* - YYYYY : Interrupt source position in the XX register (5bits)
|
||||
* - XX : Interrupt source register (2bits)
|
||||
* - 01: CR1 register
|
||||
* - 10: CR2 register
|
||||
* - 11: CR3 register
|
||||
* - ZZZZ : Flag position in the ISR register(4bits)
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_IT_PE ((uint16_t)0x0028U)
|
||||
#define IRDA_IT_TXE ((uint16_t)0x0727U)
|
||||
#define IRDA_IT_TC ((uint16_t)0x0626U)
|
||||
#define IRDA_IT_RXNE ((uint16_t)0x0525U)
|
||||
#define IRDA_IT_IDLE ((uint16_t)0x0424U)
|
||||
|
||||
|
||||
|
||||
/** Elements values convention: 000000000XXYYYYYb
|
||||
* - YYYYY : Interrupt source position in the XX register (5bits)
|
||||
* - XX : Interrupt source register (2bits)
|
||||
* - 01: CR1 register
|
||||
* - 10: CR2 register
|
||||
* - 11: CR3 register
|
||||
*/
|
||||
#define IRDA_IT_ERR ((uint16_t)0x0060U)
|
||||
|
||||
/** Elements values convention: 0000ZZZZ00000000b
|
||||
* - ZZZZ : Flag position in the ISR register(4bits)
|
||||
*/
|
||||
#define IRDA_IT_ORE ((uint16_t)0x0300U)
|
||||
#define IRDA_IT_NE ((uint16_t)0x0200U)
|
||||
#define IRDA_IT_FE ((uint16_t)0x0100U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_IT_CLEAR_Flags IRDA IT CLEAR Flags
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */
|
||||
#define IRDA_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */
|
||||
#define IRDA_CLEAR_NEF USART_ICR_NCF /*!< Noise detected Clear Flag */
|
||||
#define IRDA_CLEAR_OREF USART_ICR_ORECF /*!< OverRun Error Clear Flag */
|
||||
#define IRDA_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/** @defgroup IRDA_Request_Parameters IRDA Request Parameters
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_AUTOBAUD_REQUEST ((uint16_t)USART_RQR_ABRRQ) /*!< Auto-Baud Rate Request */
|
||||
#define IRDA_RXDATA_FLUSH_REQUEST ((uint16_t)USART_RQR_RXFRQ) /*!< Receive Data flush Request */
|
||||
#define IRDA_TXDATA_FLUSH_REQUEST ((uint16_t)USART_RQR_TXFRQ) /*!< Transmit data flush Request */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup IRDA_Exported_Macros IRDA Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset IRDA handle state
|
||||
* @param __HANDLE__: specifies the IRDA Handle.
|
||||
* The Handle Instance which can be USART1 or USART2.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_IRDA_STATE_RESET)
|
||||
|
||||
/** @brief Flush the IRDA DR register.
|
||||
* @param __HANDLE__: specifies the IRDA Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_FLUSH_DRREGISTER(__HANDLE__) \
|
||||
do{ \
|
||||
SET_BIT((__HANDLE__)->Instance->RQR, IRDA_RXDATA_FLUSH_REQUEST); \
|
||||
SET_BIT((__HANDLE__)->Instance->RQR, IRDA_TXDATA_FLUSH_REQUEST); \
|
||||
} while(0)
|
||||
|
||||
/** @brief Clear the specified IRDA pending flag.
|
||||
* @param __HANDLE__: specifies the IRDA Handle.
|
||||
* @param __FLAG__: specifies the flag to check.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg @ref IRDA_CLEAR_PEF
|
||||
* @arg @ref IRDA_CLEAR_FEF
|
||||
* @arg @ref IRDA_CLEAR_NEF
|
||||
* @arg @ref IRDA_CLEAR_OREF
|
||||
* @arg @ref IRDA_CLEAR_TCF
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
|
||||
|
||||
/** @brief Clear the IRDA PE pending flag.
|
||||
* @param __HANDLE__: specifies the IRDA Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_PEF)
|
||||
|
||||
|
||||
/** @brief Clear the IRDA FE pending flag.
|
||||
* @param __HANDLE__: specifies the IRDA Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_CLEAR_FEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_FEF)
|
||||
|
||||
/** @brief Clear the IRDA NE pending flag.
|
||||
* @param __HANDLE__: specifies the IRDA Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_CLEAR_NEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_NEF)
|
||||
|
||||
/** @brief Clear the IRDA ORE pending flag.
|
||||
* @param __HANDLE__: specifies the IRDA Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_CLEAR_OREFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_OREF)
|
||||
|
||||
/** @brief Clear the IRDA IDLE pending flag.
|
||||
* @param __HANDLE__: specifies the IRDA Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_CLEAR_IDLEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_IDLEF)
|
||||
|
||||
/** @brief Check whether the specified IRDA flag is set or not.
|
||||
* @param __HANDLE__: specifies the IRDA Handle.
|
||||
* The Handle Instance which can be USART1 or USART2.
|
||||
* UART peripheral
|
||||
* @param __FLAG__: specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg IRDA_FLAG_REACK: Receive enable acknowledge flag
|
||||
* @arg IRDA_FLAG_TEACK: Transmit enable acknowledge flag
|
||||
* @arg IRDA_FLAG_BUSY: Busy flag
|
||||
* @arg IRDA_FLAG_ABRF: Auto Baud rate detection flag
|
||||
* @arg IRDA_FLAG_ABRE: Auto Baud rate detection error flag
|
||||
* @arg IRDA_FLAG_TXE: Transmit data register empty flag
|
||||
* @arg IRDA_FLAG_TC: Transmission Complete flag
|
||||
* @arg IRDA_FLAG_RXNE: Receive data register not empty flag
|
||||
* @arg IRDA_FLAG_IDLE: Idle Line detection flag
|
||||
* @arg IRDA_FLAG_ORE: OverRun Error flag
|
||||
* @arg IRDA_FLAG_NE: Noise Error flag
|
||||
* @arg IRDA_FLAG_FE: Framing Error flag
|
||||
* @arg IRDA_FLAG_PE: Parity Error flag
|
||||
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_IRDA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
|
||||
|
||||
/** @brief Enable the specified IRDA interrupt.
|
||||
* @param __HANDLE__: specifies the IRDA Handle.
|
||||
* The Handle Instance which can be USART1 or USART2.
|
||||
* UART peripheral
|
||||
* @param __INTERRUPT__: specifies the IRDA interrupt source to enable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg IRDA_IT_TXE: Transmit Data Register empty interrupt
|
||||
* @arg IRDA_IT_TC: Transmission complete interrupt
|
||||
* @arg IRDA_IT_RXNE: Receive Data register not empty interrupt
|
||||
* @arg IRDA_IT_IDLE: Idle line detection interrupt
|
||||
* @arg IRDA_IT_PE: Parity Error interrupt
|
||||
* @arg IRDA_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5) == 1)? ((__HANDLE__)->Instance->CR1 |= (1 << ((__INTERRUPT__) & IRDA_IT_MASK))): \
|
||||
((((uint8_t)(__INTERRUPT__)) >> 5) == 2)? ((__HANDLE__)->Instance->CR2 |= (1 << ((__INTERRUPT__) & IRDA_IT_MASK))): \
|
||||
((__HANDLE__)->Instance->CR3 |= (1 << ((__INTERRUPT__) & IRDA_IT_MASK))))
|
||||
|
||||
/** @brief Disable the specified IRDA interrupt.
|
||||
* @param __HANDLE__: specifies the IRDA Handle.
|
||||
* The Handle Instance which can be USART1 or USART2.
|
||||
* @param __INTERRUPT__: specifies the IRDA interrupt source to disable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg IRDA_IT_TXE: Transmit Data Register empty interrupt
|
||||
* @arg IRDA_IT_TC: Transmission complete interrupt
|
||||
* @arg IRDA_IT_RXNE: Receive Data register not empty interrupt
|
||||
* @arg IRDA_IT_IDLE: Idle line detection interrupt
|
||||
* @arg IRDA_IT_PE: Parity Error interrupt
|
||||
* @arg IRDA_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1 << ((__INTERRUPT__) & IRDA_IT_MASK))): \
|
||||
((((uint8_t)(__INTERRUPT__)) >> 5) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1 << ((__INTERRUPT__) & IRDA_IT_MASK))): \
|
||||
((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1 << ((__INTERRUPT__) & IRDA_IT_MASK))))
|
||||
|
||||
/** @brief Check whether the specified IRDA interrupt has occurred or not.
|
||||
* @param __HANDLE__: specifies the IRDA Handle.
|
||||
* The Handle Instance which can be USART1 or USART2.
|
||||
* @param __IT__: specifies the IRDA interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg IRDA_IT_TXE: Transmit Data Register empty interrupt
|
||||
* @arg IRDA_IT_TC: Transmission complete interrupt
|
||||
* @arg IRDA_IT_RXNE: Receive Data register not empty interrupt
|
||||
* @arg IRDA_IT_IDLE: Idle line detection interrupt
|
||||
* @arg IRDA_IT_ORE: OverRun Error interrupt
|
||||
* @arg IRDA_IT_NE: Noise Error interrupt
|
||||
* @arg IRDA_IT_FE: Framing Error interrupt
|
||||
* @arg IRDA_IT_PE: Parity Error interrupt
|
||||
* @retval The new state of __IT__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_IRDA_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08)))
|
||||
|
||||
/** @brief Check whether the specified IRDA interrupt source is enabled.
|
||||
* @param __HANDLE__: specifies the IRDA Handle.
|
||||
* The Handle Instance which can be USART1 or USART2.
|
||||
* @param __IT__: specifies the IRDA interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg IRDA_IT_TXE: Transmit Data Register empty interrupt
|
||||
* @arg IRDA_IT_TC: Transmission complete interrupt
|
||||
* @arg IRDA_IT_RXNE: Receive Data register not empty interrupt
|
||||
* @arg IRDA_IT_IDLE: Idle line detection interrupt
|
||||
* @arg IRDA_IT_ORE: OverRun Error interrupt
|
||||
* @arg IRDA_IT_NE: Noise Error interrupt
|
||||
* @arg IRDA_IT_FE: Framing Error interrupt
|
||||
* @arg IRDA_IT_PE: Parity Error interrupt
|
||||
* @retval The new state of __IT__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5) == 1)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5) == 2)? \
|
||||
(__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << (((uint16_t)(__IT__)) & IRDA_IT_MASK)))
|
||||
|
||||
/** @brief Clear the specified IRDA ISR flag, in setting the proper ICR register flag.
|
||||
* @param __HANDLE__: specifies the IRDA Handle.
|
||||
* The Handle Instance which can be USART1 or USART2.
|
||||
* @param __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set
|
||||
* to clear the corresponding interrupt
|
||||
* This parameter can be one of the following values:
|
||||
* @arg IRDA_CLEAR_PEF: Parity Error Clear Flag
|
||||
* @arg IRDA_CLEAR_FEF: Framing Error Clear Flag
|
||||
* @arg IRDA_CLEAR_NEF: Noise detected Clear Flag
|
||||
* @arg IRDA_CLEAR_OREF: OverRun Error Clear Flag
|
||||
* @arg IRDA_CLEAR_TCF: Transmission Complete Clear Flag
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR |= (uint32_t)(__IT_CLEAR__))
|
||||
|
||||
/** @brief Set a specific IRDA request flag.
|
||||
* @param __HANDLE__: specifies the IRDA Handle.
|
||||
* The Handle Instance which can be USART1 or USART2.
|
||||
* @param __REQ__: specifies the request flag to set
|
||||
* This parameter can be one of the following values:
|
||||
* @arg IRDA_AUTOBAUD_REQUEST: Auto-Baud Rate Request
|
||||
* @arg IRDA_RXDATA_FLUSH_REQUEST: Receive Data flush Request
|
||||
* @arg IRDA_TXDATA_FLUSH_REQUEST: Transmit data flush Request
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
|
||||
|
||||
/** @brief Enable UART/USART associated to IRDA Handle
|
||||
* @param __HANDLE__: specifies the IRDA Handle.
|
||||
* The Handle Instance which can be USART1 or USART2.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
|
||||
|
||||
/** @brief Disable UART/USART associated to IRDA Handle
|
||||
* @param __HANDLE__: specifies the IRDA Handle.
|
||||
* The Handle Instance which can be USART1 or USART2.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include IRDA HAL Extension module */
|
||||
#include "stm32f7xx_hal_irda_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup IRDA_Exported_Functions IRDA Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup IRDA_Exported_Functions_Group1 IrDA Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Initialization and de-initialization functions ****************************/
|
||||
HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda);
|
||||
HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda);
|
||||
void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda);
|
||||
void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup IRDA_Exported_Functions_Group2 IO operation functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* IO operation functions *****************************************************/
|
||||
HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda);
|
||||
HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda);
|
||||
HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda);
|
||||
/* Transfer Abort functions */
|
||||
HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda);
|
||||
HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda);
|
||||
HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda);
|
||||
HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda);
|
||||
HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda);
|
||||
HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda);
|
||||
|
||||
void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda);
|
||||
void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda);
|
||||
void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda);
|
||||
void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
|
||||
void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
|
||||
void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda);
|
||||
void HAL_IRDA_AbortCpltCallback (IRDA_HandleTypeDef *hirda);
|
||||
void HAL_IRDA_AbortTransmitCpltCallback (IRDA_HandleTypeDef *hirda);
|
||||
void HAL_IRDA_AbortReceiveCpltCallback (IRDA_HandleTypeDef *hirda);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup IRDA_Exported_Functions_Group3 Peripheral Control functions
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State methods **************************************************/
|
||||
HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda);
|
||||
uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup IRDA_Private_Constants IRDA Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_Interruption_Mask IRDA Interruption Mask
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_IT_MASK ((uint16_t)0x001FU)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros --------------------------------------------------------*/
|
||||
/** @defgroup IRDA_Private_Macros IRDA Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Ensure that IRDA Baud rate is less or equal to maximum value
|
||||
* @param __BAUDRATE__: specifies the IRDA Baudrate set by the user.
|
||||
* @retval True or False
|
||||
*/
|
||||
#define IS_IRDA_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 115201)
|
||||
|
||||
/** @brief Ensure that IRDA prescaler value is strictly larger than 0
|
||||
* @param __PRESCALER__: specifies the IRDA prescaler value set by the user.
|
||||
* @retval True or False
|
||||
*/
|
||||
#define IS_IRDA_PRESCALER(__PRESCALER__) ((__PRESCALER__) > 0)
|
||||
|
||||
#define IS_IRDA_PARITY(__PARITY__) (((__PARITY__) == IRDA_PARITY_NONE) || \
|
||||
((__PARITY__) == IRDA_PARITY_EVEN) || \
|
||||
((__PARITY__) == IRDA_PARITY_ODD))
|
||||
|
||||
#define IS_IRDA_TX_RX_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(IRDA_MODE_TX_RX)))) == (uint32_t)0x00) && ((__MODE__) != (uint32_t)0x00U))
|
||||
|
||||
#define IS_IRDA_POWERMODE(__MODE__) (((__MODE__) == IRDA_POWERMODE_LOWPOWER) || \
|
||||
((__MODE__) == IRDA_POWERMODE_NORMAL))
|
||||
|
||||
#define IS_IRDA_STATE(__STATE__) (((__STATE__) == IRDA_STATE_DISABLE) || \
|
||||
((__STATE__) == IRDA_STATE_ENABLE))
|
||||
|
||||
#define IS_IRDA_MODE(__STATE__) (((__STATE__) == IRDA_MODE_DISABLE) || \
|
||||
((__STATE__) == IRDA_MODE_ENABLE))
|
||||
|
||||
#define IS_IRDA_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_DISABLE) || \
|
||||
((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_ENABLE))
|
||||
|
||||
#define IS_IRDA_DMA_TX(__DMATX__) (((__DMATX__) == IRDA_DMA_TX_DISABLE) || \
|
||||
((__DMATX__) == IRDA_DMA_TX_ENABLE))
|
||||
|
||||
#define IS_IRDA_DMA_RX(__DMARX__) (((__DMARX__) == IRDA_DMA_RX_DISABLE) || \
|
||||
((__DMARX__) == IRDA_DMA_RX_ENABLE))
|
||||
|
||||
#define IS_IRDA_REQUEST_PARAMETER(PARAM) (((PARAM) == IRDA_AUTOBAUD_REQUEST) || \
|
||||
((PARAM) == IRDA_SENDBREAK_REQUEST) || \
|
||||
((PARAM) == IRDA_MUTE_MODE_REQUEST) || \
|
||||
((PARAM) == IRDA_RXDATA_FLUSH_REQUEST) || \
|
||||
((PARAM) == IRDA_TXDATA_FLUSH_REQUEST))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup IRDA_Private_Functions IRDA Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F7xx_HAL_IRDA_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,239 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_hal_irda_ex.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.2
|
||||
* @date 14-April-2017
|
||||
* @brief Header file of IRDA HAL Extension module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F7xx_HAL_IRDA_EX_H
|
||||
#define __STM32F7xx_HAL_IRDA_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup IRDAEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup IRDAEx_Extended_Exported_Constants IRDAEx Extended Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup IRDAEx_Word_Length IRDAEx Word Length
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_WORDLENGTH_7B ((uint32_t)USART_CR1_M_1)
|
||||
#define IRDA_WORDLENGTH_8B ((uint32_t)0x00000000U)
|
||||
#define IRDA_WORDLENGTH_9B ((uint32_t)USART_CR1_M_0)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup IRDAEx_Private_Macros IRDAEx Private Macros
|
||||
* @{
|
||||
*/
|
||||
/** @brief Reports the IRDA clock source.
|
||||
* @param __HANDLE__: specifies the IRDA Handle
|
||||
* @param __CLOCKSOURCE__ : output variable
|
||||
* @retval IRDA clocking source, written in __CLOCKSOURCE__.
|
||||
*/
|
||||
#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
|
||||
do { \
|
||||
if((__HANDLE__)->Instance == USART1) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART1_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART1CLKSOURCE_PCLK2: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK2; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART2) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART2_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART2CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART3) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART3_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART3CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART3CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART3CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART3CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART6) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART6_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART6CLKSOURCE_PCLK2: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK2; \
|
||||
break; \
|
||||
case RCC_USART6CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART6CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART6CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
} while(0)
|
||||
|
||||
/** @brief Reports the mask to apply to retrieve the received data
|
||||
* according to the word length and to the parity bits activation.
|
||||
* @param __HANDLE__: specifies the IRDA Handle
|
||||
* @retval mask to apply to USART RDR register value.
|
||||
*/
|
||||
#define IRDA_MASK_COMPUTATION(__HANDLE__) \
|
||||
do { \
|
||||
if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_9B) \
|
||||
{ \
|
||||
if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x01FF ; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x00FF ; \
|
||||
} \
|
||||
} \
|
||||
else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_8B) \
|
||||
{ \
|
||||
if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x00FF ; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x007F ; \
|
||||
} \
|
||||
} \
|
||||
else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_7B) \
|
||||
{ \
|
||||
if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x007F ; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x003F ; \
|
||||
} \
|
||||
} \
|
||||
} while(0)
|
||||
|
||||
#define IS_IRDA_WORD_LENGTH(LENGTH) (((LENGTH) == IRDA_WORDLENGTH_7B) || \
|
||||
((LENGTH) == IRDA_WORDLENGTH_8B) || \
|
||||
((LENGTH) == IRDA_WORDLENGTH_9B))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F7xx_HAL_IRDA_EX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,257 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_hal_iwdg.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.2
|
||||
* @date 14-April-2017
|
||||
* @brief Header file of IWDG HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F7xx_HAL_IWDG_H
|
||||
#define __STM32F7xx_HAL_IWDG_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG IWDG
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup IWDG_Exported_Types IWDG Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief IWDG Init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Prescaler; /*!< Select the prescaler of the IWDG.
|
||||
This parameter can be a value of @ref IWDG_Prescaler */
|
||||
|
||||
uint32_t Reload; /*!< Specifies the IWDG down-counter reload value.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */
|
||||
|
||||
uint32_t Window; /*!< Specifies the window value to be compared to the down-counter.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */
|
||||
|
||||
} IWDG_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief IWDG Handle Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
IWDG_TypeDef *Instance; /*!< Register base address */
|
||||
|
||||
IWDG_InitTypeDef Init; /*!< IWDG required parameters */
|
||||
|
||||
}IWDG_HandleTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup IWDG_Exported_Constants IWDG Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_Prescaler IWDG Prescaler
|
||||
* @{
|
||||
*/
|
||||
#define IWDG_PRESCALER_4 0x00000000u /*!< IWDG prescaler set to 4 */
|
||||
#define IWDG_PRESCALER_8 IWDG_PR_PR_0 /*!< IWDG prescaler set to 8 */
|
||||
#define IWDG_PRESCALER_16 IWDG_PR_PR_1 /*!< IWDG prescaler set to 16 */
|
||||
#define IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 32 */
|
||||
#define IWDG_PRESCALER_64 IWDG_PR_PR_2 /*!< IWDG prescaler set to 64 */
|
||||
#define IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 128 */
|
||||
#define IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< IWDG prescaler set to 256 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_Window_option IWDG Window option
|
||||
* @{
|
||||
*/
|
||||
#define IWDG_WINDOW_DISABLE IWDG_WINR_WIN
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup IWDG_Exported_Macros IWDG Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable the IWDG peripheral.
|
||||
* @param __HANDLE__: IWDG handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE)
|
||||
|
||||
/**
|
||||
* @brief Reload IWDG counter with value defined in the reload register
|
||||
* (write access to IWDG_PR, IWDG_RLR & IWDG_WINR registers disabled).
|
||||
* @param __HANDLE__: IWDG handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup IWDG_Exported_Functions IWDG Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_Exported_Functions_Group1 Initialization and Start functions
|
||||
* @{
|
||||
*/
|
||||
/* Initialization/Start functions ********************************************/
|
||||
HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_Exported_Functions_Group2 IO operation functions
|
||||
* @{
|
||||
*/
|
||||
/* I/O operation functions ****************************************************/
|
||||
HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup IWDG_Private_Constants IWDG Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief IWDG Key Register BitMask
|
||||
*/
|
||||
#define IWDG_KEY_RELOAD 0x0000AAAAu /*!< IWDG Reload Counter Enable */
|
||||
#define IWDG_KEY_ENABLE 0x0000CCCCu /*!< IWDG Peripheral Enable */
|
||||
#define IWDG_KEY_WRITE_ACCESS_ENABLE 0x00005555u /*!< IWDG KR Write Access Enable */
|
||||
#define IWDG_KEY_WRITE_ACCESS_DISABLE 0x00000000u /*!< IWDG KR Write Access Disable */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup IWDG_Private_Macros IWDG Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
|
||||
* @param __HANDLE__: IWDG handle
|
||||
* @retval None
|
||||
*/
|
||||
#define IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE)
|
||||
|
||||
/**
|
||||
* @brief Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
|
||||
* @param __HANDLE__: IWDG handle
|
||||
* @retval None
|
||||
*/
|
||||
#define IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE)
|
||||
|
||||
/**
|
||||
* @brief Check IWDG prescaler value.
|
||||
* @param __PRESCALER__: IWDG prescaler value
|
||||
* @retval None
|
||||
*/
|
||||
#define IS_IWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == IWDG_PRESCALER_4) || \
|
||||
((__PRESCALER__) == IWDG_PRESCALER_8) || \
|
||||
((__PRESCALER__) == IWDG_PRESCALER_16) || \
|
||||
((__PRESCALER__) == IWDG_PRESCALER_32) || \
|
||||
((__PRESCALER__) == IWDG_PRESCALER_64) || \
|
||||
((__PRESCALER__) == IWDG_PRESCALER_128)|| \
|
||||
((__PRESCALER__) == IWDG_PRESCALER_256))
|
||||
|
||||
/**
|
||||
* @brief Check IWDG reload value.
|
||||
* @param __RELOAD__: IWDG reload value
|
||||
* @retval None
|
||||
*/
|
||||
#define IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= IWDG_RLR_RL)
|
||||
|
||||
/**
|
||||
* @brief Check IWDG window value.
|
||||
* @param __WINDOW__: IWDG window value
|
||||
* @retval None
|
||||
*/
|
||||
#define IS_IWDG_WINDOW(__WINDOW__) ((__WINDOW__) <= IWDG_WINR_WIN)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F7xx_HAL_IWDG_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,581 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_hal_jpeg.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.2
|
||||
* @date 14-April-2017
|
||||
* @brief Header file of JPEG HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F7xx_HAL_JPEG_H
|
||||
#define __STM32F7xx_HAL_JPEG_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup JPEG
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup JPEG_Exported_Types JPEG Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup JPEG_Configuration_Structure_definition JPEG Configuration for encoding Structure definition
|
||||
* @brief JPEG encoding configuration Structure definition
|
||||
* @{
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t ColorSpace; /*!< Image Color space : gray-scale, YCBCR, RGB or CMYK
|
||||
This parameter can be a value of @ref JPEG_ColorSpace_Type */
|
||||
|
||||
uint8_t ChromaSubsampling; /*!< Chroma Subsampling in case of YCBCR or CMYK color space, 0-> 4:4:4 , 1-> 4:2:2, 2 -> 4:1:1, 3 -> 4:2:0
|
||||
This parameter can be a value of @ref JPEG_ChromaSubsampling_Type */
|
||||
|
||||
uint32_t ImageHeight; /*!< Image height : number of lines */
|
||||
|
||||
uint32_t ImageWidth; /*!< Image width : number of pixels per line */
|
||||
|
||||
uint8_t ImageQuality; /*!< Quality of the JPEG encoding : from 1 to 100 */
|
||||
|
||||
}JPEG_ConfTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_JPEG_state_structure_definition HAL JPEG state structure definition
|
||||
* @brief HAL JPEG State structure definition
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_JPEG_STATE_RESET = 0x00U, /*!< JPEG not yet initialized or disabled */
|
||||
HAL_JPEG_STATE_READY = 0x01U, /*!< JPEG initialized and ready for use */
|
||||
HAL_JPEG_STATE_BUSY = 0x02U, /*!< JPEG internal processing is ongoing */
|
||||
HAL_JPEG_STATE_BUSY_ENCODING = 0x03U, /*!< JPEG encoding processing is ongoing */
|
||||
HAL_JPEG_STATE_BUSY_DECODING = 0x04U, /*!< JPEG decoding processing is ongoing */
|
||||
HAL_JPEG_STATE_TIMEOUT = 0x05U, /*!< JPEG timeout state */
|
||||
HAL_JPEG_STATE_ERROR = 0x06U /*!< JPEG error state */
|
||||
}HAL_JPEG_STATETypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup JPEG_handle_Structure_definition JPEG handle Structure definition
|
||||
* @brief JPEG handle Structure definition
|
||||
* @{
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
JPEG_TypeDef *Instance; /*!< JPEG peripheral register base address */
|
||||
|
||||
JPEG_ConfTypeDef Conf; /*!< Current JPEG encoding/decoding parameters */
|
||||
|
||||
uint8_t *pJpegInBuffPtr; /*!< Pointer to JPEG processing (encoding, decoding,...) input buffer */
|
||||
|
||||
uint8_t *pJpegOutBuffPtr; /*!< Pointer to JPEG processing (encoding, decoding,...) output buffer */
|
||||
|
||||
__IO uint32_t JpegInCount; /*!< Internal Counter of input data */
|
||||
|
||||
__IO uint32_t JpegOutCount; /*!< Internal Counter of output data */
|
||||
|
||||
uint32_t InDataLength; /*!< Input Buffer Length in Bytes */
|
||||
|
||||
uint32_t OutDataLength; /*!< Output Buffer Length in Bytes */
|
||||
|
||||
DMA_HandleTypeDef *hdmain; /*!< JPEG In DMA handle parameters */
|
||||
|
||||
DMA_HandleTypeDef *hdmaout; /*!< JPEG Out DMA handle parameters */
|
||||
|
||||
uint8_t CustomQuanTable; /*!< If set to 1 specify that user customized quantization tables are used */
|
||||
|
||||
uint8_t *QuantTable0; /*!< Basic Quantization Table for component 0 */
|
||||
|
||||
uint8_t *QuantTable1; /*!< Basic Quantization Table for component 1 */
|
||||
|
||||
uint8_t *QuantTable2; /*!< Basic Quantization Table for component 2 */
|
||||
|
||||
uint8_t *QuantTable3; /*!< Basic Quantization Table for component 3 */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< JPEG locking object */
|
||||
|
||||
__IO HAL_JPEG_STATETypeDef State; /*!< JPEG peripheral state */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< JPEG Error code */
|
||||
|
||||
__IO uint32_t Context; /*!< JPEG Internal context */
|
||||
|
||||
}JPEG_HandleTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup JPEG_Exported_Constants JPEG Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup JPEG_Error_Code_definition JPEG Error Code definition
|
||||
* @brief JPEG Error Code definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define HAL_JPEG_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
|
||||
#define HAL_JPEG_ERROR_HUFF_TABLE ((uint32_t)0x00000001U) /*!< HUffman Table programming error */
|
||||
#define HAL_JPEG_ERROR_QUANT_TABLE ((uint32_t)0x00000002U) /*!< Quantization Table programming error */
|
||||
#define HAL_JPEG_ERROR_DMA ((uint32_t)0x00000004U) /*!< DMA transfer error */
|
||||
#define HAL_JPEG_ERROR_TIMEOUT ((uint32_t)0x00000008U) /*!< Timeout error */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup JPEG_Quantization_Table_Size JPEG Quantization Table Size
|
||||
* @brief JPEG Quantization Table Size
|
||||
* @{
|
||||
*/
|
||||
#define JPEG_QUANT_TABLE_SIZE ((uint32_t)64U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup JPEG_ColorSpace_Type JPEG ColorSpace
|
||||
* @brief JPEG Color Space
|
||||
* @{
|
||||
*/
|
||||
#define JPEG_GRAYSCALE_COLORSPACE ((uint32_t)0x00000000U)
|
||||
#define JPEG_YCBCR_COLORSPACE JPEG_CONFR1_COLORSPACE_0
|
||||
#define JPEG_CMYK_COLORSPACE JPEG_CONFR1_COLORSPACE
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup JPEG_ChromaSubsampling_Type JPEG Chrominance Sampling
|
||||
* @brief JPEG Chrominance Sampling
|
||||
* @{
|
||||
*/
|
||||
#define JPEG_444_SUBSAMPLING ((uint32_t)0x00000000U) /*!< Chroma Subsampling 4:4:4 */
|
||||
#define JPEG_420_SUBSAMPLING ((uint32_t)0x00000001U) /*!< Chroma Subsampling 4:2:0 */
|
||||
#define JPEG_422_SUBSAMPLING ((uint32_t)0x00000002U) /*!< Chroma Subsampling 4:2:2 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup JPEG_ImageQuality JPEG Image Quality
|
||||
* @brief JPEG Min and Max Image Quality
|
||||
* @{
|
||||
*/
|
||||
#define JPEG_IMAGE_QUALITY_MIN ((uint32_t)1U) /*!< Minimum JPEG quality */
|
||||
#define JPEG_IMAGE_QUALITY_MAX ((uint32_t)100U) /*!< Maximum JPEG quality */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup JPEG_Interrupt_configuration_definition JPEG Interrupt configuration definition
|
||||
* @brief JPEG Interrupt definition
|
||||
* @{
|
||||
*/
|
||||
#define JPEG_IT_IFT ((uint32_t)JPEG_CR_IFTIE) /*!< Input FIFO Threshold Interrupt */
|
||||
#define JPEG_IT_IFNF ((uint32_t)JPEG_CR_IFNFIE) /*!< Input FIFO Not Full Interrupt */
|
||||
#define JPEG_IT_OFT ((uint32_t)JPEG_CR_OFTIE) /*!< Output FIFO Threshold Interrupt */
|
||||
#define JPEG_IT_OFNE ((uint32_t)JPEG_CR_OFTIE) /*!< Output FIFO Not Empty Interrupt */
|
||||
#define JPEG_IT_EOC ((uint32_t)JPEG_CR_EOCIE) /*!< End of Conversion Interrupt */
|
||||
#define JPEG_IT_HPD ((uint32_t)JPEG_CR_HPDIE) /*!< Header Parsing Done Interrupt */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup JPEG_Flag_definition JPEG Flag definition
|
||||
* @brief JPEG Flags definition
|
||||
* @{
|
||||
*/
|
||||
#define JPEG_FLAG_IFTF ((uint32_t)JPEG_SR_IFTF) /*!< Input FIFO is not full and is bellow its threshold flag */
|
||||
#define JPEG_FLAG_IFNFF ((uint32_t)JPEG_SR_IFNFF) /*!< Input FIFO Not Full Flag, a data can be written */
|
||||
#define JPEG_FLAG_OFTF ((uint32_t)JPEG_SR_OFTF) /*!< Output FIFO is not empty and has reach its threshold */
|
||||
#define JPEG_FLAG_OFNEF ((uint32_t)JPEG_SR_OFNEF) /*!< Output FIFO is not empty, a data is available */
|
||||
#define JPEG_FLAG_EOCF ((uint32_t)JPEG_SR_EOCF) /*!< JPEG Codec core has finished the encoding or the decoding process and than last data has been sent to the output FIFO */
|
||||
#define JPEG_FLAG_HPDF ((uint32_t)JPEG_SR_HPDF) /*!< JPEG Codec has finished the parsing of the headers and the internal registers have been updated */
|
||||
#define JPEG_FLAG_COF ((uint32_t)JPEG_SR_COF) /*!< JPEG Codec operation on going flag*/
|
||||
|
||||
#define JPEG_FLAG_ALL ((uint32_t)0x000000FEU) /*!< JPEG Codec All previous flag*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup JPEG_PROCESS_PAUSE_RESUME_definition JPEG Process Pause Resume definition
|
||||
* @brief JPEG process pause, resume definition
|
||||
* @{
|
||||
*/
|
||||
#define JPEG_PAUSE_RESUME_INPUT ((uint32_t)0x00000001U) /*!< Pause/Resume Input FIFO Xfer*/
|
||||
#define JPEG_PAUSE_RESUME_OUTPUT ((uint32_t)0x00000002U) /*!< Pause/Resume Output FIFO Xfer*/
|
||||
#define JPEG_PAUSE_RESUME_INPUT_OUTPUT ((uint32_t)0x00000003U) /*!< Pause/Resume Input and Output FIFO Xfer*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup JPEG_Exported_Macros JPEG Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset JPEG handle state
|
||||
* @param __HANDLE__: specifies the JPEG handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_JPEG_RESET_HANDLE_STATE(__HANDLE__) ( (__HANDLE__)->State = HAL_JPEG_STATE_RESET)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Enable the JPEG peripheral.
|
||||
* @param __HANDLE__: specifies the JPEG handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_JPEG_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= JPEG_CR_JCEN)
|
||||
|
||||
/**
|
||||
* @brief Disable the JPEG peripheral.
|
||||
* @param __HANDLE__: specifies the JPEG handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_JPEG_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~JPEG_CR_JCEN)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Check the specified JPEG status flag.
|
||||
* @param __HANDLE__: specifies the JPEG handle.
|
||||
* @param __FLAG__ : specifies the flag to check
|
||||
* This parameter can be one of the following values:
|
||||
* @arg JPEG_FLAG_IFTF : The input FIFO is not full and is bellow its threshold flag
|
||||
* @arg JPEG_FLAG_IFNFF : The input FIFO Not Full Flag, a data can be written
|
||||
* @arg JPEG_FLAG_OFTF : The output FIFO is not empty and has reach its threshold
|
||||
* @arg JPEG_FLAG_OFNEF : The output FIFO is not empty, a data is available
|
||||
* @arg JPEG_FLAG_EOCF : JPEG Codec core has finished the encoding or the decoding process
|
||||
* and than last data has been sent to the output FIFO
|
||||
* @arg JPEG_FLAG_HPDF : JPEG Codec has finished the parsing of the headers
|
||||
* and the internal registers have been updated
|
||||
* @arg JPEG_FLAG_COF : JPEG Codec operation on going flag
|
||||
*
|
||||
* @retval : __HAL_JPEG_GET_FLAG : returns The new state of __FLAG__ (TRUE or FALSE)
|
||||
*/
|
||||
|
||||
#define __HAL_JPEG_GET_FLAG(__HANDLE__,__FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)))
|
||||
|
||||
/**
|
||||
* @brief Clear the specified JPEG status flag.
|
||||
* @param __HANDLE__: specifies the JPEG handle.
|
||||
* @param __FLAG__ : specifies the flag to clear
|
||||
* This parameter can be one of the following values:
|
||||
* @arg JPEG_FLAG_EOCF : JPEG Codec core has finished the encoding or the decoding process
|
||||
* and than last data has been sent to the output FIFO
|
||||
* @arg JPEG_FLAG_HPDF : JPEG Codec has finished the parsing of the headers
|
||||
* @retval : None
|
||||
*/
|
||||
|
||||
#define __HAL_JPEG_CLEAR_FLAG(__HANDLE__,__FLAG__) (((__HANDLE__)->Instance->CFR |= ((__FLAG__) & (JPEG_FLAG_EOCF | JPEG_FLAG_HPDF))))
|
||||
|
||||
|
||||
/**
|
||||
* @brief Enable Interrupt.
|
||||
* @param __HANDLE__: specifies the JPEG handle.
|
||||
* @param __INTERRUPT__ : specifies the interrupt to enable
|
||||
* This parameter can be one of the following values:
|
||||
* @arg JPEG_IT_IFT : Input FIFO Threshold Interrupt
|
||||
* @arg JPEG_IT_IFNF : Input FIFO Not Full Interrupt
|
||||
* @arg JPEG_IT_OFT : Output FIFO Threshold Interrupt
|
||||
* @arg JPEG_IT_OFNE : Output FIFO Not empty Interrupt
|
||||
* @arg JPEG_IT_EOC : End of Conversion Interrupt
|
||||
* @arg JPEG_IT_HPD : Header Parsing Done Interrupt
|
||||
*
|
||||
* @retval : No retrun
|
||||
*/
|
||||
#define __HAL_JPEG_ENABLE_IT(__HANDLE__,__INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__) )
|
||||
|
||||
/**
|
||||
* @brief Disable Interrupt.
|
||||
* @param __HANDLE__: specifies the JPEG handle.
|
||||
* @param __INTERRUPT__ : specifies the interrupt to disable
|
||||
* This parameter can be one of the following values:
|
||||
* @arg JPEG_IT_IFT : Input FIFO Threshold Interrupt
|
||||
* @arg JPEG_IT_IFNF : Input FIFO Not Full Interrupt
|
||||
* @arg JPEG_IT_OFT : Output FIFO Threshold Interrupt
|
||||
* @arg JPEG_IT_OFNE : Output FIFO Not empty Interrupt
|
||||
* @arg JPEG_IT_EOC : End of Conversion Interrupt
|
||||
* @arg JPEG_IT_HPD : Header Parsing Done Interrupt
|
||||
*
|
||||
* @note : To disable an IT we must use MODIFY_REG macro to avoid writing "1" to the FIFO flush bits
|
||||
* located in the same IT enable register (CR register).
|
||||
* @retval : No retrun
|
||||
*/
|
||||
#define __HAL_JPEG_DISABLE_IT(__HANDLE__,__INTERRUPT__) MODIFY_REG((__HANDLE__)->Instance->CR, (__INTERRUPT__), 0)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Get Interrupt state.
|
||||
* @param __HANDLE__: specifies the JPEG handle.
|
||||
* @param __INTERRUPT__ : specifies the interrupt to check
|
||||
* This parameter can be one of the following values:
|
||||
* @arg JPEG_IT_IFT : Input FIFO Threshold Interrupt
|
||||
* @arg JPEG_IT_IFNF : Input FIFO Not Full Interrupt
|
||||
* @arg JPEG_IT_OFT : Output FIFO Threshold Interrupt
|
||||
* @arg JPEG_IT_OFNE : Output FIFO Not empty Interrupt
|
||||
* @arg JPEG_IT_EOC : End of Conversion Interrupt
|
||||
* @arg JPEG_IT_HPD : Header Parsing Done Interrupt
|
||||
*
|
||||
* @retval : returns The new state of __INTERRUPT__ (Enabled or disabled)
|
||||
*/
|
||||
#define __HAL_JPEG_GET_IT_SOURCE(__HANDLE__,__INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup JPEG_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup JPEG_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Initialization/de-initialization functions ********************************/
|
||||
HAL_StatusTypeDef HAL_JPEG_Init(JPEG_HandleTypeDef *hjpeg);
|
||||
HAL_StatusTypeDef HAL_JPEG_DeInit(JPEG_HandleTypeDef *hjpeg);
|
||||
void HAL_JPEG_MspInit(JPEG_HandleTypeDef *hjpeg);
|
||||
void HAL_JPEG_MspDeInit(JPEG_HandleTypeDef *hjpeg);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup JPEG_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* Encoding/Decoding Configuration functions ********************************/
|
||||
HAL_StatusTypeDef HAL_JPEG_ConfigEncoding(JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef *pConf);
|
||||
HAL_StatusTypeDef HAL_JPEG_GetInfo(JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef *pInfo);
|
||||
HAL_StatusTypeDef HAL_JPEG_EnableHeaderParsing(JPEG_HandleTypeDef *hjpeg);
|
||||
HAL_StatusTypeDef HAL_JPEG_DisableHeaderParsing(JPEG_HandleTypeDef *hjpeg);
|
||||
HAL_StatusTypeDef HAL_JPEG_SetUserQuantTables(JPEG_HandleTypeDef *hjpeg, uint8_t *QTable0, uint8_t *QTable1, uint8_t *QTable2, uint8_t *QTable3);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup JPEG_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
/* JPEG processing functions **************************************/
|
||||
HAL_StatusTypeDef HAL_JPEG_Encode(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength, uint8_t *pDataOut, uint32_t OutDataLength, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_JPEG_Decode(JPEG_HandleTypeDef *hjpeg ,uint8_t *pDataIn ,uint32_t InDataLength ,uint8_t *pDataOutMCU ,uint32_t OutDataLength, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_JPEG_Encode_IT(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength, uint8_t *pDataOut, uint32_t OutDataLength);
|
||||
HAL_StatusTypeDef HAL_JPEG_Decode_IT(JPEG_HandleTypeDef *hjpeg ,uint8_t *pDataIn ,uint32_t InDataLength ,uint8_t *pDataOutMCU ,uint32_t OutDataLength);
|
||||
HAL_StatusTypeDef HAL_JPEG_Encode_DMA(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength, uint8_t *pDataOut, uint32_t OutDataLength);
|
||||
HAL_StatusTypeDef HAL_JPEG_Decode_DMA(JPEG_HandleTypeDef *hjpeg ,uint8_t *pDataIn ,uint32_t InDataLength ,uint8_t *pDataOutMCU ,uint32_t OutDataLength);
|
||||
HAL_StatusTypeDef HAL_JPEG_Pause(JPEG_HandleTypeDef *hjpeg, uint32_t XferSelection);
|
||||
HAL_StatusTypeDef HAL_JPEG_Resume(JPEG_HandleTypeDef *hjpeg, uint32_t XferSelection);
|
||||
void HAL_JPEG_ConfigInputBuffer(JPEG_HandleTypeDef *hjpeg, uint8_t *pNewInputBuffer, uint32_t InDataLength);
|
||||
void HAL_JPEG_ConfigOutputBuffer(JPEG_HandleTypeDef *hjpeg, uint8_t *pNewOutputBuffer, uint32_t OutDataLength);
|
||||
HAL_StatusTypeDef HAL_JPEG_Abort(JPEG_HandleTypeDef *hjpeg);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup JPEG_Exported_Functions_Group4
|
||||
* @{
|
||||
*/
|
||||
/* JPEG Decode/Encode callback functions ********************************************************/
|
||||
void HAL_JPEG_InfoReadyCallback(JPEG_HandleTypeDef *hjpeg,JPEG_ConfTypeDef *pInfo);
|
||||
void HAL_JPEG_EncodeCpltCallback(JPEG_HandleTypeDef *hjpeg);
|
||||
void HAL_JPEG_DecodeCpltCallback(JPEG_HandleTypeDef *hjpeg);
|
||||
void HAL_JPEG_ErrorCallback(JPEG_HandleTypeDef *hjpeg);
|
||||
void HAL_JPEG_GetDataCallback(JPEG_HandleTypeDef *hjpeg, uint32_t NbDecodedData);
|
||||
void HAL_JPEG_DataReadyCallback (JPEG_HandleTypeDef *hjpeg, uint8_t *pDataOut, uint32_t OutDataLength);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup JPEG_Exported_Functions_Group5
|
||||
* @{
|
||||
*/
|
||||
/* JPEG IRQ handler management ******************************************************/
|
||||
void HAL_JPEG_IRQHandler(JPEG_HandleTypeDef *hjpeg);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup JPEG_Exported_Functions_Group6
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State and Error functions ************************************************/
|
||||
HAL_JPEG_STATETypeDef HAL_JPEG_GetState(JPEG_HandleTypeDef *hjpeg);
|
||||
uint32_t HAL_JPEG_GetError(JPEG_HandleTypeDef *hjpeg);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/** @defgroup JPEG_Private_Types JPEG Private Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private defines -----------------------------------------------------------*/
|
||||
/** @defgroup JPEG_Private_Defines JPEG Private Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/** @defgroup JPEG_Private_Variables JPEG Private Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup JPEG_Private_Constants JPEG Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup JPEG_Private_Macros JPEG Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup JPEG_IS_Definitions JPEG Private macros to check input parameters
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_JPEG_CHROMASUBSAMPLING(SUBSAMPLING) (((SUBSAMPLING) == JPEG_444_SUBSAMPLING) || \
|
||||
((SUBSAMPLING) == JPEG_420_SUBSAMPLING) || \
|
||||
((SUBSAMPLING) == JPEG_422_SUBSAMPLING))
|
||||
|
||||
#define IS_JPEG_IMAGE_QUALITY(NUMBER) (((NUMBER) >= JPEG_IMAGE_QUALITY_MIN) && ((NUMBER) <= JPEG_IMAGE_QUALITY_MAX))
|
||||
|
||||
#define IS_JPEG_COLORSPACE(COLORSPACE) (((COLORSPACE) == JPEG_GRAYSCALE_COLORSPACE) || \
|
||||
((COLORSPACE) == JPEG_YCBCR_COLORSPACE) || \
|
||||
((COLORSPACE) == JPEG_CMYK_COLORSPACE))
|
||||
|
||||
#define IS_JPEG_PAUSE_RESUME_STATE(VALUE) (((VALUE) == JPEG_PAUSE_RESUME_INPUT) || \
|
||||
((VALUE) == JPEG_PAUSE_RESUME_OUTPUT)|| \
|
||||
((VALUE) == JPEG_PAUSE_RESUME_INPUT_OUTPUT))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions prototypes ----------------------------------------------*/
|
||||
/** @defgroup JPEG_Private_Functions_Prototypes JPEG Private Functions Prototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup JPEG_Private_Functions JPEG Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F7xx_HAL_JPEG_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,739 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_hal_lptim.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.2
|
||||
* @date 14-April-2017
|
||||
* @brief Header file of LPTIM HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F7xx_HAL_LPTIM_H
|
||||
#define __STM32F7xx_HAL_LPTIM_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup LPTIM LPTIM
|
||||
* @brief LPTIM HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup LPTIM_Exported_Types LPTIM Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup LPTIM_WAKEUPTIMER_EXTILINE LPTIM WAKEUP Timer EXTI Line
|
||||
* @{
|
||||
*/
|
||||
#define LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT ((uint32_t)EXTI_IMR_MR23) /*!< External interrupt line 23 Connected to the LPTIM EXTI Line */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief LPTIM Clock configuration definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Source; /*!< Selects the clock source.
|
||||
This parameter can be a value of @ref LPTIM_Clock_Source */
|
||||
|
||||
uint32_t Prescaler; /*!< Specifies the counter clock Prescaler.
|
||||
This parameter can be a value of @ref LPTIM_Clock_Prescaler */
|
||||
|
||||
}LPTIM_ClockConfigTypeDef;
|
||||
|
||||
/**
|
||||
* @brief LPTIM Clock configuration definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Polarity; /*!< Selects the polarity of the active edge for the counter unit
|
||||
if the ULPTIM input is selected.
|
||||
Note: This parameter is used only when Ultra low power clock source is used.
|
||||
Note: If the polarity is configured on 'both edges', an auxiliary clock
|
||||
(one of the Low power oscillator) must be active.
|
||||
This parameter can be a value of @ref LPTIM_Clock_Polarity */
|
||||
|
||||
uint32_t SampleTime; /*!< Selects the clock sampling time to configure the clock glitch filter.
|
||||
Note: This parameter is used only when Ultra low power clock source is used.
|
||||
This parameter can be a value of @ref LPTIM_Clock_Sample_Time */
|
||||
|
||||
}LPTIM_ULPClockConfigTypeDef;
|
||||
|
||||
/**
|
||||
* @brief LPTIM Trigger configuration definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Source; /*!< Selects the Trigger source.
|
||||
This parameter can be a value of @ref LPTIM_Trigger_Source */
|
||||
|
||||
uint32_t ActiveEdge; /*!< Selects the Trigger active edge.
|
||||
Note: This parameter is used only when an external trigger is used.
|
||||
This parameter can be a value of @ref LPTIM_External_Trigger_Polarity */
|
||||
|
||||
uint32_t SampleTime; /*!< Selects the trigger sampling time to configure the clock glitch filter.
|
||||
Note: This parameter is used only when an external trigger is used.
|
||||
This parameter can be a value of @ref LPTIM_Trigger_Sample_Time */
|
||||
}LPTIM_TriggerConfigTypeDef;
|
||||
|
||||
/**
|
||||
* @brief LPTIM Initialization Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
LPTIM_ClockConfigTypeDef Clock; /*!< Specifies the clock parameters */
|
||||
|
||||
LPTIM_ULPClockConfigTypeDef UltraLowPowerClock; /*!< Specifies the Ultra Low Power clock parameters */
|
||||
|
||||
LPTIM_TriggerConfigTypeDef Trigger; /*!< Specifies the Trigger parameters */
|
||||
|
||||
uint32_t OutputPolarity; /*!< Specifies the Output polarity.
|
||||
This parameter can be a value of @ref LPTIM_Output_Polarity */
|
||||
|
||||
uint32_t UpdateMode; /*!< Specifies whether the update of the autorelaod and the compare
|
||||
values is done immediately or after the end of current period.
|
||||
This parameter can be a value of @ref LPTIM_Updating_Mode */
|
||||
|
||||
uint32_t CounterSource; /*!< Specifies whether the counter is incremented each internal event
|
||||
or each external event.
|
||||
This parameter can be a value of @ref LPTIM_Counter_Source */
|
||||
|
||||
}LPTIM_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL LPTIM State structure definition
|
||||
*/
|
||||
typedef enum __HAL_LPTIM_StateTypeDef
|
||||
{
|
||||
HAL_LPTIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */
|
||||
HAL_LPTIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
|
||||
HAL_LPTIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */
|
||||
HAL_LPTIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
|
||||
HAL_LPTIM_STATE_ERROR = 0x04U /*!< Internal Process is ongoing */
|
||||
}HAL_LPTIM_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief LPTIM handle Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
LPTIM_TypeDef *Instance; /*!< Register base address */
|
||||
|
||||
LPTIM_InitTypeDef Init; /*!< LPTIM required parameters */
|
||||
|
||||
HAL_StatusTypeDef Status; /*!< LPTIM peripheral status */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< LPTIM locking object */
|
||||
|
||||
__IO HAL_LPTIM_StateTypeDef State; /*!< LPTIM peripheral state */
|
||||
|
||||
}LPTIM_HandleTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup LPTIM_Exported_Constants LPTIM Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup LPTIM_Clock_Source LPTIM Clock Source
|
||||
* @{
|
||||
*/
|
||||
#define LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC ((uint32_t)0x00U)
|
||||
#define LPTIM_CLOCKSOURCE_ULPTIM LPTIM_CFGR_CKSEL
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LPTIM_Clock_Prescaler LPTIM Clock Prescaler
|
||||
* @{
|
||||
*/
|
||||
#define LPTIM_PRESCALER_DIV1 ((uint32_t)0x000000U)
|
||||
#define LPTIM_PRESCALER_DIV2 LPTIM_CFGR_PRESC_0
|
||||
#define LPTIM_PRESCALER_DIV4 LPTIM_CFGR_PRESC_1
|
||||
#define LPTIM_PRESCALER_DIV8 ((uint32_t)(LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_1))
|
||||
#define LPTIM_PRESCALER_DIV16 LPTIM_CFGR_PRESC_2
|
||||
#define LPTIM_PRESCALER_DIV32 ((uint32_t)(LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_2))
|
||||
#define LPTIM_PRESCALER_DIV64 ((uint32_t)(LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_2))
|
||||
#define LPTIM_PRESCALER_DIV128 ((uint32_t)LPTIM_CFGR_PRESC)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LPTIM_Output_Polarity LPTIM Output Polarity
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define LPTIM_OUTPUTPOLARITY_HIGH ((uint32_t)0x00000000U)
|
||||
#define LPTIM_OUTPUTPOLARITY_LOW (LPTIM_CFGR_WAVPOL)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LPTIM_Clock_Sample_Time LPTIM Clock Sample Time
|
||||
* @{
|
||||
*/
|
||||
#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION ((uint32_t)0x00000000U)
|
||||
#define LPTIM_CLOCKSAMPLETIME_2TRANSITIONS LPTIM_CFGR_CKFLT_0
|
||||
#define LPTIM_CLOCKSAMPLETIME_4TRANSITIONS LPTIM_CFGR_CKFLT_1
|
||||
#define LPTIM_CLOCKSAMPLETIME_8TRANSITIONS LPTIM_CFGR_CKFLT
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LPTIM_Clock_Polarity LPTIM Clock Polarity
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define LPTIM_CLOCKPOLARITY_RISING ((uint32_t)0x00000000U)
|
||||
#define LPTIM_CLOCKPOLARITY_FALLING LPTIM_CFGR_CKPOL_0
|
||||
#define LPTIM_CLOCKPOLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LPTIM_Trigger_Source LPTIM Trigger Source
|
||||
* @{
|
||||
*/
|
||||
#define LPTIM_TRIGSOURCE_SOFTWARE ((uint32_t)0x0000FFFFU)
|
||||
#define LPTIM_TRIGSOURCE_0 ((uint32_t)0x00000000U)
|
||||
#define LPTIM_TRIGSOURCE_1 ((uint32_t)LPTIM_CFGR_TRIGSEL_0)
|
||||
#define LPTIM_TRIGSOURCE_2 LPTIM_CFGR_TRIGSEL_1
|
||||
#define LPTIM_TRIGSOURCE_3 ((uint32_t)LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_1)
|
||||
#define LPTIM_TRIGSOURCE_4 LPTIM_CFGR_TRIGSEL_2
|
||||
#define LPTIM_TRIGSOURCE_5 ((uint32_t)LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_2)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LPTIM_External_Trigger_Polarity LPTIM External Trigger Polarity
|
||||
* @{
|
||||
*/
|
||||
#define LPTIM_ACTIVEEDGE_RISING LPTIM_CFGR_TRIGEN_0
|
||||
#define LPTIM_ACTIVEEDGE_FALLING LPTIM_CFGR_TRIGEN_1
|
||||
#define LPTIM_ACTIVEEDGE_RISING_FALLING LPTIM_CFGR_TRIGEN
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LPTIM_Trigger_Sample_Time LPTIM Trigger Sample Time
|
||||
* @{
|
||||
*/
|
||||
#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION ((uint32_t)0x00000000U)
|
||||
#define LPTIM_TRIGSAMPLETIME_2TRANSITIONS LPTIM_CFGR_TRGFLT_0
|
||||
#define LPTIM_TRIGSAMPLETIME_4TRANSITIONS LPTIM_CFGR_TRGFLT_1
|
||||
#define LPTIM_TRIGSAMPLETIME_8TRANSITIONS LPTIM_CFGR_TRGFLT
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LPTIM_Updating_Mode LPTIM Updating Mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define LPTIM_UPDATE_IMMEDIATE ((uint32_t)0x00000000U)
|
||||
#define LPTIM_UPDATE_ENDOFPERIOD LPTIM_CFGR_PRELOAD
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LPTIM_Counter_Source LPTIM Counter Source
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define LPTIM_COUNTERSOURCE_INTERNAL ((uint32_t)0x00000000U)
|
||||
#define LPTIM_COUNTERSOURCE_EXTERNAL LPTIM_CFGR_COUNTMODE
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LPTIM_Flag_Definition LPTIM Flag Definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define LPTIM_FLAG_DOWN LPTIM_ISR_DOWN
|
||||
#define LPTIM_FLAG_UP LPTIM_ISR_UP
|
||||
#define LPTIM_FLAG_ARROK LPTIM_ISR_ARROK
|
||||
#define LPTIM_FLAG_CMPOK LPTIM_ISR_CMPOK
|
||||
#define LPTIM_FLAG_EXTTRIG LPTIM_ISR_EXTTRIG
|
||||
#define LPTIM_FLAG_ARRM LPTIM_ISR_ARRM
|
||||
#define LPTIM_FLAG_CMPM LPTIM_ISR_CMPM
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LPTIM_Interrupts_Definition LPTIM Interrupts Definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define LPTIM_IT_DOWN LPTIM_IER_DOWNIE
|
||||
#define LPTIM_IT_UP LPTIM_IER_UPIE
|
||||
#define LPTIM_IT_ARROK LPTIM_IER_ARROKIE
|
||||
#define LPTIM_IT_CMPOK LPTIM_IER_CMPOKIE
|
||||
#define LPTIM_IT_EXTTRIG LPTIM_IER_EXTTRIGIE
|
||||
#define LPTIM_IT_ARRM LPTIM_IER_ARRMIE
|
||||
#define LPTIM_IT_CMPM LPTIM_IER_CMPMIE
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup LPTIM_Exported_Macros LPTIM Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset LPTIM handle state
|
||||
* @param __HANDLE__: LPTIM handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LPTIM_STATE_RESET)
|
||||
|
||||
/**
|
||||
* @brief Enable/Disable the LPTIM peripheral.
|
||||
* @param __HANDLE__: LPTIM handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_LPTIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (LPTIM_CR_ENABLE))
|
||||
#define __HAL_LPTIM_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(LPTIM_CR_ENABLE))
|
||||
|
||||
/**
|
||||
* @brief Starts the LPTIM peripheral in Continuous or in single mode.
|
||||
* @param __HANDLE__: DMA handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_LPTIM_START_CONTINUOUS(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_CNTSTRT)
|
||||
#define __HAL_LPTIM_START_SINGLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_SNGSTRT)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Writes the passed parameter in the Autoreload register.
|
||||
* @param __HANDLE__: LPTIM handle
|
||||
* @param __VALUE__ : Autoreload value
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_LPTIM_AUTORELOAD_SET(__HANDLE__ , __VALUE__) ((__HANDLE__)->Instance->ARR = (__VALUE__))
|
||||
|
||||
/**
|
||||
* @brief Writes the passed parameter in the Compare register.
|
||||
* @param __HANDLE__: LPTIM handle
|
||||
* @param __VALUE__ : Compare value
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_LPTIM_COMPARE_SET(__HANDLE__ , __VALUE__) ((__HANDLE__)->Instance->CMP = (__VALUE__))
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified LPTIM flag is set or not.
|
||||
* @param __HANDLE__: LPTIM handle
|
||||
* @param __FLAG__ : LPTIM flag to check
|
||||
* This parameter can be a value of:
|
||||
* @arg LPTIM_FLAG_DOWN : Counter direction change up Flag.
|
||||
* @arg LPTIM_FLAG_UP : Counter direction change down to up Flag.
|
||||
* @arg LPTIM_FLAG_ARROK : Autoreload register update OK Flag.
|
||||
* @arg LPTIM_FLAG_CMPOK : Compare register update OK Flag.
|
||||
* @arg LPTIM_FLAG_EXTTRIG : External trigger edge event Flag.
|
||||
* @arg LPTIM_FLAG_ARRM : Autoreload match Flag.
|
||||
* @arg LPTIM_FLAG_CMPM : Compare match Flag.
|
||||
* @retval The state of the specified flag (SET or RESET).
|
||||
*/
|
||||
#define __HAL_LPTIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR &(__FLAG__)) == (__FLAG__))
|
||||
|
||||
/**
|
||||
* @brief Clears the specified LPTIM flag.
|
||||
* @param __HANDLE__: LPTIM handle.
|
||||
* @param __FLAG__ : LPTIM flag to clear.
|
||||
* This parameter can be a value of:
|
||||
* @arg LPTIM_FLAG_DOWN : Counter direction change up Flag.
|
||||
* @arg LPTIM_FLAG_UP : Counter direction change down to up Flag.
|
||||
* @arg LPTIM_FLAG_ARROK : Autoreload register update OK Flag.
|
||||
* @arg LPTIM_FLAG_CMPOK : Compare register update OK Flag.
|
||||
* @arg LPTIM_FLAG_EXTTRIG : External trigger edge event Flag.
|
||||
* @arg LPTIM_FLAG_ARRM : Autoreload match Flag.
|
||||
* @arg LPTIM_FLAG_CMPM : Compare match Flag.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_LPTIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
|
||||
|
||||
/**
|
||||
* @brief Enable the specified LPTIM interrupt.
|
||||
* @param __HANDLE__ : LPTIM handle.
|
||||
* @param __INTERRUPT__ : LPTIM interrupt to set.
|
||||
* This parameter can be a value of:
|
||||
* @arg LPTIM_IT_DOWN : Counter direction change up Interrupt.
|
||||
* @arg LPTIM_IT_UP : Counter direction change down to up Interrupt.
|
||||
* @arg LPTIM_IT_ARROK : Autoreload register update OK Interrupt.
|
||||
* @arg LPTIM_IT_CMPOK : Compare register update OK Interrupt.
|
||||
* @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
|
||||
* @arg LPTIM_IT_ARRM : Autoreload match Interrupt.
|
||||
* @arg LPTIM_IT_CMPM : Compare match Interrupt.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_LPTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Disable the specified LPTIM interrupt.
|
||||
* @param __HANDLE__ : LPTIM handle.
|
||||
* @param __INTERRUPT__ : LPTIM interrupt to set.
|
||||
* This parameter can be a value of:
|
||||
* @arg LPTIM_IT_DOWN : Counter direction change up Interrupt.
|
||||
* @arg LPTIM_IT_UP : Counter direction change down to up Interrupt.
|
||||
* @arg LPTIM_IT_ARROK : Autoreload register update OK Interrupt.
|
||||
* @arg LPTIM_IT_CMPOK : Compare register update OK Interrupt.
|
||||
* @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
|
||||
* @arg LPTIM_IT_ARRM : Autoreload match Interrupt.
|
||||
* @arg LPTIM_IT_CMPM : Compare match Interrupt.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_LPTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified LPTIM interrupt is set or not.
|
||||
* @param __HANDLE__ : LPTIM handle.
|
||||
* @param __INTERRUPT__ : LPTIM interrupt to check.
|
||||
* This parameter can be a value of:
|
||||
* @arg LPTIM_IT_DOWN : Counter direction change up Interrupt.
|
||||
* @arg LPTIM_IT_UP : Counter direction change down to up Interrupt.
|
||||
* @arg LPTIM_IT_ARROK : Autoreload register update OK Interrupt.
|
||||
* @arg LPTIM_IT_CMPOK : Compare register update OK Interrupt.
|
||||
* @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
|
||||
* @arg LPTIM_IT_ARRM : Autoreload match Interrupt.
|
||||
* @arg LPTIM_IT_CMPM : Compare match Interrupt.
|
||||
* @retval Interrupt status.
|
||||
*/
|
||||
|
||||
#define __HAL_LPTIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
||||
|
||||
/**
|
||||
* @brief Enable interrupt on the LPTIM Wake-up Timer associated Exti line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT() (EXTI->IMR |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
|
||||
|
||||
/**
|
||||
* @brief Disable interrupt on the LPTIM Wake-up Timer associated Exti line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT() (EXTI->IMR &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))
|
||||
|
||||
/**
|
||||
* @brief Enable event on the LPTIM Wake-up Timer associated Exti line.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_EVENT() (EXTI->EMR |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
|
||||
|
||||
/**
|
||||
* @brief Disable event on the LPTIM Wake-up Timer associated Exti line.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))
|
||||
|
||||
/**
|
||||
* @brief Enable falling edge trigger on the LPTIM Wake-up Timer associated Exti line.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
|
||||
|
||||
/**
|
||||
* @brief Disable falling edge trigger on the LPTIM Wake-up Timer associated Exti line.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))
|
||||
|
||||
/**
|
||||
* @brief Enable rising edge trigger on the LPTIM Wake-up Timer associated Exti line.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
|
||||
|
||||
/**
|
||||
* @brief Disable rising edge trigger on the LPTIM Wake-up Timer associated Exti line.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))
|
||||
|
||||
/**
|
||||
* @brief Enable rising & falling edge trigger on the LPTIM Wake-up Timer associated Exti line.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE() do{__HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();\
|
||||
__HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE();\
|
||||
}while(0)
|
||||
|
||||
/**
|
||||
* @brief Disable rising & falling edge trigger on the LPTIM Wake-up Timer associated Exti line.
|
||||
* This parameter can be:
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE() do{__HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();\
|
||||
__HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE();\
|
||||
}while(0)
|
||||
|
||||
/**
|
||||
* @brief Check whether the LPTIM Wake-up Timer associated Exti line interrupt flag is set or not.
|
||||
* @retval Line Status.
|
||||
*/
|
||||
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_GET_FLAG() (EXTI->PR & LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
|
||||
|
||||
/**
|
||||
* @brief Clear the LPTIM Wake-up Timer associated Exti line flag.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_CLEAR_FLAG() (EXTI->PR = LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
|
||||
|
||||
/**
|
||||
* @brief Generate a Software interrupt on the LPTIM Wake-up Timer associated Exti line.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_GENERATE_SWIT() (EXTI->SWIER |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup LPTIM_Exported_Functions LPTIM Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Initialization/de-initialization functions ********************************/
|
||||
HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim);
|
||||
HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim);
|
||||
|
||||
/* MSP functions *************************************************************/
|
||||
void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef *hlptim);
|
||||
void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim);
|
||||
|
||||
/* Start/Stop operation functions *********************************************/
|
||||
/* ################################# PWM Mode ################################*/
|
||||
/* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_LPTIM_PWM_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
|
||||
HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim);
|
||||
/* Non-Blocking mode: Interrupt */
|
||||
HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
|
||||
HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim);
|
||||
|
||||
/* ############################# One Pulse Mode ##############################*/
|
||||
/* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
|
||||
HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim);
|
||||
/* Non-Blocking mode: Interrupt */
|
||||
HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
|
||||
HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim);
|
||||
|
||||
/* ############################## Set once Mode ##############################*/
|
||||
/* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
|
||||
HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef *hlptim);
|
||||
/* Non-Blocking mode: Interrupt */
|
||||
HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
|
||||
HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim);
|
||||
|
||||
/* ############################### Encoder Mode ##############################*/
|
||||
/* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
|
||||
HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef *hlptim);
|
||||
/* Non-Blocking mode: Interrupt */
|
||||
HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
|
||||
HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim);
|
||||
|
||||
/* ############################# Time out Mode ##############################*/
|
||||
/* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef *hlptim);
|
||||
/* Non-Blocking mode: Interrupt */
|
||||
HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim);
|
||||
|
||||
/* ############################## Counter Mode ###############################*/
|
||||
/* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
|
||||
HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim);
|
||||
/* Non-Blocking mode: Interrupt */
|
||||
HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
|
||||
HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim);
|
||||
|
||||
/* Reading operation functions ************************************************/
|
||||
uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim);
|
||||
uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim);
|
||||
uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim);
|
||||
|
||||
/* LPTIM IRQ functions *******************************************************/
|
||||
void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim);
|
||||
|
||||
/* CallBack functions ********************************************************/
|
||||
void HAL_LPTIM_CompareMatchCallback(LPTIM_HandleTypeDef *hlptim);
|
||||
void HAL_LPTIM_AutoReloadMatchCallback(LPTIM_HandleTypeDef *hlptim);
|
||||
void HAL_LPTIM_TriggerCallback(LPTIM_HandleTypeDef *hlptim);
|
||||
void HAL_LPTIM_CompareWriteCallback(LPTIM_HandleTypeDef *hlptim);
|
||||
void HAL_LPTIM_AutoReloadWriteCallback(LPTIM_HandleTypeDef *hlptim);
|
||||
void HAL_LPTIM_DirectionUpCallback(LPTIM_HandleTypeDef *hlptim);
|
||||
void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim);
|
||||
|
||||
/* Peripheral State functions ************************************************/
|
||||
HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/** @defgroup LPTIM_Private_Types LPTIM Private Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/** @defgroup LPTIM_Private_Variables LPTIM Private Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup LPTIM_Private_Constants LPTIM Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup LPTIM_Private_Macros LPTIM Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_LPTIM_CLOCK_SOURCE(__SOURCE__) (((__SOURCE__) == LPTIM_CLOCKSOURCE_ULPTIM) || \
|
||||
((__SOURCE__) == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC))
|
||||
|
||||
#define IS_LPTIM_CLOCK_PRESCALER(__PRESCALER__) (((__PRESCALER__) == LPTIM_PRESCALER_DIV1 ) || \
|
||||
((__PRESCALER__) == LPTIM_PRESCALER_DIV2 ) || \
|
||||
((__PRESCALER__) == LPTIM_PRESCALER_DIV4 ) || \
|
||||
((__PRESCALER__) == LPTIM_PRESCALER_DIV8 ) || \
|
||||
((__PRESCALER__) == LPTIM_PRESCALER_DIV16 ) || \
|
||||
((__PRESCALER__) == LPTIM_PRESCALER_DIV32 ) || \
|
||||
((__PRESCALER__) == LPTIM_PRESCALER_DIV64 ) || \
|
||||
((__PRESCALER__) == LPTIM_PRESCALER_DIV128))
|
||||
#define IS_LPTIM_CLOCK_PRESCALERDIV1(__PRESCALER__) ((__PRESCALER__) == LPTIM_PRESCALER_DIV1)
|
||||
|
||||
#define IS_LPTIM_OUTPUT_POLARITY(__POLARITY__) (((__POLARITY__) == LPTIM_OUTPUTPOLARITY_LOW ) || \
|
||||
((__POLARITY__) == LPTIM_OUTPUTPOLARITY_HIGH))
|
||||
|
||||
#define IS_LPTIM_CLOCK_SAMPLE_TIME(__SAMPLETIME__) (((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION) || \
|
||||
((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_2TRANSITIONS) || \
|
||||
((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_4TRANSITIONS) || \
|
||||
((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_8TRANSITIONS))
|
||||
|
||||
#define IS_LPTIM_CLOCK_POLARITY(__POLARITY__) (((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING) || \
|
||||
((__POLARITY__) == LPTIM_CLOCKPOLARITY_FALLING) || \
|
||||
((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING_FALLING))
|
||||
|
||||
#define IS_LPTIM_TRG_SOURCE(__TRIG__) (((__TRIG__) == LPTIM_TRIGSOURCE_SOFTWARE) || \
|
||||
((__TRIG__) == LPTIM_TRIGSOURCE_0) || \
|
||||
((__TRIG__) == LPTIM_TRIGSOURCE_1) || \
|
||||
((__TRIG__) == LPTIM_TRIGSOURCE_2) || \
|
||||
((__TRIG__) == LPTIM_TRIGSOURCE_3) || \
|
||||
((__TRIG__) == LPTIM_TRIGSOURCE_4) || \
|
||||
((__TRIG__) == LPTIM_TRIGSOURCE_5))
|
||||
|
||||
#define IS_LPTIM_EXT_TRG_POLARITY(__POLAR__) (((__POLAR__) == LPTIM_ACTIVEEDGE_RISING ) || \
|
||||
((__POLAR__) == LPTIM_ACTIVEEDGE_FALLING ) || \
|
||||
((__POLAR__) == LPTIM_ACTIVEEDGE_RISING_FALLING ))
|
||||
|
||||
#define IS_LPTIM_TRIG_SAMPLE_TIME(__SAMPLETIME__) (((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION) || \
|
||||
((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_2TRANSITIONS ) || \
|
||||
((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_4TRANSITIONS ) || \
|
||||
((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_8TRANSITIONS ))
|
||||
|
||||
#define IS_LPTIM_UPDATE_MODE(__MODE__) (((__MODE__) == LPTIM_UPDATE_IMMEDIATE) || \
|
||||
((__MODE__) == LPTIM_UPDATE_ENDOFPERIOD))
|
||||
|
||||
#define IS_LPTIM_COUNTER_SOURCE(__SOURCE__) (((__SOURCE__) == LPTIM_COUNTERSOURCE_INTERNAL) || \
|
||||
((__SOURCE__) == LPTIM_COUNTERSOURCE_EXTERNAL))
|
||||
|
||||
#define IS_LPTIM_AUTORELOAD(__AUTORELOAD__) ((__AUTORELOAD__) <= 0x0000FFFFU)
|
||||
|
||||
#define IS_LPTIM_COMPARE(__COMPARE__) ((__COMPARE__) <= 0x0000FFFFU)
|
||||
|
||||
#define IS_LPTIM_PERIOD(PERIOD) ((PERIOD) <= 0x0000FFFFU)
|
||||
|
||||
#define IS_LPTIM_PULSE(PULSE) ((PULSE) <= 0x0000FFFFU)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup LPTIM_Private_Functions LPTIM Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F7xx_HAL_LPTIM_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,662 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_hal_ltdc.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.2
|
||||
* @date 14-April-2017
|
||||
* @brief Header file of LTDC HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F7xx_HAL_LTDC_H
|
||||
#define __STM32F7xx_HAL_LTDC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx_hal_def.h"
|
||||
|
||||
|
||||
/** @addtogroup STM32F7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup LTDC LTDC
|
||||
* @brief LTDC HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup LTDC_Exported_Types LTDC Exported Types
|
||||
* @{
|
||||
*/
|
||||
#define MAX_LAYER 2
|
||||
|
||||
/**
|
||||
* @brief LTDC color structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t Blue; /*!< Configures the blue value.
|
||||
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
|
||||
|
||||
uint8_t Green; /*!< Configures the green value.
|
||||
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
|
||||
|
||||
uint8_t Red; /*!< Configures the red value.
|
||||
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
|
||||
|
||||
uint8_t Reserved; /*!< Reserved 0xFF */
|
||||
} LTDC_ColorTypeDef;
|
||||
|
||||
/**
|
||||
* @brief LTDC Init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t HSPolarity; /*!< configures the horizontal synchronization polarity.
|
||||
This parameter can be one value of @ref LTDC_HS_POLARITY */
|
||||
|
||||
uint32_t VSPolarity; /*!< configures the vertical synchronization polarity.
|
||||
This parameter can be one value of @ref LTDC_VS_POLARITY */
|
||||
|
||||
uint32_t DEPolarity; /*!< configures the data enable polarity.
|
||||
This parameter can be one of value of @ref LTDC_DE_POLARITY */
|
||||
|
||||
uint32_t PCPolarity; /*!< configures the pixel clock polarity.
|
||||
This parameter can be one of value of @ref LTDC_PC_POLARITY */
|
||||
|
||||
uint32_t HorizontalSync; /*!< configures the number of Horizontal synchronization width.
|
||||
This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
|
||||
|
||||
uint32_t VerticalSync; /*!< configures the number of Vertical synchronization height.
|
||||
This parameter must be a number between Min_Data = 0x000 and Max_Data = 0x7FF. */
|
||||
|
||||
uint32_t AccumulatedHBP; /*!< configures the accumulated horizontal back porch width.
|
||||
This parameter must be a number between Min_Data = LTDC_HorizontalSync and Max_Data = 0xFFF. */
|
||||
|
||||
uint32_t AccumulatedVBP; /*!< configures the accumulated vertical back porch height.
|
||||
This parameter must be a number between Min_Data = LTDC_VerticalSync and Max_Data = 0x7FF. */
|
||||
|
||||
uint32_t AccumulatedActiveW; /*!< configures the accumulated active width.
|
||||
This parameter must be a number between Min_Data = LTDC_AccumulatedHBP and Max_Data = 0xFFF. */
|
||||
|
||||
uint32_t AccumulatedActiveH; /*!< configures the accumulated active height.
|
||||
This parameter must be a number between Min_Data = LTDC_AccumulatedVBP and Max_Data = 0x7FF. */
|
||||
|
||||
uint32_t TotalWidth; /*!< configures the total width.
|
||||
This parameter must be a number between Min_Data = LTDC_AccumulatedActiveW and Max_Data = 0xFFF. */
|
||||
|
||||
uint32_t TotalHeigh; /*!< configures the total height.
|
||||
This parameter must be a number between Min_Data = LTDC_AccumulatedActiveH and Max_Data = 0x7FF. */
|
||||
|
||||
LTDC_ColorTypeDef Backcolor; /*!< Configures the background color. */
|
||||
} LTDC_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief LTDC Layer structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t WindowX0; /*!< Configures the Window Horizontal Start Position.
|
||||
This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
|
||||
|
||||
uint32_t WindowX1; /*!< Configures the Window Horizontal Stop Position.
|
||||
This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
|
||||
|
||||
uint32_t WindowY0; /*!< Configures the Window vertical Start Position.
|
||||
This parameter must be a number between Min_Data = 0x000 and Max_Data = 0x7FF. */
|
||||
|
||||
uint32_t WindowY1; /*!< Configures the Window vertical Stop Position.
|
||||
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x7FF. */
|
||||
|
||||
uint32_t PixelFormat; /*!< Specifies the pixel format.
|
||||
This parameter can be one of value of @ref LTDC_Pixelformat */
|
||||
|
||||
uint32_t Alpha; /*!< Specifies the constant alpha used for blending.
|
||||
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
|
||||
|
||||
uint32_t Alpha0; /*!< Configures the default alpha value.
|
||||
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
|
||||
|
||||
uint32_t BlendingFactor1; /*!< Select the blending factor 1.
|
||||
This parameter can be one of value of @ref LTDC_BlendingFactor1 */
|
||||
|
||||
uint32_t BlendingFactor2; /*!< Select the blending factor 2.
|
||||
This parameter can be one of value of @ref LTDC_BlendingFactor2 */
|
||||
|
||||
uint32_t FBStartAdress; /*!< Configures the color frame buffer address */
|
||||
|
||||
uint32_t ImageWidth; /*!< Configures the color frame buffer line length.
|
||||
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x1FFF. */
|
||||
|
||||
uint32_t ImageHeight; /*!< Specifies the number of line in frame buffer.
|
||||
This parameter must be a number between Min_Data = 0x000 and Max_Data = 0x7FF. */
|
||||
|
||||
LTDC_ColorTypeDef Backcolor; /*!< Configures the layer background color. */
|
||||
} LTDC_LayerCfgTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL LTDC State structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_LTDC_STATE_RESET = 0x00U, /*!< LTDC not yet initialized or disabled */
|
||||
HAL_LTDC_STATE_READY = 0x01U, /*!< LTDC initialized and ready for use */
|
||||
HAL_LTDC_STATE_BUSY = 0x02U, /*!< LTDC internal process is ongoing */
|
||||
HAL_LTDC_STATE_TIMEOUT = 0x03U, /*!< LTDC Timeout state */
|
||||
HAL_LTDC_STATE_ERROR = 0x04U /*!< LTDC state error */
|
||||
}HAL_LTDC_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief LTDC handle Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
LTDC_TypeDef *Instance; /*!< LTDC Register base address */
|
||||
|
||||
LTDC_InitTypeDef Init; /*!< LTDC parameters */
|
||||
|
||||
LTDC_LayerCfgTypeDef LayerCfg[MAX_LAYER]; /*!< LTDC Layers parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< LTDC Lock */
|
||||
|
||||
__IO HAL_LTDC_StateTypeDef State; /*!< LTDC state */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< LTDC Error code */
|
||||
|
||||
} LTDC_HandleTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup LTDC_Exported_Constants LTDC Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup LTDC_Error_Code LTDC Error Code
|
||||
* @{
|
||||
*/
|
||||
#define HAL_LTDC_ERROR_NONE ((uint32_t)0x00000000U) /*!< LTDC No error */
|
||||
#define HAL_LTDC_ERROR_TE ((uint32_t)0x00000001U) /*!< LTDC Transfer error */
|
||||
#define HAL_LTDC_ERROR_FU ((uint32_t)0x00000002U) /*!< LTDC FIFO Underrun */
|
||||
#define HAL_LTDC_ERROR_TIMEOUT ((uint32_t)0x00000020U) /*!< LTDC Timeout error */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LTDC_HS_POLARITY LTDC HS POLARITY
|
||||
* @{
|
||||
*/
|
||||
#define LTDC_HSPOLARITY_AL ((uint32_t)0x00000000U) /*!< Horizontal Synchronization is active low. */
|
||||
#define LTDC_HSPOLARITY_AH LTDC_GCR_HSPOL /*!< Horizontal Synchronization is active high. */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LTDC_VS_POLARITY LTDC VS POLARITY
|
||||
* @{
|
||||
*/
|
||||
#define LTDC_VSPOLARITY_AL ((uint32_t)0x00000000U) /*!< Vertical Synchronization is active low. */
|
||||
#define LTDC_VSPOLARITY_AH LTDC_GCR_VSPOL /*!< Vertical Synchronization is active high. */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LTDC_DE_POLARITY LTDC DE POLARITY
|
||||
* @{
|
||||
*/
|
||||
#define LTDC_DEPOLARITY_AL ((uint32_t)0x00000000U) /*!< Data Enable, is active low. */
|
||||
#define LTDC_DEPOLARITY_AH LTDC_GCR_DEPOL /*!< Data Enable, is active high. */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LTDC_PC_POLARITY LTDC PC POLARITY
|
||||
* @{
|
||||
*/
|
||||
#define LTDC_PCPOLARITY_IPC ((uint32_t)0x00000000U) /*!< input pixel clock. */
|
||||
#define LTDC_PCPOLARITY_IIPC LTDC_GCR_PCPOL /*!< inverted input pixel clock. */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LTDC_SYNC LTDC SYNC
|
||||
* @{
|
||||
*/
|
||||
#define LTDC_HORIZONTALSYNC (LTDC_SSCR_HSW >> 16) /*!< Horizontal synchronization width. */
|
||||
#define LTDC_VERTICALSYNC LTDC_SSCR_VSH /*!< Vertical synchronization height. */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LTDC_BACK_COLOR LTDC BACK COLOR
|
||||
* @{
|
||||
*/
|
||||
#define LTDC_COLOR ((uint32_t)0x000000FFU) /*!< Color mask */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LTDC_BlendingFactor1 LTDC Blending Factor1
|
||||
* @{
|
||||
*/
|
||||
#define LTDC_BLENDING_FACTOR1_CA ((uint32_t)0x00000400U) /*!< Blending factor : Cte Alpha */
|
||||
#define LTDC_BLENDING_FACTOR1_PAxCA ((uint32_t)0x00000600U) /*!< Blending factor : Cte Alpha x Pixel Alpha*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LTDC_BlendingFactor2 LTDC Blending Factor2
|
||||
* @{
|
||||
*/
|
||||
#define LTDC_BLENDING_FACTOR2_CA ((uint32_t)0x00000005U) /*!< Blending factor : Cte Alpha */
|
||||
#define LTDC_BLENDING_FACTOR2_PAxCA ((uint32_t)0x00000007U) /*!< Blending factor : Cte Alpha x Pixel Alpha*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LTDC_Pixelformat LTDC Pixel format
|
||||
* @{
|
||||
*/
|
||||
#define LTDC_PIXEL_FORMAT_ARGB8888 ((uint32_t)0x00000000U) /*!< ARGB8888 LTDC pixel format */
|
||||
#define LTDC_PIXEL_FORMAT_RGB888 ((uint32_t)0x00000001U) /*!< RGB888 LTDC pixel format */
|
||||
#define LTDC_PIXEL_FORMAT_RGB565 ((uint32_t)0x00000002U) /*!< RGB565 LTDC pixel format */
|
||||
#define LTDC_PIXEL_FORMAT_ARGB1555 ((uint32_t)0x00000003U) /*!< ARGB1555 LTDC pixel format */
|
||||
#define LTDC_PIXEL_FORMAT_ARGB4444 ((uint32_t)0x00000004U) /*!< ARGB4444 LTDC pixel format */
|
||||
#define LTDC_PIXEL_FORMAT_L8 ((uint32_t)0x00000005U) /*!< L8 LTDC pixel format */
|
||||
#define LTDC_PIXEL_FORMAT_AL44 ((uint32_t)0x00000006U) /*!< AL44 LTDC pixel format */
|
||||
#define LTDC_PIXEL_FORMAT_AL88 ((uint32_t)0x00000007U) /*!< AL88 LTDC pixel format */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LTDC_Alpha LTDC Alpha
|
||||
* @{
|
||||
*/
|
||||
#define LTDC_ALPHA LTDC_LxCACR_CONSTA /*!< LTDC Cte Alpha mask */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LTDC_LAYER_Config LTDC LAYER Config
|
||||
* @{
|
||||
*/
|
||||
#define LTDC_STOPPOSITION (LTDC_LxWHPCR_WHSPPOS >> 16) /*!< LTDC Layer stop position */
|
||||
#define LTDC_STARTPOSITION LTDC_LxWHPCR_WHSTPOS /*!< LTDC Layer start position */
|
||||
|
||||
#define LTDC_COLOR_FRAME_BUFFER LTDC_LxCFBLR_CFBLL /*!< LTDC Layer Line length */
|
||||
#define LTDC_LINE_NUMBER LTDC_LxCFBLNR_CFBLNBR /*!< LTDC Layer Line number */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LTDC_Interrupts LTDC Interrupts
|
||||
* @{
|
||||
*/
|
||||
#define LTDC_IT_LI LTDC_IER_LIE
|
||||
#define LTDC_IT_FU LTDC_IER_FUIE
|
||||
#define LTDC_IT_TE LTDC_IER_TERRIE
|
||||
#define LTDC_IT_RR LTDC_IER_RRIE
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LTDC_Flag LTDC Flag
|
||||
* @{
|
||||
*/
|
||||
#define LTDC_FLAG_LI LTDC_ISR_LIF
|
||||
#define LTDC_FLAG_FU LTDC_ISR_FUIF
|
||||
#define LTDC_FLAG_TE LTDC_ISR_TERRIF
|
||||
#define LTDC_FLAG_RR LTDC_ISR_RRIF
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LTDC_Reload_Type LTDC Reload Type
|
||||
* @{
|
||||
*/
|
||||
#define LTDC_RELOAD_IMMEDIATE LTDC_SRCR_IMR /*!< Immediate Reload */
|
||||
#define LTDC_RELOAD_VERTICAL_BLANKING LTDC_SRCR_VBR /*!< Vertical Blanking Reload */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup LTDC_Exported_Macros LTDC Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset LTDC handle state
|
||||
* @param __HANDLE__: specifies the LTDC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_LTDC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LTDC_STATE_RESET)
|
||||
|
||||
/**
|
||||
* @brief Enable the LTDC.
|
||||
* @param __HANDLE__: LTDC handle
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_LTDC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->GCR |= LTDC_GCR_LTDCEN)
|
||||
|
||||
/**
|
||||
* @brief Disable the LTDC.
|
||||
* @param __HANDLE__: LTDC handle
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_LTDC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->GCR &= ~(LTDC_GCR_LTDCEN))
|
||||
|
||||
/**
|
||||
* @brief Enable the LTDC Layer.
|
||||
* @param __HANDLE__: LTDC handle
|
||||
* @param __LAYER__: Specify the layer to be enabled
|
||||
* This parameter can be 0 or 1
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_LTDC_LAYER_ENABLE(__HANDLE__, __LAYER__) ((LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR |= (uint32_t)LTDC_LxCR_LEN)
|
||||
|
||||
/**
|
||||
* @brief Disable the LTDC Layer.
|
||||
* @param __HANDLE__: LTDC handle
|
||||
* @param __LAYER__: Specify the layer to be disabled
|
||||
* This parameter can be 0 or 1
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_LTDC_LAYER_DISABLE(__HANDLE__, __LAYER__) ((LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR &= ~(uint32_t)LTDC_LxCR_LEN)
|
||||
|
||||
/**
|
||||
* @brief Reload Layer Configuration.
|
||||
* @param __HANDLE__: LTDC handle
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_LTDC_RELOAD_CONFIG(__HANDLE__) ((__HANDLE__)->Instance->SRCR |= LTDC_SRCR_IMR)
|
||||
|
||||
/* Interrupt & Flag management */
|
||||
/**
|
||||
* @brief Get the LTDC pending flags.
|
||||
* @param __HANDLE__: LTDC handle
|
||||
* @param __FLAG__: Get the specified flag.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg LTDC_FLAG_LI: Line Interrupt flag
|
||||
* @arg LTDC_FLAG_FU: FIFO Underrun Interrupt flag
|
||||
* @arg LTDC_FLAG_TE: Transfer Error interrupt flag
|
||||
* @arg LTDC_FLAG_RR: Register Reload Interrupt Flag
|
||||
* @retval The state of FLAG (SET or RESET).
|
||||
*/
|
||||
#define __HAL_LTDC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
|
||||
|
||||
/**
|
||||
* @brief Clears the LTDC pending flags.
|
||||
* @param __HANDLE__: LTDC handle
|
||||
* @param __FLAG__: specifies the flag to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg LTDC_FLAG_LI: Line Interrupt flag
|
||||
* @arg LTDC_FLAG_FU: FIFO Underrun Interrupt flag
|
||||
* @arg LTDC_FLAG_TE: Transfer Error interrupt flag
|
||||
* @arg LTDC_FLAG_RR: Register Reload Interrupt Flag
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_LTDC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
|
||||
|
||||
/**
|
||||
* @brief Enables the specified LTDC interrupts.
|
||||
* @param __HANDLE__: LTDC handle
|
||||
* @param __INTERRUPT__: specifies the LTDC interrupt sources to be enabled.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg LTDC_IT_LI: Line Interrupt flag
|
||||
* @arg LTDC_IT_FU: FIFO Underrun Interrupt flag
|
||||
* @arg LTDC_IT_TE: Transfer Error interrupt flag
|
||||
* @arg LTDC_IT_RR: Register Reload Interrupt Flag
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_LTDC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Disables the specified LTDC interrupts.
|
||||
* @param __HANDLE__: LTDC handle
|
||||
* @param __INTERRUPT__: specifies the LTDC interrupt sources to be disabled.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg LTDC_IT_LI: Line Interrupt flag
|
||||
* @arg LTDC_IT_FU: FIFO Underrun Interrupt flag
|
||||
* @arg LTDC_IT_TE: Transfer Error interrupt flag
|
||||
* @arg LTDC_IT_RR: Register Reload Interrupt Flag
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_LTDC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= ~(__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified LTDC interrupt has occurred or not.
|
||||
* @param __HANDLE__: LTDC handle
|
||||
* @param __INTERRUPT__: specifies the LTDC interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg LTDC_IT_LI: Line Interrupt flag
|
||||
* @arg LTDC_IT_FU: FIFO Underrun Interrupt flag
|
||||
* @arg LTDC_IT_TE: Transfer Error interrupt flag
|
||||
* @arg LTDC_IT_RR: Register Reload Interrupt Flag
|
||||
* @retval The state of INTERRUPT (SET or RESET).
|
||||
*/
|
||||
#define __HAL_LTDC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->ISR & (__INTERRUPT__))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined (STM32F769xx) || defined (STM32F779xx)
|
||||
/* Include LTDC HAL Extension module */
|
||||
#include "stm32f7xx_hal_ltdc_ex.h"
|
||||
#endif /* STM32F769xx) | STM32F779xx */
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup LTDC_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
/** @addtogroup LTDC_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Initialization and de-initialization functions *****************************/
|
||||
HAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc);
|
||||
HAL_StatusTypeDef HAL_LTDC_DeInit(LTDC_HandleTypeDef *hltdc);
|
||||
void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc);
|
||||
void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef* hltdc);
|
||||
void HAL_LTDC_ErrorCallback(LTDC_HandleTypeDef *hltdc);
|
||||
void HAL_LTDC_LineEvenCallback(LTDC_HandleTypeDef *hltdc);
|
||||
void HAL_LTDC_ReloadEventCallback(LTDC_HandleTypeDef *hltdc);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup LTDC_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* IO operation functions *****************************************************/
|
||||
void HAL_LTDC_IRQHandler(LTDC_HandleTypeDef *hltdc);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup LTDC_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral Control functions ***********************************************/
|
||||
HAL_StatusTypeDef HAL_LTDC_ConfigLayer(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx);
|
||||
HAL_StatusTypeDef HAL_LTDC_SetWindowSize(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx);
|
||||
HAL_StatusTypeDef HAL_LTDC_SetWindowPosition(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx);
|
||||
HAL_StatusTypeDef HAL_LTDC_SetPixelFormat(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx);
|
||||
HAL_StatusTypeDef HAL_LTDC_SetAlpha(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx);
|
||||
HAL_StatusTypeDef HAL_LTDC_SetAddress(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx);
|
||||
HAL_StatusTypeDef HAL_LTDC_SetPitch(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx);
|
||||
HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx);
|
||||
HAL_StatusTypeDef HAL_LTDC_ConfigCLUT(LTDC_HandleTypeDef *hltdc, uint32_t *pCLUT, uint32_t CLUTSize, uint32_t LayerIdx);
|
||||
HAL_StatusTypeDef HAL_LTDC_EnableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
|
||||
HAL_StatusTypeDef HAL_LTDC_DisableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
|
||||
HAL_StatusTypeDef HAL_LTDC_EnableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
|
||||
HAL_StatusTypeDef HAL_LTDC_DisableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
|
||||
HAL_StatusTypeDef HAL_LTDC_ProgramLineEvent(LTDC_HandleTypeDef *hltdc, uint32_t Line);
|
||||
HAL_StatusTypeDef HAL_LTDC_EnableDither(LTDC_HandleTypeDef *hltdc);
|
||||
HAL_StatusTypeDef HAL_LTDC_DisableDither(LTDC_HandleTypeDef *hltdc);
|
||||
HAL_StatusTypeDef HAL_LTDC_Reload(LTDC_HandleTypeDef *hltdc, uint32_t ReloadType);
|
||||
HAL_StatusTypeDef HAL_LTDC_ConfigLayer_NoReload(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx);
|
||||
HAL_StatusTypeDef HAL_LTDC_SetWindowSize_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx);
|
||||
HAL_StatusTypeDef HAL_LTDC_SetWindowPosition_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx);
|
||||
HAL_StatusTypeDef HAL_LTDC_SetPixelFormat_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx);
|
||||
HAL_StatusTypeDef HAL_LTDC_SetAlpha_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx);
|
||||
HAL_StatusTypeDef HAL_LTDC_SetAddress_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx);
|
||||
HAL_StatusTypeDef HAL_LTDC_SetPitch_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx);
|
||||
HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx);
|
||||
HAL_StatusTypeDef HAL_LTDC_EnableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
|
||||
HAL_StatusTypeDef HAL_LTDC_DisableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
|
||||
HAL_StatusTypeDef HAL_LTDC_EnableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
|
||||
HAL_StatusTypeDef HAL_LTDC_DisableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup LTDC_Exported_Functions_Group4
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State functions *************************************************/
|
||||
HAL_LTDC_StateTypeDef HAL_LTDC_GetState(LTDC_HandleTypeDef *hltdc);
|
||||
uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/** @defgroup LTDC_Private_Types LTDC Private Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/** @defgroup LTDC_Private_Variables LTDC Private Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup LTDC_Private_Constants LTDC Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup LTDC_Private_Macros LTDC Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define LTDC_LAYER(__HANDLE__, __LAYER__) ((LTDC_Layer_TypeDef *)((uint32_t)(((uint32_t)((__HANDLE__)->Instance)) + 0x84 + (0x80*(__LAYER__)))))
|
||||
#define IS_LTDC_LAYER(LAYER) ((LAYER) <= MAX_LAYER)
|
||||
#define IS_LTDC_HSPOL(HSPOL) (((HSPOL) == LTDC_HSPOLARITY_AL) || \
|
||||
((HSPOL) == LTDC_HSPOLARITY_AH))
|
||||
#define IS_LTDC_VSPOL(VSPOL) (((VSPOL) == LTDC_VSPOLARITY_AL) || \
|
||||
((VSPOL) == LTDC_VSPOLARITY_AH))
|
||||
#define IS_LTDC_DEPOL(DEPOL) (((DEPOL) == LTDC_DEPOLARITY_AL) || \
|
||||
((DEPOL) == LTDC_DEPOLARITY_AH))
|
||||
#define IS_LTDC_PCPOL(PCPOL) (((PCPOL) == LTDC_PCPOLARITY_IPC) || \
|
||||
((PCPOL) == LTDC_PCPOLARITY_IIPC))
|
||||
#define IS_LTDC_HSYNC(HSYNC) ((HSYNC) <= LTDC_HORIZONTALSYNC)
|
||||
#define IS_LTDC_VSYNC(VSYNC) ((VSYNC) <= LTDC_VERTICALSYNC)
|
||||
#define IS_LTDC_AHBP(AHBP) ((AHBP) <= LTDC_HORIZONTALSYNC)
|
||||
#define IS_LTDC_AVBP(AVBP) ((AVBP) <= LTDC_VERTICALSYNC)
|
||||
#define IS_LTDC_AAW(AAW) ((AAW) <= LTDC_HORIZONTALSYNC)
|
||||
#define IS_LTDC_AAH(AAH) ((AAH) <= LTDC_VERTICALSYNC)
|
||||
#define IS_LTDC_TOTALW(TOTALW) ((TOTALW) <= LTDC_HORIZONTALSYNC)
|
||||
#define IS_LTDC_TOTALH(TOTALH) ((TOTALH) <= LTDC_VERTICALSYNC)
|
||||
#define IS_LTDC_BLUEVALUE(BBLUE) ((BBLUE) <= LTDC_COLOR)
|
||||
#define IS_LTDC_GREENVALUE(BGREEN) ((BGREEN) <= LTDC_COLOR)
|
||||
#define IS_LTDC_REDVALUE(BRED) ((BRED) <= LTDC_COLOR)
|
||||
#define IS_LTDC_BLENDING_FACTOR1(BlendingFactor1) (((BlendingFactor1) == LTDC_BLENDING_FACTOR1_CA) || \
|
||||
((BlendingFactor1) == LTDC_BLENDING_FACTOR1_PAxCA))
|
||||
#define IS_LTDC_BLENDING_FACTOR2(BlendingFactor2) (((BlendingFactor2) == LTDC_BLENDING_FACTOR2_CA) || \
|
||||
((BlendingFactor2) == LTDC_BLENDING_FACTOR2_PAxCA))
|
||||
#define IS_LTDC_PIXEL_FORMAT(Pixelformat) (((Pixelformat) == LTDC_PIXEL_FORMAT_ARGB8888) || ((Pixelformat) == LTDC_PIXEL_FORMAT_RGB888) || \
|
||||
((Pixelformat) == LTDC_PIXEL_FORMAT_RGB565) || ((Pixelformat) == LTDC_PIXEL_FORMAT_ARGB1555) || \
|
||||
((Pixelformat) == LTDC_PIXEL_FORMAT_ARGB4444) || ((Pixelformat) == LTDC_PIXEL_FORMAT_L8) || \
|
||||
((Pixelformat) == LTDC_PIXEL_FORMAT_AL44) || ((Pixelformat) == LTDC_PIXEL_FORMAT_AL88))
|
||||
#define IS_LTDC_ALPHA(ALPHA) ((ALPHA) <= LTDC_ALPHA)
|
||||
#define IS_LTDC_HCONFIGST(HCONFIGST) ((HCONFIGST) <= LTDC_STARTPOSITION)
|
||||
#define IS_LTDC_HCONFIGSP(HCONFIGSP) ((HCONFIGSP) <= LTDC_STOPPOSITION)
|
||||
#define IS_LTDC_VCONFIGST(VCONFIGST) ((VCONFIGST) <= LTDC_STARTPOSITION)
|
||||
#define IS_LTDC_VCONFIGSP(VCONFIGSP) ((VCONFIGSP) <= LTDC_STOPPOSITION)
|
||||
#define IS_LTDC_CFBP(CFBP) ((CFBP) <= LTDC_COLOR_FRAME_BUFFER)
|
||||
#define IS_LTDC_CFBLL(CFBLL) ((CFBLL) <= LTDC_COLOR_FRAME_BUFFER)
|
||||
#define IS_LTDC_CFBLNBR(CFBLNBR) ((CFBLNBR) <= LTDC_LINE_NUMBER)
|
||||
#define IS_LTDC_LIPOS(LIPOS) ((LIPOS) <= 0x7FF)
|
||||
#define IS_LTDC_RELAOD(RELOADTYPE) (((RELOADTYPE) == LTDC_RELOAD_IMMEDIATE) || ((RELOADTYPE) == LTDC_SRCR_VBR))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup LTDC_Private_Functions LTDC Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F7xx_HAL_LTDC_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,151 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_hal_ltdc_ex.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.2
|
||||
* @date 14-April-2017
|
||||
* @brief Header file of LTDC HAL Extension module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F7xx_HAL_LTDC_EX_H
|
||||
#define __STM32F7xx_HAL_LTDC_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if defined (STM32F769xx) || defined (STM32F779xx)
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx_hal_def.h"
|
||||
#include "stm32f7xx_hal_dsi.h"
|
||||
|
||||
/** @addtogroup STM32F7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup LTDCEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup LTDCEx_Exported_Constants LTDCEx Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup LTDCEx_Exported_Macros LTDC Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup LTDCEx_Exported_Functions LTDC Extended Exported Functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_LTDC_StructInitFromVideoConfig(LTDC_HandleTypeDef* hltdc, DSI_VidCfgTypeDef *VidCfg);
|
||||
HAL_StatusTypeDef HAL_LTDC_StructInitFromAdaptedCommandConfig(LTDC_HandleTypeDef* hltdc, DSI_CmdCfgTypeDef *CmdCfg);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/** @defgroup LTDCEx_Private_Types LTDCEx Private Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/** @defgroup LTDCEx_Private_Variables LTDCEx Private Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup LTDCEx_Private_Constants LTDCEx Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup LTDCEx_Private_Macros LTDCEx Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup LTDCEx_Private_Functions LTDCEx Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /*STM32F769xx | STM32F779xx */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F7xx_HAL_LTDC_EX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,537 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_hal_mdios.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.2
|
||||
* @date 14-April-2017
|
||||
* @brief Header file of MDIOS HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F7xx_HAL_MDIOS_H
|
||||
#define __STM32F7xx_HAL_MDIOS_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx_hal_def.h"
|
||||
|
||||
#if defined (MDIOS)
|
||||
|
||||
/** @addtogroup STM32F7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup MDIOS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup MDIOS_Exported_Types MDIOS Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup MDIOS_Exported_Types_Group1 MDIOS State structures definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
typedef enum
|
||||
{
|
||||
HAL_MDIOS_STATE_RESET = 0x00U, /*!< Peripheral not yet Initialized or disabled */
|
||||
HAL_MDIOS_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
|
||||
HAL_MDIOS_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */
|
||||
HAL_MDIOS_STATE_ERROR = 0x04U /*!< Reception process is ongoing */
|
||||
}HAL_MDIOS_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup MDIOS_Exported_Types_Group2 MDIOS Init Structure definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t PortAddress; /*!< Specifies the MDIOS port address.
|
||||
This parameter can be a value from 0 to 31 */
|
||||
uint32_t PreambleCheck; /*!< Specifies whether the preamble check is enabled or disabled.
|
||||
This parameter can be a value of @ref MDIOS_Preamble_Check */
|
||||
}MDIOS_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup MDIOS_Exported_Types_Group4 MDIOS handle Structure definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
MDIOS_TypeDef *Instance; /*!< Register base address */
|
||||
|
||||
MDIOS_InitTypeDef Init; /*!< MDIOS Init Structure */
|
||||
|
||||
__IO HAL_MDIOS_StateTypeDef State; /*!< MDIOS communication state */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< MDIOS Lock */
|
||||
}MDIOS_HandleTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup MDIOS_Exported_Constants MDIOS Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup MDIOS_Preamble_Check MDIOS Preamble Check
|
||||
* @{
|
||||
*/
|
||||
#define MDIOS_PREAMBLE_CHECK_ENABLE ((uint32_t)0x00000000U)
|
||||
#define MDIOS_PREAMBLE_CHECK_DISABLE MDIOS_CR_DPC
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup MDIOS_Input_Output_Registers_Definitions MDIOS Input Output Registers Definitions
|
||||
* @{
|
||||
*/
|
||||
#define MDIOS_REG0 ((uint32_t)0x00000000U)
|
||||
#define MDIOS_REG1 ((uint32_t)0x00000001U)
|
||||
#define MDIOS_REG2 ((uint32_t)0x00000002U)
|
||||
#define MDIOS_REG3 ((uint32_t)0x00000003U)
|
||||
#define MDIOS_REG4 ((uint32_t)0x00000004U)
|
||||
#define MDIOS_REG5 ((uint32_t)0x00000005U)
|
||||
#define MDIOS_REG6 ((uint32_t)0x00000006U)
|
||||
#define MDIOS_REG7 ((uint32_t)0x00000007U)
|
||||
#define MDIOS_REG8 ((uint32_t)0x00000008U)
|
||||
#define MDIOS_REG9 ((uint32_t)0x00000009U)
|
||||
#define MDIOS_REG10 ((uint32_t)0x0000000AU)
|
||||
#define MDIOS_REG11 ((uint32_t)0x0000000BU)
|
||||
#define MDIOS_REG12 ((uint32_t)0x0000000CU)
|
||||
#define MDIOS_REG13 ((uint32_t)0x0000000DU)
|
||||
#define MDIOS_REG14 ((uint32_t)0x0000000EU)
|
||||
#define MDIOS_REG15 ((uint32_t)0x0000000FU)
|
||||
#define MDIOS_REG16 ((uint32_t)0x00000010U)
|
||||
#define MDIOS_REG17 ((uint32_t)0x00000011U)
|
||||
#define MDIOS_REG18 ((uint32_t)0x00000012U)
|
||||
#define MDIOS_REG19 ((uint32_t)0x00000013U)
|
||||
#define MDIOS_REG20 ((uint32_t)0x00000014U)
|
||||
#define MDIOS_REG21 ((uint32_t)0x00000015U)
|
||||
#define MDIOS_REG22 ((uint32_t)0x00000016U)
|
||||
#define MDIOS_REG23 ((uint32_t)0x00000017U)
|
||||
#define MDIOS_REG24 ((uint32_t)0x00000018U)
|
||||
#define MDIOS_REG25 ((uint32_t)0x00000019U)
|
||||
#define MDIOS_REG26 ((uint32_t)0x0000001AU)
|
||||
#define MDIOS_REG27 ((uint32_t)0x0000001BU)
|
||||
#define MDIOS_REG28 ((uint32_t)0x0000001CU)
|
||||
#define MDIOS_REG29 ((uint32_t)0x0000001DU)
|
||||
#define MDIOS_REG30 ((uint32_t)0x0000001EU)
|
||||
#define MDIOS_REG31 ((uint32_t)0x0000001FU)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup MDIOS_Registers_Flags MDIOS Registers Flags
|
||||
* @{
|
||||
*/
|
||||
#define MDIOS_REG0_FLAG ((uint32_t)0x00000001U)
|
||||
#define MDIOS_REG1_FLAG ((uint32_t)0x00000002U)
|
||||
#define MDIOS_REG2_FLAG ((uint32_t)0x00000004U)
|
||||
#define MDIOS_REG3_FLAG ((uint32_t)0x00000008U)
|
||||
#define MDIOS_REG4_FLAG ((uint32_t)0x00000010U)
|
||||
#define MDIOS_REG5_FLAG ((uint32_t)0x00000020U)
|
||||
#define MDIOS_REG6_FLAG ((uint32_t)0x00000040U)
|
||||
#define MDIOS_REG7_FLAG ((uint32_t)0x00000080U)
|
||||
#define MDIOS_REG8_FLAG ((uint32_t)0x00000100U)
|
||||
#define MDIOS_REG9_FLAG ((uint32_t)0x00000200U)
|
||||
#define MDIOS_REG10_FLAG ((uint32_t)0x00000400U)
|
||||
#define MDIOS_REG11_FLAG ((uint32_t)0x00000800U)
|
||||
#define MDIOS_REG12_FLAG ((uint32_t)0x00001000U)
|
||||
#define MDIOS_REG13_FLAG ((uint32_t)0x00002000U)
|
||||
#define MDIOS_REG14_FLAG ((uint32_t)0x00004000U)
|
||||
#define MDIOS_REG15_FLAG ((uint32_t)0x00008000U)
|
||||
#define MDIOS_REG16_FLAG ((uint32_t)0x00010000U)
|
||||
#define MDIOS_REG17_FLAG ((uint32_t)0x00020000U)
|
||||
#define MDIOS_REG18_FLAG ((uint32_t)0x00040000U)
|
||||
#define MDIOS_REG19_FLAG ((uint32_t)0x00080000U)
|
||||
#define MDIOS_REG20_FLAG ((uint32_t)0x00100000U)
|
||||
#define MDIOS_REG21_FLAG ((uint32_t)0x00200000U)
|
||||
#define MDIOS_REG22_FLAG ((uint32_t)0x00400000U)
|
||||
#define MDIOS_REG23_FLAG ((uint32_t)0x00800000U)
|
||||
#define MDIOS_REG24_FLAG ((uint32_t)0x01000000U)
|
||||
#define MDIOS_REG25_FLAG ((uint32_t)0x02000000U)
|
||||
#define MDIOS_REG26_FLAG ((uint32_t)0x04000000U)
|
||||
#define MDIOS_REG27_FLAG ((uint32_t)0x08000000U)
|
||||
#define MDIOS_REG28_FLAG ((uint32_t)0x10000000U)
|
||||
#define MDIOS_REG29_FLAG ((uint32_t)0x20000000U)
|
||||
#define MDIOS_REG30_FLAG ((uint32_t)0x40000000U)
|
||||
#define MDIOS_REG31_FLAG ((uint32_t)0x80000000U)
|
||||
#define MDIOS_ALLREG_FLAG ((uint32_t)0xFFFFFFFFU)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup MDIOS_Interrupt_sources Interrupt Sources
|
||||
* @{
|
||||
*/
|
||||
#define MDIOS_IT_WRITE MDIOS_CR_WRIE
|
||||
#define MDIOS_IT_READ MDIOS_CR_RDIE
|
||||
#define MDIOS_IT_ERROR MDIOS_CR_EIE
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup MDIOS_Interrupt_Flags MDIOS Interrupt Flags
|
||||
* @{
|
||||
*/
|
||||
#define MDIOS_TURNAROUND_ERROR_FLAG MDIOS_SR_TERF
|
||||
#define MDIOS_START_ERROR_FLAG MDIOS_SR_SERF
|
||||
#define MDIOS_PREAMBLE_ERROR_FLAG MDIOS_SR_PERF
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup MDIOS_Wakeup_Line MDIOS Wakeup Line
|
||||
* @{
|
||||
*/
|
||||
#define MDIOS_WAKEUP_EXTI_LINE ((uint32_t)0x01000000) /* !< EXTI Line 24 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup MDIOS_Exported_Macros MDIOS Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset MDIOS handle state
|
||||
* @param __HANDLE__: MDIOS handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_MDIOS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_MDIOS_STATE_RESET)
|
||||
|
||||
/**
|
||||
* @brief Enable/Disable the MDIOS peripheral.
|
||||
* @param __HANDLE__: specifies the MDIOS handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_MDIOS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= MDIOS_CR_EN)
|
||||
#define __HAL_MDIOS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~MDIOS_CR_EN)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Enable the MDIOS device interrupt.
|
||||
* @param __HANDLE__: specifies the MDIOS handle.
|
||||
* @param __INTERRUPT__ : specifies the MDIOS interrupt sources to be enabled.
|
||||
* This parameter can be one or a combination of the following values:
|
||||
* @arg MDIOS_IT_WRITE: Register write interrupt
|
||||
* @arg MDIOS_IT_READ: Register read interrupt
|
||||
* @arg MDIOS_IT_ERROR: Error interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_MDIOS_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Disable the MDIOS device interrupt.
|
||||
* @param __HANDLE__: specifies the MDIOS handle.
|
||||
* @param __INTERRUPT__ : specifies the MDIOS interrupt sources to be disabled.
|
||||
* This parameter can be one or a combination of the following values:
|
||||
* @arg MDIOS_IT_WRITE: Register write interrupt
|
||||
* @arg MDIOS_IT_READ: Register read interrupt
|
||||
* @arg MDIOS_IT_ERROR: Error interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_MDIOS_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
|
||||
|
||||
/** @brief Set MDIOS slave get write register flag
|
||||
* @param __HANDLE__: specifies the MDIOS handle.
|
||||
* @param __FLAG__: specifies the write register flag
|
||||
* @retval The state of write flag
|
||||
*/
|
||||
#define __HAL_MDIOS_GET_WRITE_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->WRFR & (__FLAG__))
|
||||
|
||||
/** @brief MDIOS slave get read register flag
|
||||
* @param __HANDLE__: specifies the MDIOS handle.
|
||||
* @param __FLAG__: specifies the read register flag
|
||||
* @retval The state of read flag
|
||||
*/
|
||||
#define __HAL_MDIOS_GET_READ_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->RDFR & (__FLAG__))
|
||||
|
||||
/** @brief MDIOS slave get interrupt
|
||||
* @param __HANDLE__: specifies the MDIOS handle.
|
||||
* @param __FLAG__ : specifies the Error flag.
|
||||
* This parameter can be one or a combination of the following values:
|
||||
* @arg MDIOS_TURNARROUND_ERROR_FLAG: Register write interrupt
|
||||
* @arg MDIOS_START_ERROR_FLAG: Register read interrupt
|
||||
* @arg MDIOS_PREAMBLE_ERROR_FLAG: Error interrupt
|
||||
* @retval The state of the error flag
|
||||
*/
|
||||
#define __HAL_MDIOS_GET_ERROR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR & (__FLAG__))
|
||||
|
||||
/** @brief MDIOS slave clear interrupt
|
||||
* @param __HANDLE__: specifies the MDIOS handle.
|
||||
* @param __FLAG__ : specifies the Error flag.
|
||||
* This parameter can be one or a combination of the following values:
|
||||
* @arg MDIOS_TURNARROUND_ERROR_FLAG: Register write interrupt
|
||||
* @arg MDIOS_START_ERROR_FLAG: Register read interrupt
|
||||
* @arg MDIOS_PREAMBLE_ERROR_FLAG: Error interrupt
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_MDIOS_CLEAR_ERROR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CLRFR) |= (__FLAG__)
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified MDIOS interrupt is set or not.
|
||||
* @param __HANDLE__: specifies the MDIOS handle.
|
||||
* @param __INTERRUPT__ : specifies the MDIOS interrupt sources
|
||||
* This parameter can be one or a combination of the following values:
|
||||
* @arg MDIOS_IT_WRITE: Register write interrupt
|
||||
* @arg MDIOS_IT_READ: Register read interrupt
|
||||
* @arg MDIOS_IT_ERROR: Error interrupt
|
||||
* @retval The state of the interrupt source
|
||||
*/
|
||||
#define __HAL_MDIOS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Enable the MDIOS WAKEUP Exti Line.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_MDIOS_WAKEUP_EXTI_ENABLE_IT() (EXTI->IMR |= (MDIOS_WAKEUP_EXTI_LINE))
|
||||
|
||||
/**
|
||||
* @brief Disable the MDIOS WAKEUP Exti Line.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_MDIOS_WAKEUP_EXTI_DISABLE_IT() (EXTI->IMR &= ~(MDIOS_WAKEUP_EXTI_LINE))
|
||||
|
||||
/**
|
||||
* @brief Enable event on MDIOS WAKEUP Exti Line.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_MDIOS_WAKEUP_EXTI_ENABLE_EVENT() (EXTI->EMR |= (MDIOS_WAKEUP_EXTI_LINE))
|
||||
|
||||
/**
|
||||
* @brief Disable event on MDIOS WAKEUP Exti Line.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_MDIOS_WAKEUP_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(MDIOS_WAKEUP_EXTI_LINE))
|
||||
|
||||
/**
|
||||
* @brief checks whether the specified MDIOS WAKEUP Exti interrupt flag is set or not.
|
||||
* @retval EXTI MDIOS WAKEUP Line Status.
|
||||
*/
|
||||
#define __HAL_MDIOS_WAKEUP_EXTI_GET_FLAG() (EXTI->PR & (MDIOS_WAKEUP_EXTI_LINE))
|
||||
|
||||
/**
|
||||
* @brief Clear the MDIOS WAKEUP Exti flag.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_MDIOS_WAKEUP_EXTI_CLEAR_FLAG() (EXTI->PR = (MDIOS_WAKEUP_EXTI_LINE))
|
||||
|
||||
/**
|
||||
* @brief Enables rising edge trigger to the MDIOS External interrupt line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_MDIOS_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER() EXTI->RTSR |= MDIOS_WAKEUP_EXTI_LINE
|
||||
|
||||
/**
|
||||
* @brief Disables the rising edge trigger to the MDIOS External interrupt line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_MDIOS_WAKEUP_EXTI_DISABLE_RISING_EDGE_TRIGGER() EXTI->RTSR &= ~(MDIOS_WAKEUP_EXTI_LINE)
|
||||
|
||||
/**
|
||||
* @brief Enables falling edge trigger to the MDIOS External interrupt line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_MDIOS_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR |= (MDIOS_WAKEUP_EXTI_LINE)
|
||||
|
||||
/**
|
||||
* @brief Disables falling edge trigger to the MDIOS External interrupt line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_MDIOS_WAKEUP_EXTI_DISABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR &= ~(MDIOS_WAKEUP_EXTI_LINE)
|
||||
|
||||
/**
|
||||
* @brief Enables rising/falling edge trigger to the MDIOS External interrupt line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_MDIOS_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER() EXTI->RTSR |= MDIOS_WAKEUP_EXTI_LINE;\
|
||||
EXTI->FTSR |= MDIOS_WAKEUP_EXTI_LINE
|
||||
|
||||
/**
|
||||
* @brief Disables rising/falling edge trigger to the MDIOS External interrupt line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_MDIOS_WAKEUP_EXTI_DISABLE_FALLINGRISING_TRIGGER() EXTI->RTSR &= ~(MDIOS_WAKEUP_EXTI_LINE);\
|
||||
EXTI->FTSR &= ~(MDIOS_WAKEUP_EXTI_LINE)
|
||||
/**
|
||||
* @brief Generates a Software interrupt on selected EXTI line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_MDIOS_WAKEUP_EXTI_GENERATE_SWIT() (EXTI->SWIER |= (MDIOS_WAKEUP_EXTI_LINE))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup MDIOS_Exported_Functions MDIOS Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup MDIOS_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_MDIOS_Init(MDIOS_HandleTypeDef *hmdios);
|
||||
HAL_StatusTypeDef HAL_MDIOS_DeInit(MDIOS_HandleTypeDef *hmdios);
|
||||
void HAL_MDIOS_MspInit(MDIOS_HandleTypeDef *hmdios);
|
||||
void HAL_MDIOS_MspDeInit(MDIOS_HandleTypeDef *hmdios);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup MDIOS_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_MDIOS_WriteReg(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum, uint16_t Data);
|
||||
HAL_StatusTypeDef HAL_MDIOS_ReadReg(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum, uint16_t *pData);
|
||||
|
||||
uint32_t HAL_MDIOS_GetWrittenRegAddress(MDIOS_HandleTypeDef *hmdios);
|
||||
uint32_t HAL_MDIOS_GetReadRegAddress(MDIOS_HandleTypeDef *hmdios);
|
||||
HAL_StatusTypeDef HAL_MDIOS_ClearWriteRegAddress(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum);
|
||||
HAL_StatusTypeDef HAL_MDIOS_ClearReadRegAddress(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum);
|
||||
|
||||
HAL_StatusTypeDef HAL_MDIOS_EnableEvents(MDIOS_HandleTypeDef *hmdios);
|
||||
void HAL_MDIOS_IRQHandler(MDIOS_HandleTypeDef *hmdios);
|
||||
void HAL_MDIOS_WriteCpltCallback(MDIOS_HandleTypeDef *hmdios);
|
||||
void HAL_MDIOS_ReadCpltCallback(MDIOS_HandleTypeDef *hmdios);
|
||||
void HAL_MDIOS_ErrorCallback(MDIOS_HandleTypeDef *hmdios);
|
||||
void HAL_MDIOS_WakeUpCallback(MDIOS_HandleTypeDef *hmdios);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup MDIOS_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
uint32_t HAL_MDIOS_GetError(MDIOS_HandleTypeDef *hmdios);
|
||||
HAL_MDIOS_StateTypeDef HAL_MDIOS_GetState(MDIOS_HandleTypeDef *hmdios);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/** @defgroup MDIOS_Private_Types MDIOS Private Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/** @defgroup MDIOS_Private_Variables MDIOS Private Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup MDIOS_Private_Constants MDIOS Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup MDIOS_Private_Macros MDIOS Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_MDIOS_PORTADDRESS(__ADDR__) ((__ADDR__) < 32)
|
||||
|
||||
#define IS_MDIOS_REGISTER(__REGISTER__) ((__REGISTER__) < 32)
|
||||
|
||||
#define IS_MDIOS_PREAMBLECHECK(__PREAMBLECHECK__) (((__PREAMBLECHECK__) == MDIOS_PREAMBLE_CHECK_ENABLE) || \
|
||||
((__PREAMBLECHECK__) == MDIOS_PREAMBLE_CHECK_DISABLE))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup MDIOS_Private_Functions MDIOS Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* MDIOS */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F7xx_HAL_MDIOS_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,695 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_hal_mmc.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.2
|
||||
* @date 14-April-2017
|
||||
* @brief Header file of MMC HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F7xx_HAL_MMC_H
|
||||
#define __STM32F7xx_HAL_MMC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx_ll_sdmmc.h"
|
||||
|
||||
/** @addtogroup STM32F7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup MMC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup MMC_Exported_Types MMC Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup MMC_Exported_Types_Group1 MMC State enumeration structure
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_MMC_STATE_RESET = ((uint32_t)0x00000000U), /*!< MMC not yet initialized or disabled */
|
||||
HAL_MMC_STATE_READY = ((uint32_t)0x00000001U), /*!< MMC initialized and ready for use */
|
||||
HAL_MMC_STATE_TIMEOUT = ((uint32_t)0x00000002U), /*!< MMC Timeout state */
|
||||
HAL_MMC_STATE_BUSY = ((uint32_t)0x00000003U), /*!< MMC process ongoing */
|
||||
HAL_MMC_STATE_PROGRAMMING = ((uint32_t)0x00000004U), /*!< MMC Programming State */
|
||||
HAL_MMC_STATE_RECEIVING = ((uint32_t)0x00000005U), /*!< MMC Receinving State */
|
||||
HAL_MMC_STATE_TRANSFER = ((uint32_t)0x00000006U), /*!< MMC Transfert State */
|
||||
HAL_MMC_STATE_ERROR = ((uint32_t)0x0000000FU) /*!< MMC is in error state */
|
||||
}HAL_MMC_StateTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup MMC_Exported_Types_Group2 MMC Card State enumeration structure
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_MMC_CARD_READY = ((uint32_t)0x00000001U), /*!< Card state is ready */
|
||||
HAL_MMC_CARD_IDENTIFICATION = ((uint32_t)0x00000002U), /*!< Card is in identification state */
|
||||
HAL_MMC_CARD_STANDBY = ((uint32_t)0x00000003U), /*!< Card is in standby state */
|
||||
HAL_MMC_CARD_TRANSFER = ((uint32_t)0x00000004U), /*!< Card is in transfer state */
|
||||
HAL_MMC_CARD_SENDING = ((uint32_t)0x00000005U), /*!< Card is sending an operation */
|
||||
HAL_MMC_CARD_RECEIVING = ((uint32_t)0x00000006U), /*!< Card is receiving operation information */
|
||||
HAL_MMC_CARD_PROGRAMMING = ((uint32_t)0x00000007U), /*!< Card is in programming state */
|
||||
HAL_MMC_CARD_DISCONNECTED = ((uint32_t)0x00000008U), /*!< Card is disconnected */
|
||||
HAL_MMC_CARD_ERROR = ((uint32_t)0x000000FFU) /*!< Card response Error */
|
||||
}HAL_MMC_CardStateTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup MMC_Exported_Types_Group3 MMC Handle Structure definition
|
||||
* @{
|
||||
*/
|
||||
#define MMC_InitTypeDef SDMMC_InitTypeDef
|
||||
#define MMC_TypeDef SDMMC_TypeDef
|
||||
|
||||
/**
|
||||
* @brief MMC Card Information Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t CardType; /*!< Specifies the card Type */
|
||||
|
||||
uint32_t Class; /*!< Specifies the class of the card class */
|
||||
|
||||
uint32_t RelCardAdd; /*!< Specifies the Relative Card Address */
|
||||
|
||||
uint32_t BlockNbr; /*!< Specifies the Card Capacity in blocks */
|
||||
|
||||
uint32_t BlockSize; /*!< Specifies one block size in bytes */
|
||||
|
||||
uint32_t LogBlockNbr; /*!< Specifies the Card logical Capacity in blocks */
|
||||
|
||||
uint32_t LogBlockSize; /*!< Specifies logical block size in bytes */
|
||||
|
||||
}HAL_MMC_CardInfoTypeDef;
|
||||
|
||||
/**
|
||||
* @brief MMC handle Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
MMC_TypeDef *Instance; /*!< MMC registers base address */
|
||||
|
||||
MMC_InitTypeDef Init; /*!< MMC required parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< MMC locking object */
|
||||
|
||||
uint32_t *pTxBuffPtr; /*!< Pointer to MMC Tx transfer Buffer */
|
||||
|
||||
uint32_t TxXferSize; /*!< MMC Tx Transfer size */
|
||||
|
||||
uint32_t *pRxBuffPtr; /*!< Pointer to MMC Rx transfer Buffer */
|
||||
|
||||
uint32_t RxXferSize; /*!< MMC Rx Transfer size */
|
||||
|
||||
__IO uint32_t Context; /*!< MMC transfer context */
|
||||
|
||||
__IO HAL_MMC_StateTypeDef State; /*!< MMC card State */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< MMC Card Error codes */
|
||||
|
||||
DMA_HandleTypeDef *hdmarx; /*!< MMC Rx DMA handle parameters */
|
||||
|
||||
DMA_HandleTypeDef *hdmatx; /*!< MMC Tx DMA handle parameters */
|
||||
|
||||
HAL_MMC_CardInfoTypeDef MmcCard; /*!< MMC Card information */
|
||||
|
||||
uint32_t CSD[4]; /*!< MMC card specific data table */
|
||||
|
||||
uint32_t CID[4]; /*!< MMC card identification number table */
|
||||
|
||||
}MMC_HandleTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup MMC_Exported_Types_Group4 Card Specific Data: CSD Register
|
||||
* @{
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint8_t CSDStruct; /*!< CSD structure */
|
||||
__IO uint8_t SysSpecVersion; /*!< System specification version */
|
||||
__IO uint8_t Reserved1; /*!< Reserved */
|
||||
__IO uint8_t TAAC; /*!< Data read access time 1 */
|
||||
__IO uint8_t NSAC; /*!< Data read access time 2 in CLK cycles */
|
||||
__IO uint8_t MaxBusClkFrec; /*!< Max. bus clock frequency */
|
||||
__IO uint16_t CardComdClasses; /*!< Card command classes */
|
||||
__IO uint8_t RdBlockLen; /*!< Max. read data block length */
|
||||
__IO uint8_t PartBlockRead; /*!< Partial blocks for read allowed */
|
||||
__IO uint8_t WrBlockMisalign; /*!< Write block misalignment */
|
||||
__IO uint8_t RdBlockMisalign; /*!< Read block misalignment */
|
||||
__IO uint8_t DSRImpl; /*!< DSR implemented */
|
||||
__IO uint8_t Reserved2; /*!< Reserved */
|
||||
__IO uint32_t DeviceSize; /*!< Device Size */
|
||||
__IO uint8_t MaxRdCurrentVDDMin; /*!< Max. read current @ VDD min */
|
||||
__IO uint8_t MaxRdCurrentVDDMax; /*!< Max. read current @ VDD max */
|
||||
__IO uint8_t MaxWrCurrentVDDMin; /*!< Max. write current @ VDD min */
|
||||
__IO uint8_t MaxWrCurrentVDDMax; /*!< Max. write current @ VDD max */
|
||||
__IO uint8_t DeviceSizeMul; /*!< Device size multiplier */
|
||||
__IO uint8_t EraseGrSize; /*!< Erase group size */
|
||||
__IO uint8_t EraseGrMul; /*!< Erase group size multiplier */
|
||||
__IO uint8_t WrProtectGrSize; /*!< Write protect group size */
|
||||
__IO uint8_t WrProtectGrEnable; /*!< Write protect group enable */
|
||||
__IO uint8_t ManDeflECC; /*!< Manufacturer default ECC */
|
||||
__IO uint8_t WrSpeedFact; /*!< Write speed factor */
|
||||
__IO uint8_t MaxWrBlockLen; /*!< Max. write data block length */
|
||||
__IO uint8_t WriteBlockPaPartial; /*!< Partial blocks for write allowed */
|
||||
__IO uint8_t Reserved3; /*!< Reserved */
|
||||
__IO uint8_t ContentProtectAppli; /*!< Content protection application */
|
||||
__IO uint8_t FileFormatGrouop; /*!< File format group */
|
||||
__IO uint8_t CopyFlag; /*!< Copy flag (OTP) */
|
||||
__IO uint8_t PermWrProtect; /*!< Permanent write protection */
|
||||
__IO uint8_t TempWrProtect; /*!< Temporary write protection */
|
||||
__IO uint8_t FileFormat; /*!< File format */
|
||||
__IO uint8_t ECC; /*!< ECC code */
|
||||
__IO uint8_t CSD_CRC; /*!< CSD CRC */
|
||||
__IO uint8_t Reserved4; /*!< Always 1 */
|
||||
|
||||
}HAL_MMC_CardCSDTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup MMC_Exported_Types_Group5 Card Identification Data: CID Register
|
||||
* @{
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint8_t ManufacturerID; /*!< Manufacturer ID */
|
||||
__IO uint16_t OEM_AppliID; /*!< OEM/Application ID */
|
||||
__IO uint32_t ProdName1; /*!< Product Name part1 */
|
||||
__IO uint8_t ProdName2; /*!< Product Name part2 */
|
||||
__IO uint8_t ProdRev; /*!< Product Revision */
|
||||
__IO uint32_t ProdSN; /*!< Product Serial Number */
|
||||
__IO uint8_t Reserved1; /*!< Reserved1 */
|
||||
__IO uint16_t ManufactDate; /*!< Manufacturing Date */
|
||||
__IO uint8_t CID_CRC; /*!< CID CRC */
|
||||
__IO uint8_t Reserved2; /*!< Always 1 */
|
||||
|
||||
}HAL_MMC_CardCIDTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup MMC_Exported_Constants Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define BLOCKSIZE ((uint32_t)512U) /*!< Block size is 512 bytes */
|
||||
#define CAPACITY ((uint32_t)0x80000000U) /*!< 2 G bytes constant */
|
||||
|
||||
/** @defgroup MMC_Exported_Constansts_Group1 MMC Error status enumeration Structure definition
|
||||
* @{
|
||||
*/
|
||||
#define HAL_MMC_ERROR_NONE SDMMC_ERROR_NONE /*!< No error */
|
||||
#define HAL_MMC_ERROR_CMD_CRC_FAIL SDMMC_ERROR_CMD_CRC_FAIL /*!< Command response received (but CRC check failed) */
|
||||
#define HAL_MMC_ERROR_DATA_CRC_FAIL SDMMC_ERROR_DATA_CRC_FAIL /*!< Data block sent/received (CRC check failed) */
|
||||
#define HAL_MMC_ERROR_CMD_RSP_TIMEOUT SDMMC_ERROR_CMD_RSP_TIMEOUT /*!< Command response timeout */
|
||||
#define HAL_MMC_ERROR_DATA_TIMEOUT SDMMC_ERROR_DATA_TIMEOUT /*!< Data timeout */
|
||||
#define HAL_MMC_ERROR_TX_UNDERRUN SDMMC_ERROR_TX_UNDERRUN /*!< Transmit FIFO underrun */
|
||||
#define HAL_MMC_ERROR_RX_OVERRUN SDMMC_ERROR_RX_OVERRUN /*!< Receive FIFO overrun */
|
||||
#define HAL_MMC_ERROR_ADDR_MISALIGNED SDMMC_ERROR_ADDR_MISALIGNED /*!< Misaligned address */
|
||||
#define HAL_MMC_ERROR_BLOCK_LEN_ERR SDMMC_ERROR_BLOCK_LEN_ERR /*!< Transferred block length is not allowed for the card or the
|
||||
number of transferred bytes does not match the block length */
|
||||
#define HAL_MMC_ERROR_ERASE_SEQ_ERR SDMMC_ERROR_ERASE_SEQ_ERR /*!< An error in the sequence of erase command occurs */
|
||||
#define HAL_MMC_ERROR_BAD_ERASE_PARAM SDMMC_ERROR_BAD_ERASE_PARAM /*!< An invalid selection for erase groups */
|
||||
#define HAL_MMC_ERROR_WRITE_PROT_VIOLATION SDMMC_ERROR_WRITE_PROT_VIOLATION /*!< Attempt to program a write protect block */
|
||||
#define HAL_MMC_ERROR_LOCK_UNLOCK_FAILED SDMMC_ERROR_LOCK_UNLOCK_FAILED /*!< Sequence or password error has been detected in unlock
|
||||
command or if there was an attempt to access a locked card */
|
||||
#define HAL_MMC_ERROR_COM_CRC_FAILED SDMMC_ERROR_COM_CRC_FAILED /*!< CRC check of the previous command failed */
|
||||
#define HAL_MMC_ERROR_ILLEGAL_CMD SDMMC_ERROR_ILLEGAL_CMD /*!< Command is not legal for the card state */
|
||||
#define HAL_MMC_ERROR_CARD_ECC_FAILED SDMMC_ERROR_CARD_ECC_FAILED /*!< Card internal ECC was applied but failed to correct the data */
|
||||
#define HAL_MMC_ERROR_CC_ERR SDMMC_ERROR_CC_ERR /*!< Internal card controller error */
|
||||
#define HAL_MMC_ERROR_GENERAL_UNKNOWN_ERR SDMMC_ERROR_GENERAL_UNKNOWN_ERR /*!< General or unknown error */
|
||||
#define HAL_MMC_ERROR_STREAM_READ_UNDERRUN SDMMC_ERROR_STREAM_READ_UNDERRUN /*!< The card could not sustain data reading in stream rmode */
|
||||
#define HAL_MMC_ERROR_STREAM_WRITE_OVERRUN SDMMC_ERROR_STREAM_WRITE_OVERRUN /*!< The card could not sustain data programming in stream mode */
|
||||
#define HAL_MMC_ERROR_CID_CSD_OVERWRITE SDMMC_ERROR_CID_CSD_OVERWRITE /*!< CID/CSD overwrite error */
|
||||
#define HAL_MMC_ERROR_WP_ERASE_SKIP SDMMC_ERROR_WP_ERASE_SKIP /*!< Only partial address space was erased */
|
||||
#define HAL_MMC_ERROR_CARD_ECC_DISABLED SDMMC_ERROR_CARD_ECC_DISABLED /*!< Command has been executed without using internal ECC */
|
||||
#define HAL_MMC_ERROR_ERASE_RESET SDMMC_ERROR_ERASE_RESET /*!< Erase sequence was cleared before executing because an out
|
||||
of erase sequence command was received */
|
||||
#define HAL_MMC_ERROR_AKE_SEQ_ERR SDMMC_ERROR_AKE_SEQ_ERR /*!< Error in sequence of authentication */
|
||||
#define HAL_MMC_ERROR_INVALID_VOLTRANGE SDMMC_ERROR_INVALID_VOLTRANGE /*!< Error in case of invalid voltage range */
|
||||
#define HAL_MMC_ERROR_ADDR_OUT_OF_RANGE SDMMC_ERROR_ADDR_OUT_OF_RANGE /*!< Error when addressed block is out of range */
|
||||
#define HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE SDMMC_ERROR_REQUEST_NOT_APPLICABLE /*!< Error when command request is not applicable */
|
||||
#define HAL_MMC_ERROR_PARAM SDMMC_ERROR_INVALID_PARAMETER /*!< the used parameter is not valid */
|
||||
#define HAL_MMC_ERROR_UNSUPPORTED_FEATURE SDMMC_ERROR_UNSUPPORTED_FEATURE /*!< Error when feature is not insupported */
|
||||
#define HAL_MMC_ERROR_BUSY SDMMC_ERROR_BUSY /*!< Error when transfer process is busy */
|
||||
#define HAL_MMC_ERROR_DMA SDMMC_ERROR_DMA /*!< Error while DMA transfer */
|
||||
#define HAL_MMC_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT /*!< Timeout error */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup MMC_Exported_Constansts_Group2 MMC context enumeration
|
||||
* @{
|
||||
*/
|
||||
#define MMC_CONTEXT_NONE ((uint32_t)0x00000000U) /*!< None */
|
||||
#define MMC_CONTEXT_READ_SINGLE_BLOCK ((uint32_t)0x00000001U) /*!< Read single block operation */
|
||||
#define MMC_CONTEXT_READ_MULTIPLE_BLOCK ((uint32_t)0x00000002U) /*!< Read multiple blocks operation */
|
||||
#define MMC_CONTEXT_WRITE_SINGLE_BLOCK ((uint32_t)0x00000010U) /*!< Write single block operation */
|
||||
#define MMC_CONTEXT_WRITE_MULTIPLE_BLOCK ((uint32_t)0x00000020U) /*!< Write multiple blocks operation */
|
||||
#define MMC_CONTEXT_IT ((uint32_t)0x00000008U) /*!< Process in Interrupt mode */
|
||||
#define MMC_CONTEXT_DMA ((uint32_t)0x00000080U) /*!< Process in DMA mode */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup MMC_Exported_Constansts_Group3 MMC Voltage mode
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief
|
||||
*/
|
||||
#define MMC_HIGH_VOLTAGE_RANGE 0x80FF8000U /*!< VALUE OF ARGUMENT */
|
||||
#define MMC_DUAL_VOLTAGE_RANGE 0x80FF8080U /*!< VALUE OF ARGUMENT */
|
||||
#define eMMC_HIGH_VOLTAGE_RANGE 0xC0FF8000U /*!< for eMMC > 2Gb sector mode */
|
||||
#define eMMC_DUAL_VOLTAGE_RANGE 0xC0FF8080U /*!< for eMMC > 2Gb sector mode */
|
||||
#define MMC_INVALID_VOLTAGE_RANGE 0x0001FF01U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup MMC_Exported_Constansts_Group4 MMC Memory Cards
|
||||
* @{
|
||||
*/
|
||||
#define MMC_HIGH_VOLTAGE_CARD ((uint32_t)0x00000000U)
|
||||
#define MMC_DUAL_VOLTAGE_CARD ((uint32_t)0x00000001U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup MMC_Exported_macros MMC Exported Macros
|
||||
* @brief macros to handle interrupts and specific clock configurations
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable the MMC device.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_MMC_ENABLE(__HANDLE__) __SDMMC_ENABLE((__HANDLE__)->Instance)
|
||||
|
||||
/**
|
||||
* @brief Disable the MMC device.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_MMC_DISABLE(__HANDLE__) __SDMMC_DISABLE((__HANDLE__)->Instance)
|
||||
|
||||
/**
|
||||
* @brief Enable the SDMMC DMA transfer.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_MMC_DMA_ENABLE(__HANDLE__) __SDMMC_DMA_ENABLE((__HANDLE__)->Instance)
|
||||
|
||||
/**
|
||||
* @brief Disable the SDMMC DMA transfer.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_MMC_DMA_DISABLE(__HANDLE__) __SDMMC_DMA_DISABLE((__HANDLE__)->Instance)
|
||||
|
||||
/**
|
||||
* @brief Enable the MMC device interrupt.
|
||||
* @param __HANDLE__: MMC Handle
|
||||
* @param __INTERRUPT__: specifies the SDMMC interrupt sources to be enabled.
|
||||
* This parameter can be one or a combination of the following values:
|
||||
* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
|
||||
* @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
|
||||
* @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
|
||||
* @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
|
||||
* @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
|
||||
* @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
|
||||
* @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
|
||||
* @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
|
||||
* @arg SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
|
||||
* @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
|
||||
* @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt
|
||||
* @arg SDMMC_IT_TXACT: Data transmit in progress interrupt
|
||||
* @arg SDMMC_IT_RXACT: Data receive in progress interrupt
|
||||
* @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
|
||||
* @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
|
||||
* @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt
|
||||
* @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
|
||||
* @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
|
||||
* @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt
|
||||
* @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt
|
||||
* @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt
|
||||
* @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_MMC_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Disable the MMC device interrupt.
|
||||
* @param __HANDLE__: MMC Handle
|
||||
* @param __INTERRUPT__: specifies the SDMMC interrupt sources to be disabled.
|
||||
* This parameter can be one or a combination of the following values:
|
||||
* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
|
||||
* @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
|
||||
* @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
|
||||
* @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
|
||||
* @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
|
||||
* @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
|
||||
* @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
|
||||
* @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
|
||||
* @arg SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
|
||||
* @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
|
||||
* @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt
|
||||
* @arg SDMMC_IT_TXACT: Data transmit in progress interrupt
|
||||
* @arg SDMMC_IT_RXACT: Data receive in progress interrupt
|
||||
* @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
|
||||
* @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
|
||||
* @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt
|
||||
* @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
|
||||
* @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
|
||||
* @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt
|
||||
* @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt
|
||||
* @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt
|
||||
* @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_MMC_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified MMC flag is set or not.
|
||||
* @param __HANDLE__: MMC Handle
|
||||
* @param __FLAG__: specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
|
||||
* @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
|
||||
* @arg SDMMC_FLAG_CTIMEOUT: Command response timeout
|
||||
* @arg SDMMC_FLAG_DTIMEOUT: Data timeout
|
||||
* @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error
|
||||
* @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error
|
||||
* @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed)
|
||||
* @arg SDMMC_FLAG_CMDSENT: Command sent (no response required)
|
||||
* @arg SDMMC_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
|
||||
* @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed)
|
||||
* @arg SDMMC_FLAG_CMDACT: Command transfer in progress
|
||||
* @arg SDMMC_FLAG_TXACT: Data transmit in progress
|
||||
* @arg SDMMC_FLAG_RXACT: Data receive in progress
|
||||
* @arg SDMMC_FLAG_TXFIFOHE: Transmit FIFO Half Empty
|
||||
* @arg SDMMC_FLAG_RXFIFOHF: Receive FIFO Half Full
|
||||
* @arg SDMMC_FLAG_TXFIFOF: Transmit FIFO full
|
||||
* @arg SDMMC_FLAG_RXFIFOF: Receive FIFO full
|
||||
* @arg SDMMC_FLAG_TXFIFOE: Transmit FIFO empty
|
||||
* @arg SDMMC_FLAG_RXFIFOE: Receive FIFO empty
|
||||
* @arg SDMMC_FLAG_TXDAVL: Data available in transmit FIFO
|
||||
* @arg SDMMC_FLAG_RXDAVL: Data available in receive FIFO
|
||||
* @arg SDMMC_FLAG_SDIOIT: SD I/O interrupt received
|
||||
* @retval The new state of MMC FLAG (SET or RESET).
|
||||
*/
|
||||
#define __HAL_MMC_GET_FLAG(__HANDLE__, __FLAG__) __SDMMC_GET_FLAG((__HANDLE__)->Instance, (__FLAG__))
|
||||
|
||||
/**
|
||||
* @brief Clear the MMC's pending flags.
|
||||
* @param __HANDLE__: MMC Handle
|
||||
* @param __FLAG__: specifies the flag to clear.
|
||||
* This parameter can be one or a combination of the following values:
|
||||
* @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
|
||||
* @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
|
||||
* @arg SDMMC_FLAG_CTIMEOUT: Command response timeout
|
||||
* @arg SDMMC_FLAG_DTIMEOUT: Data timeout
|
||||
* @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error
|
||||
* @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error
|
||||
* @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed)
|
||||
* @arg SDMMC_FLAG_CMDSENT: Command sent (no response required)
|
||||
* @arg SDMMC_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
|
||||
* @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed)
|
||||
* @arg SDMMC_FLAG_SDIOIT: SD I/O interrupt received
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_MMC_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDMMC_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__))
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified MMC interrupt has occurred or not.
|
||||
* @param __HANDLE__: MMC Handle
|
||||
* @param __INTERRUPT__: specifies the SDMMC interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
|
||||
* @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
|
||||
* @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
|
||||
* @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
|
||||
* @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
|
||||
* @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
|
||||
* @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
|
||||
* @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
|
||||
* @arg SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
|
||||
* @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
|
||||
* @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt
|
||||
* @arg SDMMC_IT_TXACT: Data transmit in progress interrupt
|
||||
* @arg SDMMC_IT_RXACT: Data receive in progress interrupt
|
||||
* @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
|
||||
* @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
|
||||
* @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt
|
||||
* @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
|
||||
* @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
|
||||
* @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt
|
||||
* @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt
|
||||
* @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt
|
||||
* @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
|
||||
* @retval The new state of SD IT (SET or RESET).
|
||||
*/
|
||||
#define __HAL_MMC_GET_IT(__HANDLE__, __INTERRUPT__) __SDMMC_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Clear the MMC's interrupt pending bits.
|
||||
* @param __HANDLE__: MMC Handle
|
||||
* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
|
||||
* This parameter can be one or a combination of the following values:
|
||||
* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
|
||||
* @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
|
||||
* @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
|
||||
* @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
|
||||
* @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
|
||||
* @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
|
||||
* @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
|
||||
* @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
|
||||
* @arg SDMMC_IT_DATAEND: Data end (data counter, SDMMC_DCOUNT, is zero) interrupt
|
||||
* @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_MMC_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDMMC_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup MMC_Exported_Functions MMC Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup MMC_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_MMC_Init(MMC_HandleTypeDef *hmmc);
|
||||
HAL_StatusTypeDef HAL_MMC_InitCard(MMC_HandleTypeDef *hmmc);
|
||||
HAL_StatusTypeDef HAL_MMC_DeInit (MMC_HandleTypeDef *hmmc);
|
||||
void HAL_MMC_MspInit(MMC_HandleTypeDef *hmmc);
|
||||
void HAL_MMC_MspDeInit(MMC_HandleTypeDef *hmmc);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup MMC_Exported_Functions_Group2 Input and Output operation functions
|
||||
* @{
|
||||
*/
|
||||
/* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_MMC_Erase(MMC_HandleTypeDef *hmmc, uint32_t BlockStartAdd, uint32_t BlockEndAdd);
|
||||
/* Non-Blocking mode: IT */
|
||||
HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
|
||||
HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
|
||||
/* Non-Blocking mode: DMA */
|
||||
HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
|
||||
HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
|
||||
|
||||
void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc);
|
||||
|
||||
/* Callback in non blocking modes (DMA) */
|
||||
void HAL_MMC_TxCpltCallback(MMC_HandleTypeDef *hmmc);
|
||||
void HAL_MMC_RxCpltCallback(MMC_HandleTypeDef *hmmc);
|
||||
void HAL_MMC_ErrorCallback(MMC_HandleTypeDef *hmmc);
|
||||
void HAL_MMC_AbortCallback(MMC_HandleTypeDef *hmmc);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup MMC_Exported_Functions_Group3 Peripheral Control functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation(MMC_HandleTypeDef *hmmc, uint32_t WideMode);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup MMC_Exported_Functions_Group4 MMC card related functions
|
||||
* @{
|
||||
*/
|
||||
HAL_MMC_CardStateTypeDef HAL_MMC_GetCardState(MMC_HandleTypeDef *hmmc);
|
||||
HAL_StatusTypeDef HAL_MMC_GetCardCID(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypeDef *pCID);
|
||||
HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTypeDef *pCSD);
|
||||
HAL_StatusTypeDef HAL_MMC_GetCardInfo(MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup MMC_Exported_Functions_Group5 Peripheral State and Errors functions
|
||||
* @{
|
||||
*/
|
||||
HAL_MMC_StateTypeDef HAL_MMC_GetState(MMC_HandleTypeDef *hmmc);
|
||||
uint32_t HAL_MMC_GetError(MMC_HandleTypeDef *hmmc);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup MMC_Exported_Functions_Group6 Perioheral Abort management
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_MMC_Abort(MMC_HandleTypeDef *hmmc);
|
||||
HAL_StatusTypeDef HAL_MMC_Abort_IT(MMC_HandleTypeDef *hmmc);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/** @defgroup MMC_Private_Types MMC Private Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private defines -----------------------------------------------------------*/
|
||||
/** @defgroup MMC_Private_Defines MMC Private Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/** @defgroup MMC_Private_Variables MMC Private Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup MMC_Private_Constants MMC Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup MMC_Private_Macros MMC Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions prototypes ----------------------------------------------*/
|
||||
/** @defgroup MMC_Private_Functions_Prototypes MMC Private Functions Prototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup MMC_Private_Functions MMC Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* __STM32F7xx_HAL_MMC_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,336 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_hal_nand.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.2
|
||||
* @date 14-April-2017
|
||||
* @brief Header file of NAND HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F7xx_HAL_NAND_H
|
||||
#define __STM32F7xx_HAL_NAND_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx_ll_fmc.h"
|
||||
|
||||
/** @addtogroup STM32F7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup NAND
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported typedef ----------------------------------------------------------*/
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup NAND_Exported_Types NAND Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief HAL NAND State structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_NAND_STATE_RESET = 0x00U, /*!< NAND not yet initialized or disabled */
|
||||
HAL_NAND_STATE_READY = 0x01U, /*!< NAND initialized and ready for use */
|
||||
HAL_NAND_STATE_BUSY = 0x02U, /*!< NAND internal process is ongoing */
|
||||
HAL_NAND_STATE_ERROR = 0x03U /*!< NAND error state */
|
||||
}HAL_NAND_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief NAND Memory electronic signature Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
/*<! NAND memory electronic signature maker and device IDs */
|
||||
|
||||
uint8_t Maker_Id;
|
||||
|
||||
uint8_t Device_Id;
|
||||
|
||||
uint8_t Third_Id;
|
||||
|
||||
uint8_t Fourth_Id;
|
||||
}NAND_IDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief NAND Memory address Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint16_t Page; /*!< NAND memory Page address */
|
||||
|
||||
uint16_t Plane; /*!< NAND memory Zone address */
|
||||
|
||||
uint16_t Block; /*!< NAND memory Block address */
|
||||
|
||||
}NAND_AddressTypeDef;
|
||||
|
||||
/**
|
||||
* @brief NAND Memory info Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t PageSize; /*!< NAND memory page (without spare area) size measured in bytes
|
||||
for 8 bits adressing or words for 16 bits addressing */
|
||||
|
||||
uint32_t SpareAreaSize; /*!< NAND memory spare area size measured in bytes
|
||||
for 8 bits adressing or words for 16 bits addressing */
|
||||
|
||||
uint32_t BlockSize; /*!< NAND memory block size measured in number of pages */
|
||||
|
||||
uint32_t BlockNbr; /*!< NAND memory number of total blocks */
|
||||
|
||||
uint32_t PlaneNbr; /*!< NAND memory number of planes */
|
||||
|
||||
uint32_t PlaneSize; /*!< NAND memory zone size measured in number of blocks */
|
||||
|
||||
FunctionalState ExtraCommandEnable; /*!< NAND extra command needed for Page reading mode. This
|
||||
parameter is mandatory for some NAND parts after the read
|
||||
command (NAND_CMD_AREA_TRUE1) and before DATA reading sequence.
|
||||
Example: Toshiba THTH58BYG3S0HBAI6.
|
||||
This parameter could be ENABLE or DISABLE
|
||||
Please check the Read Mode sequnece in the NAND device datasheet */
|
||||
}NAND_DeviceConfigTypeDef;
|
||||
|
||||
/**
|
||||
* @brief NAND handle Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
FMC_NAND_TypeDef *Instance; /*!< Register base address */
|
||||
|
||||
FMC_NAND_InitTypeDef Init; /*!< NAND device control configuration parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< NAND locking object */
|
||||
|
||||
__IO HAL_NAND_StateTypeDef State; /*!< NAND device access state */
|
||||
|
||||
NAND_DeviceConfigTypeDef Config; /*!< NAND phusical characteristic information structure */
|
||||
|
||||
}NAND_HandleTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup NAND_Exported_Macros NAND Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset NAND handle state
|
||||
* @param __HANDLE__: specifies the NAND handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup NAND_Exported_Functions NAND Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Initialization/de-initialization functions ********************************/
|
||||
HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing);
|
||||
HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand);
|
||||
|
||||
HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig);
|
||||
|
||||
HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID);
|
||||
|
||||
void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand);
|
||||
void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand);
|
||||
void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand);
|
||||
void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup NAND_Exported_Functions_Group2 Input and Output functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* IO operation functions ****************************************************/
|
||||
|
||||
HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand);
|
||||
|
||||
HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead);
|
||||
HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite);
|
||||
HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
|
||||
HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
|
||||
|
||||
HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead);
|
||||
HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite);
|
||||
HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead);
|
||||
HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite);
|
||||
|
||||
HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
|
||||
|
||||
uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup NAND_Exported_Functions_Group3 Peripheral Control functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* NAND Control functions ****************************************************/
|
||||
HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand);
|
||||
HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand);
|
||||
HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup NAND_Exported_Functions_Group4 Peripheral State functions
|
||||
* @{
|
||||
*/
|
||||
/* NAND State functions *******************************************************/
|
||||
HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand);
|
||||
uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup NAND_Private_Constants NAND Private Constants
|
||||
* @{
|
||||
*/
|
||||
#define NAND_DEVICE ((uint32_t)0x80000000U)
|
||||
#define NAND_WRITE_TIMEOUT ((uint32_t)0x01000000U)
|
||||
|
||||
#define CMD_AREA ((uint32_t)(1<<16)) /* A16 = CLE high */
|
||||
#define ADDR_AREA ((uint32_t)(1<<17)) /* A17 = ALE high */
|
||||
|
||||
#define NAND_CMD_AREA_A ((uint8_t)0x00U)
|
||||
#define NAND_CMD_AREA_B ((uint8_t)0x01U)
|
||||
#define NAND_CMD_AREA_C ((uint8_t)0x50U)
|
||||
#define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30U)
|
||||
|
||||
#define NAND_CMD_WRITE0 ((uint8_t)0x80U)
|
||||
#define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10U)
|
||||
#define NAND_CMD_ERASE0 ((uint8_t)0x60U)
|
||||
#define NAND_CMD_ERASE1 ((uint8_t)0xD0U)
|
||||
#define NAND_CMD_READID ((uint8_t)0x90U)
|
||||
#define NAND_CMD_STATUS ((uint8_t)0x70U)
|
||||
#define NAND_CMD_LOCK_STATUS ((uint8_t)0x7AU)
|
||||
#define NAND_CMD_RESET ((uint8_t)0xFFU)
|
||||
|
||||
/* NAND memory status */
|
||||
#define NAND_VALID_ADDRESS ((uint32_t)0x00000100U)
|
||||
#define NAND_INVALID_ADDRESS ((uint32_t)0x00000200U)
|
||||
#define NAND_TIMEOUT_ERROR ((uint32_t)0x00000400U)
|
||||
#define NAND_BUSY ((uint32_t)0x00000000U)
|
||||
#define NAND_ERROR ((uint32_t)0x00000001U)
|
||||
#define NAND_READY ((uint32_t)0x00000040U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup NAND_Private_Macros NAND Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief NAND memory address computation.
|
||||
* @param __ADDRESS__: NAND memory address.
|
||||
* @param __HANDLE__ : NAND handle.
|
||||
* @retval NAND Raw address value
|
||||
*/
|
||||
#define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \
|
||||
(((__ADDRESS__)->Block + (((__ADDRESS__)->Plane) * ((__HANDLE__)->Config.PlaneSize)))* ((__HANDLE__)->Config.BlockSize)))
|
||||
|
||||
#define COLUMN_ADDRESS( __HANDLE__) ((__HANDLE__)->Config.PageSize)
|
||||
|
||||
/**
|
||||
* @brief NAND memory address cycling.
|
||||
* @param __ADDRESS__: NAND memory address.
|
||||
* @retval NAND address cycling value.
|
||||
*/
|
||||
#define ADDR_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st addressing cycle */
|
||||
#define ADDR_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd addressing cycle */
|
||||
#define ADDR_3RD_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 16) /* 3rd addressing cycle */
|
||||
#define ADDR_4TH_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 24) /* 4th addressing cycle */
|
||||
|
||||
/**
|
||||
* @brief NAND memory Columns cycling.
|
||||
* @param __ADDRESS__: NAND memory address.
|
||||
* @retval NAND Column address cycling value.
|
||||
*/
|
||||
#define COLUMN_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st Column addressing cycle */
|
||||
#define COLUMN_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd Column addressing cycle */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F7xx_HAL_NAND_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,299 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_hal_nor.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.2
|
||||
* @date 14-April-2017
|
||||
* @brief Header file of NOR HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F7xx_HAL_NOR_H
|
||||
#define __STM32F7xx_HAL_NOR_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx_ll_fmc.h"
|
||||
|
||||
|
||||
/** @addtogroup STM32F7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup NOR
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported typedef ----------------------------------------------------------*/
|
||||
/** @defgroup NOR_Exported_Types NOR Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief HAL SRAM State structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_NOR_STATE_RESET = 0x00U, /*!< NOR not yet initialized or disabled */
|
||||
HAL_NOR_STATE_READY = 0x01U, /*!< NOR initialized and ready for use */
|
||||
HAL_NOR_STATE_BUSY = 0x02U, /*!< NOR internal processing is ongoing */
|
||||
HAL_NOR_STATE_ERROR = 0x03U, /*!< NOR error state */
|
||||
HAL_NOR_STATE_PROTECTED = 0x04U /*!< NOR NORSRAM device write protected */
|
||||
}HAL_NOR_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief FMC NOR Status typedef
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_NOR_STATUS_SUCCESS = 0U,
|
||||
HAL_NOR_STATUS_ONGOING,
|
||||
HAL_NOR_STATUS_ERROR,
|
||||
HAL_NOR_STATUS_TIMEOUT
|
||||
}HAL_NOR_StatusTypeDef;
|
||||
|
||||
/**
|
||||
* @brief FMC NOR ID typedef
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint16_t Manufacturer_Code; /*!< Defines the device's manufacturer code used to identify the memory */
|
||||
|
||||
uint16_t Device_Code1;
|
||||
|
||||
uint16_t Device_Code2;
|
||||
|
||||
uint16_t Device_Code3; /*!< Defines the device's codes used to identify the memory.
|
||||
These codes can be accessed by performing read operations with specific
|
||||
control signals and addresses set.They can also be accessed by issuing
|
||||
an Auto Select command */
|
||||
}NOR_IDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief FMC NOR CFI typedef
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
/*!< Defines the information stored in the memory's Common flash interface
|
||||
which contains a description of various electrical and timing parameters,
|
||||
density information and functions supported by the memory */
|
||||
|
||||
uint16_t CFI_1;
|
||||
|
||||
uint16_t CFI_2;
|
||||
|
||||
uint16_t CFI_3;
|
||||
|
||||
uint16_t CFI_4;
|
||||
}NOR_CFITypeDef;
|
||||
|
||||
/**
|
||||
* @brief NOR handle Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
FMC_NORSRAM_TypeDef *Instance; /*!< Register base address */
|
||||
|
||||
FMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */
|
||||
|
||||
FMC_NORSRAM_InitTypeDef Init; /*!< NOR device control configuration parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< NOR locking object */
|
||||
|
||||
__IO HAL_NOR_StateTypeDef State; /*!< NOR device access state */
|
||||
|
||||
}NOR_HandleTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup NOR_Exported_Macros NOR Exported Macros
|
||||
* @{
|
||||
*/
|
||||
/** @brief Reset NOR handle state
|
||||
* @param __HANDLE__: specifies the NOR handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup NOR_Exported_Functions NOR Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Initialization/de-initialization functions ********************************/
|
||||
HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming);
|
||||
HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor);
|
||||
void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor);
|
||||
void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor);
|
||||
void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup NOR_Exported_Functions_Group2 Input and Output functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* I/O operation functions ***************************************************/
|
||||
HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID);
|
||||
HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor);
|
||||
HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
|
||||
HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
|
||||
|
||||
HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
|
||||
HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
|
||||
|
||||
HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address);
|
||||
HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address);
|
||||
HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup NOR_Exported_Functions_Group3 NOR Control functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* NOR Control functions *****************************************************/
|
||||
HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor);
|
||||
HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup NOR_Exported_Functions_Group4 NOR State functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* NOR State functions ********************************************************/
|
||||
HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor);
|
||||
HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup NOR_Private_Constants NOR Private Constants
|
||||
* @{
|
||||
*/
|
||||
/* NOR device IDs addresses */
|
||||
#define MC_ADDRESS ((uint16_t)0x0000U)
|
||||
#define DEVICE_CODE1_ADDR ((uint16_t)0x0001U)
|
||||
#define DEVICE_CODE2_ADDR ((uint16_t)0x000EU)
|
||||
#define DEVICE_CODE3_ADDR ((uint16_t)0x000FU)
|
||||
|
||||
/* NOR CFI IDs addresses */
|
||||
#define CFI1_ADDRESS ((uint16_t)0x61U)
|
||||
#define CFI2_ADDRESS ((uint16_t)0x62U)
|
||||
#define CFI3_ADDRESS ((uint16_t)0x63U)
|
||||
#define CFI4_ADDRESS ((uint16_t)0x64U)
|
||||
|
||||
/* NOR operation wait timeout */
|
||||
#define NOR_TMEOUT ((uint16_t)0xFFFFU)
|
||||
|
||||
/* NOR memory data width */
|
||||
#define NOR_MEMORY_8B ((uint8_t)0x0U)
|
||||
#define NOR_MEMORY_16B ((uint8_t)0x1U)
|
||||
|
||||
/* NOR memory device read/write start address */
|
||||
#define NOR_MEMORY_ADRESS1 ((uint32_t)0x60000000U)
|
||||
#define NOR_MEMORY_ADRESS2 ((uint32_t)0x64000000U)
|
||||
#define NOR_MEMORY_ADRESS3 ((uint32_t)0x68000000U)
|
||||
#define NOR_MEMORY_ADRESS4 ((uint32_t)0x6C000000U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup NOR_Private_Macros NOR Private Macros
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief NOR memory address shifting.
|
||||
* @param __NOR_ADDRESS: NOR base address
|
||||
* @param __NOR_MEMORY_WIDTH_: NOR memory width
|
||||
* @param __ADDRESS__: NOR memory address
|
||||
* @retval NOR shifted address value
|
||||
*/
|
||||
#define NOR_ADDR_SHIFT(__NOR_ADDRESS, __NOR_MEMORY_WIDTH_, __ADDRESS__) \
|
||||
((uint32_t)(((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_16B)? \
|
||||
((uint32_t)((__NOR_ADDRESS) + (2 * (__ADDRESS__)))): \
|
||||
((uint32_t)((__NOR_ADDRESS) + (__ADDRESS__)))))
|
||||
|
||||
/**
|
||||
* @brief NOR memory write data to specified address.
|
||||
* @param __ADDRESS__: NOR memory address
|
||||
* @param __DATA__: Data to write
|
||||
* @retval None
|
||||
*/
|
||||
#define NOR_WRITE(__ADDRESS__, __DATA__) do{ \
|
||||
(*(__IO uint16_t *)((uint32_t)(__ADDRESS__)) = (__DATA__)); \
|
||||
__DSB(); \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F7xx_HAL_NOR_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,337 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_hal_pcd.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.2
|
||||
* @date 14-April-2017
|
||||
* @brief Header file of PCD HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F7xx_HAL_PCD_H
|
||||
#define __STM32F7xx_HAL_PCD_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx_ll_usb.h"
|
||||
|
||||
/** @addtogroup STM32F7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup PCD
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup PCD_Exported_Types PCD Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief PCD State structure definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_PCD_STATE_RESET = 0x00U,
|
||||
HAL_PCD_STATE_READY = 0x01U,
|
||||
HAL_PCD_STATE_ERROR = 0x02U,
|
||||
HAL_PCD_STATE_BUSY = 0x03U,
|
||||
HAL_PCD_STATE_TIMEOUT = 0x04U
|
||||
} PCD_StateTypeDef;
|
||||
|
||||
/* Device LPM suspend state */
|
||||
typedef enum
|
||||
{
|
||||
LPM_L0 = 0x00U, /* on */
|
||||
LPM_L1 = 0x01U, /* LPM L1 sleep */
|
||||
LPM_L2 = 0x02U, /* suspend */
|
||||
LPM_L3 = 0x03U, /* off */
|
||||
}PCD_LPM_StateTypeDef;
|
||||
|
||||
typedef USB_OTG_GlobalTypeDef PCD_TypeDef;
|
||||
typedef USB_OTG_CfgTypeDef PCD_InitTypeDef;
|
||||
typedef USB_OTG_EPTypeDef PCD_EPTypeDef ;
|
||||
|
||||
/**
|
||||
* @brief PCD Handle Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
PCD_TypeDef *Instance; /*!< Register base address */
|
||||
PCD_InitTypeDef Init; /*!< PCD required parameters */
|
||||
PCD_EPTypeDef IN_ep[16]; /*!< IN endpoint parameters */
|
||||
PCD_EPTypeDef OUT_ep[16]; /*!< OUT endpoint parameters */
|
||||
HAL_LockTypeDef Lock; /*!< PCD peripheral status */
|
||||
__IO PCD_StateTypeDef State; /*!< PCD communication state */
|
||||
uint32_t Setup[12]; /*!< Setup packet buffer */
|
||||
PCD_LPM_StateTypeDef LPM_State; /*!< LPM State */
|
||||
uint32_t BESL;
|
||||
uint32_t lpm_active; /*!< Enable or disable the Link Power Management .
|
||||
This parameter can be set to ENABLE or DISABLE */
|
||||
|
||||
uint32_t battery_charging_active; /*!< Enable or disable Battery charging.
|
||||
This parameter can be set to ENABLE or DISABLE */
|
||||
void *pData; /*!< Pointer to upper stack Handler */
|
||||
} PCD_HandleTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include PCD HAL Extension module */
|
||||
#include "stm32f7xx_hal_pcd_ex.h"
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup PCD_Exported_Constants PCD Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PCD_Speed PCD Speed
|
||||
* @{
|
||||
*/
|
||||
#define PCD_SPEED_HIGH 0U
|
||||
#define PCD_SPEED_HIGH_IN_FULL 1U
|
||||
#define PCD_SPEED_FULL 2U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PCD_PHY_Module PCD PHY Module
|
||||
* @{
|
||||
*/
|
||||
#define PCD_PHY_ULPI 1U
|
||||
#define PCD_PHY_EMBEDDED 2U
|
||||
#define PCD_PHY_UTMI 3U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PCD_Turnaround_Timeout Turnaround Timeout Value
|
||||
* @{
|
||||
*/
|
||||
#ifndef USBD_HS_TRDT_VALUE
|
||||
#define USBD_HS_TRDT_VALUE 9U
|
||||
#endif /* USBD_HS_TRDT_VALUE */
|
||||
#ifndef USBD_FS_TRDT_VALUE
|
||||
#define USBD_FS_TRDT_VALUE 5U
|
||||
#endif /* USBD_HS_TRDT_VALUE */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup PCD_Exported_Macros PCD Exported Macros
|
||||
* @brief macros to handle interrupts and specific clock configurations
|
||||
* @{
|
||||
*/
|
||||
#define __HAL_PCD_ENABLE(__HANDLE__) USB_EnableGlobalInt ((__HANDLE__)->Instance)
|
||||
#define __HAL_PCD_DISABLE(__HANDLE__) USB_DisableGlobalInt ((__HANDLE__)->Instance)
|
||||
|
||||
#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
|
||||
#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__))
|
||||
#define __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0)
|
||||
|
||||
|
||||
#define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= \
|
||||
~(USB_OTG_PCGCCTL_STOPCLK)
|
||||
|
||||
#define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK
|
||||
|
||||
#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__) ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE))&0x10)
|
||||
|
||||
#define USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE ((uint32_t)0x08U)
|
||||
#define USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE ((uint32_t)0x0CU)
|
||||
#define USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE ((uint32_t)0x10U)
|
||||
|
||||
#define USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE ((uint32_t)0x08U)
|
||||
#define USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE ((uint32_t)0x0CU)
|
||||
#define USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE ((uint32_t)0x10U)
|
||||
|
||||
#define USB_OTG_HS_WAKEUP_EXTI_LINE ((uint32_t)0x00100000U) /*!< External interrupt line 20 Connected to the USB HS EXTI Line */
|
||||
#define USB_OTG_FS_WAKEUP_EXTI_LINE ((uint32_t)0x00040000U) /*!< External interrupt line 18 Connected to the USB FS EXTI Line */
|
||||
|
||||
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= (USB_OTG_HS_WAKEUP_EXTI_LINE)
|
||||
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE)
|
||||
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (USB_OTG_HS_WAKEUP_EXTI_LINE)
|
||||
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = (USB_OTG_HS_WAKEUP_EXTI_LINE)
|
||||
|
||||
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE() EXTI->FTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE);\
|
||||
EXTI->RTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE
|
||||
|
||||
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE() EXTI->FTSR |= (USB_OTG_HS_WAKEUP_EXTI_LINE);\
|
||||
EXTI->RTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE)
|
||||
|
||||
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE() EXTI->RTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE);\
|
||||
EXTI->FTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE;)\
|
||||
EXTI->RTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE;\
|
||||
EXTI->FTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE
|
||||
|
||||
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT() (EXTI->SWIER |= USB_OTG_FS_WAKEUP_EXTI_LINE)
|
||||
|
||||
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= USB_OTG_FS_WAKEUP_EXTI_LINE
|
||||
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE)
|
||||
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (USB_OTG_FS_WAKEUP_EXTI_LINE)
|
||||
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = USB_OTG_FS_WAKEUP_EXTI_LINE
|
||||
|
||||
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE() EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\
|
||||
EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE
|
||||
|
||||
|
||||
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE() EXTI->FTSR |= (USB_OTG_FS_WAKEUP_EXTI_LINE);\
|
||||
EXTI->RTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE)
|
||||
|
||||
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE() EXTI->RTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\
|
||||
EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\
|
||||
EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE;\
|
||||
EXTI->FTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE
|
||||
|
||||
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT() (EXTI->SWIER |= USB_OTG_FS_WAKEUP_EXTI_LINE)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup PCD_Exported_Functions PCD Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Initialization/de-initialization functions ********************************/
|
||||
/** @addtogroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd);
|
||||
HAL_StatusTypeDef HAL_PCD_DeInit (PCD_HandleTypeDef *hpcd);
|
||||
void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd);
|
||||
void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* I/O operation functions ***************************************************/
|
||||
/* Non-Blocking mode: Interrupt */
|
||||
/** @addtogroup PCD_Exported_Functions_Group2 Input and Output operation functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd);
|
||||
HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd);
|
||||
void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd);
|
||||
|
||||
void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
|
||||
void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
|
||||
void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd);
|
||||
void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd);
|
||||
void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd);
|
||||
void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd);
|
||||
void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd);
|
||||
void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
|
||||
void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
|
||||
void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd);
|
||||
void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Peripheral Control functions **********************************************/
|
||||
/** @addtogroup PCD_Exported_Functions_Group3 Peripheral Control functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd);
|
||||
HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd);
|
||||
HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address);
|
||||
HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type);
|
||||
HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
|
||||
HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
|
||||
HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
|
||||
uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
|
||||
HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
|
||||
HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
|
||||
HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
|
||||
HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
|
||||
HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Peripheral State functions ************************************************/
|
||||
/** @addtogroup PCD_Exported_Functions_Group4 Peripheral State functions
|
||||
* @{
|
||||
*/
|
||||
PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup PCD_Private_Macros PCD Private Macros
|
||||
* @{
|
||||
*/
|
||||
/** @defgroup PCD_Instance_definition PCD Instance definition
|
||||
* @{
|
||||
*/
|
||||
#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
|
||||
((INSTANCE) == USB_OTG_HS))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* __STM32F7xx_HAL_PCD_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,116 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_hal_pcd_ex.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.2
|
||||
* @date 14-April-2017
|
||||
* @brief Header file of PCD HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F7xx_HAL_PCD_EX_H
|
||||
#define __STM32F7xx_HAL_PCD_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup PCDEx
|
||||
* @{
|
||||
*/
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
typedef enum
|
||||
{
|
||||
PCD_LPM_L0_ACTIVE = 0x00U, /* on */
|
||||
PCD_LPM_L1_ACTIVE = 0x01U, /* LPM L1 sleep */
|
||||
}PCD_LPM_MsgTypeDef;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
PCD_BCD_ERROR = 0xFF,
|
||||
PCD_BCD_CONTACT_DETECTION = 0xFE,
|
||||
PCD_BCD_STD_DOWNSTREAM_PORT = 0xFD,
|
||||
PCD_BCD_CHARGING_DOWNSTREAM_PORT = 0xFC,
|
||||
PCD_BCD_DEDICATED_CHARGING_PORT = 0xFB,
|
||||
PCD_BCD_DISCOVERY_COMPLETED = 0x00,
|
||||
|
||||
}PCD_BCD_MsgTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup PCDEx_Exported_Functions PCDEx Exported Functions
|
||||
* @{
|
||||
*/
|
||||
/** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size);
|
||||
HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size);
|
||||
HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd);
|
||||
HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd);
|
||||
HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd);
|
||||
HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd);
|
||||
void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd);
|
||||
void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg);
|
||||
void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* __STM32F7xx_HAL_PCD_EX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,422 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_hal_pwr.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.2
|
||||
* @date 14-April-2017
|
||||
* @brief Header file of PWR HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F7xx_HAL_PWR_H
|
||||
#define __STM32F7xx_HAL_PWR_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup PWR
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup PWR_Exported_Types PWR Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief PWR PVD configuration structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level.
|
||||
This parameter can be a value of @ref PWR_PVD_detection_level */
|
||||
|
||||
uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.
|
||||
This parameter can be a value of @ref PWR_PVD_Mode */
|
||||
}PWR_PVDTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup PWR_Exported_Constants PWR Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_PVD_detection_level PWR PVD detection level
|
||||
* @{
|
||||
*/
|
||||
#define PWR_PVDLEVEL_0 PWR_CR1_PLS_LEV0
|
||||
#define PWR_PVDLEVEL_1 PWR_CR1_PLS_LEV1
|
||||
#define PWR_PVDLEVEL_2 PWR_CR1_PLS_LEV2
|
||||
#define PWR_PVDLEVEL_3 PWR_CR1_PLS_LEV3
|
||||
#define PWR_PVDLEVEL_4 PWR_CR1_PLS_LEV4
|
||||
#define PWR_PVDLEVEL_5 PWR_CR1_PLS_LEV5
|
||||
#define PWR_PVDLEVEL_6 PWR_CR1_PLS_LEV6
|
||||
#define PWR_PVDLEVEL_7 PWR_CR1_PLS_LEV7/* External input analog voltage
|
||||
(Compare internally to VREFINT) */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_PVD_Mode PWR PVD Mode
|
||||
* @{
|
||||
*/
|
||||
#define PWR_PVD_MODE_NORMAL ((uint32_t)0x00000000U) /*!< basic mode is used */
|
||||
#define PWR_PVD_MODE_IT_RISING ((uint32_t)0x00010001U) /*!< External Interrupt Mode with Rising edge trigger detection */
|
||||
#define PWR_PVD_MODE_IT_FALLING ((uint32_t)0x00010002U) /*!< External Interrupt Mode with Falling edge trigger detection */
|
||||
#define PWR_PVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
|
||||
#define PWR_PVD_MODE_EVENT_RISING ((uint32_t)0x00020001U) /*!< Event Mode with Rising edge trigger detection */
|
||||
#define PWR_PVD_MODE_EVENT_FALLING ((uint32_t)0x00020002U) /*!< Event Mode with Falling edge trigger detection */
|
||||
#define PWR_PVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003U) /*!< Event Mode with Rising/Falling edge trigger detection */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_Regulator_state_in_STOP_mode PWR Regulator state in SLEEP/STOP mode
|
||||
* @{
|
||||
*/
|
||||
#define PWR_MAINREGULATOR_ON ((uint32_t)0x00000000U)
|
||||
#define PWR_LOWPOWERREGULATOR_ON PWR_CR1_LPDS
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry
|
||||
* @{
|
||||
*/
|
||||
#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01U)
|
||||
#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry
|
||||
* @{
|
||||
*/
|
||||
#define PWR_STOPENTRY_WFI ((uint8_t)0x01U)
|
||||
#define PWR_STOPENTRY_WFE ((uint8_t)0x02U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_Regulator_Voltage_Scale PWR Regulator Voltage Scale
|
||||
* @{
|
||||
*/
|
||||
#define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR1_VOS
|
||||
#define PWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR1_VOS_1
|
||||
#define PWR_REGULATOR_VOLTAGE_SCALE3 PWR_CR1_VOS_0
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_Flag PWR Flag
|
||||
* @{
|
||||
*/
|
||||
#define PWR_FLAG_WU PWR_CSR1_WUIF
|
||||
#define PWR_FLAG_SB PWR_CSR1_SBF
|
||||
#define PWR_FLAG_PVDO PWR_CSR1_PVDO
|
||||
#define PWR_FLAG_BRR PWR_CSR1_BRR
|
||||
#define PWR_FLAG_VOSRDY PWR_CSR1_VOSRDY
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup PWR_Exported_Macro PWR Exported Macro
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief macros configure the main internal regulator output voltage.
|
||||
* @param __REGULATOR__: specifies the regulator output voltage to achieve
|
||||
* a tradeoff between performance and power consumption when the device does
|
||||
* not operate at the maximum frequency (refer to the datasheets for more details).
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode
|
||||
* @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode
|
||||
* @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
MODIFY_REG(PWR->CR1, PWR_CR1_VOS, (__REGULATOR__)); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(PWR->CR1, PWR_CR1_VOS); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
|
||||
/** @brief Check PWR flag is set or not.
|
||||
* @param __FLAG__: specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event
|
||||
* was received on the internal wakeup line in standby mode (RTC alarm (Alarm A or Alarm B),
|
||||
* RTC Tamper event, RTC TimeStamp event or RTC Wakeup)).
|
||||
* @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was
|
||||
* resumed from StandBy mode.
|
||||
* @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled
|
||||
* by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode
|
||||
* For this reason, this bit is equal to 0 after Standby or reset
|
||||
* until the PVDE bit is set.
|
||||
* @arg PWR_FLAG_BRR: Backup regulator ready flag. This bit is not reset
|
||||
* when the device wakes up from Standby mode or by a system reset
|
||||
* or power reset.
|
||||
* @arg PWR_FLAG_VOSRDY: This flag indicates that the Regulator voltage
|
||||
* scaling output selection is ready.
|
||||
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR1 & (__FLAG__)) == (__FLAG__))
|
||||
|
||||
/** @brief Clear the PWR's pending flags.
|
||||
* @param __FLAG__: specifies the flag to clear.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_FLAG_SB: StandBy flag
|
||||
*/
|
||||
#define __HAL_PWR_CLEAR_FLAG(__FLAG__) (PWR->CR1 |= (__FLAG__) << 2)
|
||||
|
||||
/**
|
||||
* @brief Enable the PVD Exti Line 16.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_ENABLE_IT() (EXTI->IMR |= (PWR_EXTI_LINE_PVD))
|
||||
|
||||
/**
|
||||
* @brief Disable the PVD EXTI Line 16.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_DISABLE_IT() (EXTI->IMR &= ~(PWR_EXTI_LINE_PVD))
|
||||
|
||||
/**
|
||||
* @brief Enable event on PVD Exti Line 16.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() (EXTI->EMR |= (PWR_EXTI_LINE_PVD))
|
||||
|
||||
/**
|
||||
* @brief Disable event on PVD Exti Line 16.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(PWR_EXTI_LINE_PVD))
|
||||
|
||||
/**
|
||||
* @brief Enable the PVD Extended Interrupt Rising Trigger.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
|
||||
|
||||
/**
|
||||
* @brief Disable the PVD Extended Interrupt Rising Trigger.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
|
||||
|
||||
/**
|
||||
* @brief Enable the PVD Extended Interrupt Falling Trigger.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Disable the PVD Extended Interrupt Falling Trigger.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
|
||||
|
||||
|
||||
/**
|
||||
* @brief PVD EXTI line configuration: set rising & falling edge trigger.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
|
||||
|
||||
/**
|
||||
* @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
|
||||
|
||||
/**
|
||||
* @brief checks whether the specified PVD Exti interrupt flag is set or not.
|
||||
* @retval EXTI PVD Line Status.
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD))
|
||||
|
||||
/**
|
||||
* @brief Clear the PVD Exti flag.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD))
|
||||
|
||||
/**
|
||||
* @brief Generates a Software interrupt on PVD EXTI line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() (EXTI->SWIER |= (PWR_EXTI_LINE_PVD))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include PWR HAL Extension module */
|
||||
#include "stm32f7xx_hal_pwr_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup PWR_Exported_Functions PWR Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
/* Initialization and de-initialization functions *****************************/
|
||||
void HAL_PWR_DeInit(void);
|
||||
void HAL_PWR_EnableBkUpAccess(void);
|
||||
void HAL_PWR_DisableBkUpAccess(void);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral Control functions **********************************************/
|
||||
/* PVD configuration */
|
||||
void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);
|
||||
void HAL_PWR_EnablePVD(void);
|
||||
void HAL_PWR_DisablePVD(void);
|
||||
|
||||
/* WakeUp pins configuration */
|
||||
void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity);
|
||||
void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);
|
||||
|
||||
/* Low Power modes entry */
|
||||
void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
|
||||
void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
|
||||
void HAL_PWR_EnterSTANDBYMode(void);
|
||||
|
||||
/* Power PVD IRQ Handler */
|
||||
void HAL_PWR_PVD_IRQHandler(void);
|
||||
void HAL_PWR_PVDCallback(void);
|
||||
|
||||
/* Cortex System Control functions *******************************************/
|
||||
void HAL_PWR_EnableSleepOnExit(void);
|
||||
void HAL_PWR_DisableSleepOnExit(void);
|
||||
void HAL_PWR_EnableSEVOnPend(void);
|
||||
void HAL_PWR_DisableSEVOnPend(void);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup PWR_Private_Constants PWR Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_PVD_EXTI_Line PWR PVD EXTI Line
|
||||
* @{
|
||||
*/
|
||||
#define PWR_EXTI_LINE_PVD ((uint32_t)EXTI_IMR_IM16) /*!< External interrupt line 16 Connected to the PVD EXTI Line */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup PWR_Private_Macros PWR Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_IS_PWR_Definitions PWR Private macros to check input parameters
|
||||
* @{
|
||||
*/
|
||||
#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
|
||||
((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
|
||||
((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
|
||||
((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
|
||||
#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \
|
||||
((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \
|
||||
((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \
|
||||
((MODE) == PWR_PVD_MODE_NORMAL))
|
||||
#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \
|
||||
((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
|
||||
#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
|
||||
#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))
|
||||
#define IS_PWR_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
|
||||
((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \
|
||||
((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE3))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* __STM32F7xx_HAL_PWR_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,280 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_hal_pwr_ex.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.2
|
||||
* @date 14-April-2017
|
||||
* @brief Header file of PWR HAL Extension module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F7xx_HAL_PWR_EX_H
|
||||
#define __STM32F7xx_HAL_PWR_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup PWREx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup PWREx_Exported_Constants PWREx Exported Constants
|
||||
* @{
|
||||
*/
|
||||
/** @defgroup PWREx_WakeUp_Pins PWREx Wake Up Pins
|
||||
* @{
|
||||
*/
|
||||
#define PWR_WAKEUP_PIN1 PWR_CSR2_EWUP1
|
||||
#define PWR_WAKEUP_PIN2 PWR_CSR2_EWUP2
|
||||
#define PWR_WAKEUP_PIN3 PWR_CSR2_EWUP3
|
||||
#define PWR_WAKEUP_PIN4 PWR_CSR2_EWUP4
|
||||
#define PWR_WAKEUP_PIN5 PWR_CSR2_EWUP5
|
||||
#define PWR_WAKEUP_PIN6 PWR_CSR2_EWUP6
|
||||
#define PWR_WAKEUP_PIN1_HIGH PWR_CSR2_EWUP1
|
||||
#define PWR_WAKEUP_PIN2_HIGH PWR_CSR2_EWUP2
|
||||
#define PWR_WAKEUP_PIN3_HIGH PWR_CSR2_EWUP3
|
||||
#define PWR_WAKEUP_PIN4_HIGH PWR_CSR2_EWUP4
|
||||
#define PWR_WAKEUP_PIN5_HIGH PWR_CSR2_EWUP5
|
||||
#define PWR_WAKEUP_PIN6_HIGH PWR_CSR2_EWUP6
|
||||
#define PWR_WAKEUP_PIN1_LOW (uint32_t)((PWR_CR2_WUPP1<<6) | PWR_CSR2_EWUP1)
|
||||
#define PWR_WAKEUP_PIN2_LOW (uint32_t)((PWR_CR2_WUPP2<<6) | PWR_CSR2_EWUP2)
|
||||
#define PWR_WAKEUP_PIN3_LOW (uint32_t)((PWR_CR2_WUPP3<<6) | PWR_CSR2_EWUP3)
|
||||
#define PWR_WAKEUP_PIN4_LOW (uint32_t)((PWR_CR2_WUPP4<<6) | PWR_CSR2_EWUP4)
|
||||
#define PWR_WAKEUP_PIN5_LOW (uint32_t)((PWR_CR2_WUPP5<<6) | PWR_CSR2_EWUP5)
|
||||
#define PWR_WAKEUP_PIN6_LOW (uint32_t)((PWR_CR2_WUPP6<<6) | PWR_CSR2_EWUP6)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWREx_Regulator_state_in_UnderDrive_mode PWREx Regulator state in UnderDrive mode
|
||||
* @{
|
||||
*/
|
||||
#define PWR_MAINREGULATOR_UNDERDRIVE_ON PWR_CR1_MRUDS
|
||||
#define PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON ((uint32_t)(PWR_CR1_LPDS | PWR_CR1_LPUDS))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWREx_Over_Under_Drive_Flag PWREx Over Under Drive Flag
|
||||
* @{
|
||||
*/
|
||||
#define PWR_FLAG_ODRDY PWR_CSR1_ODRDY
|
||||
#define PWR_FLAG_ODSWRDY PWR_CSR1_ODSWRDY
|
||||
#define PWR_FLAG_UDRDY PWR_CSR1_UDRDY
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWREx_Wakeup_Pins_Flag PWREx Wake Up Pin Flags
|
||||
* @{
|
||||
*/
|
||||
#define PWR_WAKEUP_PIN_FLAG1 PWR_CSR2_WUPF1
|
||||
#define PWR_WAKEUP_PIN_FLAG2 PWR_CSR2_WUPF2
|
||||
#define PWR_WAKEUP_PIN_FLAG3 PWR_CSR2_WUPF3
|
||||
#define PWR_WAKEUP_PIN_FLAG4 PWR_CSR2_WUPF4
|
||||
#define PWR_WAKEUP_PIN_FLAG5 PWR_CSR2_WUPF5
|
||||
#define PWR_WAKEUP_PIN_FLAG6 PWR_CSR2_WUPF6
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup PWREx_Exported_Macro PWREx Exported Macro
|
||||
* @{
|
||||
*/
|
||||
/** @brief Macros to enable or disable the Over drive mode.
|
||||
*/
|
||||
#define __HAL_PWR_OVERDRIVE_ENABLE() (PWR->CR1 |= (uint32_t)PWR_CR1_ODEN)
|
||||
#define __HAL_PWR_OVERDRIVE_DISABLE() (PWR->CR1 &= (uint32_t)(~PWR_CR1_ODEN))
|
||||
|
||||
/** @brief Macros to enable or disable the Over drive switching.
|
||||
*/
|
||||
#define __HAL_PWR_OVERDRIVESWITCHING_ENABLE() (PWR->CR1 |= (uint32_t)PWR_CR1_ODSWEN)
|
||||
#define __HAL_PWR_OVERDRIVESWITCHING_DISABLE() (PWR->CR1 &= (uint32_t)(~PWR_CR1_ODSWEN))
|
||||
|
||||
/** @brief Macros to enable or disable the Under drive mode.
|
||||
* @note This mode is enabled only with STOP low power mode.
|
||||
* In this mode, the 1.2V domain is preserved in reduced leakage mode. This
|
||||
* mode is only available when the main regulator or the low power regulator
|
||||
* is in low voltage mode.
|
||||
* @note If the Under-drive mode was enabled, it is automatically disabled after
|
||||
* exiting Stop mode.
|
||||
* When the voltage regulator operates in Under-drive mode, an additional
|
||||
* startup delay is induced when waking up from Stop mode.
|
||||
*/
|
||||
#define __HAL_PWR_UNDERDRIVE_ENABLE() (PWR->CR1 |= (uint32_t)PWR_CR1_UDEN)
|
||||
#define __HAL_PWR_UNDERDRIVE_DISABLE() (PWR->CR1 &= (uint32_t)(~PWR_CR1_UDEN))
|
||||
|
||||
/** @brief Check PWR flag is set or not.
|
||||
* @param __FLAG__: specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_FLAG_ODRDY: This flag indicates that the Over-drive mode
|
||||
* is ready
|
||||
* @arg PWR_FLAG_ODSWRDY: This flag indicates that the Over-drive mode
|
||||
* switching is ready
|
||||
* @arg PWR_FLAG_UDRDY: This flag indicates that the Under-drive mode
|
||||
* is enabled in Stop mode
|
||||
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_PWR_GET_ODRUDR_FLAG(__FLAG__) ((PWR->CSR1 & (__FLAG__)) == (__FLAG__))
|
||||
|
||||
/** @brief Clear the Under-Drive Ready flag.
|
||||
*/
|
||||
#define __HAL_PWR_CLEAR_ODRUDR_FLAG() (PWR->CSR1 |= PWR_FLAG_UDRDY)
|
||||
|
||||
/** @brief Check Wake Up flag is set or not.
|
||||
* @param __WUFLAG__: specifies the Wake Up flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_WAKEUP_PIN_FLAG1: Wakeup Pin Flag for PA0
|
||||
* @arg PWR_WAKEUP_PIN_FLAG2: Wakeup Pin Flag for PA2
|
||||
* @arg PWR_WAKEUP_PIN_FLAG3: Wakeup Pin Flag for PC1
|
||||
* @arg PWR_WAKEUP_PIN_FLAG4: Wakeup Pin Flag for PC13
|
||||
* @arg PWR_WAKEUP_PIN_FLAG5: Wakeup Pin Flag for PI8
|
||||
* @arg PWR_WAKEUP_PIN_FLAG6: Wakeup Pin Flag for PI11
|
||||
*/
|
||||
#define __HAL_PWR_GET_WAKEUP_FLAG(__WUFLAG__) (PWR->CSR2 & (__WUFLAG__))
|
||||
|
||||
/** @brief Clear the WakeUp pins flags.
|
||||
* @param __WUFLAG__: specifies the Wake Up pin flag to clear.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_WAKEUP_PIN_FLAG1: Wakeup Pin Flag for PA0
|
||||
* @arg PWR_WAKEUP_PIN_FLAG2: Wakeup Pin Flag for PA2
|
||||
* @arg PWR_WAKEUP_PIN_FLAG3: Wakeup Pin Flag for PC1
|
||||
* @arg PWR_WAKEUP_PIN_FLAG4: Wakeup Pin Flag for PC13
|
||||
* @arg PWR_WAKEUP_PIN_FLAG5: Wakeup Pin Flag for PI8
|
||||
* @arg PWR_WAKEUP_PIN_FLAG6: Wakeup Pin Flag for PI11
|
||||
*/
|
||||
#define __HAL_PWR_CLEAR_WAKEUP_FLAG(__WUFLAG__) (PWR->CR2 |= (__WUFLAG__))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup PWREx_Exported_Functions PWREx Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup PWREx_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
uint32_t HAL_PWREx_GetVoltageRange(void);
|
||||
HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling);
|
||||
|
||||
void HAL_PWREx_EnableFlashPowerDown(void);
|
||||
void HAL_PWREx_DisableFlashPowerDown(void);
|
||||
HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void);
|
||||
HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void);
|
||||
|
||||
void HAL_PWREx_EnableMainRegulatorLowVoltage(void);
|
||||
void HAL_PWREx_DisableMainRegulatorLowVoltage(void);
|
||||
void HAL_PWREx_EnableLowRegulatorLowVoltage(void);
|
||||
void HAL_PWREx_DisableLowRegulatorLowVoltage(void);
|
||||
|
||||
HAL_StatusTypeDef HAL_PWREx_EnableOverDrive(void);
|
||||
HAL_StatusTypeDef HAL_PWREx_DisableOverDrive(void);
|
||||
HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup PWREx_Private_Macros PWREx Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PWREx_IS_PWR_Definitions PWREx Private macros to check input parameters
|
||||
* @{
|
||||
*/
|
||||
#define IS_PWR_REGULATOR_UNDERDRIVE(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_UNDERDRIVE_ON) || \
|
||||
((REGULATOR) == PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON))
|
||||
#define IS_PWR_WAKEUP_PIN(__PIN__) (((__PIN__) == PWR_WAKEUP_PIN1) || \
|
||||
((__PIN__) == PWR_WAKEUP_PIN2) || \
|
||||
((__PIN__) == PWR_WAKEUP_PIN3) || \
|
||||
((__PIN__) == PWR_WAKEUP_PIN4) || \
|
||||
((__PIN__) == PWR_WAKEUP_PIN5) || \
|
||||
((__PIN__) == PWR_WAKEUP_PIN6) || \
|
||||
((__PIN__) == PWR_WAKEUP_PIN1_HIGH) || \
|
||||
((__PIN__) == PWR_WAKEUP_PIN2_HIGH) || \
|
||||
((__PIN__) == PWR_WAKEUP_PIN3_HIGH) || \
|
||||
((__PIN__) == PWR_WAKEUP_PIN4_HIGH) || \
|
||||
((__PIN__) == PWR_WAKEUP_PIN5_HIGH) || \
|
||||
((__PIN__) == PWR_WAKEUP_PIN6_HIGH) || \
|
||||
((__PIN__) == PWR_WAKEUP_PIN1_LOW) || \
|
||||
((__PIN__) == PWR_WAKEUP_PIN2_LOW) || \
|
||||
((__PIN__) == PWR_WAKEUP_PIN3_LOW) || \
|
||||
((__PIN__) == PWR_WAKEUP_PIN4_LOW) || \
|
||||
((__PIN__) == PWR_WAKEUP_PIN5_LOW) || \
|
||||
((__PIN__) == PWR_WAKEUP_PIN6_LOW))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* __STM32F7xx_HAL_PWR_EX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,781 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_hal_qspi.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.2
|
||||
* @date 14-April-2017
|
||||
* @brief Header file of QSPI HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F7xx_HAL_QSPI_H
|
||||
#define __STM32F7xx_HAL_QSPI_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup QSPI
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup QSPI_Exported_Types QSPI Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief QSPI Init structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t ClockPrescaler; /* Specifies the prescaler factor for generating clock based on the AHB clock.
|
||||
This parameter can be a number between 0 and 255 */
|
||||
|
||||
uint32_t FifoThreshold; /* Specifies the threshold number of bytes in the FIFO (used only in indirect mode)
|
||||
This parameter can be a value between 1 and 32 */
|
||||
|
||||
uint32_t SampleShifting; /* Specifies the Sample Shift. The data is sampled 1/2 clock cycle delay later to
|
||||
take in account external signal delays. (It should be QSPI_SAMPLE_SHIFTING_NONE in DDR mode)
|
||||
This parameter can be a value of @ref QSPI_SampleShifting */
|
||||
|
||||
uint32_t FlashSize; /* Specifies the Flash Size. FlashSize+1 is effectively the number of address bits
|
||||
required to address the flash memory. The flash capacity can be up to 4GB
|
||||
(addressed using 32 bits) in indirect mode, but the addressable space in
|
||||
memory-mapped mode is limited to 256MB
|
||||
This parameter can be a number between 0 and 31 */
|
||||
|
||||
uint32_t ChipSelectHighTime; /* Specifies the Chip Select High Time. ChipSelectHighTime+1 defines the minimum number
|
||||
of clock cycles which the chip select must remain high between commands.
|
||||
This parameter can be a value of @ref QSPI_ChipSelectHighTime */
|
||||
|
||||
uint32_t ClockMode; /* Specifies the Clock Mode. It indicates the level that clock takes between commands.
|
||||
This parameter can be a value of @ref QSPI_ClockMode */
|
||||
|
||||
uint32_t FlashID; /* Specifies the Flash which will be used,
|
||||
This parameter can be a value of @ref QSPI_Flash_Select */
|
||||
|
||||
uint32_t DualFlash; /* Specifies the Dual Flash Mode State
|
||||
This parameter can be a value of @ref QSPI_DualFlash_Mode */
|
||||
}QSPI_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL QSPI State structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_QSPI_STATE_RESET = 0x00U, /*!< Peripheral not initialized */
|
||||
HAL_QSPI_STATE_READY = 0x01U, /*!< Peripheral initialized and ready for use */
|
||||
HAL_QSPI_STATE_BUSY = 0x02U, /*!< Peripheral in indirect mode and busy */
|
||||
HAL_QSPI_STATE_BUSY_INDIRECT_TX = 0x12U, /*!< Peripheral in indirect mode with transmission ongoing */
|
||||
HAL_QSPI_STATE_BUSY_INDIRECT_RX = 0x22U, /*!< Peripheral in indirect mode with reception ongoing */
|
||||
HAL_QSPI_STATE_BUSY_AUTO_POLLING = 0x42U, /*!< Peripheral in auto polling mode ongoing */
|
||||
HAL_QSPI_STATE_BUSY_MEM_MAPPED = 0x82U, /*!< Peripheral in memory mapped mode ongoing */
|
||||
HAL_QSPI_STATE_ABORT = 0x08U, /*!< Peripheral with abort request ongoing */
|
||||
HAL_QSPI_STATE_ERROR = 0x04U /*!< Peripheral in error */
|
||||
}HAL_QSPI_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief QSPI Handle Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
QUADSPI_TypeDef *Instance; /* QSPI registers base address */
|
||||
QSPI_InitTypeDef Init; /* QSPI communication parameters */
|
||||
uint8_t *pTxBuffPtr; /* Pointer to QSPI Tx transfer Buffer */
|
||||
__IO uint32_t TxXferSize; /* QSPI Tx Transfer size */
|
||||
__IO uint32_t TxXferCount; /* QSPI Tx Transfer Counter */
|
||||
uint8_t *pRxBuffPtr; /* Pointer to QSPI Rx transfer Buffer */
|
||||
__IO uint32_t RxXferSize; /* QSPI Rx Transfer size */
|
||||
__IO uint32_t RxXferCount; /* QSPI Rx Transfer Counter */
|
||||
DMA_HandleTypeDef *hdma; /* QSPI Rx/Tx DMA Handle parameters */
|
||||
__IO HAL_LockTypeDef Lock; /* Locking object */
|
||||
__IO HAL_QSPI_StateTypeDef State; /* QSPI communication state */
|
||||
__IO uint32_t ErrorCode; /* QSPI Error code */
|
||||
uint32_t Timeout; /* Timeout for the QSPI memory access */
|
||||
}QSPI_HandleTypeDef;
|
||||
|
||||
/**
|
||||
* @brief QSPI Command structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Instruction; /* Specifies the Instruction to be sent
|
||||
This parameter can be a value (8-bit) between 0x00 and 0xFF */
|
||||
uint32_t Address; /* Specifies the Address to be sent (Size from 1 to 4 bytes according AddressSize)
|
||||
This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */
|
||||
uint32_t AlternateBytes; /* Specifies the Alternate Bytes to be sent (Size from 1 to 4 bytes according AlternateBytesSize)
|
||||
This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */
|
||||
uint32_t AddressSize; /* Specifies the Address Size
|
||||
This parameter can be a value of @ref QSPI_AddressSize */
|
||||
uint32_t AlternateBytesSize; /* Specifies the Alternate Bytes Size
|
||||
This parameter can be a value of @ref QSPI_AlternateBytesSize */
|
||||
uint32_t DummyCycles; /* Specifies the Number of Dummy Cycles.
|
||||
This parameter can be a number between 0 and 31 */
|
||||
uint32_t InstructionMode; /* Specifies the Instruction Mode
|
||||
This parameter can be a value of @ref QSPI_InstructionMode */
|
||||
uint32_t AddressMode; /* Specifies the Address Mode
|
||||
This parameter can be a value of @ref QSPI_AddressMode */
|
||||
uint32_t AlternateByteMode; /* Specifies the Alternate Bytes Mode
|
||||
This parameter can be a value of @ref QSPI_AlternateBytesMode */
|
||||
uint32_t DataMode; /* Specifies the Data Mode (used for dummy cycles and data phases)
|
||||
This parameter can be a value of @ref QSPI_DataMode */
|
||||
uint32_t NbData; /* Specifies the number of data to transfer.
|
||||
This parameter can be any value between 0 and 0xFFFFFFFF (0 means undefined length
|
||||
until end of memory)*/
|
||||
uint32_t DdrMode; /* Specifies the double data rate mode for address, alternate byte and data phase
|
||||
This parameter can be a value of @ref QSPI_DdrMode */
|
||||
uint32_t DdrHoldHalfCycle; /* Specifies the DDR hold half cycle. It delays the data output by one half of
|
||||
system clock in DDR mode.
|
||||
This parameter can be a value of @ref QSPI_DdrHoldHalfCycle */
|
||||
uint32_t SIOOMode; /* Specifies the send instruction only once mode
|
||||
This parameter can be a value of @ref QSPI_SIOOMode */
|
||||
}QSPI_CommandTypeDef;
|
||||
|
||||
/**
|
||||
* @brief QSPI Auto Polling mode configuration structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Match; /* Specifies the value to be compared with the masked status register to get a match.
|
||||
This parameter can be any value between 0 and 0xFFFFFFFF */
|
||||
uint32_t Mask; /* Specifies the mask to be applied to the status bytes received.
|
||||
This parameter can be any value between 0 and 0xFFFFFFFF */
|
||||
uint32_t Interval; /* Specifies the number of clock cycles between two read during automatic polling phases.
|
||||
This parameter can be any value between 0 and 0xFFFF */
|
||||
uint32_t StatusBytesSize; /* Specifies the size of the status bytes received.
|
||||
This parameter can be any value between 1 and 4 */
|
||||
uint32_t MatchMode; /* Specifies the method used for determining a match.
|
||||
This parameter can be a value of @ref QSPI_MatchMode */
|
||||
uint32_t AutomaticStop; /* Specifies if automatic polling is stopped after a match.
|
||||
This parameter can be a value of @ref QSPI_AutomaticStop */
|
||||
}QSPI_AutoPollingTypeDef;
|
||||
|
||||
/**
|
||||
* @brief QSPI Memory Mapped mode configuration structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t TimeOutPeriod; /* Specifies the number of clock to wait when the FIFO is full before to release the chip select.
|
||||
This parameter can be any value between 0 and 0xFFFF */
|
||||
uint32_t TimeOutActivation; /* Specifies if the time out counter is enabled to release the chip select.
|
||||
This parameter can be a value of @ref QSPI_TimeOutActivation */
|
||||
}QSPI_MemoryMappedTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup QSPI_Exported_Constants QSPI Exported Constants
|
||||
* @{
|
||||
*/
|
||||
/** @defgroup QSPI_ErrorCode QSPI Error Code
|
||||
* @{
|
||||
*/
|
||||
#define HAL_QSPI_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
|
||||
#define HAL_QSPI_ERROR_TIMEOUT ((uint32_t)0x00000001U) /*!< Timeout error */
|
||||
#define HAL_QSPI_ERROR_TRANSFER ((uint32_t)0x00000002U) /*!< Transfer error */
|
||||
#define HAL_QSPI_ERROR_DMA ((uint32_t)0x00000004U) /*!< DMA transfer error */
|
||||
#define HAL_QSPI_ERROR_INVALID_PARAM ((uint32_t)0x00000008U) /*!< Invalid parameters error */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup QSPI_SampleShifting QSPI Sample Shifting
|
||||
* @{
|
||||
*/
|
||||
#define QSPI_SAMPLE_SHIFTING_NONE ((uint32_t)0x00000000U) /*!<No clock cycle shift to sample data*/
|
||||
#define QSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)QUADSPI_CR_SSHIFT) /*!<1/2 clock cycle shift to sample data*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup QSPI_ChipSelectHighTime QSPI Chip Select High Time
|
||||
* @{
|
||||
*/
|
||||
#define QSPI_CS_HIGH_TIME_1_CYCLE ((uint32_t)0x00000000U) /*!<nCS stay high for at least 1 clock cycle between commands*/
|
||||
#define QSPI_CS_HIGH_TIME_2_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 2 clock cycles between commands*/
|
||||
#define QSPI_CS_HIGH_TIME_3_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 3 clock cycles between commands*/
|
||||
#define QSPI_CS_HIGH_TIME_4_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 4 clock cycles between commands*/
|
||||
#define QSPI_CS_HIGH_TIME_5_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2) /*!<nCS stay high for at least 5 clock cycles between commands*/
|
||||
#define QSPI_CS_HIGH_TIME_6_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 6 clock cycles between commands*/
|
||||
#define QSPI_CS_HIGH_TIME_7_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 7 clock cycles between commands*/
|
||||
#define QSPI_CS_HIGH_TIME_8_CYCLE ((uint32_t)QUADSPI_DCR_CSHT) /*!<nCS stay high for at least 8 clock cycles between commands*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup QSPI_ClockMode QSPI Clock Mode
|
||||
* @{
|
||||
*/
|
||||
#define QSPI_CLOCK_MODE_0 ((uint32_t)0x00000000U) /*!<Clk stays low while nCS is released*/
|
||||
#define QSPI_CLOCK_MODE_3 ((uint32_t)QUADSPI_DCR_CKMODE) /*!<Clk goes high while nCS is released*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup QSPI_Flash_Select QSPI Flash Select
|
||||
* @{
|
||||
*/
|
||||
#define QSPI_FLASH_ID_1 ((uint32_t)0x00000000U)
|
||||
#define QSPI_FLASH_ID_2 ((uint32_t)QUADSPI_CR_FSEL)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup QSPI_DualFlash_Mode QSPI Dual Flash Mode
|
||||
* @{
|
||||
*/
|
||||
#define QSPI_DUALFLASH_ENABLE ((uint32_t)QUADSPI_CR_DFM)
|
||||
#define QSPI_DUALFLASH_DISABLE ((uint32_t)0x00000000U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup QSPI_AddressSize QSPI Address Size
|
||||
* @{
|
||||
*/
|
||||
#define QSPI_ADDRESS_8_BITS ((uint32_t)0x00000000U) /*!<8-bit address*/
|
||||
#define QSPI_ADDRESS_16_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_0) /*!<16-bit address*/
|
||||
#define QSPI_ADDRESS_24_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_1) /*!<24-bit address*/
|
||||
#define QSPI_ADDRESS_32_BITS ((uint32_t)QUADSPI_CCR_ADSIZE) /*!<32-bit address*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup QSPI_AlternateBytesSize QSPI Alternate Bytes Size
|
||||
* @{
|
||||
*/
|
||||
#define QSPI_ALTERNATE_BYTES_8_BITS ((uint32_t)0x00000000U) /*!<8-bit alternate bytes*/
|
||||
#define QSPI_ALTERNATE_BYTES_16_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_0) /*!<16-bit alternate bytes*/
|
||||
#define QSPI_ALTERNATE_BYTES_24_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_1) /*!<24-bit alternate bytes*/
|
||||
#define QSPI_ALTERNATE_BYTES_32_BITS ((uint32_t)QUADSPI_CCR_ABSIZE) /*!<32-bit alternate bytes*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup QSPI_InstructionMode QSPI Instruction Mode
|
||||
* @{
|
||||
*/
|
||||
#define QSPI_INSTRUCTION_NONE ((uint32_t)0x00000000U) /*!<No instruction*/
|
||||
#define QSPI_INSTRUCTION_1_LINE ((uint32_t)QUADSPI_CCR_IMODE_0) /*!<Instruction on a single line*/
|
||||
#define QSPI_INSTRUCTION_2_LINES ((uint32_t)QUADSPI_CCR_IMODE_1) /*!<Instruction on two lines*/
|
||||
#define QSPI_INSTRUCTION_4_LINES ((uint32_t)QUADSPI_CCR_IMODE) /*!<Instruction on four lines*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup QSPI_AddressMode QSPI Address Mode
|
||||
* @{
|
||||
*/
|
||||
#define QSPI_ADDRESS_NONE ((uint32_t)0x00000000U) /*!<No address*/
|
||||
#define QSPI_ADDRESS_1_LINE ((uint32_t)QUADSPI_CCR_ADMODE_0) /*!<Address on a single line*/
|
||||
#define QSPI_ADDRESS_2_LINES ((uint32_t)QUADSPI_CCR_ADMODE_1) /*!<Address on two lines*/
|
||||
#define QSPI_ADDRESS_4_LINES ((uint32_t)QUADSPI_CCR_ADMODE) /*!<Address on four lines*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup QSPI_AlternateBytesMode QSPI Alternate Bytes Mode
|
||||
* @{
|
||||
*/
|
||||
#define QSPI_ALTERNATE_BYTES_NONE ((uint32_t)0x00000000U) /*!<No alternate bytes*/
|
||||
#define QSPI_ALTERNATE_BYTES_1_LINE ((uint32_t)QUADSPI_CCR_ABMODE_0) /*!<Alternate bytes on a single line*/
|
||||
#define QSPI_ALTERNATE_BYTES_2_LINES ((uint32_t)QUADSPI_CCR_ABMODE_1) /*!<Alternate bytes on two lines*/
|
||||
#define QSPI_ALTERNATE_BYTES_4_LINES ((uint32_t)QUADSPI_CCR_ABMODE) /*!<Alternate bytes on four lines*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup QSPI_DataMode QSPI Data Mode
|
||||
* @{
|
||||
*/
|
||||
#define QSPI_DATA_NONE ((uint32_t)0X00000000) /*!<No data*/
|
||||
#define QSPI_DATA_1_LINE ((uint32_t)QUADSPI_CCR_DMODE_0) /*!<Data on a single line*/
|
||||
#define QSPI_DATA_2_LINES ((uint32_t)QUADSPI_CCR_DMODE_1) /*!<Data on two lines*/
|
||||
#define QSPI_DATA_4_LINES ((uint32_t)QUADSPI_CCR_DMODE) /*!<Data on four lines*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup QSPI_DdrMode QSPI Ddr Mode
|
||||
* @{
|
||||
*/
|
||||
#define QSPI_DDR_MODE_DISABLE ((uint32_t)0x00000000U) /*!<Double data rate mode disabled*/
|
||||
#define QSPI_DDR_MODE_ENABLE ((uint32_t)QUADSPI_CCR_DDRM) /*!<Double data rate mode enabled*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup QSPI_DdrHoldHalfCycle QSPI Ddr HoldHalfCycle
|
||||
* @{
|
||||
*/
|
||||
#define QSPI_DDR_HHC_ANALOG_DELAY ((uint32_t)0x00000000U) /*!<Delay the data output using analog delay in DDR mode*/
|
||||
#define QSPI_DDR_HHC_HALF_CLK_DELAY ((uint32_t)QUADSPI_CCR_DHHC) /*!<Delay the data output by 1/2 clock cycle in DDR mode*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup QSPI_SIOOMode QSPI SIOO Mode
|
||||
* @{
|
||||
*/
|
||||
#define QSPI_SIOO_INST_EVERY_CMD ((uint32_t)0x00000000U) /*!<Send instruction on every transaction*/
|
||||
#define QSPI_SIOO_INST_ONLY_FIRST_CMD ((uint32_t)QUADSPI_CCR_SIOO) /*!<Send instruction only for the first command*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup QSPI_MatchMode QSPI Match Mode
|
||||
* @{
|
||||
*/
|
||||
#define QSPI_MATCH_MODE_AND ((uint32_t)0x00000000U) /*!<AND match mode between unmasked bits*/
|
||||
#define QSPI_MATCH_MODE_OR ((uint32_t)QUADSPI_CR_PMM) /*!<OR match mode between unmasked bits*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup QSPI_AutomaticStop QSPI Automatic Stop
|
||||
* @{
|
||||
*/
|
||||
#define QSPI_AUTOMATIC_STOP_DISABLE ((uint32_t)0x00000000U) /*!<AutoPolling stops only with abort or QSPI disabling*/
|
||||
#define QSPI_AUTOMATIC_STOP_ENABLE ((uint32_t)QUADSPI_CR_APMS) /*!<AutoPolling stops as soon as there is a match*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup QSPI_TimeOutActivation QSPI TimeOut Activation
|
||||
* @{
|
||||
*/
|
||||
#define QSPI_TIMEOUT_COUNTER_DISABLE ((uint32_t)0x00000000U) /*!<Timeout counter disabled, nCS remains active*/
|
||||
#define QSPI_TIMEOUT_COUNTER_ENABLE ((uint32_t)QUADSPI_CR_TCEN) /*!<Timeout counter enabled, nCS released when timeout expires*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup QSPI_Flags QSPI Flags
|
||||
* @{
|
||||
*/
|
||||
#define QSPI_FLAG_BUSY QUADSPI_SR_BUSY /*!<Busy flag: operation is ongoing*/
|
||||
#define QSPI_FLAG_TO QUADSPI_SR_TOF /*!<Timeout flag: timeout occurs in memory-mapped mode*/
|
||||
#define QSPI_FLAG_SM QUADSPI_SR_SMF /*!<Status match flag: received data matches in autopolling mode*/
|
||||
#define QSPI_FLAG_FT QUADSPI_SR_FTF /*!<Fifo threshold flag: Fifo threshold reached or data left after read from memory is complete*/
|
||||
#define QSPI_FLAG_TC QUADSPI_SR_TCF /*!<Transfer complete flag: programmed number of data have been transferred or the transfer has been aborted*/
|
||||
#define QSPI_FLAG_TE QUADSPI_SR_TEF /*!<Transfer error flag: invalid address is being accessed*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup QSPI_Interrupts QSPI Interrupts
|
||||
* @{
|
||||
*/
|
||||
#define QSPI_IT_TO QUADSPI_CR_TOIE /*!<Interrupt on the timeout flag*/
|
||||
#define QSPI_IT_SM QUADSPI_CR_SMIE /*!<Interrupt on the status match flag*/
|
||||
#define QSPI_IT_FT QUADSPI_CR_FTIE /*!<Interrupt on the fifo threshold flag*/
|
||||
#define QSPI_IT_TC QUADSPI_CR_TCIE /*!<Interrupt on the transfer complete flag*/
|
||||
#define QSPI_IT_TE QUADSPI_CR_TEIE /*!<Interrupt on the transfer error flag*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup QSPI_Timeout_definition QSPI Timeout definition
|
||||
* @{
|
||||
*/
|
||||
#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE ((uint32_t)5000)/* 5 s */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup QSPI_Exported_Macros QSPI Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset QSPI handle state
|
||||
* @param __HANDLE__: QSPI handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_QSPI_STATE_RESET)
|
||||
|
||||
/** @brief Enable QSPI
|
||||
* @param __HANDLE__: specifies the QSPI Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_QSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
|
||||
|
||||
/** @brief Disable QSPI
|
||||
* @param __HANDLE__: specifies the QSPI Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_QSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
|
||||
|
||||
/** @brief Enables the specified QSPI interrupt.
|
||||
* @param __HANDLE__: specifies the QSPI Handle.
|
||||
* @param __INTERRUPT__: specifies the QSPI interrupt source to enable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg QSPI_IT_TO: QSPI Time out interrupt
|
||||
* @arg QSPI_IT_SM: QSPI Status match interrupt
|
||||
* @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
|
||||
* @arg QSPI_IT_TC: QSPI Transfer complete interrupt
|
||||
* @arg QSPI_IT_TE: QSPI Transfer error interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_QSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
|
||||
|
||||
|
||||
/** @brief Disables the specified QSPI interrupt.
|
||||
* @param __HANDLE__: specifies the QSPI Handle.
|
||||
* @param __INTERRUPT__: specifies the QSPI interrupt source to disable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg QSPI_IT_TO: QSPI Timeout interrupt
|
||||
* @arg QSPI_IT_SM: QSPI Status match interrupt
|
||||
* @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
|
||||
* @arg QSPI_IT_TC: QSPI Transfer complete interrupt
|
||||
* @arg QSPI_IT_TE: QSPI Transfer error interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
|
||||
|
||||
/** @brief Checks whether the specified QSPI interrupt source is enabled.
|
||||
* @param __HANDLE__: specifies the QSPI Handle.
|
||||
* @param __INTERRUPT__: specifies the QSPI interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg QSPI_IT_TO: QSPI Time out interrupt
|
||||
* @arg QSPI_IT_SM: QSPI Status match interrupt
|
||||
* @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
|
||||
* @arg QSPI_IT_TC: QSPI Transfer complete interrupt
|
||||
* @arg QSPI_IT_TE: QSPI Transfer error interrupt
|
||||
* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_QSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Get the selected QSPI's flag status.
|
||||
* @param __HANDLE__: specifies the QSPI Handle.
|
||||
* @param __FLAG__: specifies the QSPI flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg QSPI_FLAG_BUSY: QSPI Busy flag
|
||||
* @arg QSPI_FLAG_TO: QSPI Time out flag
|
||||
* @arg QSPI_FLAG_SM: QSPI Status match flag
|
||||
* @arg QSPI_FLAG_FT: QSPI FIFO threshold flag
|
||||
* @arg QSPI_FLAG_TC: QSPI Transfer complete flag
|
||||
* @arg QSPI_FLAG_TE: QSPI Transfer error flag
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) (READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0)
|
||||
|
||||
/** @brief Clears the specified QSPI's flag status.
|
||||
* @param __HANDLE__: specifies the QSPI Handle.
|
||||
* @param __FLAG__: specifies the QSPI clear register flag that needs to be set
|
||||
* This parameter can be one of the following values:
|
||||
* @arg QSPI_FLAG_TO: QSPI Time out flag
|
||||
* @arg QSPI_FLAG_SM: QSPI Status match flag
|
||||
* @arg QSPI_FLAG_TC: QSPI Transfer complete flag
|
||||
* @arg QSPI_FLAG_TE: QSPI Transfer error flag
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_QSPI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup QSPI_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup QSPI_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Initialization/de-initialization functions ********************************/
|
||||
HAL_StatusTypeDef HAL_QSPI_Init (QSPI_HandleTypeDef *hqspi);
|
||||
HAL_StatusTypeDef HAL_QSPI_DeInit (QSPI_HandleTypeDef *hqspi);
|
||||
void HAL_QSPI_MspInit (QSPI_HandleTypeDef *hqspi);
|
||||
void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup QSPI_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* IO operation functions *****************************************************/
|
||||
/* QSPI IRQ handler method */
|
||||
void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi);
|
||||
|
||||
/* QSPI indirect mode */
|
||||
HAL_StatusTypeDef HAL_QSPI_Command (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_QSPI_Transmit (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_QSPI_Receive (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_QSPI_Command_IT (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd);
|
||||
HAL_StatusTypeDef HAL_QSPI_Transmit_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
|
||||
HAL_StatusTypeDef HAL_QSPI_Receive_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
|
||||
HAL_StatusTypeDef HAL_QSPI_Transmit_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
|
||||
HAL_StatusTypeDef HAL_QSPI_Receive_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
|
||||
|
||||
/* QSPI status flag polling mode */
|
||||
HAL_StatusTypeDef HAL_QSPI_AutoPolling (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg);
|
||||
|
||||
/* QSPI memory-mapped mode */
|
||||
HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup QSPI_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
/* Callback functions in non-blocking modes ***********************************/
|
||||
void HAL_QSPI_ErrorCallback (QSPI_HandleTypeDef *hqspi);
|
||||
void HAL_QSPI_AbortCpltCallback (QSPI_HandleTypeDef *hqspi);
|
||||
void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi);
|
||||
|
||||
/* QSPI indirect mode */
|
||||
void HAL_QSPI_CmdCpltCallback (QSPI_HandleTypeDef *hqspi);
|
||||
void HAL_QSPI_RxCpltCallback (QSPI_HandleTypeDef *hqspi);
|
||||
void HAL_QSPI_TxCpltCallback (QSPI_HandleTypeDef *hqspi);
|
||||
void HAL_QSPI_RxHalfCpltCallback (QSPI_HandleTypeDef *hqspi);
|
||||
void HAL_QSPI_TxHalfCpltCallback (QSPI_HandleTypeDef *hqspi);
|
||||
|
||||
/* QSPI status flag polling mode */
|
||||
void HAL_QSPI_StatusMatchCallback (QSPI_HandleTypeDef *hqspi);
|
||||
|
||||
/* QSPI memory-mapped mode */
|
||||
void HAL_QSPI_TimeOutCallback (QSPI_HandleTypeDef *hqspi);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup QSPI_Exported_Functions_Group4
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral Control and State functions ************************************/
|
||||
HAL_QSPI_StateTypeDef HAL_QSPI_GetState (QSPI_HandleTypeDef *hqspi);
|
||||
uint32_t HAL_QSPI_GetError (QSPI_HandleTypeDef *hqspi);
|
||||
HAL_StatusTypeDef HAL_QSPI_Abort (QSPI_HandleTypeDef *hqspi);
|
||||
HAL_StatusTypeDef HAL_QSPI_Abort_IT (QSPI_HandleTypeDef *hqspi);
|
||||
void HAL_QSPI_SetTimeout (QSPI_HandleTypeDef *hqspi, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold);
|
||||
uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup QSPI_Private_Macros QSPI Private Macros
|
||||
* @{
|
||||
*/
|
||||
/** @defgroup QSPI_ClockPrescaler QSPI Clock Prescaler
|
||||
* @{
|
||||
*/
|
||||
#define IS_QSPI_CLOCK_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFF)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup QSPI_FifoThreshold QSPI Fifo Threshold
|
||||
* @{
|
||||
*/
|
||||
#define IS_QSPI_FIFO_THRESHOLD(THR) (((THR) > 0) && ((THR) <= 32))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#define IS_QSPI_SSHIFT(SSHIFT) (((SSHIFT) == QSPI_SAMPLE_SHIFTING_NONE) || \
|
||||
((SSHIFT) == QSPI_SAMPLE_SHIFTING_HALFCYCLE))
|
||||
|
||||
/** @defgroup QSPI_FlashSize QSPI Flash Size
|
||||
* @{
|
||||
*/
|
||||
#define IS_QSPI_FLASH_SIZE(FSIZE) (((FSIZE) <= 31))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#define IS_QSPI_CS_HIGH_TIME(CSHTIME) (((CSHTIME) == QSPI_CS_HIGH_TIME_1_CYCLE) || \
|
||||
((CSHTIME) == QSPI_CS_HIGH_TIME_2_CYCLE) || \
|
||||
((CSHTIME) == QSPI_CS_HIGH_TIME_3_CYCLE) || \
|
||||
((CSHTIME) == QSPI_CS_HIGH_TIME_4_CYCLE) || \
|
||||
((CSHTIME) == QSPI_CS_HIGH_TIME_5_CYCLE) || \
|
||||
((CSHTIME) == QSPI_CS_HIGH_TIME_6_CYCLE) || \
|
||||
((CSHTIME) == QSPI_CS_HIGH_TIME_7_CYCLE) || \
|
||||
((CSHTIME) == QSPI_CS_HIGH_TIME_8_CYCLE))
|
||||
|
||||
#define IS_QSPI_CLOCK_MODE(CLKMODE) (((CLKMODE) == QSPI_CLOCK_MODE_0) || \
|
||||
((CLKMODE) == QSPI_CLOCK_MODE_3))
|
||||
|
||||
#define IS_QSPI_FLASH_ID(FLA) (((FLA) == QSPI_FLASH_ID_1) || \
|
||||
((FLA) == QSPI_FLASH_ID_2))
|
||||
|
||||
#define IS_QSPI_DUAL_FLASH_MODE(MODE) (((MODE) == QSPI_DUALFLASH_ENABLE) || \
|
||||
((MODE) == QSPI_DUALFLASH_DISABLE))
|
||||
|
||||
|
||||
/** @defgroup QSPI_Instruction QSPI Instruction
|
||||
* @{
|
||||
*/
|
||||
#define IS_QSPI_INSTRUCTION(INSTRUCTION) ((INSTRUCTION) <= 0xFF)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#define IS_QSPI_ADDRESS_SIZE(ADDR_SIZE) (((ADDR_SIZE) == QSPI_ADDRESS_8_BITS) || \
|
||||
((ADDR_SIZE) == QSPI_ADDRESS_16_BITS) || \
|
||||
((ADDR_SIZE) == QSPI_ADDRESS_24_BITS) || \
|
||||
((ADDR_SIZE) == QSPI_ADDRESS_32_BITS))
|
||||
|
||||
#define IS_QSPI_ALTERNATE_BYTES_SIZE(SIZE) (((SIZE) == QSPI_ALTERNATE_BYTES_8_BITS) || \
|
||||
((SIZE) == QSPI_ALTERNATE_BYTES_16_BITS) || \
|
||||
((SIZE) == QSPI_ALTERNATE_BYTES_24_BITS) || \
|
||||
((SIZE) == QSPI_ALTERNATE_BYTES_32_BITS))
|
||||
|
||||
|
||||
/** @defgroup QSPI_DummyCycles QSPI Dummy Cycles
|
||||
* @{
|
||||
*/
|
||||
#define IS_QSPI_DUMMY_CYCLES(DCY) ((DCY) <= 31)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#define IS_QSPI_INSTRUCTION_MODE(MODE) (((MODE) == QSPI_INSTRUCTION_NONE) || \
|
||||
((MODE) == QSPI_INSTRUCTION_1_LINE) || \
|
||||
((MODE) == QSPI_INSTRUCTION_2_LINES) || \
|
||||
((MODE) == QSPI_INSTRUCTION_4_LINES))
|
||||
|
||||
#define IS_QSPI_ADDRESS_MODE(MODE) (((MODE) == QSPI_ADDRESS_NONE) || \
|
||||
((MODE) == QSPI_ADDRESS_1_LINE) || \
|
||||
((MODE) == QSPI_ADDRESS_2_LINES) || \
|
||||
((MODE) == QSPI_ADDRESS_4_LINES))
|
||||
|
||||
#define IS_QSPI_ALTERNATE_BYTES_MODE(MODE) (((MODE) == QSPI_ALTERNATE_BYTES_NONE) || \
|
||||
((MODE) == QSPI_ALTERNATE_BYTES_1_LINE) || \
|
||||
((MODE) == QSPI_ALTERNATE_BYTES_2_LINES) || \
|
||||
((MODE) == QSPI_ALTERNATE_BYTES_4_LINES))
|
||||
|
||||
#define IS_QSPI_DATA_MODE(MODE) (((MODE) == QSPI_DATA_NONE) || \
|
||||
((MODE) == QSPI_DATA_1_LINE) || \
|
||||
((MODE) == QSPI_DATA_2_LINES) || \
|
||||
((MODE) == QSPI_DATA_4_LINES))
|
||||
|
||||
#define IS_QSPI_DDR_MODE(DDR_MODE) (((DDR_MODE) == QSPI_DDR_MODE_DISABLE) || \
|
||||
((DDR_MODE) == QSPI_DDR_MODE_ENABLE))
|
||||
|
||||
#define IS_QSPI_DDR_HHC(DDR_HHC) (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY) || \
|
||||
((DDR_HHC) == QSPI_DDR_HHC_HALF_CLK_DELAY))
|
||||
|
||||
#define IS_QSPI_SIOO_MODE(SIOO_MODE) (((SIOO_MODE) == QSPI_SIOO_INST_EVERY_CMD) || \
|
||||
((SIOO_MODE) == QSPI_SIOO_INST_ONLY_FIRST_CMD))
|
||||
|
||||
/** @defgroup QSPI_Interval QSPI Interval
|
||||
* @{
|
||||
*/
|
||||
#define IS_QSPI_INTERVAL(INTERVAL) ((INTERVAL) <= QUADSPI_PIR_INTERVAL)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup QSPI_StatusBytesSize QSPI Status Bytes Size
|
||||
* @{
|
||||
*/
|
||||
#define IS_QSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1) && ((SIZE) <= 4))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#define IS_QSPI_MATCH_MODE(MODE) (((MODE) == QSPI_MATCH_MODE_AND) || \
|
||||
((MODE) == QSPI_MATCH_MODE_OR))
|
||||
|
||||
#define IS_QSPI_AUTOMATIC_STOP(APMS) (((APMS) == QSPI_AUTOMATIC_STOP_DISABLE) || \
|
||||
((APMS) == QSPI_AUTOMATIC_STOP_ENABLE))
|
||||
|
||||
#define IS_QSPI_TIMEOUT_ACTIVATION(TCEN) (((TCEN) == QSPI_TIMEOUT_COUNTER_DISABLE) || \
|
||||
((TCEN) == QSPI_TIMEOUT_COUNTER_ENABLE))
|
||||
|
||||
/** @defgroup QSPI_TimeOutPeriod QSPI TimeOut Period
|
||||
* @{
|
||||
*/
|
||||
#define IS_QSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFF)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#define IS_QSPI_GET_FLAG(FLAG) (((FLAG) == QSPI_FLAG_BUSY) || \
|
||||
((FLAG) == QSPI_FLAG_TO) || \
|
||||
((FLAG) == QSPI_FLAG_SM) || \
|
||||
((FLAG) == QSPI_FLAG_FT) || \
|
||||
((FLAG) == QSPI_FLAG_TC) || \
|
||||
((FLAG) == QSPI_FLAG_TE))
|
||||
|
||||
#define IS_QSPI_IT(IT) ((((IT) & (uint32_t)0xFFE0FFFFU) == 0x00000000U) && ((IT) != 0x00000000U))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup QSPI_Private_Functions QSPI Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F7xx_HAL_QSPI_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,358 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_hal_rng.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.2
|
||||
* @date 14-April-2017
|
||||
* @brief Header file of RNG HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F7xx_HAL_RNG_H
|
||||
#define __STM32F7xx_HAL_RNG_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup RNG RNG
|
||||
* @brief RNG HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup RNG_Exported_Types RNG Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup RNG_Exported_Types_Group1 RNG State Structure definition
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_RNG_STATE_RESET = 0x00U, /*!< RNG not yet initialized or disabled */
|
||||
HAL_RNG_STATE_READY = 0x01U, /*!< RNG initialized and ready for use */
|
||||
HAL_RNG_STATE_BUSY = 0x02U, /*!< RNG internal process is ongoing */
|
||||
HAL_RNG_STATE_TIMEOUT = 0x03U, /*!< RNG timeout state */
|
||||
HAL_RNG_STATE_ERROR = 0x04U /*!< RNG error state */
|
||||
|
||||
}HAL_RNG_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RNG_Exported_Types_Group2 RNG Handle Structure definition
|
||||
* @{
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
RNG_TypeDef *Instance; /*!< Register base address */
|
||||
|
||||
uint32_t RandomNumber; /*!< Last Generated random number */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< RNG locking object */
|
||||
|
||||
__IO HAL_RNG_StateTypeDef State; /*!< RNG communication state */
|
||||
|
||||
}RNG_HandleTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup RNG_Exported_Constants RNG Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup RNG_Exported_Constants_Group1 RNG Interrupt definition
|
||||
* @{
|
||||
*/
|
||||
#define RNG_IT_DRDY RNG_SR_DRDY /*!< Data Ready interrupt */
|
||||
#define RNG_IT_CEI RNG_SR_CEIS /*!< Clock error interrupt */
|
||||
#define RNG_IT_SEI RNG_SR_SEIS /*!< Seed error interrupt */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RNG_Exported_Constants_Group2 RNG Flag definition
|
||||
* @{
|
||||
*/
|
||||
#define RNG_FLAG_DRDY RNG_SR_DRDY /*!< Data ready */
|
||||
#define RNG_FLAG_CECS RNG_SR_CECS /*!< Clock error current status */
|
||||
#define RNG_FLAG_SECS RNG_SR_SECS /*!< Seed error current status */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
|
||||
/** @defgroup RNG_Exported_Macros RNG Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset RNG handle state
|
||||
* @param __HANDLE__: RNG Handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RNG_STATE_RESET)
|
||||
|
||||
/**
|
||||
* @brief Enables the RNG peripheral.
|
||||
* @param __HANDLE__: RNG Handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RNG_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= RNG_CR_RNGEN)
|
||||
|
||||
/**
|
||||
* @brief Disables the RNG peripheral.
|
||||
* @param __HANDLE__: RNG Handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RNG_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_RNGEN)
|
||||
|
||||
/**
|
||||
* @brief Check the selected RNG flag status.
|
||||
* @param __HANDLE__: RNG Handle
|
||||
* @param __FLAG__: RNG flag
|
||||
* This parameter can be one of the following values:
|
||||
* @arg RNG_FLAG_DRDY: Data ready
|
||||
* @arg RNG_FLAG_CECS: Clock error current status
|
||||
* @arg RNG_FLAG_SECS: Seed error current status
|
||||
* @retval The new state of __FLAG__ (SET or RESET).
|
||||
*/
|
||||
#define __HAL_RNG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
|
||||
|
||||
/**
|
||||
* @brief Clears the selected RNG flag status.
|
||||
* @param __HANDLE__: RNG handle
|
||||
* @param __FLAG__: RNG flag to clear
|
||||
* @note WARNING: This is a dummy macro for HAL code alignment,
|
||||
* flags RNG_FLAG_DRDY, RNG_FLAG_CECS and RNG_FLAG_SECS are read-only.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RNG_CLEAR_FLAG(__HANDLE__, __FLAG__) /* dummy macro */
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Enables the RNG interrupts.
|
||||
* @param __HANDLE__: RNG Handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RNG_ENABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR |= RNG_CR_IE)
|
||||
|
||||
/**
|
||||
* @brief Disables the RNG interrupts.
|
||||
* @param __HANDLE__: RNG Handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RNG_DISABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_IE)
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified RNG interrupt has occurred or not.
|
||||
* @param __HANDLE__: RNG Handle
|
||||
* @param __INTERRUPT__: specifies the RNG interrupt status flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg RNG_IT_DRDY: Data ready interrupt
|
||||
* @arg RNG_IT_CEI: Clock error interrupt
|
||||
* @arg RNG_IT_SEI: Seed error interrupt
|
||||
* @retval The new state of __INTERRUPT__ (SET or RESET).
|
||||
*/
|
||||
#define __HAL_RNG_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Clear the RNG interrupt status flags.
|
||||
* @param __HANDLE__: RNG Handle
|
||||
* @param __INTERRUPT__: specifies the RNG interrupt status flag to clear.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg RNG_IT_CEI: Clock error interrupt
|
||||
* @arg RNG_IT_SEI: Seed error interrupt
|
||||
* @note RNG_IT_DRDY flag is read-only, reading RNG_DR register automatically clears RNG_IT_DRDY.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RNG_CLEAR_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR) = ~(__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup RNG_Exported_Functions RNG Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup RNG_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng);
|
||||
HAL_StatusTypeDef HAL_RNG_DeInit (RNG_HandleTypeDef *hrng);
|
||||
void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng);
|
||||
void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RNG_Exported_Functions_Group2 Peripheral Control functions
|
||||
* @{
|
||||
*/
|
||||
uint32_t HAL_RNG_GetRandomNumber(RNG_HandleTypeDef *hrng); /* Obsolete, use HAL_RNG_GenerateRandomNumber() instead */
|
||||
uint32_t HAL_RNG_GetRandomNumber_IT(RNG_HandleTypeDef *hrng); /* Obsolete, use HAL_RNG_GenerateRandomNumber_IT() instead */
|
||||
|
||||
HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit);
|
||||
HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng);
|
||||
uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng);
|
||||
|
||||
void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng);
|
||||
void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng);
|
||||
void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef* hrng, uint32_t random32bit);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RNG_Exported_Functions_Group3 Peripheral State functions
|
||||
* @{
|
||||
*/
|
||||
HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/** @defgroup RNG_Private_Types RNG Private Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private defines -----------------------------------------------------------*/
|
||||
/** @defgroup RNG_Private_Defines RNG Private Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/** @defgroup RNG_Private_Variables RNG Private Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup RNG_Private_Constants RNG Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup RNG_Private_Macros RNG Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_RNG_IT(IT) (((IT) == RNG_IT_CEI) || \
|
||||
((IT) == RNG_IT_SEI))
|
||||
|
||||
#define IS_RNG_FLAG(FLAG) (((FLAG) == RNG_FLAG_DRDY) || \
|
||||
((FLAG) == RNG_FLAG_CECS) || \
|
||||
((FLAG) == RNG_FLAG_SECS))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions prototypes ----------------------------------------------*/
|
||||
/** @defgroup RNG_Private_Functions_Prototypes RNG Private Functions Prototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup RNG_Private_Functions RNG Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F7xx_HAL_RNG_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,813 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_hal_rtc.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.2
|
||||
* @date 14-April-2017
|
||||
* @brief Header file of RTC HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F7xx_HAL_RTC_H
|
||||
#define __STM32F7xx_HAL_RTC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup RTC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup RTC_Exported_Types RTC Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief HAL State structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_RTC_STATE_RESET = 0x00U, /*!< RTC not yet initialized or disabled */
|
||||
HAL_RTC_STATE_READY = 0x01U, /*!< RTC initialized and ready for use */
|
||||
HAL_RTC_STATE_BUSY = 0x02U, /*!< RTC process is ongoing */
|
||||
HAL_RTC_STATE_TIMEOUT = 0x03U, /*!< RTC timeout state */
|
||||
HAL_RTC_STATE_ERROR = 0x04U /*!< RTC error state */
|
||||
|
||||
}HAL_RTCStateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief RTC Configuration Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t HourFormat; /*!< Specifies the RTC Hour Format.
|
||||
This parameter can be a value of @ref RTC_Hour_Formats */
|
||||
|
||||
uint32_t AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value.
|
||||
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F */
|
||||
|
||||
uint32_t SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value.
|
||||
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF */
|
||||
|
||||
uint32_t OutPut; /*!< Specifies which signal will be routed to the RTC output.
|
||||
This parameter can be a value of @ref RTCEx_Output_selection_Definitions */
|
||||
|
||||
uint32_t OutPutPolarity; /*!< Specifies the polarity of the output signal.
|
||||
This parameter can be a value of @ref RTC_Output_Polarity_Definitions */
|
||||
|
||||
uint32_t OutPutType; /*!< Specifies the RTC Output Pin mode.
|
||||
This parameter can be a value of @ref RTC_Output_Type_ALARM_OUT */
|
||||
}RTC_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief RTC Time structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t Hours; /*!< Specifies the RTC Time Hour.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the RTC_HourFormat_12 is selected.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the RTC_HourFormat_24 is selected */
|
||||
|
||||
uint8_t Minutes; /*!< Specifies the RTC Time Minutes.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
|
||||
|
||||
uint8_t Seconds; /*!< Specifies the RTC Time Seconds.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
|
||||
|
||||
uint32_t SubSeconds; /*!< Specifies the RTC_SSR RTC Sub Second register content.
|
||||
This parameter corresponds to a time unit range between [0-1] Second
|
||||
with [1 Sec / SecondFraction +1] granularity */
|
||||
|
||||
uint32_t SecondFraction; /*!< Specifies the range or granularity of Sub Second register content
|
||||
corresponding to Synchronous pre-scaler factor value (PREDIV_S)
|
||||
This parameter corresponds to a time unit range between [0-1] Second
|
||||
with [1 Sec / SecondFraction +1] granularity.
|
||||
This field will be used only by HAL_RTC_GetTime function */
|
||||
|
||||
uint8_t TimeFormat; /*!< Specifies the RTC AM/PM Time.
|
||||
This parameter can be a value of @ref RTC_AM_PM_Definitions */
|
||||
|
||||
uint32_t DayLightSaving; /*!< Specifies RTC_DayLightSaveOperation: the value of hour adjustment.
|
||||
This parameter can be a value of @ref RTC_DayLightSaving_Definitions */
|
||||
|
||||
uint32_t StoreOperation; /*!< Specifies RTC_StoreOperation value to be written in the BCK bit
|
||||
in CR register to store the operation.
|
||||
This parameter can be a value of @ref RTC_StoreOperation_Definitions */
|
||||
}RTC_TimeTypeDef;
|
||||
|
||||
/**
|
||||
* @brief RTC Date structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t WeekDay; /*!< Specifies the RTC Date WeekDay.
|
||||
This parameter can be a value of @ref RTC_WeekDay_Definitions */
|
||||
|
||||
uint8_t Month; /*!< Specifies the RTC Date Month (in BCD format).
|
||||
This parameter can be a value of @ref RTC_Month_Date_Definitions */
|
||||
|
||||
uint8_t Date; /*!< Specifies the RTC Date.
|
||||
This parameter must be a number between Min_Data = 1 and Max_Data = 31 */
|
||||
|
||||
uint8_t Year; /*!< Specifies the RTC Date Year.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 99 */
|
||||
|
||||
}RTC_DateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief RTC Alarm structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
RTC_TimeTypeDef AlarmTime; /*!< Specifies the RTC Alarm Time members */
|
||||
|
||||
uint32_t AlarmMask; /*!< Specifies the RTC Alarm Masks.
|
||||
This parameter can be a value of @ref RTC_AlarmMask_Definitions */
|
||||
|
||||
uint32_t AlarmSubSecondMask; /*!< Specifies the RTC Alarm SubSeconds Masks.
|
||||
This parameter can be a value of @ref RTC_Alarm_Sub_Seconds_Masks_Definitions */
|
||||
|
||||
uint32_t AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on Date or WeekDay.
|
||||
This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */
|
||||
|
||||
uint8_t AlarmDateWeekDay; /*!< Specifies the RTC Alarm Date/WeekDay.
|
||||
If the Alarm Date is selected, this parameter must be set to a value in the 1-31 range.
|
||||
If the Alarm WeekDay is selected, this parameter can be a value of @ref RTC_WeekDay_Definitions */
|
||||
|
||||
uint32_t Alarm; /*!< Specifies the alarm .
|
||||
This parameter can be a value of @ref RTC_Alarms_Definitions */
|
||||
}RTC_AlarmTypeDef;
|
||||
|
||||
/**
|
||||
* @brief RTC Handle Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
RTC_TypeDef *Instance; /*!< Register base address */
|
||||
|
||||
RTC_InitTypeDef Init; /*!< RTC required parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< RTC locking object */
|
||||
|
||||
__IO HAL_RTCStateTypeDef State; /*!< Time communication state */
|
||||
|
||||
}RTC_HandleTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup RTC_Exported_Constants RTC Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Hour_Formats RTC Hour Formats
|
||||
* @{
|
||||
*/
|
||||
#define RTC_HOURFORMAT_24 0x00000000U
|
||||
#define RTC_HOURFORMAT_12 0x00000040U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup RTC_Output_Polarity_Definitions RTC Output Polarity Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_OUTPUT_POLARITY_HIGH 0x00000000U
|
||||
#define RTC_OUTPUT_POLARITY_LOW 0x00100000U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Output_Type_ALARM_OUT RTC Output Type ALARM OUT
|
||||
* @{
|
||||
*/
|
||||
#define RTC_OUTPUT_TYPE_OPENDRAIN 0x00000000U
|
||||
#define RTC_OUTPUT_TYPE_PUSHPULL RTC_OR_ALARMTYPE /* 0x00000008 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_AM_PM_Definitions RTC AM PM Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_HOURFORMAT12_AM ((uint8_t)0x00U)
|
||||
#define RTC_HOURFORMAT12_PM ((uint8_t)0x40U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_DayLightSaving_Definitions RTC DayLight Saving Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_DAYLIGHTSAVING_SUB1H 0x00020000U
|
||||
#define RTC_DAYLIGHTSAVING_ADD1H 0x00010000U
|
||||
#define RTC_DAYLIGHTSAVING_NONE 0x00000000U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_StoreOperation_Definitions RTC Store Operation Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_STOREOPERATION_RESET 0x00000000U
|
||||
#define RTC_STOREOPERATION_SET 0x00040000U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Input_parameter_format_definitions RTC Input Parameter Format Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_FORMAT_BIN 0x00000000U
|
||||
#define RTC_FORMAT_BCD 0x00000001U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Month_Date_Definitions RTC Month Date Definitions
|
||||
* @{
|
||||
*/
|
||||
/* Coded in BCD format */
|
||||
#define RTC_MONTH_JANUARY ((uint8_t)0x01U)
|
||||
#define RTC_MONTH_FEBRUARY ((uint8_t)0x02U)
|
||||
#define RTC_MONTH_MARCH ((uint8_t)0x03U)
|
||||
#define RTC_MONTH_APRIL ((uint8_t)0x04U)
|
||||
#define RTC_MONTH_MAY ((uint8_t)0x05U)
|
||||
#define RTC_MONTH_JUNE ((uint8_t)0x06U)
|
||||
#define RTC_MONTH_JULY ((uint8_t)0x07U)
|
||||
#define RTC_MONTH_AUGUST ((uint8_t)0x08U)
|
||||
#define RTC_MONTH_SEPTEMBER ((uint8_t)0x09U)
|
||||
#define RTC_MONTH_OCTOBER ((uint8_t)0x10U)
|
||||
#define RTC_MONTH_NOVEMBER ((uint8_t)0x11U)
|
||||
#define RTC_MONTH_DECEMBER ((uint8_t)0x12U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_WeekDay_Definitions RTC WeekDay Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_WEEKDAY_MONDAY ((uint8_t)0x01U)
|
||||
#define RTC_WEEKDAY_TUESDAY ((uint8_t)0x02U)
|
||||
#define RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03U)
|
||||
#define RTC_WEEKDAY_THURSDAY ((uint8_t)0x04U)
|
||||
#define RTC_WEEKDAY_FRIDAY ((uint8_t)0x05U)
|
||||
#define RTC_WEEKDAY_SATURDAY ((uint8_t)0x06U)
|
||||
#define RTC_WEEKDAY_SUNDAY ((uint8_t)0x07U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_AlarmDateWeekDay_Definitions RTC Alarm Date WeekDay Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_ALARMDATEWEEKDAYSEL_DATE 0x00000000U
|
||||
#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY 0x40000000U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_AlarmMask_Definitions RTC Alarm Mask Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_ALARMMASK_NONE 0x00000000U
|
||||
#define RTC_ALARMMASK_DATEWEEKDAY RTC_ALRMAR_MSK4
|
||||
#define RTC_ALARMMASK_HOURS RTC_ALRMAR_MSK3
|
||||
#define RTC_ALARMMASK_MINUTES RTC_ALRMAR_MSK2
|
||||
#define RTC_ALARMMASK_SECONDS RTC_ALRMAR_MSK1
|
||||
#define RTC_ALARMMASK_ALL 0x80808080U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Alarms_Definitions RTC Alarms Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_ALARM_A RTC_CR_ALRAE
|
||||
#define RTC_ALARM_B RTC_CR_ALRBE
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions RTC Alarm Sub Seconds Masks Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_ALARMSUBSECONDMASK_ALL 0x00000000U /*!< All Alarm SS fields are masked.
|
||||
There is no comparison on sub seconds
|
||||
for Alarm */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_1 0x01000000U /*!< SS[14:1] are don't care in Alarm
|
||||
comparison. Only SS[0] is compared. */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_2 0x02000000U /*!< SS[14:2] are don't care in Alarm
|
||||
comparison. Only SS[1:0] are compared */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_3 0x03000000U /*!< SS[14:3] are don't care in Alarm
|
||||
comparison. Only SS[2:0] are compared */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_4 0x04000000U /*!< SS[14:4] are don't care in Alarm
|
||||
comparison. Only SS[3:0] are compared */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_5 0x05000000U /*!< SS[14:5] are don't care in Alarm
|
||||
comparison. Only SS[4:0] are compared */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_6 0x06000000U /*!< SS[14:6] are don't care in Alarm
|
||||
comparison. Only SS[5:0] are compared */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_7 0x07000000U /*!< SS[14:7] are don't care in Alarm
|
||||
comparison. Only SS[6:0] are compared */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_8 0x08000000U /*!< SS[14:8] are don't care in Alarm
|
||||
comparison. Only SS[7:0] are compared */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_9 0x09000000U /*!< SS[14:9] are don't care in Alarm
|
||||
comparison. Only SS[8:0] are compared */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_10 0x0A000000U /*!< SS[14:10] are don't care in Alarm
|
||||
comparison. Only SS[9:0] are compared */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_11 0x0B000000U /*!< SS[14:11] are don't care in Alarm
|
||||
comparison. Only SS[10:0] are compared */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_12 0x0C000000U /*!< SS[14:12] are don't care in Alarm
|
||||
comparison.Only SS[11:0] are compared */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_13 0x0D000000U /*!< SS[14:13] are don't care in Alarm
|
||||
comparison. Only SS[12:0] are compared */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14 0x0E000000U /*!< SS[14] is don't care in Alarm
|
||||
comparison.Only SS[13:0] are compared */
|
||||
#define RTC_ALARMSUBSECONDMASK_NONE 0x0F000000U /*!< SS[14:0] are compared and must match
|
||||
to activate alarm. */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Interrupts_Definitions RTC Interrupts Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_IT_TS RTC_CR_TSIE
|
||||
#define RTC_IT_WUT RTC_CR_WUTIE
|
||||
#define RTC_IT_ALRA RTC_CR_ALRAIE
|
||||
#define RTC_IT_ALRB RTC_CR_ALRBIE
|
||||
#define RTC_IT_TAMP RTC_TAMPCR_TAMPIE /* Used only to Enable the Tamper Interrupt */
|
||||
#define RTC_IT_TAMP1 RTC_TAMPCR_TAMP1IE
|
||||
#define RTC_IT_TAMP2 RTC_TAMPCR_TAMP2IE
|
||||
#define RTC_IT_TAMP3 RTC_TAMPCR_TAMP3IE
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Flags_Definitions RTC Flags Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_FLAG_RECALPF RTC_ISR_RECALPF
|
||||
#define RTC_FLAG_TAMP3F RTC_ISR_TAMP3F
|
||||
#define RTC_FLAG_TAMP2F RTC_ISR_TAMP2F
|
||||
#define RTC_FLAG_TAMP1F RTC_ISR_TAMP1F
|
||||
#define RTC_FLAG_TSOVF RTC_ISR_TSOVF
|
||||
#define RTC_FLAG_TSF RTC_ISR_TSF
|
||||
#define RTC_FLAG_ITSF RTC_ISR_ITSF
|
||||
#define RTC_FLAG_WUTF RTC_ISR_WUTF
|
||||
#define RTC_FLAG_ALRBF RTC_ISR_ALRBF
|
||||
#define RTC_FLAG_ALRAF RTC_ISR_ALRAF
|
||||
#define RTC_FLAG_INITF RTC_ISR_INITF
|
||||
#define RTC_FLAG_RSF RTC_ISR_RSF
|
||||
#define RTC_FLAG_INITS RTC_ISR_INITS
|
||||
#define RTC_FLAG_SHPF RTC_ISR_SHPF
|
||||
#define RTC_FLAG_WUTWF RTC_ISR_WUTWF
|
||||
#define RTC_FLAG_ALRBWF RTC_ISR_ALRBWF
|
||||
#define RTC_FLAG_ALRAWF RTC_ISR_ALRAWF
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup RTC_Exported_Macros RTC Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset RTC handle state
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET)
|
||||
|
||||
/**
|
||||
* @brief Disable the write protection for RTC registers.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__) \
|
||||
do{ \
|
||||
(__HANDLE__)->Instance->WPR = 0xCAU; \
|
||||
(__HANDLE__)->Instance->WPR = 0x53U; \
|
||||
} while(0U)
|
||||
|
||||
/**
|
||||
* @brief Enable the write protection for RTC registers.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__) \
|
||||
do{ \
|
||||
(__HANDLE__)->Instance->WPR = 0xFFU; \
|
||||
} while(0U)
|
||||
|
||||
/**
|
||||
* @brief Enable the RTC ALARMA peripheral.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_ALARMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRAE))
|
||||
|
||||
/**
|
||||
* @brief Disable the RTC ALARMA peripheral.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_ALARMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRAE))
|
||||
|
||||
/**
|
||||
* @brief Enable the RTC ALARMB peripheral.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_ALARMB_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRBE))
|
||||
|
||||
/**
|
||||
* @brief Disable the RTC ALARMB peripheral.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_ALARMB_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRBE))
|
||||
|
||||
/**
|
||||
* @brief Enable the RTC Alarm interrupt.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to be enabled or disabled.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg RTC_IT_ALRA: Alarm A interrupt
|
||||
* @arg RTC_IT_ALRB: Alarm B interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Disable the RTC Alarm interrupt.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to be enabled or disabled.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg RTC_IT_ALRA: Alarm A interrupt
|
||||
* @arg RTC_IT_ALRB: Alarm B interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified RTC Alarm interrupt has occurred or not.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @param __INTERRUPT__: specifies the RTC Alarm interrupt to check.
|
||||
* This parameter can be:
|
||||
* @arg RTC_IT_ALRA: Alarm A interrupt
|
||||
* @arg RTC_IT_ALRB: Alarm B interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) ((((((__HANDLE__)->Instance->ISR)& ((__INTERRUPT__)>> 4U)) & 0x0000FFFFU) != RESET)? SET : RESET)
|
||||
|
||||
/**
|
||||
* @brief Get the selected RTC Alarm's flag status.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @param __FLAG__: specifies the RTC Alarm Flag to check.
|
||||
* This parameter can be:
|
||||
* @arg RTC_FLAG_ALRAF
|
||||
* @arg RTC_FLAG_ALRBF
|
||||
* @arg RTC_FLAG_ALRAWF
|
||||
* @arg RTC_FLAG_ALRBWF
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
|
||||
|
||||
/**
|
||||
* @brief Clear the RTC Alarm's pending flags.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @param __FLAG__: specifies the RTC Alarm Flag sources to be enabled or disabled.
|
||||
* This parameter can be:
|
||||
* @arg RTC_FLAG_ALRAF
|
||||
* @arg RTC_FLAG_ALRBF
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0000FFFFU)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified RTC Alarm interrupt has been enabled or not.
|
||||
* @param __HANDLE__: specifies the RTC handle.
|
||||
* @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to check.
|
||||
* This parameter can be:
|
||||
* @arg RTC_IT_ALRA: Alarm A interrupt
|
||||
* @arg RTC_IT_ALRB: Alarm B interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
|
||||
|
||||
/**
|
||||
* @brief Enable interrupt on the RTC Alarm associated Exti line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_EXTI_ENABLE_IT() (EXTI->IMR |= RTC_EXTI_LINE_ALARM_EVENT)
|
||||
|
||||
/**
|
||||
* @brief Disable interrupt on the RTC Alarm associated Exti line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_EXTI_DISABLE_IT() (EXTI->IMR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
|
||||
|
||||
/**
|
||||
* @brief Enable event on the RTC Alarm associated Exti line.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_ALARM_EVENT)
|
||||
|
||||
/**
|
||||
* @brief Disable event on the RTC Alarm associated Exti line.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
|
||||
|
||||
/**
|
||||
* @brief Enable falling edge trigger on the RTC Alarm associated Exti line.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= RTC_EXTI_LINE_ALARM_EVENT)
|
||||
|
||||
/**
|
||||
* @brief Disable falling edge trigger on the RTC Alarm associated Exti line.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
|
||||
|
||||
/**
|
||||
* @brief Enable rising edge trigger on the RTC Alarm associated Exti line.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= RTC_EXTI_LINE_ALARM_EVENT)
|
||||
|
||||
/**
|
||||
* @brief Disable rising edge trigger on the RTC Alarm associated Exti line.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
|
||||
|
||||
/**
|
||||
* @brief Enable rising & falling edge trigger on the RTC Alarm associated Exti line.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE();__HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE();
|
||||
|
||||
/**
|
||||
* @brief Disable rising & falling edge trigger on the RTC Alarm associated Exti line.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE();__HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE();
|
||||
|
||||
/**
|
||||
* @brief Check whether the RTC Alarm associated Exti line interrupt flag is set or not.
|
||||
* @retval Line Status.
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_EXTI_GET_FLAG() (EXTI->PR & RTC_EXTI_LINE_ALARM_EVENT)
|
||||
|
||||
/**
|
||||
* @brief Clear the RTC Alarm associated Exti line flag.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() (EXTI->PR = RTC_EXTI_LINE_ALARM_EVENT)
|
||||
|
||||
/**
|
||||
* @brief Generate a Software interrupt on RTC Alarm associated Exti line.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() (EXTI->SWIER |= RTC_EXTI_LINE_ALARM_EVENT)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include RTC HAL Extension module */
|
||||
#include "stm32f7xx_hal_rtc_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup RTC_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup RTC_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Initialization and de-initialization functions ****************************/
|
||||
HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc);
|
||||
HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc);
|
||||
void HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc);
|
||||
void HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup RTC_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* RTC Time and Date functions ************************************************/
|
||||
HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
|
||||
HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
|
||||
HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
|
||||
HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup RTC_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
/* RTC Alarm functions ********************************************************/
|
||||
HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);
|
||||
HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);
|
||||
HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm);
|
||||
HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format);
|
||||
void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc);
|
||||
HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
|
||||
void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup RTC_Exported_Functions_Group4
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral Control functions ***********************************************/
|
||||
HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup RTC_Exported_Functions_Group5
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State functions *************************************************/
|
||||
HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup RTC_Private_Constants RTC Private Constants
|
||||
* @{
|
||||
*/
|
||||
/* Masks Definition */
|
||||
#define RTC_TR_RESERVED_MASK 0x007F7F7FU
|
||||
#define RTC_DR_RESERVED_MASK 0x00FFFF3FU
|
||||
#define RTC_INIT_MASK 0xFFFFFFFFU
|
||||
#define RTC_RSF_MASK 0xFFFFFF5FU
|
||||
|
||||
#define RTC_TIMEOUT_VALUE 1000U
|
||||
|
||||
#define RTC_EXTI_LINE_ALARM_EVENT EXTI_IMR_IM17 /*!< External interrupt line 17 Connected to the RTC Alarm event */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup RTC_Private_Macros RTC Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_IS_RTC_Definitions RTC Private macros to check input parameters
|
||||
* @{
|
||||
*/
|
||||
#define IS_RTC_HOUR_FORMAT(__FORMAT__) (((__FORMAT__) == RTC_HOURFORMAT_12) || \
|
||||
((__FORMAT__) == RTC_HOURFORMAT_24))
|
||||
#define IS_RTC_OUTPUT_POL(__POL__) (((__POL__) == RTC_OUTPUT_POLARITY_HIGH) || \
|
||||
((__POL__) == RTC_OUTPUT_POLARITY_LOW))
|
||||
#define IS_RTC_OUTPUT_TYPE(__TYPE__) (((__TYPE__) == RTC_OUTPUT_TYPE_OPENDRAIN) || \
|
||||
((__TYPE__) == RTC_OUTPUT_TYPE_PUSHPULL))
|
||||
#define IS_RTC_ASYNCH_PREDIV(__PREDIV__) ((__PREDIV__) <= 0x7FU)
|
||||
#define IS_RTC_SYNCH_PREDIV(__PREDIV__) ((__PREDIV__) <= 0x7FFFU)
|
||||
#define IS_RTC_HOUR12(__HOUR__) (((__HOUR__) > 0U) && ((__HOUR__) <= 12U))
|
||||
#define IS_RTC_HOUR24(__HOUR__) ((__HOUR__) <= 23U)
|
||||
#define IS_RTC_MINUTES(__MINUTES__) ((__MINUTES__) <= 59U)
|
||||
#define IS_RTC_SECONDS(__SECONDS__) ((__SECONDS__) <= 59U)
|
||||
#define IS_RTC_HOURFORMAT12(__PM__) (((__PM__) == RTC_HOURFORMAT12_AM) || ((__PM__) == RTC_HOURFORMAT12_PM))
|
||||
#define IS_RTC_DAYLIGHT_SAVING(__SAVE__) (((__SAVE__) == RTC_DAYLIGHTSAVING_SUB1H) || \
|
||||
((__SAVE__) == RTC_DAYLIGHTSAVING_ADD1H) || \
|
||||
((__SAVE__) == RTC_DAYLIGHTSAVING_NONE))
|
||||
#define IS_RTC_STORE_OPERATION(__OPERATION__) (((__OPERATION__) == RTC_STOREOPERATION_RESET) || \
|
||||
((__OPERATION__) == RTC_STOREOPERATION_SET))
|
||||
#define IS_RTC_FORMAT(__FORMAT__) (((__FORMAT__) == RTC_FORMAT_BIN) || ((__FORMAT__) == RTC_FORMAT_BCD))
|
||||
#define IS_RTC_YEAR(__YEAR__) ((__YEAR__) <= 99U)
|
||||
#define IS_RTC_MONTH(__MONTH__) (((__MONTH__) >= 1U) && ((__MONTH__) <= 12U))
|
||||
#define IS_RTC_DATE(__DATE__) (((__DATE__) >= 1U) && ((__DATE__) <= 31U))
|
||||
#define IS_RTC_WEEKDAY(__WEEKDAY__) (((__WEEKDAY__) == RTC_WEEKDAY_MONDAY) || \
|
||||
((__WEEKDAY__) == RTC_WEEKDAY_TUESDAY) || \
|
||||
((__WEEKDAY__) == RTC_WEEKDAY_WEDNESDAY) || \
|
||||
((__WEEKDAY__) == RTC_WEEKDAY_THURSDAY) || \
|
||||
((__WEEKDAY__) == RTC_WEEKDAY_FRIDAY) || \
|
||||
((__WEEKDAY__) == RTC_WEEKDAY_SATURDAY) || \
|
||||
((__WEEKDAY__) == RTC_WEEKDAY_SUNDAY))
|
||||
|
||||
#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(__DATE__) (((__DATE__) >0U) && ((__DATE__) <= 31U))
|
||||
#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(__WEEKDAY__) (((__WEEKDAY__) == RTC_WEEKDAY_MONDAY) || \
|
||||
((__WEEKDAY__) == RTC_WEEKDAY_TUESDAY) || \
|
||||
((__WEEKDAY__) == RTC_WEEKDAY_WEDNESDAY) || \
|
||||
((__WEEKDAY__) == RTC_WEEKDAY_THURSDAY) || \
|
||||
((__WEEKDAY__) == RTC_WEEKDAY_FRIDAY) || \
|
||||
((__WEEKDAY__) == RTC_WEEKDAY_SATURDAY) || \
|
||||
((__WEEKDAY__) == RTC_WEEKDAY_SUNDAY))
|
||||
#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(__SEL__) (((__SEL__) == RTC_ALARMDATEWEEKDAYSEL_DATE) || \
|
||||
((__SEL__) == RTC_ALARMDATEWEEKDAYSEL_WEEKDAY))
|
||||
#define IS_RTC_ALARM_MASK(__MASK__) (((__MASK__) & 0x7F7F7F7FU) == (uint32_t)RESET)
|
||||
#define IS_RTC_ALARM(__ALARM__) (((__ALARM__) == RTC_ALARM_A) || ((__ALARM__) == RTC_ALARM_B))
|
||||
#define IS_RTC_ALARM_SUB_SECOND_VALUE(__VALUE__) ((__VALUE__) <= 0x00007FFFU)
|
||||
#define IS_RTC_ALARM_SUB_SECOND_MASK(__MASK__) (((__MASK__) == RTC_ALARMSUBSECONDMASK_ALL) || \
|
||||
((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_1) || \
|
||||
((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_2) || \
|
||||
((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_3) || \
|
||||
((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_4) || \
|
||||
((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_5) || \
|
||||
((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_6) || \
|
||||
((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_7) || \
|
||||
((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_8) || \
|
||||
((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_9) || \
|
||||
((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_10) || \
|
||||
((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_11) || \
|
||||
((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_12) || \
|
||||
((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_13) || \
|
||||
((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14) || \
|
||||
((__MASK__) == RTC_ALARMSUBSECONDMASK_NONE))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup RTC_Private_Functions RTC Private Functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc);
|
||||
uint8_t RTC_ByteToBcd2(uint8_t Value);
|
||||
uint8_t RTC_Bcd2ToByte(uint8_t Value);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F7xx_HAL_RTC_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,850 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_hal_sai.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.2
|
||||
* @date 14-April-2017
|
||||
* @brief Header file of SAI HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F7xx_HAL_SAI_H
|
||||
#define __STM32F7xx_HAL_SAI_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup SAI
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup SAI_Exported_Types SAI Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief HAL State structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_SAI_STATE_RESET = 0x00U, /*!< SAI not yet initialized or disabled */
|
||||
HAL_SAI_STATE_READY = 0x01U, /*!< SAI initialized and ready for use */
|
||||
HAL_SAI_STATE_BUSY = 0x02U, /*!< SAI internal process is ongoing */
|
||||
HAL_SAI_STATE_BUSY_TX = 0x12U, /*!< Data transmission process is ongoing */
|
||||
HAL_SAI_STATE_BUSY_RX = 0x22U, /*!< Data reception process is ongoing */
|
||||
}HAL_SAI_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief SAI Callback prototype
|
||||
*/
|
||||
typedef void (*SAIcallback)(void);
|
||||
|
||||
/** @defgroup SAI_Init_Structure_definition SAI Init Structure definition
|
||||
* @brief SAI Init Structure definition
|
||||
* @{
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t AudioMode; /*!< Specifies the SAI Block audio Mode.
|
||||
This parameter can be a value of @ref SAI_Block_Mode */
|
||||
|
||||
uint32_t Synchro; /*!< Specifies SAI Block synchronization
|
||||
This parameter can be a value of @ref SAI_Block_Synchronization */
|
||||
|
||||
uint32_t SynchroExt; /*!< Specifies SAI external output synchronization, this setup is common
|
||||
for BlockA and BlockB
|
||||
This parameter can be a value of @ref SAI_Block_SyncExt
|
||||
@note: If both audio blocks of same SAI are used, this parameter has
|
||||
to be set to the same value for each audio block */
|
||||
|
||||
uint32_t OutputDrive; /*!< Specifies when SAI Block outputs are driven.
|
||||
This parameter can be a value of @ref SAI_Block_Output_Drive
|
||||
@note this value has to be set before enabling the audio block
|
||||
but after the audio block configuration. */
|
||||
|
||||
uint32_t NoDivider; /*!< Specifies whether master clock will be divided or not.
|
||||
This parameter can be a value of @ref SAI_Block_NoDivider
|
||||
@note: If bit NODIV in the SAI_xCR1 register is cleared, the frame length
|
||||
should be aligned to a number equal to a power of 2, from 8 to 256.
|
||||
If bit NODIV in the SAI_xCR1 register is set, the frame length can
|
||||
take any of the values without constraint since the input clock of
|
||||
the audio block should be equal to the bit clock.
|
||||
There is no MCLK_x clock which can be output. */
|
||||
|
||||
uint32_t FIFOThreshold; /*!< Specifies SAI Block FIFO threshold.
|
||||
This parameter can be a value of @ref SAI_Block_Fifo_Threshold */
|
||||
|
||||
uint32_t AudioFrequency; /*!< Specifies the audio frequency sampling.
|
||||
This parameter can be a value of @ref SAI_Audio_Frequency */
|
||||
|
||||
uint32_t Mckdiv; /*!< Specifies the master clock divider, the parameter will be used if for
|
||||
AudioFrequency the user choice
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 15 */
|
||||
|
||||
uint32_t MonoStereoMode; /*!< Specifies if the mono or stereo mode is selected.
|
||||
This parameter can be a value of @ref SAI_Mono_Stereo_Mode */
|
||||
|
||||
uint32_t CompandingMode; /*!< Specifies the companding mode type.
|
||||
This parameter can be a value of @ref SAI_Block_Companding_Mode */
|
||||
|
||||
uint32_t TriState; /*!< Specifies the companding mode type.
|
||||
This parameter can be a value of @ref SAI_TRIState_Management */
|
||||
|
||||
/* This part of the structure is automatically filled if your are using the high level initialisation
|
||||
function HAL_SAI_InitProtocol */
|
||||
|
||||
uint32_t Protocol; /*!< Specifies the SAI Block protocol.
|
||||
This parameter can be a value of @ref SAI_Block_Protocol */
|
||||
|
||||
uint32_t DataSize; /*!< Specifies the SAI Block data size.
|
||||
This parameter can be a value of @ref SAI_Block_Data_Size */
|
||||
|
||||
uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
|
||||
This parameter can be a value of @ref SAI_Block_MSB_LSB_transmission */
|
||||
|
||||
uint32_t ClockStrobing; /*!< Specifies the SAI Block clock strobing edge sensitivity.
|
||||
This parameter can be a value of @ref SAI_Block_Clock_Strobing */
|
||||
}SAI_InitTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SAI_Frame_Structure_definition SAI Frame Structure definition
|
||||
* @brief SAI Frame Init structure definition
|
||||
* @{
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
|
||||
uint32_t FrameLength; /*!< Specifies the Frame length, the number of SCK clocks for each audio frame.
|
||||
This parameter must be a number between Min_Data = 8 and Max_Data = 256.
|
||||
@note: If master clock MCLK_x pin is declared as an output, the frame length
|
||||
should be aligned to a number equal to power of 2 in order to keep
|
||||
in an audio frame, an integer number of MCLK pulses by bit Clock. */
|
||||
|
||||
uint32_t ActiveFrameLength; /*!< Specifies the Frame synchronization active level length.
|
||||
This Parameter specifies the length in number of bit clock (SCK + 1)
|
||||
of the active level of FS signal in audio frame.
|
||||
This parameter must be a number between Min_Data = 1 and Max_Data = 128 */
|
||||
|
||||
uint32_t FSDefinition; /*!< Specifies the Frame synchronization definition.
|
||||
This parameter can be a value of @ref SAI_Block_FS_Definition */
|
||||
|
||||
uint32_t FSPolarity; /*!< Specifies the Frame synchronization Polarity.
|
||||
This parameter can be a value of @ref SAI_Block_FS_Polarity */
|
||||
|
||||
uint32_t FSOffset; /*!< Specifies the Frame synchronization Offset.
|
||||
This parameter can be a value of @ref SAI_Block_FS_Offset */
|
||||
|
||||
}SAI_FrameInitTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SAI_Slot_Structure_definition SAI Slot Structure definition
|
||||
* @brief SAI Block Slot Init Structure definition
|
||||
* @{
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t FirstBitOffset; /*!< Specifies the position of first data transfer bit in the slot.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 24 */
|
||||
|
||||
uint32_t SlotSize; /*!< Specifies the Slot Size.
|
||||
This parameter can be a value of @ref SAI_Block_Slot_Size */
|
||||
|
||||
uint32_t SlotNumber; /*!< Specifies the number of slot in the audio frame.
|
||||
This parameter must be a number between Min_Data = 1 and Max_Data = 16 */
|
||||
|
||||
uint32_t SlotActive; /*!< Specifies the slots in audio frame that will be activated.
|
||||
This parameter can be a value of @ref SAI_Block_Slot_Active */
|
||||
}SAI_SlotInitTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SAI_Handle_Structure_definition SAI Handle Structure definition
|
||||
* @brief SAI handle Structure definition
|
||||
* @{
|
||||
*/
|
||||
typedef struct __SAI_HandleTypeDef
|
||||
{
|
||||
SAI_Block_TypeDef *Instance; /*!< SAI Blockx registers base address */
|
||||
|
||||
SAI_InitTypeDef Init; /*!< SAI communication parameters */
|
||||
|
||||
SAI_FrameInitTypeDef FrameInit; /*!< SAI Frame configuration parameters */
|
||||
|
||||
SAI_SlotInitTypeDef SlotInit; /*!< SAI Slot configuration parameters */
|
||||
|
||||
uint8_t *pBuffPtr; /*!< Pointer to SAI transfer Buffer */
|
||||
|
||||
uint16_t XferSize; /*!< SAI transfer size */
|
||||
|
||||
uint16_t XferCount; /*!< SAI transfer counter */
|
||||
|
||||
DMA_HandleTypeDef *hdmatx; /*!< SAI Tx DMA handle parameters */
|
||||
|
||||
DMA_HandleTypeDef *hdmarx; /*!< SAI Rx DMA handle parameters */
|
||||
|
||||
SAIcallback mutecallback; /*!< SAI mute callback */
|
||||
|
||||
void (*InterruptServiceRoutine)(struct __SAI_HandleTypeDef *hsai); /* function pointer for IRQ handler */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< SAI locking object */
|
||||
|
||||
__IO HAL_SAI_StateTypeDef State; /*!< SAI communication state */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< SAI Error code */
|
||||
}SAI_HandleTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup SAI_Exported_Constants SAI Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup SAI_Error_Code SAI Error Code
|
||||
* @{
|
||||
*/
|
||||
#define HAL_SAI_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
|
||||
#define HAL_SAI_ERROR_OVR ((uint32_t)0x00000001U) /*!< Overrun Error */
|
||||
#define HAL_SAI_ERROR_UDR ((uint32_t)0x00000002U) /*!< Underrun error */
|
||||
#define HAL_SAI_ERROR_AFSDET ((uint32_t)0x00000004U) /*!< Anticipated Frame synchronisation detection */
|
||||
#define HAL_SAI_ERROR_LFSDET ((uint32_t)0x00000008U) /*!< Late Frame synchronisation detection */
|
||||
#define HAL_SAI_ERROR_CNREADY ((uint32_t)0x00000010U) /*!< codec not ready */
|
||||
#define HAL_SAI_ERROR_WCKCFG ((uint32_t)0x00000020U) /*!< Wrong clock configuration */
|
||||
#define HAL_SAI_ERROR_TIMEOUT ((uint32_t)0x00000040U) /*!< Timeout error */
|
||||
#define HAL_SAI_ERROR_DMA ((uint32_t)0x00000080U) /*!< DMA error */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SAI_Block_SyncExt SAI External synchronisation
|
||||
* @{
|
||||
*/
|
||||
#define SAI_SYNCEXT_DISABLE 0
|
||||
#define SAI_SYNCEXT_OUTBLOCKA_ENABLE 1
|
||||
#define SAI_SYNCEXT_OUTBLOCKB_ENABLE 2
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SAI_Protocol SAI Supported protocol
|
||||
* @{
|
||||
*/
|
||||
#define SAI_I2S_STANDARD 0
|
||||
#define SAI_I2S_MSBJUSTIFIED 1
|
||||
#define SAI_I2S_LSBJUSTIFIED 2
|
||||
#define SAI_PCM_LONG 3
|
||||
#define SAI_PCM_SHORT 4
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SAI_Protocol_DataSize SAI protocol data size
|
||||
* @{
|
||||
*/
|
||||
#define SAI_PROTOCOL_DATASIZE_16BIT 0
|
||||
#define SAI_PROTOCOL_DATASIZE_16BITEXTENDED 1
|
||||
#define SAI_PROTOCOL_DATASIZE_24BIT 2
|
||||
#define SAI_PROTOCOL_DATASIZE_32BIT 3
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SAI_Audio_Frequency SAI Audio Frequency
|
||||
* @{
|
||||
*/
|
||||
#define SAI_AUDIO_FREQUENCY_192K ((uint32_t)192000U)
|
||||
#define SAI_AUDIO_FREQUENCY_96K ((uint32_t)96000U)
|
||||
#define SAI_AUDIO_FREQUENCY_48K ((uint32_t)48000U)
|
||||
#define SAI_AUDIO_FREQUENCY_44K ((uint32_t)44100U)
|
||||
#define SAI_AUDIO_FREQUENCY_32K ((uint32_t)32000U)
|
||||
#define SAI_AUDIO_FREQUENCY_22K ((uint32_t)22050U)
|
||||
#define SAI_AUDIO_FREQUENCY_16K ((uint32_t)16000U)
|
||||
#define SAI_AUDIO_FREQUENCY_11K ((uint32_t)11025U)
|
||||
#define SAI_AUDIO_FREQUENCY_8K ((uint32_t)8000U)
|
||||
#define SAI_AUDIO_FREQUENCY_MCKDIV ((uint32_t)0U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SAI_Block_Mode SAI Block Mode
|
||||
* @{
|
||||
*/
|
||||
#define SAI_MODEMASTER_TX ((uint32_t)0x00000000U)
|
||||
#define SAI_MODEMASTER_RX ((uint32_t)SAI_xCR1_MODE_0)
|
||||
#define SAI_MODESLAVE_TX ((uint32_t)SAI_xCR1_MODE_1)
|
||||
#define SAI_MODESLAVE_RX ((uint32_t)(SAI_xCR1_MODE_1 | SAI_xCR1_MODE_0))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SAI_Block_Protocol SAI Block Protocol
|
||||
* @{
|
||||
*/
|
||||
#define SAI_FREE_PROTOCOL ((uint32_t)0x00000000U)
|
||||
#define SAI_SPDIF_PROTOCOL ((uint32_t)SAI_xCR1_PRTCFG_0)
|
||||
#define SAI_AC97_PROTOCOL ((uint32_t)SAI_xCR1_PRTCFG_1)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SAI_Block_Data_Size SAI Block Data Size
|
||||
* @{
|
||||
*/
|
||||
#define SAI_DATASIZE_8 ((uint32_t)SAI_xCR1_DS_1)
|
||||
#define SAI_DATASIZE_10 ((uint32_t)(SAI_xCR1_DS_1 | SAI_xCR1_DS_0))
|
||||
#define SAI_DATASIZE_16 ((uint32_t)SAI_xCR1_DS_2)
|
||||
#define SAI_DATASIZE_20 ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_0))
|
||||
#define SAI_DATASIZE_24 ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_1))
|
||||
#define SAI_DATASIZE_32 ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_1 | SAI_xCR1_DS_0))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SAI_Block_MSB_LSB_transmission SAI Block MSB LSB transmission
|
||||
* @{
|
||||
*/
|
||||
#define SAI_FIRSTBIT_MSB ((uint32_t)0x00000000U)
|
||||
#define SAI_FIRSTBIT_LSB ((uint32_t)SAI_xCR1_LSBFIRST)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SAI_Block_Clock_Strobing SAI Block Clock Strobing
|
||||
* @{
|
||||
*/
|
||||
#define SAI_CLOCKSTROBING_FALLINGEDGE 0
|
||||
#define SAI_CLOCKSTROBING_RISINGEDGE 1
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SAI_Block_Synchronization SAI Block Synchronization
|
||||
* @{
|
||||
*/
|
||||
#define SAI_ASYNCHRONOUS 0 /*!< Asynchronous */
|
||||
#define SAI_SYNCHRONOUS 1 /*!< Synchronous with other block of same SAI */
|
||||
#define SAI_SYNCHRONOUS_EXT_SAI1 2 /*!< Synchronous with other SAI, SAI1 */
|
||||
#define SAI_SYNCHRONOUS_EXT_SAI2 3 /*!< Synchronous with other SAI, SAI2 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SAI_Block_Output_Drive SAI Block Output Drive
|
||||
* @{
|
||||
*/
|
||||
#define SAI_OUTPUTDRIVE_DISABLE ((uint32_t)0x00000000U)
|
||||
#define SAI_OUTPUTDRIVE_ENABLE ((uint32_t)SAI_xCR1_OUTDRIV)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SAI_Block_NoDivider SAI Block NoDivider
|
||||
* @{
|
||||
*/
|
||||
#define SAI_MASTERDIVIDER_ENABLE ((uint32_t)0x00000000U)
|
||||
#define SAI_MASTERDIVIDER_DISABLE ((uint32_t)SAI_xCR1_NODIV)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup SAI_Block_FS_Definition SAI Block FS Definition
|
||||
* @{
|
||||
*/
|
||||
#define SAI_FS_STARTFRAME ((uint32_t)0x00000000U)
|
||||
#define SAI_FS_CHANNEL_IDENTIFICATION ((uint32_t)SAI_xFRCR_FSDEF)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SAI_Block_FS_Polarity SAI Block FS Polarity
|
||||
* @{
|
||||
*/
|
||||
#define SAI_FS_ACTIVE_LOW ((uint32_t)0x00000000U)
|
||||
#define SAI_FS_ACTIVE_HIGH ((uint32_t)SAI_xFRCR_FSPOL)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SAI_Block_FS_Offset SAI Block FS Offset
|
||||
* @{
|
||||
*/
|
||||
#define SAI_FS_FIRSTBIT ((uint32_t)0x00000000U)
|
||||
#define SAI_FS_BEFOREFIRSTBIT ((uint32_t)SAI_xFRCR_FSOFF)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup SAI_Block_Slot_Size SAI Block Slot Size
|
||||
* @{
|
||||
*/
|
||||
#define SAI_SLOTSIZE_DATASIZE ((uint32_t)0x00000000U)
|
||||
#define SAI_SLOTSIZE_16B ((uint32_t)SAI_xSLOTR_SLOTSZ_0)
|
||||
#define SAI_SLOTSIZE_32B ((uint32_t)SAI_xSLOTR_SLOTSZ_1)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SAI_Block_Slot_Active SAI Block Slot Active
|
||||
* @{
|
||||
*/
|
||||
#define SAI_SLOT_NOTACTIVE ((uint32_t)0x00000000U)
|
||||
#define SAI_SLOTACTIVE_0 ((uint32_t)0x00000001U)
|
||||
#define SAI_SLOTACTIVE_1 ((uint32_t)0x00000002U)
|
||||
#define SAI_SLOTACTIVE_2 ((uint32_t)0x00000004U)
|
||||
#define SAI_SLOTACTIVE_3 ((uint32_t)0x00000008U)
|
||||
#define SAI_SLOTACTIVE_4 ((uint32_t)0x00000010U)
|
||||
#define SAI_SLOTACTIVE_5 ((uint32_t)0x00000020U)
|
||||
#define SAI_SLOTACTIVE_6 ((uint32_t)0x00000040U)
|
||||
#define SAI_SLOTACTIVE_7 ((uint32_t)0x00000080U)
|
||||
#define SAI_SLOTACTIVE_8 ((uint32_t)0x00000100U)
|
||||
#define SAI_SLOTACTIVE_9 ((uint32_t)0x00000200U)
|
||||
#define SAI_SLOTACTIVE_10 ((uint32_t)0x00000400U)
|
||||
#define SAI_SLOTACTIVE_11 ((uint32_t)0x00000800U)
|
||||
#define SAI_SLOTACTIVE_12 ((uint32_t)0x00001000U)
|
||||
#define SAI_SLOTACTIVE_13 ((uint32_t)0x00002000U)
|
||||
#define SAI_SLOTACTIVE_14 ((uint32_t)0x00004000U)
|
||||
#define SAI_SLOTACTIVE_15 ((uint32_t)0x00008000U)
|
||||
#define SAI_SLOTACTIVE_ALL ((uint32_t)0x0000FFFFU)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SAI_Mono_Stereo_Mode SAI Mono Stereo Mode
|
||||
* @{
|
||||
*/
|
||||
#define SAI_STEREOMODE ((uint32_t)0x00000000U)
|
||||
#define SAI_MONOMODE ((uint32_t)SAI_xCR1_MONO)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SAI_TRIState_Management SAI TRIState Management
|
||||
* @{
|
||||
*/
|
||||
#define SAI_OUTPUT_NOTRELEASED ((uint32_t)0x00000000U)
|
||||
#define SAI_OUTPUT_RELEASED ((uint32_t)SAI_xCR2_TRIS)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SAI_Block_Fifo_Threshold SAI Block Fifo Threshold
|
||||
* @{
|
||||
*/
|
||||
#define SAI_FIFOTHRESHOLD_EMPTY ((uint32_t)0x00000000U)
|
||||
#define SAI_FIFOTHRESHOLD_1QF ((uint32_t)(SAI_xCR2_FTH_0))
|
||||
#define SAI_FIFOTHRESHOLD_HF ((uint32_t)(SAI_xCR2_FTH_1))
|
||||
#define SAI_FIFOTHRESHOLD_3QF ((uint32_t)(SAI_xCR2_FTH_1 | SAI_xCR2_FTH_0))
|
||||
#define SAI_FIFOTHRESHOLD_FULL ((uint32_t)(SAI_xCR2_FTH_2))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SAI_Block_Companding_Mode SAI Block Companding Mode
|
||||
* @{
|
||||
*/
|
||||
#define SAI_NOCOMPANDING ((uint32_t)0x00000000U)
|
||||
#define SAI_ULAW_1CPL_COMPANDING ((uint32_t)(SAI_xCR2_COMP_1))
|
||||
#define SAI_ALAW_1CPL_COMPANDING ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0))
|
||||
#define SAI_ULAW_2CPL_COMPANDING ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_CPL))
|
||||
#define SAI_ALAW_2CPL_COMPANDING ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0 | SAI_xCR2_CPL))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SAI_Block_Mute_Value SAI Block Mute Value
|
||||
* @{
|
||||
*/
|
||||
#define SAI_ZERO_VALUE ((uint32_t)0x00000000U)
|
||||
#define SAI_LAST_SENT_VALUE ((uint32_t)SAI_xCR2_MUTEVAL)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SAI_Block_Interrupts_Definition SAI Block Interrupts Definition
|
||||
* @{
|
||||
*/
|
||||
#define SAI_IT_OVRUDR ((uint32_t)SAI_xIMR_OVRUDRIE)
|
||||
#define SAI_IT_MUTEDET ((uint32_t)SAI_xIMR_MUTEDETIE)
|
||||
#define SAI_IT_WCKCFG ((uint32_t)SAI_xIMR_WCKCFGIE)
|
||||
#define SAI_IT_FREQ ((uint32_t)SAI_xIMR_FREQIE)
|
||||
#define SAI_IT_CNRDY ((uint32_t)SAI_xIMR_CNRDYIE)
|
||||
#define SAI_IT_AFSDET ((uint32_t)SAI_xIMR_AFSDETIE)
|
||||
#define SAI_IT_LFSDET ((uint32_t)SAI_xIMR_LFSDETIE)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SAI_Block_Flags_Definition SAI Block Flags Definition
|
||||
* @{
|
||||
*/
|
||||
#define SAI_FLAG_OVRUDR ((uint32_t)SAI_xSR_OVRUDR)
|
||||
#define SAI_FLAG_MUTEDET ((uint32_t)SAI_xSR_MUTEDET)
|
||||
#define SAI_FLAG_WCKCFG ((uint32_t)SAI_xSR_WCKCFG)
|
||||
#define SAI_FLAG_FREQ ((uint32_t)SAI_xSR_FREQ)
|
||||
#define SAI_FLAG_CNRDY ((uint32_t)SAI_xSR_CNRDY)
|
||||
#define SAI_FLAG_AFSDET ((uint32_t)SAI_xSR_AFSDET)
|
||||
#define SAI_FLAG_LFSDET ((uint32_t)SAI_xSR_LFSDET)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SAI_Block_Fifo_Status_Level SAI Block Fifo Status Level
|
||||
* @{
|
||||
*/
|
||||
#define SAI_FIFOSTATUS_EMPTY ((uint32_t)0x00000000U)
|
||||
#define SAI_FIFOSTATUS_LESS1QUARTERFULL ((uint32_t)0x00010000U)
|
||||
#define SAI_FIFOSTATUS_1QUARTERFULL ((uint32_t)0x00020000U)
|
||||
#define SAI_FIFOSTATUS_HALFFULL ((uint32_t)0x00030000U)
|
||||
#define SAI_FIFOSTATUS_3QUARTERFULL ((uint32_t)0x00040000U)
|
||||
#define SAI_FIFOSTATUS_FULL ((uint32_t)0x00050000U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup SAI_Exported_Macros SAI Exported Macros
|
||||
* @brief macros to handle interrupts and specific configurations
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset SAI handle state.
|
||||
* @param __HANDLE__: specifies the SAI Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SAI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SAI_STATE_RESET)
|
||||
|
||||
/** @brief Enable or disable the specified SAI interrupts.
|
||||
* @param __HANDLE__: specifies the SAI Handle.
|
||||
* @param __INTERRUPT__: specifies the interrupt source to enable or disable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SAI_IT_OVRUDR: Overrun underrun interrupt enable
|
||||
* @arg SAI_IT_MUTEDET: Mute detection interrupt enable
|
||||
* @arg SAI_IT_WCKCFG: Wrong Clock Configuration interrupt enable
|
||||
* @arg SAI_IT_FREQ: FIFO request interrupt enable
|
||||
* @arg SAI_IT_CNRDY: Codec not ready interrupt enable
|
||||
* @arg SAI_IT_AFSDET: Anticipated frame synchronization detection interrupt enable
|
||||
* @arg SAI_IT_LFSDET: Late frame synchronization detection interrupt enable
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SAI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR |= (__INTERRUPT__))
|
||||
#define __HAL_SAI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR &= (~(__INTERRUPT__)))
|
||||
|
||||
/** @brief Check whether the specified SAI interrupt source is enabled or not.
|
||||
* @param __HANDLE__: specifies the SAI Handle.
|
||||
* @param __INTERRUPT__: specifies the SAI interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SAI_IT_OVRUDR: Overrun underrun interrupt enable
|
||||
* @arg SAI_IT_MUTEDET: Mute detection interrupt enable
|
||||
* @arg SAI_IT_WCKCFG: Wrong Clock Configuration interrupt enable
|
||||
* @arg SAI_IT_FREQ: FIFO request interrupt enable
|
||||
* @arg SAI_IT_CNRDY: Codec not ready interrupt enable
|
||||
* @arg SAI_IT_AFSDET: Anticipated frame synchronization detection interrupt enable
|
||||
* @arg SAI_IT_LFSDET: Late frame synchronization detection interrupt enable
|
||||
* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_SAI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IMR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
||||
|
||||
/** @brief Check whether the specified SAI flag is set or not.
|
||||
* @param __HANDLE__: specifies the SAI Handle.
|
||||
* @param __FLAG__: specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SAI_FLAG_OVRUDR: Overrun underrun flag.
|
||||
* @arg SAI_FLAG_MUTEDET: Mute detection flag.
|
||||
* @arg SAI_FLAG_WCKCFG: Wrong Clock Configuration flag.
|
||||
* @arg SAI_FLAG_FREQ: FIFO request flag.
|
||||
* @arg SAI_FLAG_CNRDY: Codec not ready flag.
|
||||
* @arg SAI_FLAG_AFSDET: Anticipated frame synchronization detection flag.
|
||||
* @arg SAI_FLAG_LFSDET: Late frame synchronization detection flag.
|
||||
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_SAI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
|
||||
|
||||
/** @brief Clear the specified SAI pending flag.
|
||||
* @param __HANDLE__: specifies the SAI Handle.
|
||||
* @param __FLAG__: specifies the flag to check.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg SAI_FLAG_OVRUDR: Clear Overrun underrun
|
||||
* @arg SAI_FLAG_MUTEDET: Clear Mute detection
|
||||
* @arg SAI_FLAG_WCKCFG: Clear Wrong Clock Configuration
|
||||
* @arg SAI_FLAG_FREQ: Clear FIFO request
|
||||
* @arg SAI_FLAG_CNRDY: Clear Codec not ready
|
||||
* @arg SAI_FLAG_AFSDET: Clear Anticipated frame synchronization detection
|
||||
* @arg SAI_FLAG_LFSDET: Clear Late frame synchronization detection
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SAI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CLRFR = (__FLAG__))
|
||||
|
||||
#define __HAL_SAI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SAI_xCR1_SAIEN)
|
||||
#define __HAL_SAI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~SAI_xCR1_SAIEN)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @addtogroup SAI_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Initialization/de-initialization functions ********************************/
|
||||
|
||||
/** @addtogroup SAI_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_SAI_InitProtocol(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot);
|
||||
HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai);
|
||||
HAL_StatusTypeDef HAL_SAI_DeInit (SAI_HandleTypeDef *hsai);
|
||||
void HAL_SAI_MspInit(SAI_HandleTypeDef *hsai);
|
||||
void HAL_SAI_MspDeInit(SAI_HandleTypeDef *hsai);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* I/O operation functions ***************************************************/
|
||||
|
||||
/** @addtogroup SAI_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_SAI_Receive(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
|
||||
/* Non-Blocking mode: Interrupt */
|
||||
HAL_StatusTypeDef HAL_SAI_Transmit_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_SAI_Receive_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size);
|
||||
|
||||
/* Non-Blocking mode: DMA */
|
||||
HAL_StatusTypeDef HAL_SAI_Transmit_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_SAI_Receive_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_SAI_DMAPause(SAI_HandleTypeDef *hsai);
|
||||
HAL_StatusTypeDef HAL_SAI_DMAResume(SAI_HandleTypeDef *hsai);
|
||||
HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai);
|
||||
|
||||
/* Abort function */
|
||||
HAL_StatusTypeDef HAL_SAI_Abort(SAI_HandleTypeDef *hsai);
|
||||
|
||||
/* Mute management */
|
||||
HAL_StatusTypeDef HAL_SAI_EnableTxMuteMode(SAI_HandleTypeDef *hsai, uint16_t val);
|
||||
HAL_StatusTypeDef HAL_SAI_DisableTxMuteMode(SAI_HandleTypeDef *hsai);
|
||||
HAL_StatusTypeDef HAL_SAI_EnableRxMuteMode(SAI_HandleTypeDef *hsai, SAIcallback callback, uint16_t counter);
|
||||
HAL_StatusTypeDef HAL_SAI_DisableRxMuteMode(SAI_HandleTypeDef *hsai);
|
||||
|
||||
/* SAI IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
|
||||
void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai);
|
||||
void HAL_SAI_TxHalfCpltCallback(SAI_HandleTypeDef *hsai);
|
||||
void HAL_SAI_TxCpltCallback(SAI_HandleTypeDef *hsai);
|
||||
void HAL_SAI_RxHalfCpltCallback(SAI_HandleTypeDef *hsai);
|
||||
void HAL_SAI_RxCpltCallback(SAI_HandleTypeDef *hsai);
|
||||
void HAL_SAI_ErrorCallback(SAI_HandleTypeDef *hsai);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup SAI_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State functions ************************************************/
|
||||
HAL_SAI_StateTypeDef HAL_SAI_GetState(SAI_HandleTypeDef *hsai);
|
||||
uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @addtogroup SAI_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_SAI_BLOCK_SYNCEXT(STATE) (((STATE) == SAI_SYNCEXT_DISABLE) ||\
|
||||
((STATE) == SAI_SYNCEXT_OUTBLOCKA_ENABLE) ||\
|
||||
((STATE) == SAI_SYNCEXT_OUTBLOCKB_ENABLE))
|
||||
|
||||
#define IS_SAI_SUPPORTED_PROTOCOL(PROTOCOL) (((PROTOCOL) == SAI_I2S_STANDARD) ||\
|
||||
((PROTOCOL) == SAI_I2S_MSBJUSTIFIED) ||\
|
||||
((PROTOCOL) == SAI_I2S_LSBJUSTIFIED) ||\
|
||||
((PROTOCOL) == SAI_PCM_LONG) ||\
|
||||
((PROTOCOL) == SAI_PCM_SHORT))
|
||||
|
||||
#define IS_SAI_PROTOCOL_DATASIZE(DATASIZE) (((DATASIZE) == SAI_PROTOCOL_DATASIZE_16BIT) ||\
|
||||
((DATASIZE) == SAI_PROTOCOL_DATASIZE_16BITEXTENDED) ||\
|
||||
((DATASIZE) == SAI_PROTOCOL_DATASIZE_24BIT) ||\
|
||||
((DATASIZE) == SAI_PROTOCOL_DATASIZE_32BIT))
|
||||
|
||||
#define IS_SAI_AUDIO_FREQUENCY(AUDIO) (((AUDIO) == SAI_AUDIO_FREQUENCY_192K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_96K) || \
|
||||
((AUDIO) == SAI_AUDIO_FREQUENCY_48K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_44K) || \
|
||||
((AUDIO) == SAI_AUDIO_FREQUENCY_32K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_22K) || \
|
||||
((AUDIO) == SAI_AUDIO_FREQUENCY_16K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_11K) || \
|
||||
((AUDIO) == SAI_AUDIO_FREQUENCY_8K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_MCKDIV))
|
||||
|
||||
#define IS_SAI_BLOCK_MODE(MODE) (((MODE) == SAI_MODEMASTER_TX) || \
|
||||
((MODE) == SAI_MODEMASTER_RX) || \
|
||||
((MODE) == SAI_MODESLAVE_TX) || \
|
||||
((MODE) == SAI_MODESLAVE_RX))
|
||||
|
||||
#define IS_SAI_BLOCK_PROTOCOL(PROTOCOL) (((PROTOCOL) == SAI_FREE_PROTOCOL) || \
|
||||
((PROTOCOL) == SAI_AC97_PROTOCOL) || \
|
||||
((PROTOCOL) == SAI_SPDIF_PROTOCOL))
|
||||
|
||||
#define IS_SAI_BLOCK_DATASIZE(DATASIZE) (((DATASIZE) == SAI_DATASIZE_8) || \
|
||||
((DATASIZE) == SAI_DATASIZE_10) || \
|
||||
((DATASIZE) == SAI_DATASIZE_16) || \
|
||||
((DATASIZE) == SAI_DATASIZE_20) || \
|
||||
((DATASIZE) == SAI_DATASIZE_24) || \
|
||||
((DATASIZE) == SAI_DATASIZE_32))
|
||||
|
||||
#define IS_SAI_BLOCK_FIRST_BIT(BIT) (((BIT) == SAI_FIRSTBIT_MSB) || \
|
||||
((BIT) == SAI_FIRSTBIT_LSB))
|
||||
|
||||
#define IS_SAI_BLOCK_CLOCK_STROBING(CLOCK) (((CLOCK) == SAI_CLOCKSTROBING_FALLINGEDGE) || \
|
||||
((CLOCK) == SAI_CLOCKSTROBING_RISINGEDGE))
|
||||
|
||||
#define IS_SAI_BLOCK_SYNCHRO(SYNCHRO) (((SYNCHRO) == SAI_ASYNCHRONOUS) || \
|
||||
((SYNCHRO) == SAI_SYNCHRONOUS) || \
|
||||
((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI1) || \
|
||||
((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI2))
|
||||
|
||||
#define IS_SAI_BLOCK_OUTPUT_DRIVE(DRIVE) (((DRIVE) == SAI_OUTPUTDRIVE_DISABLE) || \
|
||||
((DRIVE) == SAI_OUTPUTDRIVE_ENABLE))
|
||||
|
||||
#define IS_SAI_BLOCK_NODIVIDER(NODIVIDER) (((NODIVIDER) == SAI_MASTERDIVIDER_ENABLE) || \
|
||||
((NODIVIDER) == SAI_MASTERDIVIDER_DISABLE))
|
||||
|
||||
#define IS_SAI_BLOCK_MUTE_COUNTER(COUNTER) ((COUNTER) <= 63)
|
||||
|
||||
#define IS_SAI_BLOCK_MUTE_VALUE(VALUE) (((VALUE) == SAI_ZERO_VALUE) || \
|
||||
((VALUE) == SAI_LAST_SENT_VALUE))
|
||||
|
||||
#define IS_SAI_BLOCK_COMPANDING_MODE(MODE) (((MODE) == SAI_NOCOMPANDING) || \
|
||||
((MODE) == SAI_ULAW_1CPL_COMPANDING) || \
|
||||
((MODE) == SAI_ALAW_1CPL_COMPANDING) || \
|
||||
((MODE) == SAI_ULAW_2CPL_COMPANDING) || \
|
||||
((MODE) == SAI_ALAW_2CPL_COMPANDING))
|
||||
|
||||
#define IS_SAI_BLOCK_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == SAI_FIFOTHRESHOLD_EMPTY) || \
|
||||
((THRESHOLD) == SAI_FIFOTHRESHOLD_1QF) || \
|
||||
((THRESHOLD) == SAI_FIFOTHRESHOLD_HF) || \
|
||||
((THRESHOLD) == SAI_FIFOTHRESHOLD_3QF) || \
|
||||
((THRESHOLD) == SAI_FIFOTHRESHOLD_FULL))
|
||||
|
||||
#define IS_SAI_BLOCK_TRISTATE_MANAGEMENT(STATE) (((STATE) == SAI_OUTPUT_NOTRELEASED) ||\
|
||||
((STATE) == SAI_OUTPUT_RELEASED))
|
||||
|
||||
#define IS_SAI_MONO_STEREO_MODE(MODE) (((MODE) == SAI_MONOMODE) ||\
|
||||
((MODE) == SAI_STEREOMODE))
|
||||
|
||||
#define IS_SAI_SLOT_ACTIVE(ACTIVE) ((ACTIVE) <= SAI_SLOTACTIVE_ALL)
|
||||
|
||||
#define IS_SAI_BLOCK_SLOT_NUMBER(NUMBER) ((1 <= (NUMBER)) && ((NUMBER) <= 16))
|
||||
|
||||
#define IS_SAI_BLOCK_SLOT_SIZE(SIZE) (((SIZE) == SAI_SLOTSIZE_DATASIZE) || \
|
||||
((SIZE) == SAI_SLOTSIZE_16B) || \
|
||||
((SIZE) == SAI_SLOTSIZE_32B))
|
||||
|
||||
#define IS_SAI_BLOCK_FIRSTBIT_OFFSET(OFFSET) ((OFFSET) <= 24)
|
||||
|
||||
#define IS_SAI_BLOCK_FS_OFFSET(OFFSET) (((OFFSET) == SAI_FS_FIRSTBIT) || \
|
||||
((OFFSET) == SAI_FS_BEFOREFIRSTBIT))
|
||||
|
||||
#define IS_SAI_BLOCK_FS_POLARITY(POLARITY) (((POLARITY) == SAI_FS_ACTIVE_LOW) || \
|
||||
((POLARITY) == SAI_FS_ACTIVE_HIGH))
|
||||
|
||||
#define IS_SAI_BLOCK_FS_DEFINITION(DEFINITION) (((DEFINITION) == SAI_FS_STARTFRAME) || \
|
||||
((DEFINITION) == SAI_FS_CHANNEL_IDENTIFICATION))
|
||||
|
||||
#define IS_SAI_BLOCK_MASTER_DIVIDER(DIVIDER) ((DIVIDER) <= 15)
|
||||
|
||||
#define IS_SAI_BLOCK_FRAME_LENGTH(LENGTH) ((8 <= (LENGTH)) && ((LENGTH) <= 256))
|
||||
|
||||
#define IS_SAI_BLOCK_ACTIVE_FRAME(LENGTH) ((1 <= (LENGTH)) && ((LENGTH) <= 128))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup SAI_Private_Functions SAI Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F7xx_HAL_SAI_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,56 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_hal_sai_ex.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.2
|
||||
* @date 14-April-2017
|
||||
* @brief Header file of SAI Extension HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F7xx_HAL_SAI_EX_H
|
||||
#define __STM32F7xx_HAL_SAI_EX_H
|
||||
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/* Extended features functions ************************************************/
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
#endif /* __STM32F7xx_HAL_SAI_EX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,716 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_hal_sd.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.2
|
||||
* @date 14-April-2017
|
||||
* @brief Header file of SD HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F7xx_HAL_SD_H
|
||||
#define __STM32F7xx_HAL_SD_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx_ll_sdmmc.h"
|
||||
|
||||
/** @addtogroup STM32F7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup SD SD
|
||||
* @brief SD HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup SD_Exported_Types SD Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup SD_Exported_Types_Group1 SD State enumeration structure
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_SD_STATE_RESET = ((uint32_t)0x00000000U), /*!< SD not yet initialized or disabled */
|
||||
HAL_SD_STATE_READY = ((uint32_t)0x00000001U), /*!< SD initialized and ready for use */
|
||||
HAL_SD_STATE_TIMEOUT = ((uint32_t)0x00000002U), /*!< SD Timeout state */
|
||||
HAL_SD_STATE_BUSY = ((uint32_t)0x00000003U), /*!< SD process ongoing */
|
||||
HAL_SD_STATE_PROGRAMMING = ((uint32_t)0x00000004U), /*!< SD Programming State */
|
||||
HAL_SD_STATE_RECEIVING = ((uint32_t)0x00000005U), /*!< SD Receinving State */
|
||||
HAL_SD_STATE_TRANSFER = ((uint32_t)0x00000006U), /*!< SD Transfert State */
|
||||
HAL_SD_STATE_ERROR = ((uint32_t)0x0000000FU) /*!< SD is in error state */
|
||||
}HAL_SD_StateTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SD_Exported_Types_Group2 SD Card State enumeration structure
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_SD_CARD_READY = ((uint32_t)0x00000001U), /*!< Card state is ready */
|
||||
HAL_SD_CARD_IDENTIFICATION = ((uint32_t)0x00000002U), /*!< Card is in identification state */
|
||||
HAL_SD_CARD_STANDBY = ((uint32_t)0x00000003U), /*!< Card is in standby state */
|
||||
HAL_SD_CARD_TRANSFER = ((uint32_t)0x00000004U), /*!< Card is in transfer state */
|
||||
HAL_SD_CARD_SENDING = ((uint32_t)0x00000005U), /*!< Card is sending an operation */
|
||||
HAL_SD_CARD_RECEIVING = ((uint32_t)0x00000006U), /*!< Card is receiving operation information */
|
||||
HAL_SD_CARD_PROGRAMMING = ((uint32_t)0x00000007U), /*!< Card is in programming state */
|
||||
HAL_SD_CARD_DISCONNECTED = ((uint32_t)0x00000008U), /*!< Card is disconnected */
|
||||
HAL_SD_CARD_ERROR = ((uint32_t)0x000000FFU) /*!< Card response Error */
|
||||
}HAL_SD_CardStateTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SD_Exported_Types_Group3 SD Handle Structure definition
|
||||
* @{
|
||||
*/
|
||||
#define SD_InitTypeDef SDMMC_InitTypeDef
|
||||
#define SD_TypeDef SDMMC_TypeDef
|
||||
|
||||
/**
|
||||
* @brief SD Card Information Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t CardType; /*!< Specifies the card Type */
|
||||
|
||||
uint32_t CardVersion; /*!< Specifies the card version */
|
||||
|
||||
uint32_t Class; /*!< Specifies the class of the card class */
|
||||
|
||||
uint32_t RelCardAdd; /*!< Specifies the Relative Card Address */
|
||||
|
||||
uint32_t BlockNbr; /*!< Specifies the Card Capacity in blocks */
|
||||
|
||||
uint32_t BlockSize; /*!< Specifies one block size in bytes */
|
||||
|
||||
uint32_t LogBlockNbr; /*!< Specifies the Card logical Capacity in blocks */
|
||||
|
||||
uint32_t LogBlockSize; /*!< Specifies logical block size in bytes */
|
||||
|
||||
}HAL_SD_CardInfoTypeDef;
|
||||
|
||||
/**
|
||||
* @brief SD handle Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
SD_TypeDef *Instance; /*!< SD registers base address */
|
||||
|
||||
SD_InitTypeDef Init; /*!< SD required parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< SD locking object */
|
||||
|
||||
uint32_t *pTxBuffPtr; /*!< Pointer to SD Tx transfer Buffer */
|
||||
|
||||
uint32_t TxXferSize; /*!< SD Tx Transfer size */
|
||||
|
||||
uint32_t *pRxBuffPtr; /*!< Pointer to SD Rx transfer Buffer */
|
||||
|
||||
uint32_t RxXferSize; /*!< SD Rx Transfer size */
|
||||
|
||||
__IO uint32_t Context; /*!< SD transfer context */
|
||||
|
||||
__IO HAL_SD_StateTypeDef State; /*!< SD card State */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< SD Card Error codes */
|
||||
|
||||
DMA_HandleTypeDef *hdmarx; /*!< SD Rx DMA handle parameters */
|
||||
|
||||
DMA_HandleTypeDef *hdmatx; /*!< SD Tx DMA handle parameters */
|
||||
|
||||
HAL_SD_CardInfoTypeDef SdCard; /*!< SD Card information */
|
||||
|
||||
uint32_t CSD[4]; /*!< SD card specific data table */
|
||||
|
||||
uint32_t CID[4]; /*!< SD card identification number table */
|
||||
|
||||
}SD_HandleTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SD_Exported_Types_Group4 Card Specific Data: CSD Register
|
||||
* @{
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint8_t CSDStruct; /*!< CSD structure */
|
||||
__IO uint8_t SysSpecVersion; /*!< System specification version */
|
||||
__IO uint8_t Reserved1; /*!< Reserved */
|
||||
__IO uint8_t TAAC; /*!< Data read access time 1 */
|
||||
__IO uint8_t NSAC; /*!< Data read access time 2 in CLK cycles */
|
||||
__IO uint8_t MaxBusClkFrec; /*!< Max. bus clock frequency */
|
||||
__IO uint16_t CardComdClasses; /*!< Card command classes */
|
||||
__IO uint8_t RdBlockLen; /*!< Max. read data block length */
|
||||
__IO uint8_t PartBlockRead; /*!< Partial blocks for read allowed */
|
||||
__IO uint8_t WrBlockMisalign; /*!< Write block misalignment */
|
||||
__IO uint8_t RdBlockMisalign; /*!< Read block misalignment */
|
||||
__IO uint8_t DSRImpl; /*!< DSR implemented */
|
||||
__IO uint8_t Reserved2; /*!< Reserved */
|
||||
__IO uint32_t DeviceSize; /*!< Device Size */
|
||||
__IO uint8_t MaxRdCurrentVDDMin; /*!< Max. read current @ VDD min */
|
||||
__IO uint8_t MaxRdCurrentVDDMax; /*!< Max. read current @ VDD max */
|
||||
__IO uint8_t MaxWrCurrentVDDMin; /*!< Max. write current @ VDD min */
|
||||
__IO uint8_t MaxWrCurrentVDDMax; /*!< Max. write current @ VDD max */
|
||||
__IO uint8_t DeviceSizeMul; /*!< Device size multiplier */
|
||||
__IO uint8_t EraseGrSize; /*!< Erase group size */
|
||||
__IO uint8_t EraseGrMul; /*!< Erase group size multiplier */
|
||||
__IO uint8_t WrProtectGrSize; /*!< Write protect group size */
|
||||
__IO uint8_t WrProtectGrEnable; /*!< Write protect group enable */
|
||||
__IO uint8_t ManDeflECC; /*!< Manufacturer default ECC */
|
||||
__IO uint8_t WrSpeedFact; /*!< Write speed factor */
|
||||
__IO uint8_t MaxWrBlockLen; /*!< Max. write data block length */
|
||||
__IO uint8_t WriteBlockPaPartial; /*!< Partial blocks for write allowed */
|
||||
__IO uint8_t Reserved3; /*!< Reserved */
|
||||
__IO uint8_t ContentProtectAppli; /*!< Content protection application */
|
||||
__IO uint8_t FileFormatGrouop; /*!< File format group */
|
||||
__IO uint8_t CopyFlag; /*!< Copy flag (OTP) */
|
||||
__IO uint8_t PermWrProtect; /*!< Permanent write protection */
|
||||
__IO uint8_t TempWrProtect; /*!< Temporary write protection */
|
||||
__IO uint8_t FileFormat; /*!< File format */
|
||||
__IO uint8_t ECC; /*!< ECC code */
|
||||
__IO uint8_t CSD_CRC; /*!< CSD CRC */
|
||||
__IO uint8_t Reserved4; /*!< Always 1 */
|
||||
|
||||
}HAL_SD_CardCSDTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SD_Exported_Types_Group5 Card Identification Data: CID Register
|
||||
* @{
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint8_t ManufacturerID; /*!< Manufacturer ID */
|
||||
__IO uint16_t OEM_AppliID; /*!< OEM/Application ID */
|
||||
__IO uint32_t ProdName1; /*!< Product Name part1 */
|
||||
__IO uint8_t ProdName2; /*!< Product Name part2 */
|
||||
__IO uint8_t ProdRev; /*!< Product Revision */
|
||||
__IO uint32_t ProdSN; /*!< Product Serial Number */
|
||||
__IO uint8_t Reserved1; /*!< Reserved1 */
|
||||
__IO uint16_t ManufactDate; /*!< Manufacturing Date */
|
||||
__IO uint8_t CID_CRC; /*!< CID CRC */
|
||||
__IO uint8_t Reserved2; /*!< Always 1 */
|
||||
|
||||
}HAL_SD_CardCIDTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SD_Exported_Types_Group6 SD Card Status returned by ACMD13
|
||||
* @{
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint8_t DataBusWidth; /*!< Shows the currently defined data bus width */
|
||||
__IO uint8_t SecuredMode; /*!< Card is in secured mode of operation */
|
||||
__IO uint16_t CardType; /*!< Carries information about card type */
|
||||
__IO uint32_t ProtectedAreaSize; /*!< Carries information about the capacity of protected area */
|
||||
__IO uint8_t SpeedClass; /*!< Carries information about the speed class of the card */
|
||||
__IO uint8_t PerformanceMove; /*!< Carries information about the card's performance move */
|
||||
__IO uint8_t AllocationUnitSize; /*!< Carries information about the card's allocation unit size */
|
||||
__IO uint16_t EraseSize; /*!< Determines the number of AUs to be erased in one operation */
|
||||
__IO uint8_t EraseTimeout; /*!< Determines the timeout for any number of AU erase */
|
||||
__IO uint8_t EraseOffset; /*!< Carries information about the erase offset */
|
||||
|
||||
}HAL_SD_CardStatusTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup SD_Exported_Constants Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define BLOCKSIZE ((uint32_t)512U) /*!< Block size is 512 bytes */
|
||||
|
||||
/** @defgroup SD_Exported_Constansts_Group1 SD Error status enumeration Structure definition
|
||||
* @{
|
||||
*/
|
||||
#define HAL_SD_ERROR_NONE SDMMC_ERROR_NONE /*!< No error */
|
||||
#define HAL_SD_ERROR_CMD_CRC_FAIL SDMMC_ERROR_CMD_CRC_FAIL /*!< Command response received (but CRC check failed) */
|
||||
#define HAL_SD_ERROR_DATA_CRC_FAIL SDMMC_ERROR_DATA_CRC_FAIL /*!< Data block sent/received (CRC check failed) */
|
||||
#define HAL_SD_ERROR_CMD_RSP_TIMEOUT SDMMC_ERROR_CMD_RSP_TIMEOUT /*!< Command response timeout */
|
||||
#define HAL_SD_ERROR_DATA_TIMEOUT SDMMC_ERROR_DATA_TIMEOUT /*!< Data timeout */
|
||||
#define HAL_SD_ERROR_TX_UNDERRUN SDMMC_ERROR_TX_UNDERRUN /*!< Transmit FIFO underrun */
|
||||
#define HAL_SD_ERROR_RX_OVERRUN SDMMC_ERROR_RX_OVERRUN /*!< Receive FIFO overrun */
|
||||
#define HAL_SD_ERROR_ADDR_MISALIGNED SDMMC_ERROR_ADDR_MISALIGNED /*!< Misaligned address */
|
||||
#define HAL_SD_ERROR_BLOCK_LEN_ERR SDMMC_ERROR_BLOCK_LEN_ERR /*!< Transferred block length is not allowed for the card or the
|
||||
number of transferred bytes does not match the block length */
|
||||
#define HAL_SD_ERROR_ERASE_SEQ_ERR SDMMC_ERROR_ERASE_SEQ_ERR /*!< An error in the sequence of erase command occurs */
|
||||
#define HAL_SD_ERROR_BAD_ERASE_PARAM SDMMC_ERROR_BAD_ERASE_PARAM /*!< An invalid selection for erase groups */
|
||||
#define HAL_SD_ERROR_WRITE_PROT_VIOLATION SDMMC_ERROR_WRITE_PROT_VIOLATION /*!< Attempt to program a write protect block */
|
||||
#define HAL_SD_ERROR_LOCK_UNLOCK_FAILED SDMMC_ERROR_LOCK_UNLOCK_FAILED /*!< Sequence or password error has been detected in unlock
|
||||
command or if there was an attempt to access a locked card */
|
||||
#define HAL_SD_ERROR_COM_CRC_FAILED SDMMC_ERROR_COM_CRC_FAILED /*!< CRC check of the previous command failed */
|
||||
#define HAL_SD_ERROR_ILLEGAL_CMD SDMMC_ERROR_ILLEGAL_CMD /*!< Command is not legal for the card state */
|
||||
#define HAL_SD_ERROR_CARD_ECC_FAILED SDMMC_ERROR_CARD_ECC_FAILED /*!< Card internal ECC was applied but failed to correct the data */
|
||||
#define HAL_SD_ERROR_CC_ERR SDMMC_ERROR_CC_ERR /*!< Internal card controller error */
|
||||
#define HAL_SD_ERROR_GENERAL_UNKNOWN_ERR SDMMC_ERROR_GENERAL_UNKNOWN_ERR /*!< General or unknown error */
|
||||
#define HAL_SD_ERROR_STREAM_READ_UNDERRUN SDMMC_ERROR_STREAM_READ_UNDERRUN /*!< The card could not sustain data reading in stream rmode */
|
||||
#define HAL_SD_ERROR_STREAM_WRITE_OVERRUN SDMMC_ERROR_STREAM_WRITE_OVERRUN /*!< The card could not sustain data programming in stream mode */
|
||||
#define HAL_SD_ERROR_CID_CSD_OVERWRITE SDMMC_ERROR_CID_CSD_OVERWRITE /*!< CID/CSD overwrite error */
|
||||
#define HAL_SD_ERROR_WP_ERASE_SKIP SDMMC_ERROR_WP_ERASE_SKIP /*!< Only partial address space was erased */
|
||||
#define HAL_SD_ERROR_CARD_ECC_DISABLED SDMMC_ERROR_CARD_ECC_DISABLED /*!< Command has been executed without using internal ECC */
|
||||
#define HAL_SD_ERROR_ERASE_RESET SDMMC_ERROR_ERASE_RESET /*!< Erase sequence was cleared before executing because an out
|
||||
of erase sequence command was received */
|
||||
#define HAL_SD_ERROR_AKE_SEQ_ERR SDMMC_ERROR_AKE_SEQ_ERR /*!< Error in sequence of authentication */
|
||||
#define HAL_SD_ERROR_INVALID_VOLTRANGE SDMMC_ERROR_INVALID_VOLTRANGE /*!< Error in case of invalid voltage range */
|
||||
#define HAL_SD_ERROR_ADDR_OUT_OF_RANGE SDMMC_ERROR_ADDR_OUT_OF_RANGE /*!< Error when addressed block is out of range */
|
||||
#define HAL_SD_ERROR_REQUEST_NOT_APPLICABLE SDMMC_ERROR_REQUEST_NOT_APPLICABLE /*!< Error when command request is not applicable */
|
||||
#define HAL_SD_ERROR_PARAM SDMMC_ERROR_INVALID_PARAMETER /*!< the used parameter is not valid */
|
||||
#define HAL_SD_ERROR_UNSUPPORTED_FEATURE SDMMC_ERROR_UNSUPPORTED_FEATURE /*!< Error when feature is not insupported */
|
||||
#define HAL_SD_ERROR_BUSY SDMMC_ERROR_BUSY /*!< Error when transfer process is busy */
|
||||
#define HAL_SD_ERROR_DMA SDMMC_ERROR_DMA /*!< Error while DMA transfer */
|
||||
#define HAL_SD_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT /*!< Timeout error */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SD_Exported_Constansts_Group2 SD context enumeration
|
||||
* @{
|
||||
*/
|
||||
#define SD_CONTEXT_NONE ((uint32_t)0x00000000U) /*!< None */
|
||||
#define SD_CONTEXT_READ_SINGLE_BLOCK ((uint32_t)0x00000001U) /*!< Read single block operation */
|
||||
#define SD_CONTEXT_READ_MULTIPLE_BLOCK ((uint32_t)0x00000002U) /*!< Read multiple blocks operation */
|
||||
#define SD_CONTEXT_WRITE_SINGLE_BLOCK ((uint32_t)0x00000010U) /*!< Write single block operation */
|
||||
#define SD_CONTEXT_WRITE_MULTIPLE_BLOCK ((uint32_t)0x00000020U) /*!< Write multiple blocks operation */
|
||||
#define SD_CONTEXT_IT ((uint32_t)0x00000008U) /*!< Process in Interrupt mode */
|
||||
#define SD_CONTEXT_DMA ((uint32_t)0x00000080U) /*!< Process in DMA mode */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SD_Exported_Constansts_Group3 SD Supported Memory Cards
|
||||
* @{
|
||||
*/
|
||||
#define CARD_SDSC ((uint32_t)0x00000000U)
|
||||
#define CARD_SDHC_SDXC ((uint32_t)0x00000001U)
|
||||
#define CARD_SECURED ((uint32_t)0x00000003U)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SD_Exported_Constansts_Group4 SD Supported Version
|
||||
* @{
|
||||
*/
|
||||
#define CARD_V1_X ((uint32_t)0x00000000U)
|
||||
#define CARD_V2_X ((uint32_t)0x00000001U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup SD_Exported_macros SD Exported Macros
|
||||
* @brief macros to handle interrupts and specific clock configurations
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable the SD device.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SD_ENABLE(__HANDLE__) __SDMMC_ENABLE((__HANDLE__)->Instance)
|
||||
|
||||
/**
|
||||
* @brief Disable the SD device.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SD_DISABLE(__HANDLE__) __SDMMC_DISABLE((__HANDLE__)->Instance)
|
||||
|
||||
/**
|
||||
* @brief Enable the SDMMC DMA transfer.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SD_DMA_ENABLE(__HANDLE__) __SDMMC_DMA_ENABLE((__HANDLE__)->Instance)
|
||||
|
||||
/**
|
||||
* @brief Disable the SDMMC DMA transfer.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SD_DMA_DISABLE(__HANDLE__) __SDMMC_DMA_DISABLE((__HANDLE__)->Instance)
|
||||
|
||||
/**
|
||||
* @brief Enable the SD device interrupt.
|
||||
* @param __HANDLE__: SD Handle
|
||||
* @param __INTERRUPT__: specifies the SDMMC interrupt sources to be enabled.
|
||||
* This parameter can be one or a combination of the following values:
|
||||
* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
|
||||
* @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
|
||||
* @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
|
||||
* @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
|
||||
* @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
|
||||
* @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
|
||||
* @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
|
||||
* @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
|
||||
* @arg SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
|
||||
* @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
|
||||
* @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt
|
||||
* @arg SDMMC_IT_TXACT: Data transmit in progress interrupt
|
||||
* @arg SDMMC_IT_RXACT: Data receive in progress interrupt
|
||||
* @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
|
||||
* @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
|
||||
* @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt
|
||||
* @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
|
||||
* @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
|
||||
* @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt
|
||||
* @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt
|
||||
* @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt
|
||||
* @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SD_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Disable the SD device interrupt.
|
||||
* @param __HANDLE__: SD Handle
|
||||
* @param __INTERRUPT__: specifies the SDMMC interrupt sources to be disabled.
|
||||
* This parameter can be one or a combination of the following values:
|
||||
* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
|
||||
* @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
|
||||
* @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
|
||||
* @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
|
||||
* @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
|
||||
* @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
|
||||
* @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
|
||||
* @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
|
||||
* @arg SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
|
||||
* @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
|
||||
* @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt
|
||||
* @arg SDMMC_IT_TXACT: Data transmit in progress interrupt
|
||||
* @arg SDMMC_IT_RXACT: Data receive in progress interrupt
|
||||
* @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
|
||||
* @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
|
||||
* @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt
|
||||
* @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
|
||||
* @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
|
||||
* @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt
|
||||
* @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt
|
||||
* @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt
|
||||
* @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SD_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified SD flag is set or not.
|
||||
* @param __HANDLE__: SD Handle
|
||||
* @param __FLAG__: specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
|
||||
* @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
|
||||
* @arg SDMMC_FLAG_CTIMEOUT: Command response timeout
|
||||
* @arg SDMMC_FLAG_DTIMEOUT: Data timeout
|
||||
* @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error
|
||||
* @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error
|
||||
* @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed)
|
||||
* @arg SDMMC_FLAG_CMDSENT: Command sent (no response required)
|
||||
* @arg SDMMC_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
|
||||
* @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed)
|
||||
* @arg SDMMC_FLAG_CMDACT: Command transfer in progress
|
||||
* @arg SDMMC_FLAG_TXACT: Data transmit in progress
|
||||
* @arg SDMMC_FLAG_RXACT: Data receive in progress
|
||||
* @arg SDMMC_FLAG_TXFIFOHE: Transmit FIFO Half Empty
|
||||
* @arg SDMMC_FLAG_RXFIFOHF: Receive FIFO Half Full
|
||||
* @arg SDMMC_FLAG_TXFIFOF: Transmit FIFO full
|
||||
* @arg SDMMC_FLAG_RXFIFOF: Receive FIFO full
|
||||
* @arg SDMMC_FLAG_TXFIFOE: Transmit FIFO empty
|
||||
* @arg SDMMC_FLAG_RXFIFOE: Receive FIFO empty
|
||||
* @arg SDMMC_FLAG_TXDAVL: Data available in transmit FIFO
|
||||
* @arg SDMMC_FLAG_RXDAVL: Data available in receive FIFO
|
||||
* @arg SDMMC_FLAG_SDIOIT: SD I/O interrupt received
|
||||
* @retval The new state of SD FLAG (SET or RESET).
|
||||
*/
|
||||
#define __HAL_SD_GET_FLAG(__HANDLE__, __FLAG__) __SDMMC_GET_FLAG((__HANDLE__)->Instance, (__FLAG__))
|
||||
|
||||
/**
|
||||
* @brief Clear the SD's pending flags.
|
||||
* @param __HANDLE__: SD Handle
|
||||
* @param __FLAG__: specifies the flag to clear.
|
||||
* This parameter can be one or a combination of the following values:
|
||||
* @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
|
||||
* @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
|
||||
* @arg SDMMC_FLAG_CTIMEOUT: Command response timeout
|
||||
* @arg SDMMC_FLAG_DTIMEOUT: Data timeout
|
||||
* @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error
|
||||
* @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error
|
||||
* @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed)
|
||||
* @arg SDMMC_FLAG_CMDSENT: Command sent (no response required)
|
||||
* @arg SDMMC_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
|
||||
* @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed)
|
||||
* @arg SDMMC_FLAG_SDIOIT: SD I/O interrupt received
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SD_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDMMC_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__))
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified SD interrupt has occurred or not.
|
||||
* @param __HANDLE__: SD Handle
|
||||
* @param __INTERRUPT__: specifies the SDMMC interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
|
||||
* @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
|
||||
* @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
|
||||
* @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
|
||||
* @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
|
||||
* @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
|
||||
* @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
|
||||
* @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
|
||||
* @arg SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
|
||||
* @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
|
||||
* @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt
|
||||
* @arg SDMMC_IT_TXACT: Data transmit in progress interrupt
|
||||
* @arg SDMMC_IT_RXACT: Data receive in progress interrupt
|
||||
* @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
|
||||
* @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
|
||||
* @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt
|
||||
* @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
|
||||
* @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
|
||||
* @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt
|
||||
* @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt
|
||||
* @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt
|
||||
* @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
|
||||
* @retval The new state of SD IT (SET or RESET).
|
||||
*/
|
||||
#define __HAL_SD_GET_IT(__HANDLE__, __INTERRUPT__) __SDMMC_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Clear the SD's interrupt pending bits.
|
||||
* @param __HANDLE__: SD Handle
|
||||
* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
|
||||
* This parameter can be one or a combination of the following values:
|
||||
* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
|
||||
* @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
|
||||
* @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
|
||||
* @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
|
||||
* @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
|
||||
* @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
|
||||
* @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
|
||||
* @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
|
||||
* @arg SDMMC_IT_DATAEND: Data end (data counter, SDMMC_DCOUNT, is zero) interrupt
|
||||
* @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SD_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDMMC_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup SD_Exported_Functions SD Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup SD_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd);
|
||||
HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd);
|
||||
HAL_StatusTypeDef HAL_SD_DeInit (SD_HandleTypeDef *hsd);
|
||||
void HAL_SD_MspInit(SD_HandleTypeDef *hsd);
|
||||
void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SD_Exported_Functions_Group2 Input and Output operation functions
|
||||
* @{
|
||||
*/
|
||||
/* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, uint32_t BlockEndAdd);
|
||||
/* Non-Blocking mode: IT */
|
||||
HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
|
||||
HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
|
||||
/* Non-Blocking mode: DMA */
|
||||
HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
|
||||
HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
|
||||
|
||||
void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd);
|
||||
|
||||
/* Callback in non blocking modes (DMA) */
|
||||
void HAL_SD_TxCpltCallback(SD_HandleTypeDef *hsd);
|
||||
void HAL_SD_RxCpltCallback(SD_HandleTypeDef *hsd);
|
||||
void HAL_SD_ErrorCallback(SD_HandleTypeDef *hsd);
|
||||
void HAL_SD_AbortCallback(SD_HandleTypeDef *hsd);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SD_Exported_Functions_Group3 Peripheral Control functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t WideMode);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SD_Exported_Functions_Group4 SD card related functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus);
|
||||
HAL_SD_CardStateTypeDef HAL_SD_GetCardState(SD_HandleTypeDef *hsd);
|
||||
HAL_StatusTypeDef HAL_SD_GetCardCID(SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID);
|
||||
HAL_StatusTypeDef HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef *pCSD);
|
||||
HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypeDef *pStatus);
|
||||
HAL_StatusTypeDef HAL_SD_GetCardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SD_Exported_Functions_Group5 Peripheral State and Errors functions
|
||||
* @{
|
||||
*/
|
||||
HAL_SD_StateTypeDef HAL_SD_GetState(SD_HandleTypeDef *hsd);
|
||||
uint32_t HAL_SD_GetError(SD_HandleTypeDef *hsd);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SD_Exported_Functions_Group6 Perioheral Abort management
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd);
|
||||
HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/** @defgroup SD_Private_Types SD Private Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private defines -----------------------------------------------------------*/
|
||||
/** @defgroup SD_Private_Defines SD Private Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/** @defgroup SD_Private_Variables SD Private Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup SD_Private_Constants SD Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup SD_Private_Macros SD Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions prototypes ----------------------------------------------*/
|
||||
/** @defgroup SD_Private_Functions_Prototypes SD Private Functions Prototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup SD_Private_Functions SD Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* __STM32F7xx_HAL_SD_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,199 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_hal_sdram.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.2
|
||||
* @date 14-April-2017
|
||||
* @brief Header file of SDRAM HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F7xx_HAL_SDRAM_H
|
||||
#define __STM32F7xx_HAL_SDRAM_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx_ll_fmc.h"
|
||||
|
||||
/** @addtogroup STM32F7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup SDRAM
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported typedef ----------------------------------------------------------*/
|
||||
|
||||
/** @defgroup SDRAM_Exported_Types SDRAM Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief HAL SDRAM State structure definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_SDRAM_STATE_RESET = 0x00U, /*!< SDRAM not yet initialized or disabled */
|
||||
HAL_SDRAM_STATE_READY = 0x01U, /*!< SDRAM initialized and ready for use */
|
||||
HAL_SDRAM_STATE_BUSY = 0x02U, /*!< SDRAM internal process is ongoing */
|
||||
HAL_SDRAM_STATE_ERROR = 0x03U, /*!< SDRAM error state */
|
||||
HAL_SDRAM_STATE_WRITE_PROTECTED = 0x04U, /*!< SDRAM device write protected */
|
||||
HAL_SDRAM_STATE_PRECHARGED = 0x05U /*!< SDRAM device precharged */
|
||||
|
||||
}HAL_SDRAM_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief SDRAM handle Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
FMC_SDRAM_TypeDef *Instance; /*!< Register base address */
|
||||
|
||||
FMC_SDRAM_InitTypeDef Init; /*!< SDRAM device configuration parameters */
|
||||
|
||||
__IO HAL_SDRAM_StateTypeDef State; /*!< SDRAM access state */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< SDRAM locking object */
|
||||
|
||||
DMA_HandleTypeDef *hdma; /*!< Pointer DMA handler */
|
||||
|
||||
}SDRAM_HandleTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup SDRAM_Exported_Macros SDRAM Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset SDRAM handle state
|
||||
* @param __HANDLE__: specifies the SDRAM handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SDRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SDRAM_STATE_RESET)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @addtogroup SDRAM_Exported_Functions SDRAM Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup SDRAM_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Initialization/de-initialization functions *********************************/
|
||||
HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing);
|
||||
HAL_StatusTypeDef HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram);
|
||||
void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram);
|
||||
void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram);
|
||||
|
||||
void HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef *hsdram);
|
||||
void HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef *hsdram);
|
||||
void HAL_SDRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma);
|
||||
void HAL_SDRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup SDRAM_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* I/O operation functions ****************************************************/
|
||||
HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize);
|
||||
HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize);
|
||||
HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize);
|
||||
HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize);
|
||||
HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
|
||||
HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
|
||||
|
||||
HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t * pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
|
||||
HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup SDRAM_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
/* SDRAM Control functions *****************************************************/
|
||||
HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef *hsdram);
|
||||
HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef *hsdram);
|
||||
HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate);
|
||||
HAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber);
|
||||
uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup SDRAM_Exported_Functions_Group4
|
||||
* @{
|
||||
*/
|
||||
/* SDRAM State functions ********************************************************/
|
||||
HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F7xx_HAL_SDRAM_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,949 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_hal_smartcard.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.2
|
||||
* @date 14-April-2017
|
||||
* @brief Header file of SMARTCARD HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F7xx_HAL_SMARTCARD_H
|
||||
#define __STM32F7xx_HAL_SMARTCARD_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup SMARTCARD
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup SMARTCARD_Exported_Types SMARTCARD Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief SMARTCARD Init Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t BaudRate; /*!< Configures the SmartCard communication baud rate.
|
||||
The baud rate register is computed using the following formula:
|
||||
Baud Rate Register = ((PCLKx) / ((hsmartcard->Init.BaudRate))) */
|
||||
|
||||
uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
|
||||
This parameter @ref SMARTCARD_Word_Length can only be set to 9 (8 data + 1 parity bits). */
|
||||
|
||||
uint32_t StopBits; /*!< Specifies the number of stop bits.
|
||||
This parameter can be a value of @ref SMARTCARD_Stop_Bits. */
|
||||
|
||||
uint32_t Parity; /*!< Specifies the parity mode.
|
||||
This parameter can be a value of @ref SMARTCARD_Parity
|
||||
@note The parity is enabled by default (PCE is forced to 1).
|
||||
Since the WordLength is forced to 8 bits + parity, M is
|
||||
forced to 1 and the parity bit is the 9th bit. */
|
||||
|
||||
uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
|
||||
This parameter can be a value of @ref SMARTCARD_Mode */
|
||||
|
||||
uint32_t CLKPolarity; /*!< Specifies the steady state of the serial clock.
|
||||
This parameter can be a value of @ref SMARTCARD_Clock_Polarity */
|
||||
|
||||
uint32_t CLKPhase; /*!< Specifies the clock transition on which the bit capture is made.
|
||||
This parameter can be a value of @ref SMARTCARD_Clock_Phase */
|
||||
|
||||
uint32_t CLKLastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
|
||||
data bit (MSB) has to be output on the SCLK pin in synchronous mode.
|
||||
This parameter can be a value of @ref SMARTCARD_Last_Bit */
|
||||
|
||||
uint32_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote is selected.
|
||||
Selecting the single sample method increases the receiver tolerance to clock
|
||||
deviations. This parameter can be a value of @ref SMARTCARD_OneBit_Sampling */
|
||||
|
||||
uint32_t Prescaler; /*!< Specifies the SmartCard Prescaler */
|
||||
|
||||
uint32_t GuardTime; /*!< Specifies the SmartCard Guard Time */
|
||||
|
||||
uint16_t NACKEnable; /*!< Specifies whether the SmartCard NACK transmission is enabled
|
||||
in case of parity error.
|
||||
This parameter can be a value of @ref SMARTCARD_NACK_State */
|
||||
|
||||
uint32_t TimeOutEnable; /*!< Specifies whether the receiver timeout is enabled.
|
||||
This parameter can be a value of @ref SMARTCARD_Timeout_Enable*/
|
||||
|
||||
uint32_t TimeOutValue; /*!< Specifies the receiver time out value in number of baud blocks:
|
||||
it is used to implement the Character Wait Time (CWT) and
|
||||
Block Wait Time (BWT). It is coded over 24 bits. */
|
||||
|
||||
uint32_t BlockLength; /*!< Specifies the SmartCard Block Length in T=1 Reception mode.
|
||||
This parameter can be any value from 0x0 to 0xFF */
|
||||
|
||||
uint32_t AutoRetryCount; /*!< Specifies the SmartCard auto-retry count (number of retries in
|
||||
receive and transmit mode). When set to 0, retransmission is
|
||||
disabled. Otherwise, its maximum value is 7 (before signalling
|
||||
an error) */
|
||||
|
||||
}SMARTCARD_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief SMARTCARD advanced features initalization structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t AdvFeatureInit; /*!< Specifies which advanced SMARTCARD features is initialized. Several
|
||||
advanced features may be initialized at the same time. This parameter
|
||||
can be a value of @ref SMARTCARDEx_Advanced_Features_Initialization_Type */
|
||||
|
||||
uint32_t TxPinLevelInvert; /*!< Specifies whether the TX pin active level is inverted.
|
||||
This parameter can be a value of @ref SMARTCARD_Tx_Inv */
|
||||
|
||||
uint32_t RxPinLevelInvert; /*!< Specifies whether the RX pin active level is inverted.
|
||||
This parameter can be a value of @ref SMARTCARD_Rx_Inv */
|
||||
|
||||
uint32_t DataInvert; /*!< Specifies whether data are inverted (positive/direct logic
|
||||
vs negative/inverted logic).
|
||||
This parameter can be a value of @ref SMARTCARD_Data_Inv */
|
||||
|
||||
uint32_t Swap; /*!< Specifies whether TX and RX pins are swapped.
|
||||
This parameter can be a value of @ref SMARTCARD_Rx_Tx_Swap */
|
||||
|
||||
uint32_t OverrunDisable; /*!< Specifies whether the reception overrun detection is disabled.
|
||||
This parameter can be a value of @ref SMARTCARD_Overrun_Disable */
|
||||
|
||||
uint32_t DMADisableonRxError; /*!< Specifies whether the DMA is disabled in case of reception error.
|
||||
This parameter can be a value of @ref SMARTCARD_DMA_Disable_on_Rx_Error */
|
||||
|
||||
uint32_t MSBFirst; /*!< Specifies whether MSB is sent first on UART line.
|
||||
This parameter can be a value of @ref SMARTCARD_MSB_First */
|
||||
|
||||
uint16_t TxCompletionIndication; /*!< Specifies which transmission completion indication is used: before (when
|
||||
relevant flag is available) or once guard time period has elapsed.
|
||||
This parameter can be a value of @ref SMARTCARDEx_Transmission_Completion_Indication. */
|
||||
}SMARTCARD_AdvFeatureInitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL SMARTCARD State structures definition
|
||||
* @note HAL SMARTCARD State value is a combination of 2 different substates: gState and RxState.
|
||||
* - gState contains SMARTCARD state information related to global Handle management
|
||||
* and also information related to Tx operations.
|
||||
* gState value coding follow below described bitmap :
|
||||
* b7-b6 Error information
|
||||
* 00 : No Error
|
||||
* 01 : (Not Used)
|
||||
* 10 : Timeout
|
||||
* 11 : Error
|
||||
* b5 IP initilisation status
|
||||
* 0 : Reset (IP not initialized)
|
||||
* 1 : Init done (IP not initialized. HAL SMARTCARD Init function already called)
|
||||
* b4-b3 (not used)
|
||||
* xx : Should be set to 00
|
||||
* b2 Intrinsic process state
|
||||
* 0 : Ready
|
||||
* 1 : Busy (IP busy with some configuration or internal operations)
|
||||
* b1 (not used)
|
||||
* x : Should be set to 0
|
||||
* b0 Tx state
|
||||
* 0 : Ready (no Tx operation ongoing)
|
||||
* 1 : Busy (Tx operation ongoing)
|
||||
* - RxState contains information related to Rx operations.
|
||||
* RxState value coding follow below described bitmap :
|
||||
* b7-b6 (not used)
|
||||
* xx : Should be set to 00
|
||||
* b5 IP initilisation status
|
||||
* 0 : Reset (IP not initialized)
|
||||
* 1 : Init done (IP not initialized)
|
||||
* b4-b2 (not used)
|
||||
* xxx : Should be set to 000
|
||||
* b1 Rx state
|
||||
* 0 : Ready (no Rx operation ongoing)
|
||||
* 1 : Busy (Rx operation ongoing)
|
||||
* b0 (not used)
|
||||
* x : Should be set to 0.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_SMARTCARD_STATE_RESET = 0x00U, /*!< Peripheral is not initialized
|
||||
Value is allowed for gState and RxState */
|
||||
HAL_SMARTCARD_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use
|
||||
Value is allowed for gState and RxState */
|
||||
HAL_SMARTCARD_STATE_BUSY = 0x24U, /*!< an internal process is ongoing
|
||||
Value is allowed for gState only */
|
||||
HAL_SMARTCARD_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing
|
||||
Value is allowed for gState only */
|
||||
HAL_SMARTCARD_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing
|
||||
Value is allowed for RxState only */
|
||||
HAL_SMARTCARD_STATE_BUSY_TX_RX = 0x23U, /*!< Data Transmission and Reception process is ongoing
|
||||
Not to be used for neither gState nor RxState.
|
||||
Value is result of combination (Or) between gState and RxState values */
|
||||
HAL_SMARTCARD_STATE_TIMEOUT = 0xA0U, /*!< Timeout state
|
||||
Value is allowed for gState only */
|
||||
HAL_SMARTCARD_STATE_ERROR = 0xE0U /*!< Error
|
||||
Value is allowed for gState only */
|
||||
}HAL_SMARTCARD_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief SMARTCARD clock sources definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
SMARTCARD_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */
|
||||
SMARTCARD_CLOCKSOURCE_PCLK2 = 0x01U, /*!< PCLK2 clock source */
|
||||
SMARTCARD_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */
|
||||
SMARTCARD_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */
|
||||
SMARTCARD_CLOCKSOURCE_LSE = 0x08U, /*!< LSE clock source */
|
||||
SMARTCARD_CLOCKSOURCE_UNDEFINED = 0x10 /*!< undefined clock source */
|
||||
}SMARTCARD_ClockSourceTypeDef;
|
||||
|
||||
/**
|
||||
* @brief SMARTCARD handle Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
USART_TypeDef *Instance; /*!< USART registers base address */
|
||||
|
||||
SMARTCARD_InitTypeDef Init; /*!< SmartCard communication parameters */
|
||||
|
||||
SMARTCARD_AdvFeatureInitTypeDef AdvancedInit; /*!< SmartCard advanced features initialization parameters */
|
||||
|
||||
uint8_t *pTxBuffPtr; /*!< Pointer to SmartCard Tx transfer Buffer */
|
||||
|
||||
uint16_t TxXferSize; /*!< SmartCard Tx Transfer size */
|
||||
|
||||
__IO uint16_t TxXferCount; /*!< SmartCard Tx Transfer Counter */
|
||||
|
||||
uint8_t *pRxBuffPtr; /*!< Pointer to SmartCard Rx transfer Buffer */
|
||||
|
||||
uint16_t RxXferSize; /*!< SmartCard Rx Transfer size */
|
||||
|
||||
__IO uint16_t RxXferCount; /*!< SmartCard Rx Transfer Counter */
|
||||
|
||||
DMA_HandleTypeDef *hdmatx; /*!< SmartCard Tx DMA Handle parameters */
|
||||
|
||||
DMA_HandleTypeDef *hdmarx; /*!< SmartCard Rx DMA Handle parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< Locking object */
|
||||
|
||||
__IO HAL_SMARTCARD_StateTypeDef gState; /*!< SmartCard state information related to global Handle management
|
||||
and also related to Tx operations.
|
||||
This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */
|
||||
|
||||
__IO HAL_SMARTCARD_StateTypeDef RxState; /*!< SmartCard state information related to Rx operations.
|
||||
This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */
|
||||
|
||||
__IO uint32_t ErrorCode; /* SmartCard Error code */
|
||||
|
||||
}SMARTCARD_HandleTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup SMARTCARD_Exported_Constants SMARTCARD Exported constants
|
||||
* @{
|
||||
*/
|
||||
/** @defgroup SMARTCARD_Error_Code SMARTCARD Error Code
|
||||
* @brief SMARTCARD Error Code
|
||||
* @{
|
||||
*/
|
||||
#define HAL_SMARTCARD_ERROR_NONE ((uint32_t)0x00U) /*!< No error */
|
||||
#define HAL_SMARTCARD_ERROR_PE ((uint32_t)0x01U) /*!< Parity error */
|
||||
#define HAL_SMARTCARD_ERROR_NE ((uint32_t)0x02U) /*!< Noise error */
|
||||
#define HAL_SMARTCARD_ERROR_FE ((uint32_t)0x04U) /*!< frame error */
|
||||
#define HAL_SMARTCARD_ERROR_ORE ((uint32_t)0x08U) /*!< Overrun error */
|
||||
#define HAL_SMARTCARD_ERROR_DMA ((uint32_t)0x10U) /*!< DMA transfer error */
|
||||
#define HAL_SMARTCARD_ERROR_RTO ((uint32_t)0x20U) /*!< Receiver TimeOut error */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMARTCARD_Word_Length SMARTCARD Word Length
|
||||
* @{
|
||||
*/
|
||||
#define SMARTCARD_WORDLENGTH_9B ((uint32_t)USART_CR1_M_0)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMARTCARD_Stop_Bits SMARTCARD Number of Stop Bits
|
||||
* @{
|
||||
*/
|
||||
#define SMARTCARD_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMARTCARD_Parity SMARTCARD Parity
|
||||
* @{
|
||||
*/
|
||||
#define SMARTCARD_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
|
||||
#define SMARTCARD_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMARTCARD_Mode SMARTCARD Mode
|
||||
* @{
|
||||
*/
|
||||
#define SMARTCARD_MODE_RX ((uint32_t)USART_CR1_RE)
|
||||
#define SMARTCARD_MODE_TX ((uint32_t)USART_CR1_TE)
|
||||
#define SMARTCARD_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMARTCARD_Clock_Polarity SMARTCARD Clock Polarity
|
||||
* @{
|
||||
*/
|
||||
#define SMARTCARD_POLARITY_LOW ((uint32_t)0x0000U)
|
||||
#define SMARTCARD_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMARTCARD_Clock_Phase SMARTCARD Clock Phase
|
||||
* @{
|
||||
*/
|
||||
#define SMARTCARD_PHASE_1EDGE ((uint32_t)0x0000U)
|
||||
#define SMARTCARD_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMARTCARD_Last_Bit SMARTCARD Last Bit
|
||||
* @{
|
||||
*/
|
||||
#define SMARTCARD_LASTBIT_DISABLE ((uint32_t)0x0000U)
|
||||
#define SMARTCARD_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMARTCARD_OneBit_Sampling SMARTCARD OneBit Sampling
|
||||
* @{
|
||||
*/
|
||||
#define SMARTCARD_ONE_BIT_SAMPLE_DISABLE ((uint32_t)0x0000U)
|
||||
#define SMARTCARD_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup SMARTCARD_NACK_State SMARTCARD NACK State
|
||||
* @{
|
||||
*/
|
||||
#define SMARTCARD_NACK_ENABLE ((uint32_t)USART_CR3_NACK)
|
||||
#define SMARTCARD_NACK_DISABLE ((uint32_t)0x0000U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMARTCARD_Timeout_Enable SMARTCARD Timeout Enable
|
||||
* @{
|
||||
*/
|
||||
#define SMARTCARD_TIMEOUT_DISABLE ((uint32_t)0x00000000U)
|
||||
#define SMARTCARD_TIMEOUT_ENABLE ((uint32_t)USART_CR2_RTOEN)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMARTCARD_DMA_Requests SMARTCARD DMA requests
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SMARTCARD_DMAREQ_TX ((uint32_t)USART_CR3_DMAT)
|
||||
#define SMARTCARD_DMAREQ_RX ((uint32_t)USART_CR3_DMAR)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMARTCARD_Advanced_Features_Initialization_Type SMARTCARD Advanced Features Initialization Type
|
||||
* @{
|
||||
*/
|
||||
#define SMARTCARD_ADVFEATURE_NO_INIT ((uint32_t)0x00000000U)
|
||||
#define SMARTCARD_ADVFEATURE_TXINVERT_INIT ((uint32_t)0x00000001U)
|
||||
#define SMARTCARD_ADVFEATURE_RXINVERT_INIT ((uint32_t)0x00000002U)
|
||||
#define SMARTCARD_ADVFEATURE_DATAINVERT_INIT ((uint32_t)0x00000004U)
|
||||
#define SMARTCARD_ADVFEATURE_SWAP_INIT ((uint32_t)0x00000008U)
|
||||
#define SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT ((uint32_t)0x00000010U)
|
||||
#define SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT ((uint32_t)0x00000020U)
|
||||
#define SMARTCARD_ADVFEATURE_MSBFIRST_INIT ((uint32_t)0x00000080U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMARTCARD_Tx_Inv SMARTCARD Tx Inv
|
||||
* @{
|
||||
*/
|
||||
#define SMARTCARD_ADVFEATURE_TXINV_DISABLE ((uint32_t)0x00000000U)
|
||||
#define SMARTCARD_ADVFEATURE_TXINV_ENABLE ((uint32_t)USART_CR2_TXINV)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMARTCARD_Rx_Inv SMARTCARD Rx Inv
|
||||
* @{
|
||||
*/
|
||||
#define SMARTCARD_ADVFEATURE_RXINV_DISABLE ((uint32_t)0x00000000U)
|
||||
#define SMARTCARD_ADVFEATURE_RXINV_ENABLE ((uint32_t)USART_CR2_RXINV)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMARTCARD_Data_Inv SMARTCARD Data Inv
|
||||
* @{
|
||||
*/
|
||||
#define SMARTCARD_ADVFEATURE_DATAINV_DISABLE ((uint32_t)0x00000000U)
|
||||
#define SMARTCARD_ADVFEATURE_DATAINV_ENABLE ((uint32_t)USART_CR2_DATAINV)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMARTCARD_Rx_Tx_Swap SMARTCARD Rx Tx Swap
|
||||
* @{
|
||||
*/
|
||||
#define SMARTCARD_ADVFEATURE_SWAP_DISABLE ((uint32_t)0x00000000U)
|
||||
#define SMARTCARD_ADVFEATURE_SWAP_ENABLE ((uint32_t)USART_CR2_SWAP)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMARTCARD_Overrun_Disable SMARTCARD Overrun Disable
|
||||
* @{
|
||||
*/
|
||||
#define SMARTCARD_ADVFEATURE_OVERRUN_ENABLE ((uint32_t)0x00000000U)
|
||||
#define SMARTCARD_ADVFEATURE_OVERRUN_DISABLE ((uint32_t)USART_CR3_OVRDIS)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMARTCARD_DMA_Disable_on_Rx_Error SMARTCARD DMA Disable on Rx Error
|
||||
* @{
|
||||
*/
|
||||
#define SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR ((uint32_t)0x00000000U)
|
||||
#define SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR ((uint32_t)USART_CR3_DDRE)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMARTCARD_MSB_First SMARTCARD MSB First
|
||||
* @{
|
||||
*/
|
||||
#define SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE ((uint32_t)0x00000000U)
|
||||
#define SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE ((uint32_t)USART_CR2_MSBFIRST)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SmartCard_Flags SMARTCARD Flags
|
||||
* Elements values convention: 0xXXXX
|
||||
* - 0xXXXX : Flag mask in the ISR register
|
||||
* @{
|
||||
*/
|
||||
#define SMARTCARD_FLAG_REACK ((uint32_t)0x00400000U)
|
||||
#define SMARTCARD_FLAG_TEACK ((uint32_t)0x00200000U)
|
||||
#define SMARTCARD_FLAG_BUSY ((uint32_t)0x00010000U)
|
||||
#define SMARTCARD_FLAG_EOBF ((uint32_t)0x00001000U)
|
||||
#define SMARTCARD_FLAG_RTOF ((uint32_t)0x00000800U)
|
||||
#define SMARTCARD_FLAG_TXE ((uint32_t)0x00000080U)
|
||||
#define SMARTCARD_FLAG_TC ((uint32_t)0x00000040U)
|
||||
#define SMARTCARD_FLAG_RXNE ((uint32_t)0x00000020U)
|
||||
#define SMARTCARD_FLAG_IDLE ((uint32_t)0x00000010U)
|
||||
#define SMARTCARD_FLAG_ORE ((uint32_t)0x00000008U)
|
||||
#define SMARTCARD_FLAG_NE ((uint32_t)0x00000004U)
|
||||
#define SMARTCARD_FLAG_FE ((uint32_t)0x00000002U)
|
||||
#define SMARTCARD_FLAG_PE ((uint32_t)0x00000001U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMARTCARD_Interrupt_definition SMARTCARD Interrupt definition
|
||||
* Elements values convention: 0000ZZZZ0XXYYYYYb
|
||||
* - YYYYY : Interrupt source position in the XX register (5bits)
|
||||
* - XX : Interrupt source register (2bits)
|
||||
* - 01: CR1 register
|
||||
* - 10: CR2 register
|
||||
* - 11: CR3 register
|
||||
* - ZZZZ : Flag position in the ISR register(4bits)
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SMARTCARD_IT_PE ((uint16_t)0x0028U)
|
||||
#define SMARTCARD_IT_TXE ((uint16_t)0x0727U)
|
||||
#define SMARTCARD_IT_TC ((uint16_t)0x0626U)
|
||||
#define SMARTCARD_IT_RXNE ((uint16_t)0x0525U)
|
||||
#define SMARTCARD_IT_IDLE ((uint16_t)0x0424U)
|
||||
#define SMARTCARD_IT_ERR ((uint16_t)0x0060U)
|
||||
#define SMARTCARD_IT_ORE ((uint16_t)0x0300U)
|
||||
#define SMARTCARD_IT_NE ((uint16_t)0x0200U)
|
||||
#define SMARTCARD_IT_FE ((uint16_t)0x0100U)
|
||||
|
||||
#define SMARTCARD_IT_EOB ((uint16_t)0x0C3BU)
|
||||
#define SMARTCARD_IT_RTO ((uint16_t)0x0B3AU)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup SMARTCARD_IT_CLEAR_Flags SMARTCARD IT CLEAR Flags
|
||||
* @{
|
||||
*/
|
||||
#define SMARTCARD_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */
|
||||
#define SMARTCARD_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */
|
||||
#define SMARTCARD_CLEAR_NEF USART_ICR_NCF /*!< Noise detected Clear Flag */
|
||||
#define SMARTCARD_CLEAR_OREF USART_ICR_ORECF /*!< OverRun Error Clear Flag */
|
||||
#define SMARTCARD_CLEAR_IDLEF USART_ICR_IDLECF /*!< Idle line detected clear Flag */
|
||||
#define SMARTCARD_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */
|
||||
#define SMARTCARD_CLEAR_RTOF USART_ICR_RTOCF /*!< Receiver Time Out Clear Flag */
|
||||
#define SMARTCARD_CLEAR_EOBF USART_ICR_EOBCF /*!< End Of Block Clear Flag */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMARTCARD_Request_Parameters SMARTCARD Request Parameters
|
||||
* @{
|
||||
*/
|
||||
#define SMARTCARD_RXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_RXFRQ) /*!< Receive Data flush Request */
|
||||
#define SMARTCARD_TXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_TXFRQ) /*!< Transmit data flush Request */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup SMARTCARD_CR3_SCAR_CNT_LSB_POS SMARTCARD CR3 SCAR CNT LSB POS
|
||||
* @{
|
||||
*/
|
||||
#define SMARTCARD_CR3_SCARCNT_LSB_POS ((uint32_t) 17U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMARTCARD_GTPR_GT_LSBPOS SMARTCARD GTPR GT LSBPOS
|
||||
* @{
|
||||
*/
|
||||
#define SMARTCARD_GTPR_GT_LSB_POS ((uint32_t) 8U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMARTCARD_RTOR_BLEN_LSBPOS SMARTCARD RTOR BLEN LSBPOS
|
||||
* @{
|
||||
*/
|
||||
#define SMARTCARD_RTOR_BLEN_LSB_POS ((uint32_t) 24U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMARTCARD_Interruption_Mask SMARTCARD Interruption Mask
|
||||
* @{
|
||||
*/
|
||||
#define SMARTCARD_IT_MASK ((uint16_t)0x001FU)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup SMARTCARD_Exported_Macros SMARTCARD Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset SMARTCARD handle state
|
||||
* @param __HANDLE__: specifies the SMARTCARD Handle.
|
||||
* The Handle Instance which can be USART1 or USART2
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMARTCARD_STATE_RESET)
|
||||
|
||||
/** @brief Flush the Smartcard DR register
|
||||
* @param __HANDLE__: specifies the SMARTCARD Handle.
|
||||
* The Handle Instance which can be USART1 or USART2.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__) (__HAL_SMARTCARD_SEND_REQ((__HANDLE__), SMARTCARD_RXDATA_FLUSH_REQUEST))
|
||||
|
||||
/** @brief Checks whether the specified Smartcard flag is set or not.
|
||||
* @param __HANDLE__: specifies the SMARTCARD Handle.
|
||||
* The Handle Instance which can be USART1 or USART2.
|
||||
* @param __FLAG__: specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SMARTCARD_FLAG_REACK: Receive enable acknowledge flag
|
||||
* @arg SMARTCARD_FLAG_TEACK: Transmit enable acknowledge flag
|
||||
* @arg SMARTCARD_FLAG_BUSY: Busy flag
|
||||
* @arg SMARTCARD_FLAG_EOBF: End of block flag
|
||||
* @arg SMARTCARD_FLAG_RTOF: Receiver timeout flag
|
||||
* @arg SMARTCARD_FLAG_TXE: Transmit data register empty flag
|
||||
* @arg SMARTCARD_FLAG_TC: Transmission Complete flag
|
||||
* @arg SMARTCARD_FLAG_RXNE: Receive data register not empty flag
|
||||
* @arg SMARTCARD_FLAG_ORE: OverRun Error flag
|
||||
* @arg SMARTCARD_FLAG_NE: Noise Error flag
|
||||
* @arg SMARTCARD_FLAG_FE: Framing Error flag
|
||||
* @arg SMARTCARD_FLAG_PE: Parity Error flag
|
||||
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_SMARTCARD_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
|
||||
|
||||
/** @brief Clear the specified SMARTCARD pending flag.
|
||||
* @param __HANDLE__: specifies the SMARTCARD Handle.
|
||||
* @param __FLAG__: specifies the flag to check.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg @ref SMARTCARD_CLEAR_PEF Parity error clear flag
|
||||
* @arg @ref SMARTCARD_CLEAR_FEF Framing error clear flag
|
||||
* @arg @ref SMARTCARD_CLEAR_NEF Noise detected clear flag
|
||||
* @arg @ref SMARTCARD_CLEAR_OREF OverRun error clear flag
|
||||
* @arg @ref SMARTCARD_CLEAR_IDLEF Idle line detected clear flag
|
||||
* @arg @ref SMARTCARD_CLEAR_TCF Transmission complete clear flag
|
||||
@if STM32L443xx
|
||||
* @arg @ref SMARTCARD_CLEAR_TCBGTF Transmission complete before guard time clear flag (when flag available)
|
||||
@endif
|
||||
* @arg @ref SMARTCARD_CLEAR_RTOF Receiver timeout clear flag
|
||||
* @arg @ref SMARTCARD_CLEAR_EOBF End of block clear flag
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SMARTCARD_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
|
||||
|
||||
/** @brief Clear the SMARTCARD PE pending flag.
|
||||
* @param __HANDLE__: specifies the SMARTCARD Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_PEF)
|
||||
|
||||
|
||||
/** @brief Clear the SMARTCARD FE pending flag.
|
||||
* @param __HANDLE__: specifies the SMARTCARD Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SMARTCARD_CLEAR_FEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_FEF)
|
||||
|
||||
/** @brief Clear the SMARTCARD NE pending flag.
|
||||
* @param __HANDLE__: specifies the SMARTCARD Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SMARTCARD_CLEAR_NEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_NEF)
|
||||
|
||||
/** @brief Clear the SMARTCARD ORE pending flag.
|
||||
* @param __HANDLE__: specifies the SMARTCARD Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SMARTCARD_CLEAR_OREFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_OREF)
|
||||
|
||||
/** @brief Clear the SMARTCARD IDLE pending flag.
|
||||
* @param __HANDLE__: specifies the SMARTCARD Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SMARTCARD_CLEAR_IDLEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_IDLEF)
|
||||
|
||||
/** @brief Enables the specified SmartCard interrupt.
|
||||
* @param __HANDLE__: specifies the SMARTCARD Handle.
|
||||
* The Handle Instance which can be USART1 or USART2.
|
||||
* @param __INTERRUPT__: specifies the SMARTCARD interrupt to enable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SMARTCARD_IT_EOBF: End Of Block interrupt
|
||||
* @arg SMARTCARD_IT_RTOF: Receive TimeOut interrupt
|
||||
* @arg SMARTCARD_IT_TXE: Transmit Data Register empty interrupt
|
||||
* @arg SMARTCARD_IT_TC: Transmission complete interrupt
|
||||
* @arg SMARTCARD_IT_RXNE: Receive Data register not empty interrupt
|
||||
* @arg SMARTCARD_IT_PE: Parity Error interrupt
|
||||
* @arg SMARTCARD_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
|
||||
((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
|
||||
((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))))
|
||||
/** @brief Disables the specified SmartCard interrupt.
|
||||
* @param __HANDLE__: specifies the SMARTCARD Handle.
|
||||
* The Handle Instance which can be USART1 or USART2.
|
||||
* @param __INTERRUPT__: specifies the SMARTCARD interrupt to enable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SMARTCARD_IT_EOBF: End Of Block interrupt
|
||||
* @arg SMARTCARD_IT_RTOF: Receive TimeOut interrupt
|
||||
* @arg SMARTCARD_IT_TXE: Transmit Data Register empty interrupt
|
||||
* @arg SMARTCARD_IT_TC: Transmission complete interrupt
|
||||
* @arg SMARTCARD_IT_RXNE: Receive Data register not empty interrupt
|
||||
* @arg SMARTCARD_IT_PE: Parity Error interrupt
|
||||
* @arg SMARTCARD_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
|
||||
((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
|
||||
((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))))
|
||||
|
||||
/** @brief Checks whether the specified SmartCard interrupt has occurred or not.
|
||||
* @param __HANDLE__: specifies the SMARTCARD Handle.
|
||||
* The Handle Instance which can be USART1 or USART2.
|
||||
* @param __IT__: specifies the SMARTCARD interrupt to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SMARTCARD_IT_EOBF: End Of Block interrupt
|
||||
* @arg SMARTCARD_IT_RTOF: Receive TimeOut interrupt
|
||||
* @arg SMARTCARD_IT_TXE: Transmit Data Register empty interrupt
|
||||
* @arg SMARTCARD_IT_TC: Transmission complete interrupt
|
||||
* @arg SMARTCARD_IT_RXNE: Receive Data register not empty interrupt
|
||||
* @arg SMARTCARD_IT_ORE: OverRun Error interrupt
|
||||
* @arg SMARTCARD_IT_NE: Noise Error interrupt
|
||||
* @arg SMARTCARD_IT_FE: Framing Error interrupt
|
||||
* @arg SMARTCARD_IT_PE: Parity Error interrupt
|
||||
* @retval The new state of __IT__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_SMARTCARD_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1U << ((__IT__)>> 0x08U)))
|
||||
|
||||
/** @brief Checks whether the specified SmartCard interrupt interrupt source is enabled.
|
||||
* @param __HANDLE__: specifies the SMARTCARD Handle.
|
||||
* The Handle Instance which can be USART1 or USART2.
|
||||
* @param __IT__: specifies the SMARTCARD interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SMARTCARD_IT_EOBF: End Of Block interrupt
|
||||
* @arg SMARTCARD_IT_RTOF: Receive TimeOut interrupt
|
||||
* @arg SMARTCARD_IT_TXE: Transmit Data Register empty interrupt
|
||||
* @arg SMARTCARD_IT_TC: Transmission complete interrupt
|
||||
* @arg SMARTCARD_IT_RXNE: Receive Data register not empty interrupt
|
||||
* @arg SMARTCARD_IT_ORE: OverRun Error interrupt
|
||||
* @arg SMARTCARD_IT_NE: Noise Error interrupt
|
||||
* @arg SMARTCARD_IT_FE: Framing Error interrupt
|
||||
* @arg SMARTCARD_IT_PE: Parity Error interrupt
|
||||
* @retval The new state of __IT__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5U) == 1U)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5U) == 2U)? \
|
||||
(__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << \
|
||||
(((uint16_t)(__IT__)) & SMARTCARD_IT_MASK)))
|
||||
|
||||
|
||||
/** @brief Clears the specified SMARTCARD ISR flag, in setting the proper ICR register flag.
|
||||
* @param __HANDLE__: specifies the SMARTCARD Handle.
|
||||
* The Handle Instance which can be USART1 or USART2.
|
||||
* @param __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set
|
||||
* to clear the corresponding interrupt
|
||||
* This parameter can be one of the following values:
|
||||
* @arg USART_CLEAR_PEF: Parity Error Clear Flag
|
||||
* @arg USART_CLEAR_FEF: Framing Error Clear Flag
|
||||
* @arg USART_CLEAR_NEF: Noise detected Clear Flag
|
||||
* @arg USART_CLEAR_OREF: OverRun Error Clear Flag
|
||||
* @arg USART_CLEAR_TCF: Transmission Complete Clear Flag
|
||||
* @arg USART_CLEAR_RTOF: Receiver Time Out Clear Flag
|
||||
* @arg USART_CLEAR_EOBF: End Of Block Clear Flag
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SMARTCARD_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
|
||||
|
||||
/** @brief Set a specific SMARTCARD request flag.
|
||||
* @param __HANDLE__: specifies the SMARTCARD Handle.
|
||||
* The Handle Instance which can be USART1 or USART2.
|
||||
* @param __REQ__: specifies the request flag to set
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SMARTCARD_RXDATA_FLUSH_REQUEST: Receive Data flush Request
|
||||
* @arg SMARTCARD_TXDATA_FLUSH_REQUEST: Transmit data flush Request
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SMARTCARD_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint32_t)(__REQ__))
|
||||
|
||||
/** @brief Enable the USART associated to the SMARTCARD Handle
|
||||
* @param __HANDLE__: specifies the SMARTCARD Handle.
|
||||
* The Handle Instance which can be USART1 or USART2.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SMARTCARD_ENABLE(__HANDLE__) ( (__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
|
||||
|
||||
/** @brief Disable the USART associated to the SMARTCARD Handle
|
||||
* @param __HANDLE__: specifies the SMARTCARD Handle.
|
||||
* The Handle Instance which can be USART1 or USART2.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SMARTCARD_DISABLE(__HANDLE__) ( (__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
|
||||
|
||||
/** @brief Macros to enable or disable the SmartCard DMA request.
|
||||
* @param __HANDLE__: specifies the SMARTCARD Handle.
|
||||
* The Handle Instance which can be USART1 or USART2.
|
||||
* @param __REQUEST__: specifies the SmartCard DMA request.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SMARTCARD_DMAREQ_TX: SmartCard DMA transmit request
|
||||
* @arg SMARTCARD_DMAREQ_RX: SmartCard DMA receive request
|
||||
*/
|
||||
#define __HAL_SMARTCARD_DMA_REQUEST_ENABLE(__HANDLE__, __REQUEST__) ((__HANDLE__)->Instance->CR3 |= (__REQUEST__))
|
||||
#define __HAL_SMARTCARD_DMA_REQUEST_DISABLE(__HANDLE__, __REQUEST__) ((__HANDLE__)->Instance->CR3 &= ~(__REQUEST__))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include SMARTCARD HAL Extension module */
|
||||
#include "stm32f7xx_hal_smartcard_ex.h"
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup SMARTCARD_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup SMARTCARD_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Initialization/de-initialization functions **********************************/
|
||||
HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsmartcard);
|
||||
HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsmartcard);
|
||||
void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsmartcard);
|
||||
void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup SMARTCARD_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* IO operation functions *******************************************************/
|
||||
HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
|
||||
/* Transfer Abort functions */
|
||||
HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard);
|
||||
HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsmartcard);
|
||||
HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsmartcard);
|
||||
HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard);
|
||||
HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard);
|
||||
HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartcard);
|
||||
|
||||
void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard);
|
||||
void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard);
|
||||
void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard);
|
||||
void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsmartcard);
|
||||
void HAL_SMARTCARD_AbortCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard);
|
||||
void HAL_SMARTCARD_AbortTransmitCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard);
|
||||
void HAL_SMARTCARD_AbortReceiveCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup SMARTCARD_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State functions **************************************************/
|
||||
HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsmartcard);
|
||||
uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmartcard);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup SMARTCARD_Private_Constants SMARTCARD Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_SMARTCARD_WORD_LENGTH(__LENGTH__) ((__LENGTH__) == SMARTCARD_WORDLENGTH_9B)
|
||||
#define IS_SMARTCARD_STOPBITS(__STOPBITS__) ((__STOPBITS__) == SMARTCARD_STOPBITS_1_5)
|
||||
#define IS_SMARTCARD_PARITY(__PARITY__) (((__PARITY__) == SMARTCARD_PARITY_EVEN) || \
|
||||
((__PARITY__) == SMARTCARD_PARITY_ODD))
|
||||
#define IS_SMARTCARD_MODE(__MODE__) ((((__MODE__) & (uint32_t)0xFFF3) == 0x00) && ((__MODE__) != (uint32_t)0x00))
|
||||
#define IS_SMARTCARD_POLARITY(__CPOL__) (((__CPOL__) == SMARTCARD_POLARITY_LOW) || ((__CPOL__) == SMARTCARD_POLARITY_HIGH))
|
||||
#define IS_SMARTCARD_PHASE(__CPHA__) (((__CPHA__) == SMARTCARD_PHASE_1EDGE) || ((__CPHA__) == SMARTCARD_PHASE_2EDGE))
|
||||
#define IS_SMARTCARD_LASTBIT(__LASTBIT__) (((__LASTBIT__) == SMARTCARD_LASTBIT_DISABLE) || \
|
||||
((__LASTBIT__) == SMARTCARD_LASTBIT_ENABLE))
|
||||
#define IS_SMARTCARD_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == SMARTCARD_ONE_BIT_SAMPLE_DISABLE) || \
|
||||
((__ONEBIT__) == SMARTCARD_ONE_BIT_SAMPLE_ENABLE))
|
||||
#define IS_SMARTCARD_NACK(__NACK__) (((__NACK__) == SMARTCARD_NACK_ENABLE) || \
|
||||
((__NACK__) == SMARTCARD_NACK_DISABLE))
|
||||
#define IS_SMARTCARD_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == SMARTCARD_TIMEOUT_DISABLE) || \
|
||||
((__TIMEOUT__) == SMARTCARD_TIMEOUT_ENABLE))
|
||||
#define IS_SMARTCARD_ADVFEATURE_INIT(INIT) ((INIT) <= (SMARTCARD_ADVFEATURE_NO_INIT | \
|
||||
SMARTCARD_ADVFEATURE_TXINVERT_INIT | \
|
||||
SMARTCARD_ADVFEATURE_RXINVERT_INIT | \
|
||||
SMARTCARD_ADVFEATURE_DATAINVERT_INIT | \
|
||||
SMARTCARD_ADVFEATURE_SWAP_INIT | \
|
||||
SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT | \
|
||||
SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT | \
|
||||
SMARTCARD_ADVFEATURE_MSBFIRST_INIT))
|
||||
#define IS_SMARTCARD_ADVFEATURE_TXINV(TXINV) (((TXINV) == SMARTCARD_ADVFEATURE_TXINV_DISABLE) || \
|
||||
((TXINV) == SMARTCARD_ADVFEATURE_TXINV_ENABLE))
|
||||
#define IS_SMARTCARD_ADVFEATURE_RXINV(RXINV) (((RXINV) == SMARTCARD_ADVFEATURE_RXINV_DISABLE) || \
|
||||
((RXINV) == SMARTCARD_ADVFEATURE_RXINV_ENABLE))
|
||||
#define IS_SMARTCARD_ADVFEATURE_DATAINV(DATAINV) (((DATAINV) == SMARTCARD_ADVFEATURE_DATAINV_DISABLE) || \
|
||||
((DATAINV) == SMARTCARD_ADVFEATURE_DATAINV_ENABLE))
|
||||
#define IS_SMARTCARD_ADVFEATURE_SWAP(SWAP) (((SWAP) == SMARTCARD_ADVFEATURE_SWAP_DISABLE) || \
|
||||
((SWAP) == SMARTCARD_ADVFEATURE_SWAP_ENABLE))
|
||||
#define IS_SMARTCARD_OVERRUN(OVERRUN) (((OVERRUN) == SMARTCARD_ADVFEATURE_OVERRUN_ENABLE) || \
|
||||
((OVERRUN) == SMARTCARD_ADVFEATURE_OVERRUN_DISABLE))
|
||||
#define IS_SMARTCARD_ADVFEATURE_DMAONRXERROR(DMA) (((DMA) == SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR) || \
|
||||
((DMA) == SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR))
|
||||
#define IS_SMARTCARD_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 4500001)
|
||||
#define IS_SMARTCARD_BLOCKLENGTH(__LENGTH__) ((__LENGTH__) <= 0xFF)
|
||||
#define IS_SMARTCARD_TIMEOUT_VALUE(__TIMEOUTVALUE__) ((__TIMEOUTVALUE__) <= 0xFFFFFF)
|
||||
#define IS_SMARTCARD_AUTORETRY_COUNT(__COUNT__) ((__COUNT__) <= 0x7)
|
||||
#define IS_SMARTCARD_ADVFEATURE_MSBFIRST(MSBFIRST) (((MSBFIRST) == SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE) || \
|
||||
((MSBFIRST) == SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE))
|
||||
#define IS_SMARTCARD_REQUEST_PARAMETER(PARAM) (((PARAM) == SMARTCARD_RXDATA_FLUSH_REQUEST) || \
|
||||
((PARAM) == SMARTCARD_TXDATA_FLUSH_REQUEST))
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup SMARTCARD_Private_Functions SMARTCARD Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F7xx_HAL_SMARTCARD_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,308 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_hal_smartcard_ex.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.2
|
||||
* @date 14-April-2017
|
||||
* @brief Header file of SMARTCARD HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F7xx_HAL_SMARTCARD_EX_H
|
||||
#define __STM32F7xx_HAL_SMARTCARD_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup SMARTCARDEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @addtogroup SMARTCARDEx_Exported_Constants SMARTCARD Extended Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup SMARTCARDEx_Transmission_Completion_Indication SMARTCARD Transmission Completion Indication
|
||||
* @{
|
||||
*/
|
||||
#if defined(USART_TCBGT_SUPPORT)
|
||||
#define SMARTCARD_TCBGT SMARTCARD_IT_TCBGT /*!< SMARTCARD transmission complete before guard time */
|
||||
#endif /* USART_TCBGT_SUPPORT */
|
||||
#define SMARTCARD_TC SMARTCARD_IT_TC /*!< SMARTCARD transmission complete (flag raised when guard time has elapsed) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMARTCARDEx_Advanced_Features_Initialization_Type SMARTCARD advanced feature initialization type
|
||||
* @{
|
||||
*/
|
||||
#if defined(USART_TCBGT_SUPPORT)
|
||||
#define SMARTCARD_ADVFEATURE_TXCOMPLETION ((uint32_t)0x00000100) /*!< TX completion indication before of after guard time */
|
||||
#endif /* USART_TCBGT_SUPPORT */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
|
||||
|
||||
/** @defgroup SMARTCARDEx_Flags SMARTCARD Flags
|
||||
* Elements values convention: 0xXXXX
|
||||
* - 0xXXXX : Flag mask in the ISR register
|
||||
* @{
|
||||
*/
|
||||
#if defined(USART_TCBGT_SUPPORT)
|
||||
#define SMARTCARD_FLAG_TCBGT USART_ISR_TCBGT /*!< SMARTCARD transmission complete before guard time completion */
|
||||
#endif /* USART_TCBGT_SUPPORT */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMARTCARDEx_Interrupt_definition SMARTCARD Interrupts Definition
|
||||
* Elements values convention: 000ZZZZZ0XXYYYYYb
|
||||
* - YYYYY : Interrupt source position in the XX register (5 bits)
|
||||
* - XX : Interrupt source register (2 bits)
|
||||
* - 01: CR1 register
|
||||
* - 10: CR2 register
|
||||
* - 11: CR3 register
|
||||
* - ZZZZZ : Flag position in the ISR register(5 bits)
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(USART_TCBGT_SUPPORT)
|
||||
#define SMARTCARD_IT_TCBGT ((uint16_t)0x1978) /*!< SMARTCARD transmission complete before guard time completion interruption */
|
||||
#endif /* USART_TCBGT_SUPPORT */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMARTCARDEx_IT_CLEAR_Flags SMARTCARD Interruption Clear Flags
|
||||
* @{
|
||||
*/
|
||||
#define SMARTCARD_CLEAR_PEF USART_ICR_PECF /*!< SMARTCARD parity error clear flag */
|
||||
#define SMARTCARD_CLEAR_FEF USART_ICR_FECF /*!< SMARTCARD framing error clear flag */
|
||||
#define SMARTCARD_CLEAR_NEF USART_ICR_NCF /*!< SMARTCARD noise detected clear flag */
|
||||
#define SMARTCARD_CLEAR_OREF USART_ICR_ORECF /*!< SMARTCARD overrun error clear flag */
|
||||
#define SMARTCARD_CLEAR_IDLEF USART_ICR_IDLECF /*!< SMARTCARD idle line detected clear flag */
|
||||
#define SMARTCARD_CLEAR_TCF USART_ICR_TCCF /*!< SMARTCARD transmission complete clear flag */
|
||||
#if defined(USART_TCBGT_SUPPORT)
|
||||
#define SMARTCARD_CLEAR_TCBGTF USART_ICR_TCBGTCF /*!< SMARTCARD transmission complete before guard time completion clear flag */
|
||||
#endif /* USART_TCBGT_SUPPORT */
|
||||
#define SMARTCARD_CLEAR_RTOF USART_ICR_RTOCF /*!< SMARTCARD receiver time out clear flag */
|
||||
#define SMARTCARD_CLEAR_EOBF USART_ICR_EOBCF /*!< SMARTCARD end of block clear flag */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
|
||||
/** @brief Reports the SMARTCARD clock source.
|
||||
* @param __HANDLE__: specifies the USART Handle
|
||||
* @param __CLOCKSOURCE__ : output variable
|
||||
* @retval the USART clocking source, written in __CLOCKSOURCE__.
|
||||
*/
|
||||
#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
|
||||
do { \
|
||||
if((__HANDLE__)->Instance == USART1) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART1_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART1CLKSOURCE_PCLK2: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK2; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART2) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART2_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART2CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART3) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART3_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART3CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART3CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART3CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART3CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART6) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART6_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART6CLKSOURCE_PCLK2: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK2; \
|
||||
break; \
|
||||
case RCC_USART6CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART6CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART6CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
} while(0)
|
||||
|
||||
/** @brief Set the Transmission Completion flag
|
||||
* @param __HANDLE__: specifies the SMARTCARD Handle.
|
||||
* @note If TCBGT (Transmission Complete Before Guard Time) flag is not available or if
|
||||
* AdvancedInit.TxCompletionIndication is not already filled, the latter is forced
|
||||
* to SMARTCARD_TC (transmission completion indication when guard time has elapsed).
|
||||
* @retval None
|
||||
*/
|
||||
#if defined(USART_TCBGT_SUPPORT)
|
||||
#define SMARTCARD_TRANSMISSION_COMPLETION_SETTING(__HANDLE__) \
|
||||
do { \
|
||||
if (HAL_IS_BIT_CLR((__HANDLE__)->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_TXCOMPLETION)) \
|
||||
{ \
|
||||
(__HANDLE__)->AdvancedInit.TxCompletionIndication = SMARTCARD_TC; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
assert_param(IS_SMARTCARD_TRANSMISSION_COMPLETION((__HANDLE__)->AdvancedInit.TxCompletionIndication)); \
|
||||
} \
|
||||
} while(0)
|
||||
#else
|
||||
#define SMARTCARD_TRANSMISSION_COMPLETION_SETTING(__HANDLE__) \
|
||||
do { \
|
||||
(__HANDLE__)->AdvancedInit.TxCompletionIndication = SMARTCARD_TC; \
|
||||
} while(0)
|
||||
#endif
|
||||
|
||||
/** @brief Return the transmission completion flag.
|
||||
* @param __HANDLE__: specifies the SMARTCARD Handle.
|
||||
* @note Based on AdvancedInit.TxCompletionIndication setting, return TC or TCBGT flag.
|
||||
* When TCBGT flag (Transmission Complete Before Guard Time) is not available, TC flag is
|
||||
* reported.
|
||||
* @retval Transmission completion flag
|
||||
*/
|
||||
#if defined(USART_TCBGT_SUPPORT)
|
||||
#define SMARTCARD_TRANSMISSION_COMPLETION_FLAG(__HANDLE__) \
|
||||
(((__HANDLE__)->AdvancedInit.TxCompletionIndication == SMARTCARD_TC) ? (SMARTCARD_FLAG_TC) : (SMARTCARD_FLAG_TCBGT))
|
||||
#else
|
||||
#define SMARTCARD_TRANSMISSION_COMPLETION_FLAG(__HANDLE__) (SMARTCARD_FLAG_TC)
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Ensure that SMARTCARD frame transmission completion used flag is valid.
|
||||
* @param __TXCOMPLETE__: SMARTCARD frame transmission completion used flag.
|
||||
* @retval SET (__TXCOMPLETE__ is valid) or RESET (__TXCOMPLETE__ is invalid)
|
||||
*/
|
||||
#if defined(USART_TCBGT_SUPPORT)
|
||||
#define IS_SMARTCARD_TRANSMISSION_COMPLETION(__TXCOMPLETE__) (((__TXCOMPLETE__) == SMARTCARD_TCBGT) ||\
|
||||
((__TXCOMPLETE__) == SMARTCARD_TC))
|
||||
#else
|
||||
#define IS_SMARTCARD_TRANSMISSION_COMPLETION(__TXCOMPLETE__) ((__TXCOMPLETE__) == SMARTCARD_TC)
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/* Initialization and de-initialization functions ****************************/
|
||||
/* IO operation functions *****************************************************/
|
||||
/* Peripheral Control functions ***********************************************/
|
||||
void HAL_SMARTCARDEx_BlockLength_Config(SMARTCARD_HandleTypeDef *hsc, uint8_t BlockLength);
|
||||
void HAL_SMARTCARDEx_TimeOut_Config(SMARTCARD_HandleTypeDef *hsc, uint32_t TimeOutValue);
|
||||
HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsc);
|
||||
HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsc);
|
||||
|
||||
/* Peripheral State and Error functions ***************************************/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F7xx_HAL_SMARTCARD_EX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,697 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_hal_smbus.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.2
|
||||
* @date 14-April-2017
|
||||
* @brief Header file of SMBUS HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F7xx_HAL_SMBUS_H
|
||||
#define __STM32F7xx_HAL_SMBUS_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup SMBUS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup SMBUS_Exported_Types SMBUS Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup SMBUS_Configuration_Structure_definition SMBUS Configuration Structure definition
|
||||
* @brief SMBUS Configuration Structure definition
|
||||
* @{
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Timing; /*!< Specifies the SMBUS_TIMINGR_register value.
|
||||
This parameter calculated by referring to SMBUS initialization
|
||||
section in Reference manual */
|
||||
uint32_t AnalogFilter; /*!< Specifies if Analog Filter is enable or not.
|
||||
This parameter can be a value of @ref SMBUS_Analog_Filter */
|
||||
|
||||
uint32_t OwnAddress1; /*!< Specifies the first device own address.
|
||||
This parameter can be a 7-bit or 10-bit address. */
|
||||
|
||||
uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode for master is selected.
|
||||
This parameter can be a value of @ref SMBUS_addressing_mode */
|
||||
|
||||
uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected.
|
||||
This parameter can be a value of @ref SMBUS_dual_addressing_mode */
|
||||
|
||||
uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected
|
||||
This parameter can be a 7-bit address. */
|
||||
|
||||
uint32_t OwnAddress2Masks; /*!< Specifies the acknoledge mask address second device own address if dual addressing mode is selected
|
||||
This parameter can be a value of @ref SMBUS_own_address2_masks. */
|
||||
|
||||
uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
|
||||
This parameter can be a value of @ref SMBUS_general_call_addressing_mode. */
|
||||
|
||||
uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
|
||||
This parameter can be a value of @ref SMBUS_nostretch_mode */
|
||||
|
||||
uint32_t PacketErrorCheckMode; /*!< Specifies if Packet Error Check mode is selected.
|
||||
This parameter can be a value of @ref SMBUS_packet_error_check_mode */
|
||||
|
||||
uint32_t PeripheralMode; /*!< Specifies which mode of Periphal is selected.
|
||||
This parameter can be a value of @ref SMBUS_peripheral_mode */
|
||||
|
||||
uint32_t SMBusTimeout; /*!< Specifies the content of the 32 Bits SMBUS_TIMEOUT_register value.
|
||||
(Enable bits and different timeout values)
|
||||
This parameter calculated by referring to SMBUS initialization
|
||||
section in Reference manual */
|
||||
} SMBUS_InitTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_state_definition HAL state definition
|
||||
* @brief HAL State definition
|
||||
* @{
|
||||
*/
|
||||
#define HAL_SMBUS_STATE_RESET (0x00000000U) /*!< SMBUS not yet initialized or disabled */
|
||||
#define HAL_SMBUS_STATE_READY (0x00000001U) /*!< SMBUS initialized and ready for use */
|
||||
#define HAL_SMBUS_STATE_BUSY (0x00000002U) /*!< SMBUS internal process is ongoing */
|
||||
#define HAL_SMBUS_STATE_MASTER_BUSY_TX (0x00000012U) /*!< Master Data Transmission process is ongoing */
|
||||
#define HAL_SMBUS_STATE_MASTER_BUSY_RX (0x00000022U) /*!< Master Data Reception process is ongoing */
|
||||
#define HAL_SMBUS_STATE_SLAVE_BUSY_TX (0x00000032U) /*!< Slave Data Transmission process is ongoing */
|
||||
#define HAL_SMBUS_STATE_SLAVE_BUSY_RX (0x00000042U) /*!< Slave Data Reception process is ongoing */
|
||||
#define HAL_SMBUS_STATE_TIMEOUT (0x00000003U) /*!< Timeout state */
|
||||
#define HAL_SMBUS_STATE_ERROR (0x00000004U) /*!< Reception process is ongoing */
|
||||
#define HAL_SMBUS_STATE_LISTEN (0x00000008U) /*!< Address Listen Mode is ongoing */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMBUS_Error_Code_definition SMBUS Error Code definition
|
||||
* @brief SMBUS Error Code definition
|
||||
* @{
|
||||
*/
|
||||
#define HAL_SMBUS_ERROR_NONE (0x00000000U) /*!< No error */
|
||||
#define HAL_SMBUS_ERROR_BERR (0x00000001U) /*!< BERR error */
|
||||
#define HAL_SMBUS_ERROR_ARLO (0x00000002U) /*!< ARLO error */
|
||||
#define HAL_SMBUS_ERROR_ACKF (0x00000004U) /*!< ACKF error */
|
||||
#define HAL_SMBUS_ERROR_OVR (0x00000008U) /*!< OVR error */
|
||||
#define HAL_SMBUS_ERROR_HALTIMEOUT (0x00000010U) /*!< Timeout error */
|
||||
#define HAL_SMBUS_ERROR_BUSTIMEOUT (0x00000020U) /*!< Bus Timeout error */
|
||||
#define HAL_SMBUS_ERROR_ALERT (0x00000040U) /*!< Alert error */
|
||||
#define HAL_SMBUS_ERROR_PECERR (0x00000080U) /*!< PEC error */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMBUS_handle_Structure_definition SMBUS handle Structure definition
|
||||
* @brief SMBUS handle Structure definition
|
||||
* @{
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
I2C_TypeDef *Instance; /*!< SMBUS registers base address */
|
||||
|
||||
SMBUS_InitTypeDef Init; /*!< SMBUS communication parameters */
|
||||
|
||||
uint8_t *pBuffPtr; /*!< Pointer to SMBUS transfer buffer */
|
||||
|
||||
uint16_t XferSize; /*!< SMBUS transfer size */
|
||||
|
||||
__IO uint16_t XferCount; /*!< SMBUS transfer counter */
|
||||
|
||||
__IO uint32_t XferOptions; /*!< SMBUS transfer options */
|
||||
|
||||
__IO uint32_t PreviousState; /*!< SMBUS communication Previous state */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< SMBUS locking object */
|
||||
|
||||
__IO uint32_t State; /*!< SMBUS communication state */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< SMBUS Error code */
|
||||
|
||||
}SMBUS_HandleTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup SMBUS_Exported_Constants SMBUS Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup SMBUS_Analog_Filter SMBUS Analog Filter
|
||||
* @{
|
||||
*/
|
||||
#define SMBUS_ANALOGFILTER_ENABLE (0x00000000U)
|
||||
#define SMBUS_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMBUS_addressing_mode SMBUS addressing mode
|
||||
* @{
|
||||
*/
|
||||
#define SMBUS_ADDRESSINGMODE_7BIT (0x00000001U)
|
||||
#define SMBUS_ADDRESSINGMODE_10BIT (0x00000002U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMBUS_dual_addressing_mode SMBUS dual addressing mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SMBUS_DUALADDRESS_DISABLE (0x00000000U)
|
||||
#define SMBUS_DUALADDRESS_ENABLE I2C_OAR2_OA2EN
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMBUS_own_address2_masks SMBUS ownaddress2 masks
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SMBUS_OA2_NOMASK ((uint8_t)0x00U)
|
||||
#define SMBUS_OA2_MASK01 ((uint8_t)0x01U)
|
||||
#define SMBUS_OA2_MASK02 ((uint8_t)0x02U)
|
||||
#define SMBUS_OA2_MASK03 ((uint8_t)0x03U)
|
||||
#define SMBUS_OA2_MASK04 ((uint8_t)0x04U)
|
||||
#define SMBUS_OA2_MASK05 ((uint8_t)0x05U)
|
||||
#define SMBUS_OA2_MASK06 ((uint8_t)0x06U)
|
||||
#define SMBUS_OA2_MASK07 ((uint8_t)0x07U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup SMBUS_general_call_addressing_mode SMBUS general call addressing mode
|
||||
* @{
|
||||
*/
|
||||
#define SMBUS_GENERALCALL_DISABLE (0x00000000U)
|
||||
#define SMBUS_GENERALCALL_ENABLE I2C_CR1_GCEN
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMBUS_nostretch_mode SMBUS nostretch mode
|
||||
* @{
|
||||
*/
|
||||
#define SMBUS_NOSTRETCH_DISABLE (0x00000000U)
|
||||
#define SMBUS_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMBUS_packet_error_check_mode SMBUS packet error check mode
|
||||
* @{
|
||||
*/
|
||||
#define SMBUS_PEC_DISABLE (0x00000000U)
|
||||
#define SMBUS_PEC_ENABLE I2C_CR1_PECEN
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMBUS_peripheral_mode SMBUS peripheral mode
|
||||
* @{
|
||||
*/
|
||||
#define SMBUS_PERIPHERAL_MODE_SMBUS_HOST I2C_CR1_SMBHEN
|
||||
#define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE (0x00000000U)
|
||||
#define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP I2C_CR1_SMBDEN
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMBUS_ReloadEndMode_definition SMBUS ReloadEndMode definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SMBUS_SOFTEND_MODE (0x00000000U)
|
||||
#define SMBUS_RELOAD_MODE I2C_CR2_RELOAD
|
||||
#define SMBUS_AUTOEND_MODE I2C_CR2_AUTOEND
|
||||
#define SMBUS_SENDPEC_MODE I2C_CR2_PECBYTE
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMBUS_StartStopMode_definition SMBUS StartStopMode definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SMBUS_NO_STARTSTOP (0x00000000U)
|
||||
#define SMBUS_GENERATE_STOP I2C_CR2_STOP
|
||||
#define SMBUS_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)
|
||||
#define SMBUS_GENERATE_START_WRITE I2C_CR2_START
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMBUS_XferOptions_definition SMBUS XferOptions definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* List of XferOptions in usage of :
|
||||
* 1- Restart condition when direction change
|
||||
* 2- No Restart condition in other use cases
|
||||
*/
|
||||
#define SMBUS_FIRST_FRAME SMBUS_SOFTEND_MODE
|
||||
#define SMBUS_NEXT_FRAME ((uint32_t)(SMBUS_RELOAD_MODE | SMBUS_SOFTEND_MODE))
|
||||
#define SMBUS_FIRST_AND_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE
|
||||
#define SMBUS_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE
|
||||
#define SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
|
||||
#define SMBUS_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
|
||||
|
||||
/* List of XferOptions in usage of :
|
||||
* 1- Restart condition in all use cases (direction change or not)
|
||||
*/
|
||||
#define SMBUS_OTHER_FRAME_NO_PEC (0x000000AAU)
|
||||
#define SMBUS_OTHER_FRAME_WITH_PEC (0x0000AA00U)
|
||||
#define SMBUS_OTHER_AND_LAST_FRAME_NO_PEC (0x00AA0000U)
|
||||
#define SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC (0xAA000000U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMBUS_Interrupt_configuration_definition SMBUS Interrupt configuration definition
|
||||
* @brief SMBUS Interrupt definition
|
||||
* Elements values convention: 0xXXXXXXXX
|
||||
* - XXXXXXXX : Interrupt control mask
|
||||
* @{
|
||||
*/
|
||||
#define SMBUS_IT_ERRI I2C_CR1_ERRIE
|
||||
#define SMBUS_IT_TCI I2C_CR1_TCIE
|
||||
#define SMBUS_IT_STOPI I2C_CR1_STOPIE
|
||||
#define SMBUS_IT_NACKI I2C_CR1_NACKIE
|
||||
#define SMBUS_IT_ADDRI I2C_CR1_ADDRIE
|
||||
#define SMBUS_IT_RXI I2C_CR1_RXIE
|
||||
#define SMBUS_IT_TXI I2C_CR1_TXIE
|
||||
#define SMBUS_IT_TX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI)
|
||||
#define SMBUS_IT_RX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_NACKI | SMBUS_IT_RXI)
|
||||
#define SMBUS_IT_ALERT (SMBUS_IT_ERRI)
|
||||
#define SMBUS_IT_ADDR (SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SMBUS_Flag_definition SMBUS Flag definition
|
||||
* @brief Flag definition
|
||||
* Elements values convention: 0xXXXXYYYY
|
||||
* - XXXXXXXX : Flag mask
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SMBUS_FLAG_TXE I2C_ISR_TXE
|
||||
#define SMBUS_FLAG_TXIS I2C_ISR_TXIS
|
||||
#define SMBUS_FLAG_RXNE I2C_ISR_RXNE
|
||||
#define SMBUS_FLAG_ADDR I2C_ISR_ADDR
|
||||
#define SMBUS_FLAG_AF I2C_ISR_NACKF
|
||||
#define SMBUS_FLAG_STOPF I2C_ISR_STOPF
|
||||
#define SMBUS_FLAG_TC I2C_ISR_TC
|
||||
#define SMBUS_FLAG_TCR I2C_ISR_TCR
|
||||
#define SMBUS_FLAG_BERR I2C_ISR_BERR
|
||||
#define SMBUS_FLAG_ARLO I2C_ISR_ARLO
|
||||
#define SMBUS_FLAG_OVR I2C_ISR_OVR
|
||||
#define SMBUS_FLAG_PECERR I2C_ISR_PECERR
|
||||
#define SMBUS_FLAG_TIMEOUT I2C_ISR_TIMEOUT
|
||||
#define SMBUS_FLAG_ALERT I2C_ISR_ALERT
|
||||
#define SMBUS_FLAG_BUSY I2C_ISR_BUSY
|
||||
#define SMBUS_FLAG_DIR I2C_ISR_DIR
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros ------------------------------------------------------------*/
|
||||
/** @defgroup SMBUS_Exported_Macros SMBUS Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset SMBUS handle state.
|
||||
* @param __HANDLE__ specifies the SMBUS Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMBUS_STATE_RESET)
|
||||
|
||||
/** @brief Enable the specified SMBUS interrupts.
|
||||
* @param __HANDLE__ specifies the SMBUS Handle.
|
||||
* @param __INTERRUPT__ specifies the interrupt source to enable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref SMBUS_IT_ERRI Errors interrupt enable
|
||||
* @arg @ref SMBUS_IT_TCI Transfer complete interrupt enable
|
||||
* @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable
|
||||
* @arg @ref SMBUS_IT_NACKI NACK received interrupt enable
|
||||
* @arg @ref SMBUS_IT_ADDRI Address match interrupt enable
|
||||
* @arg @ref SMBUS_IT_RXI RX interrupt enable
|
||||
* @arg @ref SMBUS_IT_TXI TX interrupt enable
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SMBUS_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
|
||||
|
||||
/** @brief Disable the specified SMBUS interrupts.
|
||||
* @param __HANDLE__ specifies the SMBUS Handle.
|
||||
* @param __INTERRUPT__ specifies the interrupt source to disable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref SMBUS_IT_ERRI Errors interrupt enable
|
||||
* @arg @ref SMBUS_IT_TCI Transfer complete interrupt enable
|
||||
* @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable
|
||||
* @arg @ref SMBUS_IT_NACKI NACK received interrupt enable
|
||||
* @arg @ref SMBUS_IT_ADDRI Address match interrupt enable
|
||||
* @arg @ref SMBUS_IT_RXI RX interrupt enable
|
||||
* @arg @ref SMBUS_IT_TXI TX interrupt enable
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SMBUS_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
|
||||
|
||||
/** @brief Check whether the specified SMBUS interrupt source is enabled or not.
|
||||
* @param __HANDLE__ specifies the SMBUS Handle.
|
||||
* @param __INTERRUPT__ specifies the SMBUS interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref SMBUS_IT_ERRI Errors interrupt enable
|
||||
* @arg @ref SMBUS_IT_TCI Transfer complete interrupt enable
|
||||
* @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable
|
||||
* @arg @ref SMBUS_IT_NACKI NACK received interrupt enable
|
||||
* @arg @ref SMBUS_IT_ADDRI Address match interrupt enable
|
||||
* @arg @ref SMBUS_IT_RXI RX interrupt enable
|
||||
* @arg @ref SMBUS_IT_TXI TX interrupt enable
|
||||
*
|
||||
* @retval The new state of __IT__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
||||
|
||||
/** @brief Check whether the specified SMBUS flag is set or not.
|
||||
* @param __HANDLE__ specifies the SMBUS Handle.
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref SMBUS_FLAG_TXE Transmit data register empty
|
||||
* @arg @ref SMBUS_FLAG_TXIS Transmit interrupt status
|
||||
* @arg @ref SMBUS_FLAG_RXNE Receive data register not empty
|
||||
* @arg @ref SMBUS_FLAG_ADDR Address matched (slave mode)
|
||||
* @arg @ref SMBUS_FLAG_AF NACK received flag
|
||||
* @arg @ref SMBUS_FLAG_STOPF STOP detection flag
|
||||
* @arg @ref SMBUS_FLAG_TC Transfer complete (master mode)
|
||||
* @arg @ref SMBUS_FLAG_TCR Transfer complete reload
|
||||
* @arg @ref SMBUS_FLAG_BERR Bus error
|
||||
* @arg @ref SMBUS_FLAG_ARLO Arbitration lost
|
||||
* @arg @ref SMBUS_FLAG_OVR Overrun/Underrun
|
||||
* @arg @ref SMBUS_FLAG_PECERR PEC error in reception
|
||||
* @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag
|
||||
* @arg @ref SMBUS_FLAG_ALERT SMBus alert
|
||||
* @arg @ref SMBUS_FLAG_BUSY Bus busy
|
||||
* @arg @ref SMBUS_FLAG_DIR Transfer direction (slave mode)
|
||||
*
|
||||
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
#define SMBUS_FLAG_MASK (0x0001FFFFU)
|
||||
#define __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)))
|
||||
|
||||
/** @brief Clear the SMBUS pending flags which are cleared by writing 1 in a specific bit.
|
||||
* @param __HANDLE__ specifies the SMBUS Handle.
|
||||
* @param __FLAG__ specifies the flag to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg @ref SMBUS_FLAG_ADDR Address matched (slave mode)
|
||||
* @arg @ref SMBUS_FLAG_AF NACK received flag
|
||||
* @arg @ref SMBUS_FLAG_STOPF STOP detection flag
|
||||
* @arg @ref SMBUS_FLAG_BERR Bus error
|
||||
* @arg @ref SMBUS_FLAG_ARLO Arbitration lost
|
||||
* @arg @ref SMBUS_FLAG_OVR Overrun/Underrun
|
||||
* @arg @ref SMBUS_FLAG_PECERR PEC error in reception
|
||||
* @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag
|
||||
* @arg @ref SMBUS_FLAG_ALERT SMBus alert
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
|
||||
|
||||
/** @brief Enable the specified SMBUS peripheral.
|
||||
* @param __HANDLE__ specifies the SMBUS Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SMBUS_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
|
||||
|
||||
/** @brief Disable the specified SMBUS peripheral.
|
||||
* @param __HANDLE__ specifies the SMBUS Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SMBUS_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
|
||||
|
||||
/** @brief Generate a Non-Acknowledge SMBUS peripheral in Slave mode.
|
||||
* @param __HANDLE__ specifies the SMBUS Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SMBUS_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup SMBUS_Private_Macro SMBUS Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_SMBUS_ANALOG_FILTER(FILTER) (((FILTER) == SMBUS_ANALOGFILTER_ENABLE) || \
|
||||
((FILTER) == SMBUS_ANALOGFILTER_DISABLE))
|
||||
|
||||
#define IS_SMBUS_ADDRESSING_MODE(MODE) (((MODE) == SMBUS_ADDRESSINGMODE_7BIT) || \
|
||||
((MODE) == SMBUS_ADDRESSINGMODE_10BIT))
|
||||
|
||||
#define IS_SMBUS_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == SMBUS_DUALADDRESS_DISABLE) || \
|
||||
((ADDRESS) == SMBUS_DUALADDRESS_ENABLE))
|
||||
|
||||
#define IS_SMBUS_OWN_ADDRESS2_MASK(MASK) (((MASK) == SMBUS_OA2_NOMASK) || \
|
||||
((MASK) == SMBUS_OA2_MASK01) || \
|
||||
((MASK) == SMBUS_OA2_MASK02) || \
|
||||
((MASK) == SMBUS_OA2_MASK03) || \
|
||||
((MASK) == SMBUS_OA2_MASK04) || \
|
||||
((MASK) == SMBUS_OA2_MASK05) || \
|
||||
((MASK) == SMBUS_OA2_MASK06) || \
|
||||
((MASK) == SMBUS_OA2_MASK07))
|
||||
|
||||
#define IS_SMBUS_GENERAL_CALL(CALL) (((CALL) == SMBUS_GENERALCALL_DISABLE) || \
|
||||
((CALL) == SMBUS_GENERALCALL_ENABLE))
|
||||
|
||||
#define IS_SMBUS_NO_STRETCH(STRETCH) (((STRETCH) == SMBUS_NOSTRETCH_DISABLE) || \
|
||||
((STRETCH) == SMBUS_NOSTRETCH_ENABLE))
|
||||
|
||||
#define IS_SMBUS_PEC(PEC) (((PEC) == SMBUS_PEC_DISABLE) || \
|
||||
((PEC) == SMBUS_PEC_ENABLE))
|
||||
|
||||
#define IS_SMBUS_PERIPHERAL_MODE(MODE) (((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_HOST) || \
|
||||
((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || \
|
||||
((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP))
|
||||
|
||||
#define IS_SMBUS_TRANSFER_MODE(MODE) (((MODE) == SMBUS_RELOAD_MODE) || \
|
||||
((MODE) == SMBUS_AUTOEND_MODE) || \
|
||||
((MODE) == SMBUS_SOFTEND_MODE) || \
|
||||
((MODE) == SMBUS_SENDPEC_MODE) || \
|
||||
((MODE) == (SMBUS_RELOAD_MODE | SMBUS_SENDPEC_MODE)) || \
|
||||
((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) || \
|
||||
((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE)) || \
|
||||
((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | SMBUS_RELOAD_MODE )))
|
||||
|
||||
|
||||
#define IS_SMBUS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == SMBUS_GENERATE_STOP) || \
|
||||
((REQUEST) == SMBUS_GENERATE_START_READ) || \
|
||||
((REQUEST) == SMBUS_GENERATE_START_WRITE) || \
|
||||
((REQUEST) == SMBUS_NO_STARTSTOP))
|
||||
|
||||
|
||||
#define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_FIRST_FRAME) || \
|
||||
((REQUEST) == SMBUS_NEXT_FRAME) || \
|
||||
((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \
|
||||
((REQUEST) == SMBUS_LAST_FRAME_NO_PEC) || \
|
||||
((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \
|
||||
((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC) || \
|
||||
IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST))
|
||||
|
||||
#define IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_OTHER_FRAME_NO_PEC) || \
|
||||
((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC) || \
|
||||
((REQUEST) == SMBUS_OTHER_FRAME_WITH_PEC) || \
|
||||
((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC))
|
||||
|
||||
#define SMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | I2C_CR1_PECEN)))
|
||||
#define SMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
|
||||
|
||||
#define SMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == SMBUS_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \
|
||||
(uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
|
||||
|
||||
#define SMBUS_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17U)
|
||||
#define SMBUS_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U)
|
||||
#define SMBUS_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
|
||||
#define SMBUS_GET_PEC_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE)
|
||||
#define SMBUS_GET_ALERT_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN)
|
||||
|
||||
#define SMBUS_GET_ISR_REG(__HANDLE__) ((__HANDLE__)->Instance->ISR)
|
||||
#define SMBUS_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)))
|
||||
|
||||
#define IS_SMBUS_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)
|
||||
#define IS_SMBUS_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup SMBUS_Exported_Functions SMBUS Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Initialization and de-initialization functions **********************************/
|
||||
HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus);
|
||||
HAL_StatusTypeDef HAL_SMBUS_DeInit (SMBUS_HandleTypeDef *hsmbus);
|
||||
void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus);
|
||||
void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup SMBUS_Exported_Functions_Group2 Input and Output operation functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* IO operation functions *****************************************************/
|
||||
/** @addtogroup Blocking_mode_Polling Blocking mode Polling
|
||||
* @{
|
||||
*/
|
||||
/******* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup Non-Blocking_mode_Interrupt Non-Blocking mode Interrupt
|
||||
* @{
|
||||
*/
|
||||
/******* Non-Blocking mode: Interrupt */
|
||||
HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress);
|
||||
HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
|
||||
|
||||
HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus);
|
||||
HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus);
|
||||
HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus);
|
||||
HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup SMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
|
||||
* @{
|
||||
*/
|
||||
/******* SMBUS IRQHandler and Callbacks used in non blocking modes (Interrupt) */
|
||||
void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus);
|
||||
void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus);
|
||||
void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
|
||||
void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
|
||||
void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
|
||||
void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
|
||||
void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode);
|
||||
void HAL_SMBUS_ListenCpltCallback(SMBUS_HandleTypeDef *hsmbus);
|
||||
void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Peripheral State and Errors functions **************************************************/
|
||||
uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus);
|
||||
uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private Functions ---------------------------------------------------------*/
|
||||
/** @defgroup SMBUS_Private_Functions SMBUS Private Functions
|
||||
* @{
|
||||
*/
|
||||
/* Private functions are defined in stm32f7xx_hal_smbus.c file */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* __STM32F7xx_HAL_SMBUS_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,560 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_hal_spdifrx.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.2
|
||||
* @date 14-April-2017
|
||||
* @brief Header file of SPDIFRX HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F7xx_HAL_SPDIFRX_H
|
||||
#define __STM32F7xx_HAL_SPDIFRX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx_hal_def.h"
|
||||
|
||||
#if defined (SPDIFRX)
|
||||
|
||||
/** @addtogroup STM32F7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup SPDIFRX
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup SPDIFRX_Exported_Types SPDIFRX Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief SPDIFRX Init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t InputSelection; /*!< Specifies the SPDIF input selection.
|
||||
This parameter can be a value of @ref SPDIFRX_Input_Selection */
|
||||
|
||||
uint32_t Retries; /*!< Specifies the Maximum allowed re-tries during synchronization phase.
|
||||
This parameter can be a value of @ref SPDIFRX_Max_Retries */
|
||||
|
||||
uint32_t WaitForActivity; /*!< Specifies the wait for activity on SPDIF selected input.
|
||||
This parameter can be a value of @ref SPDIFRX_Wait_For_Activity. */
|
||||
|
||||
uint32_t ChannelSelection; /*!< Specifies whether the control flow will take the channel status from channel A or B.
|
||||
This parameter can be a value of @ref SPDIFRX_Channel_Selection */
|
||||
|
||||
uint32_t DataFormat; /*!< Specifies the Data samples format (LSB, MSB, ...).
|
||||
This parameter can be a value of @ref SPDIFRX_Data_Format */
|
||||
|
||||
uint32_t StereoMode; /*!< Specifies whether the peripheral is in stereo or mono mode.
|
||||
This parameter can be a value of @ref SPDIFRX_Stereo_Mode */
|
||||
|
||||
uint32_t PreambleTypeMask; /*!< Specifies whether The preamble type bits are copied or not into the received frame.
|
||||
This parameter can be a value of @ref SPDIFRX_PT_Mask */
|
||||
|
||||
uint32_t ChannelStatusMask; /*!< Specifies whether the channel status and user bits are copied or not into the received frame.
|
||||
This parameter can be a value of @ref SPDIFRX_ChannelStatus_Mask */
|
||||
|
||||
uint32_t ValidityBitMask; /*!< Specifies whether the validity bit is copied or not into the received frame.
|
||||
This parameter can be a value of @ref SPDIFRX_V_Mask */
|
||||
|
||||
uint32_t ParityErrorMask; /*!< Specifies whether the parity error bit is copied or not into the received frame.
|
||||
This parameter can be a value of @ref SPDIFRX_PE_Mask */
|
||||
|
||||
}SPDIFRX_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief SPDIFRX SetDataFormat structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t DataFormat; /*!< Specifies the Data samples format (LSB, MSB, ...).
|
||||
This parameter can be a value of @ref SPDIFRX_Data_Format */
|
||||
|
||||
uint32_t StereoMode; /*!< Specifies whether the peripheral is in stereo or mono mode.
|
||||
This parameter can be a value of @ref SPDIFRX_Stereo_Mode */
|
||||
|
||||
uint32_t PreambleTypeMask; /*!< Specifies whether The preamble type bits are copied or not into the received frame.
|
||||
This parameter can be a value of @ref SPDIFRX_PT_Mask */
|
||||
|
||||
uint32_t ChannelStatusMask; /*!< Specifies whether the channel status and user bits are copied or not into the received frame.
|
||||
This parameter can be a value of @ref SPDIFRX_ChannelStatus_Mask */
|
||||
|
||||
uint32_t ValidityBitMask; /*!< Specifies whether the validity bit is copied or not into the received frame.
|
||||
This parameter can be a value of @ref SPDIFRX_V_Mask */
|
||||
|
||||
uint32_t ParityErrorMask; /*!< Specifies whether the parity error bit is copied or not into the received frame.
|
||||
This parameter can be a value of @ref SPDIFRX_PE_Mask */
|
||||
|
||||
}SPDIFRX_SetDataFormatTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL State structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_SPDIFRX_STATE_RESET = 0x00U, /*!< SPDIFRX not yet initialized or disabled */
|
||||
HAL_SPDIFRX_STATE_READY = 0x01U, /*!< SPDIFRX initialized and ready for use */
|
||||
HAL_SPDIFRX_STATE_BUSY = 0x02U, /*!< SPDIFRX internal process is ongoing */
|
||||
HAL_SPDIFRX_STATE_BUSY_RX = 0x03U, /*!< SPDIFRX internal Data Flow RX process is ongoing */
|
||||
HAL_SPDIFRX_STATE_BUSY_CX = 0x04U, /*!< SPDIFRX internal Control Flow RX process is ongoing */
|
||||
HAL_SPDIFRX_STATE_ERROR = 0x07U /*!< SPDIFRX error state */
|
||||
}HAL_SPDIFRX_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief SPDIFRX handle Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
SPDIFRX_TypeDef *Instance; /* SPDIFRX registers base address */
|
||||
|
||||
SPDIFRX_InitTypeDef Init; /* SPDIFRX communication parameters */
|
||||
|
||||
uint32_t *pRxBuffPtr; /* Pointer to SPDIFRX Rx transfer buffer */
|
||||
|
||||
uint32_t *pCsBuffPtr; /* Pointer to SPDIFRX Cx transfer buffer */
|
||||
|
||||
__IO uint16_t RxXferSize; /* SPDIFRX Rx transfer size */
|
||||
|
||||
__IO uint16_t RxXferCount; /* SPDIFRX Rx transfer counter
|
||||
(This field is initialized at the
|
||||
same value as transfer size at the
|
||||
beginning of the transfer and
|
||||
decremented when a sample is received.
|
||||
NbSamplesReceived = RxBufferSize-RxBufferCount) */
|
||||
|
||||
__IO uint16_t CsXferSize; /* SPDIFRX Rx transfer size */
|
||||
|
||||
__IO uint16_t CsXferCount; /* SPDIFRX Rx transfer counter
|
||||
(This field is initialized at the
|
||||
same value as transfer size at the
|
||||
beginning of the transfer and
|
||||
decremented when a sample is received.
|
||||
NbSamplesReceived = RxBufferSize-RxBufferCount) */
|
||||
|
||||
DMA_HandleTypeDef *hdmaCsRx; /* SPDIFRX EC60958_channel_status and user_information DMA handle parameters */
|
||||
|
||||
DMA_HandleTypeDef *hdmaDrRx; /* SPDIFRX Rx DMA handle parameters */
|
||||
|
||||
__IO HAL_LockTypeDef Lock; /* SPDIFRX locking object */
|
||||
|
||||
__IO HAL_SPDIFRX_StateTypeDef State; /* SPDIFRX communication state */
|
||||
|
||||
__IO uint32_t ErrorCode; /* SPDIFRX Error code */
|
||||
|
||||
}SPDIFRX_HandleTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup SPDIFRX_Exported_Constants SPDIFRX Exported Constants
|
||||
* @{
|
||||
*/
|
||||
/** @defgroup SPDIFRX_ErrorCode SPDIFRX Error Code
|
||||
* @{
|
||||
*/
|
||||
#define HAL_SPDIFRX_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
|
||||
#define HAL_SPDIFRX_ERROR_TIMEOUT ((uint32_t)0x00000001U) /*!< Timeout error */
|
||||
#define HAL_SPDIFRX_ERROR_OVR ((uint32_t)0x00000002U) /*!< OVR error */
|
||||
#define HAL_SPDIFRX_ERROR_PE ((uint32_t)0x00000004U) /*!< Parity error */
|
||||
#define HAL_SPDIFRX_ERROR_DMA ((uint32_t)0x00000008U) /*!< DMA transfer error */
|
||||
#define HAL_SPDIFRX_ERROR_UNKNOWN ((uint32_t)0x00000010U) /*!< Unknown Error error */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPDIFRX_Input_Selection SPDIFRX Input Selection
|
||||
* @{
|
||||
*/
|
||||
#define SPDIFRX_INPUT_IN0 ((uint32_t)0x00000000U)
|
||||
#define SPDIFRX_INPUT_IN1 ((uint32_t)0x00010000U)
|
||||
#define SPDIFRX_INPUT_IN2 ((uint32_t)0x00020000U)
|
||||
#define SPDIFRX_INPUT_IN3 ((uint32_t)0x00030000U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPDIFRX_Max_Retries SPDIFRX Maximum Retries
|
||||
* @{
|
||||
*/
|
||||
#define SPDIFRX_MAXRETRIES_NONE ((uint32_t)0x00000000U)
|
||||
#define SPDIFRX_MAXRETRIES_3 ((uint32_t)0x00001000U)
|
||||
#define SPDIFRX_MAXRETRIES_15 ((uint32_t)0x00002000U)
|
||||
#define SPDIFRX_MAXRETRIES_63 ((uint32_t)0x00003000U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPDIFRX_Wait_For_Activity SPDIFRX Wait For Activity
|
||||
* @{
|
||||
*/
|
||||
#define SPDIFRX_WAITFORACTIVITY_OFF ((uint32_t)0x00000000U)
|
||||
#define SPDIFRX_WAITFORACTIVITY_ON ((uint32_t)SPDIFRX_CR_WFA)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPDIFRX_PT_Mask SPDIFRX Preamble Type Mask
|
||||
* @{
|
||||
*/
|
||||
#define SPDIFRX_PREAMBLETYPEMASK_OFF ((uint32_t)0x00000000U)
|
||||
#define SPDIFRX_PREAMBLETYPEMASK_ON ((uint32_t)SPDIFRX_CR_PTMSK)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPDIFRX_ChannelStatus_Mask SPDIFRX Channel Status Mask
|
||||
* @{
|
||||
*/
|
||||
#define SPDIFRX_CHANNELSTATUS_OFF ((uint32_t)0x00000000U) /* The channel status and user bits are copied into the SPDIF_DR */
|
||||
#define SPDIFRX_CHANNELSTATUS_ON ((uint32_t)SPDIFRX_CR_CUMSK) /* The channel status and user bits are not copied into the SPDIF_DR, zeros are written instead*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPDIFRX_V_Mask SPDIFRX Validity Mask
|
||||
* @{
|
||||
*/
|
||||
#define SPDIFRX_VALIDITYMASK_OFF ((uint32_t)0x00000000U)
|
||||
#define SPDIFRX_VALIDITYMASK_ON ((uint32_t)SPDIFRX_CR_VMSK)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPDIFRX_PE_Mask SPDIFRX Parity Error Mask
|
||||
* @{
|
||||
*/
|
||||
#define SPDIFRX_PARITYERRORMASK_OFF ((uint32_t)0x00000000U)
|
||||
#define SPDIFRX_PARITYERRORMASK_ON ((uint32_t)SPDIFRX_CR_PMSK)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPDIFRX_Channel_Selection SPDIFRX Channel Selection
|
||||
* @{
|
||||
*/
|
||||
#define SPDIFRX_CHANNEL_A ((uint32_t)0x00000000U)
|
||||
#define SPDIFRX_CHANNEL_B ((uint32_t)SPDIFRX_CR_CHSEL)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPDIFRX_Data_Format SPDIFRX Data Format
|
||||
* @{
|
||||
*/
|
||||
#define SPDIFRX_DATAFORMAT_LSB ((uint32_t)0x00000000U)
|
||||
#define SPDIFRX_DATAFORMAT_MSB ((uint32_t)0x00000010U)
|
||||
#define SPDIFRX_DATAFORMAT_32BITS ((uint32_t)0x00000020U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPDIFRX_Stereo_Mode SPDIFRX Stereo Mode
|
||||
* @{
|
||||
*/
|
||||
#define SPDIFRX_STEREOMODE_DISABLE ((uint32_t)0x00000000U)
|
||||
#define SPDIFRX_STEREOMODE_ENABLE ((uint32_t)SPDIFRX_CR_RXSTEO)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPDIFRX_State SPDIFRX State
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPDIFRX_STATE_IDLE ((uint32_t)0xFFFFFFFCU)
|
||||
#define SPDIFRX_STATE_SYNC ((uint32_t)0x00000001U)
|
||||
#define SPDIFRX_STATE_RCV ((uint32_t)SPDIFRX_CR_SPDIFEN)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPDIFRX_Interrupts_Definition SPDIFRX Interrupts Definition
|
||||
* @{
|
||||
*/
|
||||
#define SPDIFRX_IT_RXNE ((uint32_t)SPDIFRX_IMR_RXNEIE)
|
||||
#define SPDIFRX_IT_CSRNE ((uint32_t)SPDIFRX_IMR_CSRNEIE)
|
||||
#define SPDIFRX_IT_PERRIE ((uint32_t)SPDIFRX_IMR_PERRIE)
|
||||
#define SPDIFRX_IT_OVRIE ((uint32_t)SPDIFRX_IMR_OVRIE)
|
||||
#define SPDIFRX_IT_SBLKIE ((uint32_t)SPDIFRX_IMR_SBLKIE)
|
||||
#define SPDIFRX_IT_SYNCDIE ((uint32_t)SPDIFRX_IMR_SYNCDIE)
|
||||
#define SPDIFRX_IT_IFEIE ((uint32_t)SPDIFRX_IMR_IFEIE )
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPDIFRX_Flags_Definition SPDIFRX Flags Definition
|
||||
* @{
|
||||
*/
|
||||
#define SPDIFRX_FLAG_RXNE ((uint32_t)SPDIFRX_SR_RXNE)
|
||||
#define SPDIFRX_FLAG_CSRNE ((uint32_t)SPDIFRX_SR_CSRNE)
|
||||
#define SPDIFRX_FLAG_PERR ((uint32_t)SPDIFRX_SR_PERR)
|
||||
#define SPDIFRX_FLAG_OVR ((uint32_t)SPDIFRX_SR_OVR)
|
||||
#define SPDIFRX_FLAG_SBD ((uint32_t)SPDIFRX_SR_SBD)
|
||||
#define SPDIFRX_FLAG_SYNCD ((uint32_t)SPDIFRX_SR_SYNCD)
|
||||
#define SPDIFRX_FLAG_FERR ((uint32_t)SPDIFRX_SR_FERR)
|
||||
#define SPDIFRX_FLAG_SERR ((uint32_t)SPDIFRX_SR_SERR)
|
||||
#define SPDIFRX_FLAG_TERR ((uint32_t)SPDIFRX_SR_TERR)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup SPDIFRX_Exported_macros SPDIFRX Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset SPDIFRX handle state
|
||||
* @param __HANDLE__: SPDIFRX handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SPDIFRX_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = (uint16_t)SPDIFRX_CR_SPDIFEN)
|
||||
|
||||
/** @brief Disable the specified SPDIFRX peripheral (IDLE State).
|
||||
* @param __HANDLE__: specifies the SPDIFRX Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SPDIFRX_IDLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= SPDIFRX_STATE_IDLE)
|
||||
|
||||
/** @brief Enable the specified SPDIFRX peripheral (SYNC State).
|
||||
* @param __HANDLE__: specifies the SPDIFRX Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SPDIFRX_SYNC(__HANDLE__) ((__HANDLE__)->Instance->CR |= SPDIFRX_STATE_SYNC)
|
||||
|
||||
|
||||
/** @brief Enable the specified SPDIFRX peripheral (RCV State).
|
||||
* @param __HANDLE__: specifies the SPDIFRX Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SPDIFRX_RCV(__HANDLE__) ((__HANDLE__)->Instance->CR |= SPDIFRX_STATE_RCV)
|
||||
|
||||
|
||||
/** @brief Enable or disable the specified SPDIFRX interrupts.
|
||||
* @param __HANDLE__: specifies the SPDIFRX Handle.
|
||||
* @param __INTERRUPT__: specifies the interrupt source to enable or disable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SPDIFRX_IT_RXNE
|
||||
* @arg SPDIFRX_IT_CSRNE
|
||||
* @arg SPDIFRX_IT_PERRIE
|
||||
* @arg SPDIFRX_IT_OVRIE
|
||||
* @arg SPDIFRX_IT_SBLKIE
|
||||
* @arg SPDIFRX_IT_SYNCDIE
|
||||
* @arg SPDIFRX_IT_IFEIE
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SPDIFRX_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR |= (__INTERRUPT__))
|
||||
#define __HAL_SPDIFRX_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR &= (uint16_t)(~(__INTERRUPT__)))
|
||||
|
||||
/** @brief Checks if the specified SPDIFRX interrupt source is enabled or disabled.
|
||||
* @param __HANDLE__: specifies the SPDIFRX Handle.
|
||||
* @param __INTERRUPT__: specifies the SPDIFRX interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SPDIFRX_IT_RXNE
|
||||
* @arg SPDIFRX_IT_CSRNE
|
||||
* @arg SPDIFRX_IT_PERRIE
|
||||
* @arg SPDIFRX_IT_OVRIE
|
||||
* @arg SPDIFRX_IT_SBLKIE
|
||||
* @arg SPDIFRX_IT_SYNCDIE
|
||||
* @arg SPDIFRX_IT_IFEIE
|
||||
* @retval The new state of __IT__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_SPDIFRX_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IMR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
||||
|
||||
/** @brief Checks whether the specified SPDIFRX flag is set or not.
|
||||
* @param __HANDLE__: specifies the SPDIFRX Handle.
|
||||
* @param __FLAG__: specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SPDIFRX_FLAG_RXNE
|
||||
* @arg SPDIFRX_FLAG_CSRNE
|
||||
* @arg SPDIFRX_FLAG_PERR
|
||||
* @arg SPDIFRX_FLAG_OVR
|
||||
* @arg SPDIFRX_FLAG_SBD
|
||||
* @arg SPDIFRX_FLAG_SYNCD
|
||||
* @arg SPDIFRX_FLAG_FERR
|
||||
* @arg SPDIFRX_FLAG_SERR
|
||||
* @arg SPDIFRX_FLAG_TERR
|
||||
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_SPDIFRX_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
|
||||
|
||||
/** @brief Clears the specified SPDIFRX SR flag, in setting the proper IFCR register bit.
|
||||
* @param __HANDLE__: specifies the USART Handle.
|
||||
* @param __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set
|
||||
* to clear the corresponding interrupt
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SPDIFRX_FLAG_PERR
|
||||
* @arg SPDIFRX_FLAG_OVR
|
||||
* @arg SPDIFRX_SR_SBD
|
||||
* @arg SPDIFRX_SR_SYNCD
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SPDIFRX_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->IFCR = (uint32_t)(__IT_CLEAR__))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup SPDIFRX_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup SPDIFRX_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Initialization/de-initialization functions **********************************/
|
||||
HAL_StatusTypeDef HAL_SPDIFRX_Init(SPDIFRX_HandleTypeDef *hspdif);
|
||||
HAL_StatusTypeDef HAL_SPDIFRX_DeInit (SPDIFRX_HandleTypeDef *hspdif);
|
||||
void HAL_SPDIFRX_MspInit(SPDIFRX_HandleTypeDef *hspdif);
|
||||
void HAL_SPDIFRX_MspDeInit(SPDIFRX_HandleTypeDef *hspdif);
|
||||
HAL_StatusTypeDef HAL_SPDIFRX_SetDataFormat(SPDIFRX_HandleTypeDef *hspdif, SPDIFRX_SetDataFormatTypeDef sDataFormat);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup SPDIFRX_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* I/O operation functions ***************************************************/
|
||||
/* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
|
||||
/* Non-Blocking mode: Interrupt */
|
||||
HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size);
|
||||
void HAL_SPDIFRX_IRQHandler(SPDIFRX_HandleTypeDef *hspdif);
|
||||
|
||||
/* Non-Blocking mode: DMA */
|
||||
HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size);
|
||||
|
||||
HAL_StatusTypeDef HAL_SPDIFRX_DMAStop(SPDIFRX_HandleTypeDef *hspdif);
|
||||
|
||||
/* Callbacks used in non blocking modes (Interrupt and DMA) *******************/
|
||||
void HAL_SPDIFRX_RxHalfCpltCallback(SPDIFRX_HandleTypeDef *hspdif);
|
||||
void HAL_SPDIFRX_RxCpltCallback(SPDIFRX_HandleTypeDef *hspdif);
|
||||
void HAL_SPDIFRX_ErrorCallback(SPDIFRX_HandleTypeDef *hspdif);
|
||||
void HAL_SPDIFRX_CxHalfCpltCallback(SPDIFRX_HandleTypeDef *hspdif);
|
||||
void HAL_SPDIFRX_CxCpltCallback(SPDIFRX_HandleTypeDef *hspdif);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup SPDIFRX_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral Control and State functions ************************************/
|
||||
HAL_SPDIFRX_StateTypeDef HAL_SPDIFRX_GetState(SPDIFRX_HandleTypeDef *hspdif);
|
||||
uint32_t HAL_SPDIFRX_GetError(SPDIFRX_HandleTypeDef *hspdif);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup SPDIFRX_Private_Macros SPDIFRX Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_SPDIFRX_INPUT_SELECT(INPUT) (((INPUT) == SPDIFRX_INPUT_IN1) || \
|
||||
((INPUT) == SPDIFRX_INPUT_IN2) || \
|
||||
((INPUT) == SPDIFRX_INPUT_IN3) || \
|
||||
((INPUT) == SPDIFRX_INPUT_IN0))
|
||||
#define IS_SPDIFRX_MAX_RETRIES(RET) (((RET) == SPDIFRX_MAXRETRIES_NONE) || \
|
||||
((RET) == SPDIFRX_MAXRETRIES_3) || \
|
||||
((RET) == SPDIFRX_MAXRETRIES_15) || \
|
||||
((RET) == SPDIFRX_MAXRETRIES_63))
|
||||
#define IS_SPDIFRX_WAIT_FOR_ACTIVITY(VAL) (((VAL) == SPDIFRX_WAITFORACTIVITY_ON) || \
|
||||
((VAL) == SPDIFRX_WAITFORACTIVITY_OFF))
|
||||
#define IS_PREAMBLE_TYPE_MASK(VAL) (((VAL) == SPDIFRX_PREAMBLETYPEMASK_ON) || \
|
||||
((VAL) == SPDIFRX_PREAMBLETYPEMASK_OFF))
|
||||
#define IS_VALIDITY_MASK(VAL) (((VAL) == SPDIFRX_VALIDITYMASK_OFF) || \
|
||||
((VAL) == SPDIFRX_VALIDITYMASK_ON))
|
||||
#define IS_PARITY_ERROR_MASK(VAL) (((VAL) == SPDIFRX_PARITYERRORMASK_OFF) || \
|
||||
((VAL) == SPDIFRX_PARITYERRORMASK_ON))
|
||||
#define IS_SPDIFRX_CHANNEL(CHANNEL) (((CHANNEL) == SPDIFRX_CHANNEL_A) || \
|
||||
((CHANNEL) == SPDIFRX_CHANNEL_B))
|
||||
#define IS_SPDIFRX_DATA_FORMAT(FORMAT) (((FORMAT) == SPDIFRX_DATAFORMAT_LSB) || \
|
||||
((FORMAT) == SPDIFRX_DATAFORMAT_MSB) || \
|
||||
((FORMAT) == SPDIFRX_DATAFORMAT_32BITS))
|
||||
#define IS_STEREO_MODE(MODE) (((MODE) == SPDIFRX_STEREOMODE_DISABLE) || \
|
||||
((MODE) == SPDIFRX_STEREOMODE_ENABLE))
|
||||
|
||||
#define IS_CHANNEL_STATUS_MASK(VAL) (((VAL) == SPDIFRX_CHANNELSTATUS_ON) || \
|
||||
((VAL) == SPDIFRX_CHANNELSTATUS_OFF))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup SPDIFRX_Private_Functions SPDIFRX Private Functions
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* SPDIFRX */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* __STM32F7xx_HAL_SPDIFRX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,689 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_hal_spi.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.2
|
||||
* @date 14-April-2017
|
||||
* @brief Header file of SPI HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F7xx_HAL_SPI_H
|
||||
#define __STM32F7xx_HAL_SPI_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup SPI
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup SPI_Exported_Types SPI Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief SPI Configuration Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Mode; /*!< Specifies the SPI operating mode.
|
||||
This parameter can be a value of @ref SPI_Mode */
|
||||
|
||||
uint32_t Direction; /*!< Specifies the SPI bidirectional mode state.
|
||||
This parameter can be a value of @ref SPI_Direction */
|
||||
|
||||
uint32_t DataSize; /*!< Specifies the SPI data size.
|
||||
This parameter can be a value of @ref SPI_Data_Size */
|
||||
|
||||
uint32_t CLKPolarity; /*!< Specifies the serial clock steady state.
|
||||
This parameter can be a value of @ref SPI_Clock_Polarity */
|
||||
|
||||
uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture.
|
||||
This parameter can be a value of @ref SPI_Clock_Phase */
|
||||
|
||||
uint32_t NSS; /*!< Specifies whether the NSS signal is managed by
|
||||
hardware (NSS pin) or by software using the SSI bit.
|
||||
This parameter can be a value of @ref SPI_Slave_Select_management */
|
||||
|
||||
uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
|
||||
used to configure the transmit and receive SCK clock.
|
||||
This parameter can be a value of @ref SPI_BaudRate_Prescaler
|
||||
@note The communication clock is derived from the master
|
||||
clock. The slave clock does not need to be set. */
|
||||
|
||||
uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
|
||||
This parameter can be a value of @ref SPI_MSB_LSB_transmission */
|
||||
|
||||
uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not.
|
||||
This parameter can be a value of @ref SPI_TI_mode */
|
||||
|
||||
uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
|
||||
This parameter can be a value of @ref SPI_CRC_Calculation */
|
||||
|
||||
uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation.
|
||||
This parameter must be an odd number between Min_Data = 0 and Max_Data = 65535 */
|
||||
|
||||
uint32_t CRCLength; /*!< Specifies the CRC Length used for the CRC calculation.
|
||||
CRC Length is only used with Data8 and Data16, not other data size
|
||||
This parameter can be a value of @ref SPI_CRC_length */
|
||||
|
||||
uint32_t NSSPMode; /*!< Specifies whether the NSSP signal is enabled or not .
|
||||
This parameter can be a value of @ref SPI_NSSP_Mode
|
||||
This mode is activated by the NSSP bit in the SPIx_CR2 register and
|
||||
it takes effect only if the SPI interface is configured as Motorola SPI
|
||||
master (FRF=0) with capture on the first edge (SPIx_CR1 CPHA = 0,
|
||||
CPOL setting is ignored).. */
|
||||
} SPI_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL SPI State structure definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_SPI_STATE_RESET = 0x00U, /*!< Peripheral not Initialized */
|
||||
HAL_SPI_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
|
||||
HAL_SPI_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */
|
||||
HAL_SPI_STATE_BUSY_TX = 0x03U, /*!< Data Transmission process is ongoing */
|
||||
HAL_SPI_STATE_BUSY_RX = 0x04U, /*!< Data Reception process is ongoing */
|
||||
HAL_SPI_STATE_BUSY_TX_RX = 0x05U, /*!< Data Transmission and Reception process is ongoing */
|
||||
HAL_SPI_STATE_ERROR = 0x06U, /*!< SPI error state */
|
||||
HAL_SPI_STATE_ABORT = 0x07U /*!< SPI abort is ongoing */
|
||||
} HAL_SPI_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief SPI handle Structure definition
|
||||
*/
|
||||
typedef struct __SPI_HandleTypeDef
|
||||
{
|
||||
SPI_TypeDef *Instance; /*!< SPI registers base address */
|
||||
|
||||
SPI_InitTypeDef Init; /*!< SPI communication parameters */
|
||||
|
||||
uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */
|
||||
|
||||
uint16_t TxXferSize; /*!< SPI Tx Transfer size */
|
||||
|
||||
__IO uint16_t TxXferCount; /*!< SPI Tx Transfer Counter */
|
||||
|
||||
uint8_t *pRxBuffPtr; /*!< Pointer to SPI Rx transfer Buffer */
|
||||
|
||||
uint16_t RxXferSize; /*!< SPI Rx Transfer size */
|
||||
|
||||
__IO uint16_t RxXferCount; /*!< SPI Rx Transfer Counter */
|
||||
|
||||
uint32_t CRCSize; /*!< SPI CRC size used for the transfer */
|
||||
|
||||
void (*RxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Rx ISR */
|
||||
|
||||
void (*TxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Tx ISR */
|
||||
|
||||
DMA_HandleTypeDef *hdmatx; /*!< SPI Tx DMA Handle parameters */
|
||||
|
||||
DMA_HandleTypeDef *hdmarx; /*!< SPI Rx DMA Handle parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< Locking object */
|
||||
|
||||
__IO HAL_SPI_StateTypeDef State; /*!< SPI communication state */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< SPI Error code */
|
||||
|
||||
} SPI_HandleTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup SPI_Exported_Constants SPI Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_Error_Code SPI Error Code
|
||||
* @{
|
||||
*/
|
||||
#define HAL_SPI_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
|
||||
#define HAL_SPI_ERROR_MODF ((uint32_t)0x00000001U) /*!< MODF error */
|
||||
#define HAL_SPI_ERROR_CRC ((uint32_t)0x00000002U) /*!< CRC error */
|
||||
#define HAL_SPI_ERROR_OVR ((uint32_t)0x00000004U) /*!< OVR error */
|
||||
#define HAL_SPI_ERROR_FRE ((uint32_t)0x00000008U) /*!< FRE error */
|
||||
#define HAL_SPI_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */
|
||||
#define HAL_SPI_ERROR_FLAG ((uint32_t)0x00000020U) /*!< Error on RXNE/TXE/BSY/FTLVL/FRLVL Flag */
|
||||
#define HAL_SPI_ERROR_ABORT ((uint32_t)0x00000040U) /*!< Error during SPI Abort procedure */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_Mode SPI Mode
|
||||
* @{
|
||||
*/
|
||||
#define SPI_MODE_SLAVE ((uint32_t)0x00000000U)
|
||||
#define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_Direction SPI Direction Mode
|
||||
* @{
|
||||
*/
|
||||
#define SPI_DIRECTION_2LINES ((uint32_t)0x00000000U)
|
||||
#define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY
|
||||
#define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_Data_Size SPI Data Size
|
||||
* @{
|
||||
*/
|
||||
#define SPI_DATASIZE_4BIT ((uint32_t)0x00000300U)
|
||||
#define SPI_DATASIZE_5BIT ((uint32_t)0x00000400U)
|
||||
#define SPI_DATASIZE_6BIT ((uint32_t)0x00000500U)
|
||||
#define SPI_DATASIZE_7BIT ((uint32_t)0x00000600U)
|
||||
#define SPI_DATASIZE_8BIT ((uint32_t)0x00000700U)
|
||||
#define SPI_DATASIZE_9BIT ((uint32_t)0x00000800U)
|
||||
#define SPI_DATASIZE_10BIT ((uint32_t)0x00000900U)
|
||||
#define SPI_DATASIZE_11BIT ((uint32_t)0x00000A00U)
|
||||
#define SPI_DATASIZE_12BIT ((uint32_t)0x00000B00U)
|
||||
#define SPI_DATASIZE_13BIT ((uint32_t)0x00000C00U)
|
||||
#define SPI_DATASIZE_14BIT ((uint32_t)0x00000D00U)
|
||||
#define SPI_DATASIZE_15BIT ((uint32_t)0x00000E00U)
|
||||
#define SPI_DATASIZE_16BIT ((uint32_t)0x00000F00U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_Clock_Polarity SPI Clock Polarity
|
||||
* @{
|
||||
*/
|
||||
#define SPI_POLARITY_LOW ((uint32_t)0x00000000U)
|
||||
#define SPI_POLARITY_HIGH SPI_CR1_CPOL
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_Clock_Phase SPI Clock Phase
|
||||
* @{
|
||||
*/
|
||||
#define SPI_PHASE_1EDGE ((uint32_t)0x00000000U)
|
||||
#define SPI_PHASE_2EDGE SPI_CR1_CPHA
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_Slave_Select_management SPI Slave Select Management
|
||||
* @{
|
||||
*/
|
||||
#define SPI_NSS_SOFT SPI_CR1_SSM
|
||||
#define SPI_NSS_HARD_INPUT ((uint32_t)0x00000000U)
|
||||
#define SPI_NSS_HARD_OUTPUT ((uint32_t)0x00040000U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_NSSP_Mode SPI NSS Pulse Mode
|
||||
* @{
|
||||
*/
|
||||
#define SPI_NSS_PULSE_ENABLE SPI_CR2_NSSP
|
||||
#define SPI_NSS_PULSE_DISABLE ((uint32_t)0x00000000U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler
|
||||
* @{
|
||||
*/
|
||||
#define SPI_BAUDRATEPRESCALER_2 ((uint32_t)0x00000000U)
|
||||
#define SPI_BAUDRATEPRESCALER_4 ((uint32_t)0x00000008U)
|
||||
#define SPI_BAUDRATEPRESCALER_8 ((uint32_t)0x00000010U)
|
||||
#define SPI_BAUDRATEPRESCALER_16 ((uint32_t)0x00000018U)
|
||||
#define SPI_BAUDRATEPRESCALER_32 ((uint32_t)0x00000020U)
|
||||
#define SPI_BAUDRATEPRESCALER_64 ((uint32_t)0x00000028U)
|
||||
#define SPI_BAUDRATEPRESCALER_128 ((uint32_t)0x00000030U)
|
||||
#define SPI_BAUDRATEPRESCALER_256 ((uint32_t)0x00000038U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB Transmission
|
||||
* @{
|
||||
*/
|
||||
#define SPI_FIRSTBIT_MSB ((uint32_t)0x00000000U)
|
||||
#define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_TI_mode SPI TI Mode
|
||||
* @{
|
||||
*/
|
||||
#define SPI_TIMODE_DISABLE ((uint32_t)0x00000000U)
|
||||
#define SPI_TIMODE_ENABLE SPI_CR2_FRF
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_CRC_Calculation SPI CRC Calculation
|
||||
* @{
|
||||
*/
|
||||
#define SPI_CRCCALCULATION_DISABLE ((uint32_t)0x00000000U)
|
||||
#define SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_CRC_length SPI CRC Length
|
||||
* @{
|
||||
* This parameter can be one of the following values:
|
||||
* SPI_CRC_LENGTH_DATASIZE: aligned with the data size
|
||||
* SPI_CRC_LENGTH_8BIT : CRC 8bit
|
||||
* SPI_CRC_LENGTH_16BIT : CRC 16bit
|
||||
*/
|
||||
#define SPI_CRC_LENGTH_DATASIZE ((uint32_t)0x00000000U)
|
||||
#define SPI_CRC_LENGTH_8BIT ((uint32_t)0x00000001U)
|
||||
#define SPI_CRC_LENGTH_16BIT ((uint32_t)0x00000002U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_FIFO_reception_threshold SPI FIFO Reception Threshold
|
||||
* @{
|
||||
* This parameter can be one of the following values:
|
||||
* SPI_RXFIFO_THRESHOLD or SPI_RXFIFO_THRESHOLD_QF :
|
||||
* RXNE event is generated if the FIFO
|
||||
* level is greater or equal to 1/2(16-bits).
|
||||
* SPI_RXFIFO_THRESHOLD_HF: RXNE event is generated if the FIFO
|
||||
* level is greater or equal to 1/4(8 bits). */
|
||||
#define SPI_RXFIFO_THRESHOLD SPI_CR2_FRXTH
|
||||
#define SPI_RXFIFO_THRESHOLD_QF SPI_CR2_FRXTH
|
||||
#define SPI_RXFIFO_THRESHOLD_HF ((uint32_t)0x00000000U)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_Interrupt_definition SPI Interrupt Definition
|
||||
* @{
|
||||
*/
|
||||
#define SPI_IT_TXE SPI_CR2_TXEIE
|
||||
#define SPI_IT_RXNE SPI_CR2_RXNEIE
|
||||
#define SPI_IT_ERR SPI_CR2_ERRIE
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_Flags_definition SPI Flags Definition
|
||||
* @{
|
||||
*/
|
||||
#define SPI_FLAG_RXNE SPI_SR_RXNE /* SPI status flag: Rx buffer not empty flag */
|
||||
#define SPI_FLAG_TXE SPI_SR_TXE /* SPI status flag: Tx buffer empty flag */
|
||||
#define SPI_FLAG_BSY SPI_SR_BSY /* SPI status flag: Busy flag */
|
||||
#define SPI_FLAG_CRCERR SPI_SR_CRCERR /* SPI Error flag: CRC error flag */
|
||||
#define SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */
|
||||
#define SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */
|
||||
#define SPI_FLAG_FRE SPI_SR_FRE /* SPI Error flag: TI mode frame format error flag */
|
||||
#define SPI_FLAG_FTLVL SPI_SR_FTLVL /* SPI fifo transmission level */
|
||||
#define SPI_FLAG_FRLVL SPI_SR_FRLVL /* SPI fifo reception level */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_transmission_fifo_status_level SPI Transmission FIFO Status Level
|
||||
* @{
|
||||
*/
|
||||
#define SPI_FTLVL_EMPTY ((uint32_t)0x00000000U)
|
||||
#define SPI_FTLVL_QUARTER_FULL ((uint32_t)0x00000800U)
|
||||
#define SPI_FTLVL_HALF_FULL ((uint32_t)0x00001000U)
|
||||
#define SPI_FTLVL_FULL ((uint32_t)0x00001800U)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_reception_fifo_status_level SPI Reception FIFO Status Level
|
||||
* @{
|
||||
*/
|
||||
#define SPI_FRLVL_EMPTY ((uint32_t)0x00000000U)
|
||||
#define SPI_FRLVL_QUARTER_FULL ((uint32_t)0x00000200U)
|
||||
#define SPI_FRLVL_HALF_FULL ((uint32_t)0x00000400U)
|
||||
#define SPI_FRLVL_FULL ((uint32_t)0x00000600U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup SPI_Exported_Macros SPI Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset SPI handle state.
|
||||
* @param __HANDLE__: specifies the SPI Handle.
|
||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
|
||||
|
||||
/** @brief Enable or disable the specified SPI interrupts.
|
||||
* @param __HANDLE__: specifies the SPI Handle.
|
||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
||||
* @param __INTERRUPT__: specifies the interrupt source to enable or disable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SPI_IT_TXE: Tx buffer empty interrupt enable
|
||||
* @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
|
||||
* @arg SPI_IT_ERR: Error interrupt enable
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
|
||||
#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__)))
|
||||
|
||||
/** @brief Check whether the specified SPI interrupt source is enabled or not.
|
||||
* @param __HANDLE__: specifies the SPI Handle.
|
||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
||||
* @param __INTERRUPT__: specifies the SPI interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SPI_IT_TXE: Tx buffer empty interrupt enable
|
||||
* @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
|
||||
* @arg SPI_IT_ERR: Error interrupt enable
|
||||
* @retval The new state of __IT__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
||||
|
||||
/** @brief Check whether the specified SPI flag is set or not.
|
||||
* @param __HANDLE__: specifies the SPI Handle.
|
||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
||||
* @param __FLAG__: specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SPI_FLAG_RXNE: Receive buffer not empty flag
|
||||
* @arg SPI_FLAG_TXE: Transmit buffer empty flag
|
||||
* @arg SPI_FLAG_CRCERR: CRC error flag
|
||||
* @arg SPI_FLAG_MODF: Mode fault flag
|
||||
* @arg SPI_FLAG_OVR: Overrun flag
|
||||
* @arg SPI_FLAG_BSY: Busy flag
|
||||
* @arg SPI_FLAG_FRE: Frame format error flag
|
||||
* @arg SPI_FLAG_FTLVL: SPI fifo transmission level
|
||||
* @arg SPI_FLAG_FRLVL: SPI fifo reception level
|
||||
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
|
||||
|
||||
/** @brief Clear the SPI CRCERR pending flag.
|
||||
* @param __HANDLE__: specifies the SPI Handle.
|
||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR))
|
||||
|
||||
/** @brief Clear the SPI MODF pending flag.
|
||||
* @param __HANDLE__: specifies the SPI Handle.
|
||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) \
|
||||
do{ \
|
||||
__IO uint32_t tmpreg_modf = 0x00U; \
|
||||
tmpreg_modf = (__HANDLE__)->Instance->SR; \
|
||||
(__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE); \
|
||||
UNUSED(tmpreg_modf); \
|
||||
} while(0)
|
||||
|
||||
/** @brief Clear the SPI OVR pending flag.
|
||||
* @param __HANDLE__: specifies the SPI Handle.
|
||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) \
|
||||
do{ \
|
||||
__IO uint32_t tmpreg_ovr = 0x00U; \
|
||||
tmpreg_ovr = (__HANDLE__)->Instance->DR; \
|
||||
tmpreg_ovr = (__HANDLE__)->Instance->SR; \
|
||||
UNUSED(tmpreg_ovr); \
|
||||
} while(0)
|
||||
|
||||
/** @brief Clear the SPI FRE pending flag.
|
||||
* @param __HANDLE__: specifies the SPI Handle.
|
||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) \
|
||||
do{ \
|
||||
__IO uint32_t tmpreg_fre = 0x00U; \
|
||||
tmpreg_fre = (__HANDLE__)->Instance->SR; \
|
||||
UNUSED(tmpreg_fre); \
|
||||
}while(0)
|
||||
|
||||
/** @brief Enable the SPI peripheral.
|
||||
* @param __HANDLE__: specifies the SPI Handle.
|
||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SPI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_SPE)
|
||||
|
||||
/** @brief Disable the SPI peripheral.
|
||||
* @param __HANDLE__: specifies the SPI Handle.
|
||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SPI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup SPI_Private_Macros SPI Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Set the SPI transmit-only mode.
|
||||
* @param __HANDLE__: specifies the SPI Handle.
|
||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
#define SPI_1LINE_TX(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_BIDIOE)
|
||||
|
||||
/** @brief Set the SPI receive-only mode.
|
||||
* @param __HANDLE__: specifies the SPI Handle.
|
||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
#define SPI_1LINE_RX(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_BIDIOE))
|
||||
|
||||
/** @brief Reset the CRC calculation of the SPI.
|
||||
* @param __HANDLE__: specifies the SPI Handle.
|
||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
#define SPI_RESET_CRC(__HANDLE__) do{(__HANDLE__)->Instance->CR1 &= (uint16_t)(~SPI_CR1_CRCEN);\
|
||||
(__HANDLE__)->Instance->CR1 |= SPI_CR1_CRCEN;}while(0)
|
||||
|
||||
#define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \
|
||||
((MODE) == SPI_MODE_MASTER))
|
||||
|
||||
#define IS_SPI_DIRECTION(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \
|
||||
((MODE) == SPI_DIRECTION_2LINES_RXONLY) || \
|
||||
((MODE) == SPI_DIRECTION_1LINE))
|
||||
|
||||
#define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES)
|
||||
|
||||
#define IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \
|
||||
((MODE) == SPI_DIRECTION_1LINE))
|
||||
|
||||
#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_16BIT) || \
|
||||
((DATASIZE) == SPI_DATASIZE_15BIT) || \
|
||||
((DATASIZE) == SPI_DATASIZE_14BIT) || \
|
||||
((DATASIZE) == SPI_DATASIZE_13BIT) || \
|
||||
((DATASIZE) == SPI_DATASIZE_12BIT) || \
|
||||
((DATASIZE) == SPI_DATASIZE_11BIT) || \
|
||||
((DATASIZE) == SPI_DATASIZE_10BIT) || \
|
||||
((DATASIZE) == SPI_DATASIZE_9BIT) || \
|
||||
((DATASIZE) == SPI_DATASIZE_8BIT) || \
|
||||
((DATASIZE) == SPI_DATASIZE_7BIT) || \
|
||||
((DATASIZE) == SPI_DATASIZE_6BIT) || \
|
||||
((DATASIZE) == SPI_DATASIZE_5BIT) || \
|
||||
((DATASIZE) == SPI_DATASIZE_4BIT))
|
||||
|
||||
#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || \
|
||||
((CPOL) == SPI_POLARITY_HIGH))
|
||||
|
||||
#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \
|
||||
((CPHA) == SPI_PHASE_2EDGE))
|
||||
|
||||
#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || \
|
||||
((NSS) == SPI_NSS_HARD_INPUT) || \
|
||||
((NSS) == SPI_NSS_HARD_OUTPUT))
|
||||
|
||||
#define IS_SPI_NSSP(NSSP) (((NSSP) == SPI_NSS_PULSE_ENABLE) || \
|
||||
((NSSP) == SPI_NSS_PULSE_DISABLE))
|
||||
|
||||
#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \
|
||||
((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \
|
||||
((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \
|
||||
((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \
|
||||
((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \
|
||||
((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \
|
||||
((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \
|
||||
((PRESCALER) == SPI_BAUDRATEPRESCALER_256))
|
||||
|
||||
#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \
|
||||
((BIT) == SPI_FIRSTBIT_LSB))
|
||||
|
||||
#define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLE) || \
|
||||
((MODE) == SPI_TIMODE_ENABLE))
|
||||
|
||||
#define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLE) || \
|
||||
((CALCULATION) == SPI_CRCCALCULATION_ENABLE))
|
||||
|
||||
#define IS_SPI_CRC_LENGTH(LENGTH) (((LENGTH) == SPI_CRC_LENGTH_DATASIZE) ||\
|
||||
((LENGTH) == SPI_CRC_LENGTH_8BIT) || \
|
||||
((LENGTH) == SPI_CRC_LENGTH_16BIT))
|
||||
|
||||
#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1) && ((POLYNOMIAL) <= 0xFFFFU) && (((POLYNOMIAL)&0x1U) != 0))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup SPI_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
/* Initialization/de-initialization functions ********************************/
|
||||
HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);
|
||||
HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi);
|
||||
void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);
|
||||
void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup SPI_Exported_Functions_Group2 IO operation functions
|
||||
* @{
|
||||
*/
|
||||
/* I/O operation functions ***************************************************/
|
||||
HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
|
||||
uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
|
||||
uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
|
||||
uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);
|
||||
HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);
|
||||
HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);
|
||||
/* Transfer Abort functions */
|
||||
HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi);
|
||||
HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi);
|
||||
|
||||
void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);
|
||||
void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);
|
||||
void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi);
|
||||
void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi);
|
||||
void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi);
|
||||
void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);
|
||||
void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi);
|
||||
void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);
|
||||
void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Peripheral State and Error functions ***************************************/
|
||||
HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);
|
||||
uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F7xx_HAL_SPI_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,195 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_hal_sram.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.2
|
||||
* @date 14-April-2017
|
||||
* @brief Header file of SRAM HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F7xx_HAL_SRAM_H
|
||||
#define __STM32F7xx_HAL_SRAM_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx_ll_fmc.h"
|
||||
|
||||
/** @addtogroup STM32F7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
/** @addtogroup SRAM
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported typedef ----------------------------------------------------------*/
|
||||
|
||||
/** @defgroup SRAM_Exported_Types SRAM Exported Types
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief HAL SRAM State structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_SRAM_STATE_RESET = 0x00U, /*!< SRAM not yet initialized or disabled */
|
||||
HAL_SRAM_STATE_READY = 0x01U, /*!< SRAM initialized and ready for use */
|
||||
HAL_SRAM_STATE_BUSY = 0x02U, /*!< SRAM internal process is ongoing */
|
||||
HAL_SRAM_STATE_ERROR = 0x03U, /*!< SRAM error state */
|
||||
HAL_SRAM_STATE_PROTECTED = 0x04U /*!< SRAM peripheral NORSRAM device write protected */
|
||||
|
||||
}HAL_SRAM_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief SRAM handle Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
FMC_NORSRAM_TypeDef *Instance; /*!< Register base address */
|
||||
|
||||
FMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */
|
||||
|
||||
FMC_NORSRAM_InitTypeDef Init; /*!< SRAM device control configuration parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< SRAM locking object */
|
||||
|
||||
__IO HAL_SRAM_StateTypeDef State; /*!< SRAM device access state */
|
||||
|
||||
DMA_HandleTypeDef *hdma; /*!< Pointer DMA handler */
|
||||
|
||||
}SRAM_HandleTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup SRAM_Exported_Macros SRAM Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset SRAM handle state
|
||||
* @param __HANDLE__: SRAM handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup SRAM_Exported_Functions SRAM Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Initialization/de-initialization functions ********************************/
|
||||
HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming);
|
||||
HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram);
|
||||
void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram);
|
||||
void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup SRAM_Exported_Functions_Group2 Input Output and memory control functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* I/O operation functions ***************************************************/
|
||||
HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize);
|
||||
HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize);
|
||||
HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize);
|
||||
HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize);
|
||||
HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
|
||||
HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
|
||||
HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
|
||||
HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
|
||||
|
||||
void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma);
|
||||
void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup SRAM_Exported_Functions_Group3 Control functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* SRAM Control functions ****************************************************/
|
||||
HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram);
|
||||
HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup SRAM_Exported_Functions_Group4 Peripheral State functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* SRAM State functions ******************************************************/
|
||||
HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F7xx_HAL_SRAM_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,648 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_hal_tim_ex.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.2
|
||||
* @date 14-April-2017
|
||||
* @brief Header file of TIM HAL Extension module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F7xx_HAL_TIM_EX_H
|
||||
#define __STM32F7xx_HAL_TIM_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup TIMEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup TIMEx_Exported_Types TIM Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief TIM Hall sensor Configuration Structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
|
||||
uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
|
||||
This parameter can be a value of @ref TIM_Input_Capture_Polarity */
|
||||
|
||||
uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
|
||||
This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
|
||||
|
||||
uint32_t IC1Filter; /*!< Specifies the input capture filter.
|
||||
This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
|
||||
uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
|
||||
This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
|
||||
} TIM_HallSensor_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief TIM Master configuration Structure definition
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection.
|
||||
This parameter can be a value of @ref TIM_Master_Mode_Selection */
|
||||
uint32_t MasterOutputTrigger2; /*!< Trigger output2 (TRGO2) selection
|
||||
This parameter can be a value of @ref TIMEx_Master_Mode_Selection_2 */
|
||||
uint32_t MasterSlaveMode; /*!< Master/slave mode selection.
|
||||
This parameter can be a value of @ref TIM_Master_Slave_Mode */
|
||||
}TIM_MasterConfigTypeDef;
|
||||
|
||||
/**
|
||||
* @brief TIM Break input(s) and Dead time configuration Structure definition
|
||||
* @note 2 break inputs can be configured (BKIN and BKIN2) with configurable
|
||||
* filter and polarity.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t OffStateRunMode; /*!< TIM off state in run mode.
|
||||
This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
|
||||
uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode.
|
||||
This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
|
||||
uint32_t LockLevel; /*!< TIM Lock level.
|
||||
This parameter can be a value of @ref TIM_Lock_level */
|
||||
uint32_t DeadTime; /*!< TIM dead Time.
|
||||
This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
|
||||
uint32_t BreakState; /*!< TIM Break State.
|
||||
This parameter can be a value of @ref TIM_Break_Input_enable_disable */
|
||||
uint32_t BreakPolarity; /*!< TIM Break input polarity.
|
||||
This parameter can be a value of @ref TIM_Break_Polarity */
|
||||
uint32_t BreakFilter; /*!< Specifies the break input filter.
|
||||
This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
|
||||
uint32_t Break2State; /*!< TIM Break2 State
|
||||
This parameter can be a value of @ref TIMEx_Break2_Input_enable_disable */
|
||||
uint32_t Break2Polarity; /*!< TIM Break2 input polarity
|
||||
This parameter can be a value of @ref TIMEx_Break2_Polarity */
|
||||
uint32_t Break2Filter; /*!< TIM break2 input filter.
|
||||
This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
|
||||
uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state
|
||||
This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
|
||||
} TIM_BreakDeadTimeConfigTypeDef;
|
||||
|
||||
#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)
|
||||
/**
|
||||
* @brief TIM Break/Break2 input configuration
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t Source; /*!< Specifies the source of the timer break input.
|
||||
This parameter can be a value of @ref TIMEx_Break_Input_Source */
|
||||
uint32_t Enable; /*!< Specifies whether or not the break input source is enabled.
|
||||
This parameter can be a value of @ref TIMEx_Break_Input_Source_Enable */
|
||||
} TIMEx_BreakInputConfigTypeDef;
|
||||
#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup TIMEx_Exported_Constants TIMEx Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup TIMEx_Channel TIMEx Channel
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define TIM_CHANNEL_1 ((uint32_t)0x0000U)
|
||||
#define TIM_CHANNEL_2 ((uint32_t)0x0004U)
|
||||
#define TIM_CHANNEL_3 ((uint32_t)0x0008U)
|
||||
#define TIM_CHANNEL_4 ((uint32_t)0x000CU)
|
||||
#define TIM_CHANNEL_5 ((uint32_t)0x0010U)
|
||||
#define TIM_CHANNEL_6 ((uint32_t)0x0014U)
|
||||
#define TIM_CHANNEL_ALL ((uint32_t)0x003CU)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIMEx_Output_Compare_and_PWM_modes TIMEx Output Compare and PWM Modes
|
||||
* @{
|
||||
*/
|
||||
#define TIM_OCMODE_TIMING ((uint32_t)0x0000U)
|
||||
#define TIM_OCMODE_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_0)
|
||||
#define TIM_OCMODE_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_1)
|
||||
#define TIM_OCMODE_TOGGLE ((uint32_t)TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
|
||||
#define TIM_OCMODE_PWM1 ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)
|
||||
#define TIM_OCMODE_PWM2 ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
|
||||
#define TIM_OCMODE_FORCED_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)
|
||||
#define TIM_OCMODE_FORCED_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_2)
|
||||
|
||||
#define TIM_OCMODE_RETRIGERRABLE_OPM1 ((uint32_t)TIM_CCMR1_OC1M_3)
|
||||
#define TIM_OCMODE_RETRIGERRABLE_OPM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)
|
||||
#define TIM_OCMODE_COMBINED_PWM1 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)
|
||||
#define TIM_OCMODE_COMBINED_PWM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
|
||||
#define TIM_OCMODE_ASSYMETRIC_PWM1 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)
|
||||
#define TIM_OCMODE_ASSYMETRIC_PWM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIMEx_Remap TIMEx Remap
|
||||
* @{
|
||||
*/
|
||||
#define TIM_TIM2_TIM8_TRGO (0x00000000U)
|
||||
#define TIM_TIM2_ETH_PTP (0x00000400U)
|
||||
#define TIM_TIM2_USBFS_SOF (0x00000800U)
|
||||
#define TIM_TIM2_USBHS_SOF (0x00000C00U)
|
||||
#define TIM_TIM5_GPIO (0x00000000U)
|
||||
#define TIM_TIM5_LSI (0x00000040U)
|
||||
#define TIM_TIM5_LSE (0x00000080U)
|
||||
#define TIM_TIM5_RTC (0x000000C0U)
|
||||
#define TIM_TIM11_GPIO (0x00000000U)
|
||||
#define TIM_TIM11_SPDIFRX (0x00000001U)
|
||||
#define TIM_TIM11_HSE (0x00000002U)
|
||||
#define TIM_TIM11_MCO1 (0x00000003U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIMEx_ClearInput_Source TIMEx Clear Input Source
|
||||
* @{
|
||||
*/
|
||||
#define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001U)
|
||||
#define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIMEx_Break2_Input_enable_disable TIMEx Break input 2 Enable
|
||||
* @{
|
||||
*/
|
||||
#define TIM_BREAK2_DISABLE ((uint32_t)0x00000000U)
|
||||
#define TIM_BREAK2_ENABLE ((uint32_t)TIM_BDTR_BK2E)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIMEx_Break2_Polarity TIMEx Break2 Polarity
|
||||
* @{
|
||||
*/
|
||||
#define TIM_BREAK2POLARITY_LOW ((uint32_t)0x00000000U)
|
||||
#define TIM_BREAK2POLARITY_HIGH (TIM_BDTR_BK2P)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIMEx_Group_Channel5 TIMEx Group Channel 5 and Channel 1, 2 or 3
|
||||
* @{
|
||||
*/
|
||||
#define TIM_GROUPCH5_NONE ((uint32_t)0x00000000U) /* !< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
|
||||
#define TIM_GROUPCH5_OC1REFC (TIM_CCR5_GC5C1) /* !< OC1REFC is the logical AND of OC1REFC and OC5REF */
|
||||
#define TIM_GROUPCH5_OC2REFC (TIM_CCR5_GC5C2) /* !< OC2REFC is the logical AND of OC2REFC and OC5REF */
|
||||
#define TIM_GROUPCH5_OC3REFC (TIM_CCR5_GC5C3) /* !< OC3REFC is the logical AND of OC3REFC and OC5REF */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIMEx_Master_Mode_Selection_2 TIMEx Master Mode Selection 2 (TRGO2)
|
||||
* @{
|
||||
*/
|
||||
#define TIM_TRGO2_RESET ((uint32_t)0x00000000U)
|
||||
#define TIM_TRGO2_ENABLE ((uint32_t)(TIM_CR2_MMS2_0))
|
||||
#define TIM_TRGO2_UPDATE ((uint32_t)(TIM_CR2_MMS2_1))
|
||||
#define TIM_TRGO2_OC1 ((uint32_t)(TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
|
||||
#define TIM_TRGO2_OC1REF ((uint32_t)(TIM_CR2_MMS2_2))
|
||||
#define TIM_TRGO2_OC2REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0))
|
||||
#define TIM_TRGO2_OC3REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1))
|
||||
#define TIM_TRGO2_OC4REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
|
||||
#define TIM_TRGO2_OC5REF ((uint32_t)(TIM_CR2_MMS2_3))
|
||||
#define TIM_TRGO2_OC6REF ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0))
|
||||
#define TIM_TRGO2_OC4REF_RISINGFALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1))
|
||||
#define TIM_TRGO2_OC6REF_RISINGFALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
|
||||
#define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2))
|
||||
#define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0))
|
||||
#define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1))
|
||||
#define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIMEx_Slave_Mode TIMEx Slave mode
|
||||
* @{
|
||||
*/
|
||||
#define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000U)
|
||||
#define TIM_SLAVEMODE_RESET ((uint32_t)(TIM_SMCR_SMS_2))
|
||||
#define TIM_SLAVEMODE_GATED ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0))
|
||||
#define TIM_SLAVEMODE_TRIGGER ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1))
|
||||
#define TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0))
|
||||
#define TIM_SLAVEMODE_COMBINED_RESETTRIGGER ((uint32_t)(TIM_SMCR_SMS_3))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#if defined(STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)
|
||||
/** @defgroup TIMEx_Break_Input TIM Extended Break input
|
||||
* @{
|
||||
*/
|
||||
#define TIM_BREAKINPUT_BRK ((uint32_t)0x00000001U) /* !< Timer break input */
|
||||
#define TIM_BREAKINPUT_BRK2 ((uint32_t)0x00000002U) /* !< Timer break2 input */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIMEx_Break_Input_Source TIM Extended Break input source
|
||||
* @{
|
||||
*/
|
||||
#define TIM_BREAKINPUTSOURCE_BKIN ((uint32_t)0x00000001U) /* !< An external source (GPIO) is connected to the BKIN pin */
|
||||
#define TIM_BREAKINPUTSOURCE_DFSDM1 ((uint32_t)0x00000008U) /* !< The analog watchdog output of the DFSDM1 peripheral is connected to the break input */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIMEx_Break_Input_Source_Enable TIM Extended Break input source enabling
|
||||
* @{
|
||||
*/
|
||||
#define TIM_BREAKINPUTSOURCE_DISABLE ((uint32_t)0x00000000U) /* !< Break input source is disabled */
|
||||
#define TIM_BREAKINPUTSOURCE_ENABLE ((uint32_t)0x00000001U) /* !< Break input source is enabled */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup TIMEx_Exported_Macros TIMEx Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Sets the TIM Capture Compare Register value on runtime without
|
||||
* calling another time ConfigChannel function.
|
||||
* @param __HANDLE__: TIM handle.
|
||||
* @param __CHANNEL__ : TIM Channels to be configured.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
||||
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
||||
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
|
||||
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
|
||||
* @arg TIM_CHANNEL_5: TIM Channel 5 selected
|
||||
* @arg TIM_CHANNEL_6: TIM Channel 6 selected
|
||||
* @param __COMPARE__: specifies the Capture Compare register new value.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
|
||||
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\
|
||||
((__HANDLE__)->Instance->CCR6 = (__COMPARE__)))
|
||||
|
||||
/**
|
||||
* @brief Gets the TIM Capture Compare Register value on runtime
|
||||
* @param __HANDLE__: TIM handle.
|
||||
* @param __CHANNEL__ : TIM Channel associated with the capture compare register
|
||||
* This parameter can be one of the following values:
|
||||
* @arg TIM_CHANNEL_1: get capture/compare 1 register value
|
||||
* @arg TIM_CHANNEL_2: get capture/compare 2 register value
|
||||
* @arg TIM_CHANNEL_3: get capture/compare 3 register value
|
||||
* @arg TIM_CHANNEL_4: get capture/compare 4 register value
|
||||
* @arg TIM_CHANNEL_5: get capture/compare 5 register value
|
||||
* @arg TIM_CHANNEL_6: get capture/compare 6 register value
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
|
||||
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\
|
||||
((__HANDLE__)->Instance->CCR6))
|
||||
|
||||
/**
|
||||
* @brief Sets the TIM Output compare preload.
|
||||
* @param __HANDLE__: TIM handle.
|
||||
* @param __CHANNEL__: TIM Channels to be configured.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
||||
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
||||
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
|
||||
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
|
||||
* @arg TIM_CHANNEL_5: TIM Channel 5 selected
|
||||
* @arg TIM_CHANNEL_6: TIM Channel 6 selected
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
|
||||
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE) :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5PE) :\
|
||||
((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6PE))
|
||||
|
||||
/**
|
||||
* @brief Resets the TIM Output compare preload.
|
||||
* @param __HANDLE__: TIM handle.
|
||||
* @param __CHANNEL__: TIM Channels to be configured.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
||||
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
||||
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
|
||||
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
|
||||
* @arg TIM_CHANNEL_5: TIM Channel 5 selected
|
||||
* @arg TIM_CHANNEL_6: TIM Channel 6 selected
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
|
||||
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC1PE) :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC2PE) :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC3PE) :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC4PE) :\
|
||||
((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= (uint16_t)~TIM_CCMR3_OC5PE) :\
|
||||
((__HANDLE__)->Instance->CCMR3 &= (uint16_t)~TIM_CCMR3_OC6PE))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup TIMEx_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup TIMEx_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Timer Hall Sensor functions **********************************************/
|
||||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef* htim, TIM_HallSensor_InitTypeDef* sConfig);
|
||||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef* htim);
|
||||
|
||||
void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef* htim);
|
||||
void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef* htim);
|
||||
|
||||
/* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef* htim);
|
||||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef* htim);
|
||||
/* Non-Blocking mode: Interrupt */
|
||||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef* htim);
|
||||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef* htim);
|
||||
/* Non-Blocking mode: DMA */
|
||||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef* htim, uint32_t *pData, uint16_t Length);
|
||||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef* htim);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup TIMEx_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* Timer Complementary Output Compare functions *****************************/
|
||||
/* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef* htim, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef* htim, uint32_t Channel);
|
||||
|
||||
/* Non-Blocking mode: Interrupt */
|
||||
HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef* htim, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef* htim, uint32_t Channel);
|
||||
|
||||
/* Non-Blocking mode: DMA */
|
||||
HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef* htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
|
||||
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef* htim, uint32_t Channel);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup TIMEx_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
/* Timer Complementary PWM functions ****************************************/
|
||||
/* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef* htim, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef* htim, uint32_t Channel);
|
||||
|
||||
/* Non-Blocking mode: Interrupt */
|
||||
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef* htim, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef* htim, uint32_t Channel);
|
||||
/* Non-Blocking mode: DMA */
|
||||
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef* htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
|
||||
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef* htim, uint32_t Channel);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup TIMEx_Exported_Functions_Group4
|
||||
* @{
|
||||
*/
|
||||
/* Timer Complementary One Pulse functions **********************************/
|
||||
/* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef* htim, uint32_t OutputChannel);
|
||||
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef* htim, uint32_t OutputChannel);
|
||||
|
||||
/* Non-Blocking mode: Interrupt */
|
||||
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef* htim, uint32_t OutputChannel);
|
||||
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef* htim, uint32_t OutputChannel);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup TIMEx_Exported_Functions_Group5
|
||||
* @{
|
||||
*/
|
||||
/* Extension Control functions ************************************************/
|
||||
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef* htim, uint32_t InputTrigger, uint32_t CommutationSource);
|
||||
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef* htim, uint32_t InputTrigger, uint32_t CommutationSource);
|
||||
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef* htim, uint32_t InputTrigger, uint32_t CommutationSource);
|
||||
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef* htim, TIM_MasterConfigTypeDef * sMasterConfig);
|
||||
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef* htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
|
||||
#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)
|
||||
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput, TIMEx_BreakInputConfigTypeDef *sBreakInputConfig);
|
||||
#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
|
||||
HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef* htim, uint32_t Remap);
|
||||
HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t OCRef);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup TIMEx_Exported_Functions_Group6
|
||||
* @{
|
||||
*/
|
||||
/* Extension Callback *********************************************************/
|
||||
void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef* htim);
|
||||
void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef* htim);
|
||||
void HAL_TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup TIMEx_Exported_Functions_Group7
|
||||
* @{
|
||||
*/
|
||||
/* Extension Peripheral State functions **************************************/
|
||||
HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef* htim);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup TIMEx_Private_Macros TIMEx Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
|
||||
((CHANNEL) == TIM_CHANNEL_2) || \
|
||||
((CHANNEL) == TIM_CHANNEL_3) || \
|
||||
((CHANNEL) == TIM_CHANNEL_4) || \
|
||||
((CHANNEL) == TIM_CHANNEL_5) || \
|
||||
((CHANNEL) == TIM_CHANNEL_6) || \
|
||||
((CHANNEL) == TIM_CHANNEL_ALL))
|
||||
|
||||
#define IS_TIM_PWMI_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
|
||||
((CHANNEL) == TIM_CHANNEL_2))
|
||||
|
||||
#define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
|
||||
((CHANNEL) == TIM_CHANNEL_2))
|
||||
|
||||
#define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
|
||||
((CHANNEL) == TIM_CHANNEL_2) || \
|
||||
((CHANNEL) == TIM_CHANNEL_3))
|
||||
#define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || \
|
||||
((MODE) == TIM_OCMODE_PWM2) || \
|
||||
((MODE) == TIM_OCMODE_COMBINED_PWM1) || \
|
||||
((MODE) == TIM_OCMODE_COMBINED_PWM2) || \
|
||||
((MODE) == TIM_OCMODE_ASSYMETRIC_PWM1) || \
|
||||
((MODE) == TIM_OCMODE_ASSYMETRIC_PWM2))
|
||||
|
||||
#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) || \
|
||||
((MODE) == TIM_OCMODE_ACTIVE) || \
|
||||
((MODE) == TIM_OCMODE_INACTIVE) || \
|
||||
((MODE) == TIM_OCMODE_TOGGLE) || \
|
||||
((MODE) == TIM_OCMODE_FORCED_ACTIVE) || \
|
||||
((MODE) == TIM_OCMODE_FORCED_INACTIVE) || \
|
||||
((MODE) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \
|
||||
((MODE) == TIM_OCMODE_RETRIGERRABLE_OPM2))
|
||||
#define IS_TIM_REMAP(__TIM_REMAP__) (((__TIM_REMAP__) == TIM_TIM2_TIM8_TRGO)||\
|
||||
((__TIM_REMAP__) == TIM_TIM2_ETH_PTP)||\
|
||||
((__TIM_REMAP__) == TIM_TIM2_USBFS_SOF)||\
|
||||
((__TIM_REMAP__) == TIM_TIM2_USBHS_SOF)||\
|
||||
((__TIM_REMAP__) == TIM_TIM5_GPIO)||\
|
||||
((__TIM_REMAP__) == TIM_TIM5_LSI)||\
|
||||
((__TIM_REMAP__) == TIM_TIM5_LSE)||\
|
||||
((__TIM_REMAP__) == TIM_TIM5_RTC)||\
|
||||
((__TIM_REMAP__) == TIM_TIM11_GPIO)||\
|
||||
((__TIM_REMAP__) == TIM_TIM11_SPDIFRX)||\
|
||||
((__TIM_REMAP__) == TIM_TIM11_HSE)||\
|
||||
((__TIM_REMAP__) == TIM_TIM11_MCO1))
|
||||
#define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFF)
|
||||
#define IS_TIM_BREAK_FILTER(__FILTER__) ((__FILTER__) <= 0xF)
|
||||
#define IS_TIM_CLEARINPUT_SOURCE(MODE) (((MODE) == TIM_CLEARINPUTSOURCE_ETR) || \
|
||||
((MODE) == TIM_CLEARINPUTSOURCE_NONE))
|
||||
#define IS_TIM_BREAK2_STATE(STATE) (((STATE) == TIM_BREAK2_ENABLE) || \
|
||||
((STATE) == TIM_BREAK2_DISABLE))
|
||||
#define IS_TIM_BREAK2_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAK2POLARITY_LOW) || \
|
||||
((__POLARITY__) == TIM_BREAK2POLARITY_HIGH))
|
||||
#define IS_TIM_GROUPCH5(OCREF) ((((OCREF) & 0x1FFFFFFF) == 0x00000000))
|
||||
#define IS_TIM_TRGO2_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO2_RESET) || \
|
||||
((SOURCE) == TIM_TRGO2_ENABLE) || \
|
||||
((SOURCE) == TIM_TRGO2_UPDATE) || \
|
||||
((SOURCE) == TIM_TRGO2_OC1) || \
|
||||
((SOURCE) == TIM_TRGO2_OC1REF) || \
|
||||
((SOURCE) == TIM_TRGO2_OC2REF) || \
|
||||
((SOURCE) == TIM_TRGO2_OC3REF) || \
|
||||
((SOURCE) == TIM_TRGO2_OC3REF) || \
|
||||
((SOURCE) == TIM_TRGO2_OC4REF) || \
|
||||
((SOURCE) == TIM_TRGO2_OC5REF) || \
|
||||
((SOURCE) == TIM_TRGO2_OC6REF) || \
|
||||
((SOURCE) == TIM_TRGO2_OC4REF_RISINGFALLING) || \
|
||||
((SOURCE) == TIM_TRGO2_OC6REF_RISINGFALLING) || \
|
||||
((SOURCE) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING) || \
|
||||
((SOURCE) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \
|
||||
((SOURCE) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING) || \
|
||||
((SOURCE) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING))
|
||||
#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) || \
|
||||
((MODE) == TIM_SLAVEMODE_RESET) || \
|
||||
((MODE) == TIM_SLAVEMODE_GATED) || \
|
||||
((MODE) == TIM_SLAVEMODE_TRIGGER) || \
|
||||
((MODE) == TIM_SLAVEMODE_EXTERNAL1) || \
|
||||
((MODE) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))
|
||||
|
||||
#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)
|
||||
#define IS_TIM_BREAKINPUT(__BREAKINPUT__) (((__BREAKINPUT__) == TIM_BREAKINPUT_BRK) || \
|
||||
((__BREAKINPUT__) == TIM_BREAKINPUT_BRK2))
|
||||
|
||||
#define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN) || \
|
||||
((__SOURCE__) == TIM_BREAKINPUTSOURCE_DFSDM))
|
||||
|
||||
#define IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__) (((__STATE__) == TIM_BREAKINPUTSOURCE_DISABLE) || \
|
||||
((__STATE__) == TIM_BREAKINPUTSOURCE_ENABLE))
|
||||
|
||||
#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup TIMEx_Private_Functions TIMEx Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F7xx_HAL_TIM_EX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,365 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_hal_uart_ex.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.2
|
||||
* @date 14-April-2017
|
||||
* @brief Header file of UART HAL Extension module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F7xx_HAL_UART_EX_H
|
||||
#define __STM32F7xx_HAL_UART_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup UARTEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup UARTEx_Exported_Constants UARTEx Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup UARTEx_Word_Length UARTEx Word Length
|
||||
* @{
|
||||
*/
|
||||
#define UART_WORDLENGTH_7B ((uint32_t)USART_CR1_M_1)
|
||||
#define UART_WORDLENGTH_8B ((uint32_t)0x0000U)
|
||||
#define UART_WORDLENGTH_9B ((uint32_t)USART_CR1_M_0)
|
||||
#define IS_UART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == UART_WORDLENGTH_7B) || \
|
||||
((__LENGTH__) == UART_WORDLENGTH_8B) || \
|
||||
((__LENGTH__) == UART_WORDLENGTH_9B))
|
||||
#define IS_LIN_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WORDLENGTH_8B))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup UARTEx_WakeUp_Address_Length UARTEx WakeUp Address Length
|
||||
* @{
|
||||
*/
|
||||
#define UART_ADDRESS_DETECT_4B ((uint32_t)0x00000000U)
|
||||
#define UART_ADDRESS_DETECT_7B ((uint32_t)USART_CR2_ADDM7)
|
||||
#define IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__) (((__ADDRESS__) == UART_ADDRESS_DETECT_4B) || \
|
||||
((__ADDRESS__) == UART_ADDRESS_DETECT_7B))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup UARTEx_Exported_Macros UARTEx Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reports the UART clock source.
|
||||
* @param __HANDLE__: specifies the UART Handle
|
||||
* @param __CLOCKSOURCE__: output variable
|
||||
* @retval UART clocking source, written in __CLOCKSOURCE__.
|
||||
*/
|
||||
#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
|
||||
do { \
|
||||
if((__HANDLE__)->Instance == USART1) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART1_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART1CLKSOURCE_PCLK2: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART2) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART2_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART2CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART3) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART3_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART3CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART3CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART3CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART3CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == UART4) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_UART4_SOURCE()) \
|
||||
{ \
|
||||
case RCC_UART4CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_UART4CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_UART4CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_UART4CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if ((__HANDLE__)->Instance == UART5) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_UART5_SOURCE()) \
|
||||
{ \
|
||||
case RCC_UART5CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_UART5CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_UART5CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_UART5CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART6) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART6_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART6CLKSOURCE_PCLK2: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2; \
|
||||
break; \
|
||||
case RCC_USART6CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART6CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART6CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if ((__HANDLE__)->Instance == UART7) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_UART7_SOURCE()) \
|
||||
{ \
|
||||
case RCC_UART7CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_UART7CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_UART7CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_UART7CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if ((__HANDLE__)->Instance == UART8) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_UART8_SOURCE()) \
|
||||
{ \
|
||||
case RCC_UART8CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_UART8CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_UART8CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_UART8CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
} while(0)
|
||||
|
||||
/** @brief Reports the UART mask to apply to retrieve the received data
|
||||
* according to the word length and to the parity bits activation.
|
||||
* If PCE = 1, the parity bit is not included in the data extracted
|
||||
* by the reception API().
|
||||
* This masking operation is not carried out in the case of
|
||||
* DMA transfers.
|
||||
* @param __HANDLE__: specifies the UART Handle
|
||||
* @retval mask to apply to UART RDR register value.
|
||||
*/
|
||||
#define UART_MASK_COMPUTATION(__HANDLE__) \
|
||||
do { \
|
||||
if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B) \
|
||||
{ \
|
||||
if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x01FF ; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x00FF ; \
|
||||
} \
|
||||
} \
|
||||
else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B) \
|
||||
{ \
|
||||
if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x00FF ; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x007F ; \
|
||||
} \
|
||||
} \
|
||||
else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B) \
|
||||
{ \
|
||||
if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x007F ; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x003F ; \
|
||||
} \
|
||||
} \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @addtogroup UARTEx_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup UARTEx_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Initialization and de-initialization functions ****************************/
|
||||
HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup UARTEx_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Peripheral Control functions **********************************************/
|
||||
HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F7xx_HAL_UART_EX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,696 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_hal_usart.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.2
|
||||
* @date 14-April-2017
|
||||
* @brief Header file of USART HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F7xx_HAL_USART_H
|
||||
#define __STM32F7xx_HAL_USART_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup USART
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup USART_Exported_Types USART Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief USART Init Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t BaudRate; /*!< This member configures the Usart communication baud rate.
|
||||
The baud rate is computed using the following formula:
|
||||
Baud Rate Register = ((PCLKx) / ((huart->Init.BaudRate))) */
|
||||
|
||||
uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
|
||||
This parameter can be a value of @ref USARTEx_Word_Length */
|
||||
|
||||
uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
|
||||
This parameter can be a value of @ref USART_Stop_Bits */
|
||||
|
||||
uint32_t Parity; /*!< Specifies the parity mode.
|
||||
This parameter can be a value of @ref USART_Parity
|
||||
@note When parity is enabled, the computed parity is inserted
|
||||
at the MSB position of the transmitted data (9th bit when
|
||||
the word length is set to 9 data bits; 8th bit when the
|
||||
word length is set to 8 data bits). */
|
||||
|
||||
uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
|
||||
This parameter can be a value of @ref USART_Mode */
|
||||
|
||||
uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to fPCLK/8).
|
||||
This parameter can be a value of @ref USART_Over_Sampling */
|
||||
|
||||
uint32_t CLKPolarity; /*!< Specifies the steady state of the serial clock.
|
||||
This parameter can be a value of @ref USART_Clock_Polarity */
|
||||
|
||||
uint32_t CLKPhase; /*!< Specifies the clock transition on which the bit capture is made.
|
||||
This parameter can be a value of @ref USART_Clock_Phase */
|
||||
|
||||
uint32_t CLKLastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
|
||||
data bit (MSB) has to be output on the SCLK pin in synchronous mode.
|
||||
This parameter can be a value of @ref USART_Last_Bit */
|
||||
}USART_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL USART State structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_USART_STATE_RESET = 0x00U, /*!< Peripheral is not initialized */
|
||||
HAL_USART_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
|
||||
HAL_USART_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */
|
||||
HAL_USART_STATE_BUSY_TX = 0x12U, /*!< Data Transmission process is ongoing */
|
||||
HAL_USART_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */
|
||||
HAL_USART_STATE_BUSY_TX_RX = 0x32U, /*!< Data Transmission Reception process is ongoing */
|
||||
HAL_USART_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
|
||||
HAL_USART_STATE_ERROR = 0x04U /*!< Error */
|
||||
}HAL_USART_StateTypeDef;
|
||||
|
||||
|
||||
/**
|
||||
* @brief USART clock sources definitions
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
USART_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */
|
||||
USART_CLOCKSOURCE_PCLK2 = 0x01U, /*!< PCLK2 clock source */
|
||||
USART_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */
|
||||
USART_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */
|
||||
USART_CLOCKSOURCE_LSE = 0x08U, /*!< LSE clock source */
|
||||
USART_CLOCKSOURCE_UNDEFINED = 0x10U /*!< Undefined clock source */
|
||||
}USART_ClockSourceTypeDef;
|
||||
|
||||
|
||||
/**
|
||||
* @brief USART handle Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
USART_TypeDef *Instance; /*!< USART registers base address */
|
||||
|
||||
USART_InitTypeDef Init; /*!< USART communication parameters */
|
||||
|
||||
uint8_t *pTxBuffPtr; /*!< Pointer to USART Tx transfer Buffer */
|
||||
|
||||
uint16_t TxXferSize; /*!< USART Tx Transfer size */
|
||||
|
||||
__IO uint16_t TxXferCount; /*!< USART Tx Transfer Counter */
|
||||
|
||||
uint8_t *pRxBuffPtr; /*!< Pointer to USART Rx transfer Buffer */
|
||||
|
||||
uint16_t RxXferSize; /*!< USART Rx Transfer size */
|
||||
|
||||
__IO uint16_t RxXferCount; /*!< USART Rx Transfer Counter */
|
||||
|
||||
uint16_t Mask; /*!< USART Rx RDR register mask */
|
||||
|
||||
DMA_HandleTypeDef *hdmatx; /*!< USART Tx DMA Handle parameters */
|
||||
|
||||
DMA_HandleTypeDef *hdmarx; /*!< USART Rx DMA Handle parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< Locking object */
|
||||
|
||||
HAL_USART_StateTypeDef State; /*!< USART communication state */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< USART Error code */
|
||||
|
||||
}USART_HandleTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup USART_Exported_Constants USART Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Error_Code USART Error Code
|
||||
* @brief USART Error Code
|
||||
* @{
|
||||
*/
|
||||
#define HAL_USART_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
|
||||
#define HAL_USART_ERROR_PE ((uint32_t)0x00000001U) /*!< Parity error */
|
||||
#define HAL_USART_ERROR_NE ((uint32_t)0x00000002U) /*!< Noise error */
|
||||
#define HAL_USART_ERROR_FE ((uint32_t)0x00000004U) /*!< Frame error */
|
||||
#define HAL_USART_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */
|
||||
#define HAL_USART_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Stop_Bits USART Number of Stop Bits
|
||||
* @{
|
||||
*/
|
||||
#define USART_STOPBITS_1 ((uint32_t)0x0000U)
|
||||
#define USART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1)
|
||||
#define USART_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Parity USART Parity
|
||||
* @{
|
||||
*/
|
||||
#define USART_PARITY_NONE ((uint32_t)0x0000U)
|
||||
#define USART_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
|
||||
#define USART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Mode USART Mode
|
||||
* @{
|
||||
*/
|
||||
#define USART_MODE_RX ((uint32_t)USART_CR1_RE)
|
||||
#define USART_MODE_TX ((uint32_t)USART_CR1_TE)
|
||||
#define USART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Over_Sampling USART Over Sampling
|
||||
* @{
|
||||
*/
|
||||
#define USART_OVERSAMPLING_16 ((uint32_t)0x0000U)
|
||||
#define USART_OVERSAMPLING_8 ((uint32_t)USART_CR1_OVER8)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/** @defgroup USART_Clock USART Clock
|
||||
* @{
|
||||
*/
|
||||
#define USART_CLOCK_DISABLE ((uint32_t)0x0000U)
|
||||
#define USART_CLOCK_ENABLE ((uint32_t)USART_CR2_CLKEN)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Clock_Polarity USART Clock Polarity
|
||||
* @{
|
||||
*/
|
||||
#define USART_POLARITY_LOW ((uint32_t)0x0000U)
|
||||
#define USART_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Clock_Phase USART Clock Phase
|
||||
* @{
|
||||
*/
|
||||
#define USART_PHASE_1EDGE ((uint32_t)0x0000U)
|
||||
#define USART_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Last_Bit USART Last Bit
|
||||
* @{
|
||||
*/
|
||||
#define USART_LASTBIT_DISABLE ((uint32_t)0x0000U)
|
||||
#define USART_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Request_Parameters USART Request Parameters
|
||||
* @{
|
||||
*/
|
||||
#define USART_RXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_RXFRQ) /*!< Receive Data flush Request */
|
||||
#define USART_TXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_TXFRQ) /*!< Transmit data flush Request */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Flags USART Flags
|
||||
* Elements values convention: 0xXXXX
|
||||
* - 0xXXXX : Flag mask in the ISR register
|
||||
* @{
|
||||
*/
|
||||
#define USART_FLAG_REACK ((uint32_t)0x00400000U)
|
||||
#define USART_FLAG_TEACK ((uint32_t)0x00200000U)
|
||||
#define USART_FLAG_BUSY ((uint32_t)0x00010000U)
|
||||
#define USART_FLAG_CTS ((uint32_t)0x00000400U)
|
||||
#define USART_FLAG_CTSIF ((uint32_t)0x00000200U)
|
||||
#define USART_FLAG_LBDF ((uint32_t)0x00000100U)
|
||||
#define USART_FLAG_TXE ((uint32_t)0x00000080U)
|
||||
#define USART_FLAG_TC ((uint32_t)0x00000040U)
|
||||
#define USART_FLAG_RXNE ((uint32_t)0x00000020U)
|
||||
#define USART_FLAG_IDLE ((uint32_t)0x00000010U)
|
||||
#define USART_FLAG_ORE ((uint32_t)0x00000008U)
|
||||
#define USART_FLAG_NE ((uint32_t)0x00000004U)
|
||||
#define USART_FLAG_FE ((uint32_t)0x00000002U)
|
||||
#define USART_FLAG_PE ((uint32_t)0x00000001U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Interrupt_definition USART Interrupts Definition
|
||||
* Elements values convention: 0000ZZZZ0XXYYYYYb
|
||||
* - YYYYY : Interrupt source position in the XX register (5bits)
|
||||
* - XX : Interrupt source register (2bits)
|
||||
* - 01: CR1 register
|
||||
* - 10: CR2 register
|
||||
* - 11: CR3 register
|
||||
* - ZZZZ : Flag position in the ISR register(4bits)
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_IT_PE ((uint16_t)0x0028U)
|
||||
#define USART_IT_TXE ((uint16_t)0x0727U)
|
||||
#define USART_IT_TC ((uint16_t)0x0626U)
|
||||
#define USART_IT_RXNE ((uint16_t)0x0525U)
|
||||
#define USART_IT_IDLE ((uint16_t)0x0424U)
|
||||
#define USART_IT_ERR ((uint16_t)0x0060U)
|
||||
|
||||
#define USART_IT_ORE ((uint16_t)0x0300U)
|
||||
#define USART_IT_NE ((uint16_t)0x0200U)
|
||||
#define USART_IT_FE ((uint16_t)0x0100U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_IT_CLEAR_Flags USART Interruption Clear Flags
|
||||
* @{
|
||||
*/
|
||||
#define USART_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */
|
||||
#define USART_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */
|
||||
#define USART_CLEAR_NEF USART_ICR_NCF /*!< Noise detected Clear Flag */
|
||||
#define USART_CLEAR_OREF USART_ICR_ORECF /*!< OverRun Error Clear Flag */
|
||||
#define USART_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */
|
||||
#define USART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */
|
||||
#define USART_CLEAR_CTSF USART_ICR_CTSCF /*!< CTS Interrupt Clear Flag */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup USART_Exported_Macros USART Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset USART handle state
|
||||
* @param __HANDLE__: USART handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_USART_STATE_RESET)
|
||||
|
||||
/** @brief Checks whether the specified USART flag is set or not.
|
||||
* @param __HANDLE__: specifies the USART Handle
|
||||
* @param __FLAG__: specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg USART_FLAG_REACK: Receive enable acknowledge flag
|
||||
* @arg USART_FLAG_TEACK: Transmit enable acknowledge flag
|
||||
* @arg USART_FLAG_BUSY: Busy flag
|
||||
* @arg USART_FLAG_CTS: CTS Change flag
|
||||
* @arg USART_FLAG_TXE: Transmit data register empty flag
|
||||
* @arg USART_FLAG_TC: Transmission Complete flag
|
||||
* @arg USART_FLAG_RXNE: Receive data register not empty flag
|
||||
* @arg USART_FLAG_IDLE: Idle Line detection flag
|
||||
* @arg USART_FLAG_ORE: OverRun Error flag
|
||||
* @arg USART_FLAG_NE: Noise Error flag
|
||||
* @arg USART_FLAG_FE: Framing Error flag
|
||||
* @arg USART_FLAG_PE: Parity Error flag
|
||||
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_USART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
|
||||
|
||||
|
||||
/** @brief Enables the specified USART interrupt.
|
||||
* @param __HANDLE__: specifies the USART Handle
|
||||
* @param __INTERRUPT__: specifies the USART interrupt source to enable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg USART_IT_TXE: Transmit Data Register empty interrupt
|
||||
* @arg USART_IT_TC: Transmission complete interrupt
|
||||
* @arg USART_IT_RXNE: Receive Data register not empty interrupt
|
||||
* @arg USART_IT_IDLE: Idle line detection interrupt
|
||||
* @arg USART_IT_PE: Parity Error interrupt
|
||||
* @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
|
||||
((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
|
||||
((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))))
|
||||
|
||||
/** @brief Disables the specified USART interrupt.
|
||||
* @param __HANDLE__: specifies the USART Handle.
|
||||
* @param __INTERRUPT__: specifies the USART interrupt source to disable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg USART_IT_TXE: Transmit Data Register empty interrupt
|
||||
* @arg USART_IT_TC: Transmission complete interrupt
|
||||
* @arg USART_IT_RXNE: Receive Data register not empty interrupt
|
||||
* @arg USART_IT_IDLE: Idle line detection interrupt
|
||||
* @arg USART_IT_PE: Parity Error interrupt
|
||||
* @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
|
||||
((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
|
||||
((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))))
|
||||
|
||||
|
||||
/** @brief Checks whether the specified USART interrupt has occurred or not.
|
||||
* @param __HANDLE__: specifies the USART Handle
|
||||
* @param __IT__: specifies the USART interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg USART_IT_TXE: Transmit Data Register empty interrupt
|
||||
* @arg USART_IT_TC: Transmission complete interrupt
|
||||
* @arg USART_IT_RXNE: Receive Data register not empty interrupt
|
||||
* @arg USART_IT_IDLE: Idle line detection interrupt
|
||||
* @arg USART_IT_ORE: OverRun Error interrupt
|
||||
* @arg USART_IT_NE: Noise Error interrupt
|
||||
* @arg USART_IT_FE: Framing Error interrupt
|
||||
* @arg USART_IT_PE: Parity Error interrupt
|
||||
* @retval The new state of __IT__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_USART_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08)))
|
||||
|
||||
/** @brief Checks whether the specified USART interrupt source is enabled.
|
||||
* @param __HANDLE__: specifies the USART Handle.
|
||||
* @param __IT__: specifies the USART interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg USART_IT_TXE: Transmit Data Register empty interrupt
|
||||
* @arg USART_IT_TC: Transmission complete interrupt
|
||||
* @arg USART_IT_RXNE: Receive Data register not empty interrupt
|
||||
* @arg USART_IT_IDLE: Idle line detection interrupt
|
||||
* @arg USART_IT_ORE: OverRun Error interrupt
|
||||
* @arg USART_IT_NE: Noise Error interrupt
|
||||
* @arg USART_IT_FE: Framing Error interrupt
|
||||
* @arg USART_IT_PE: Parity Error interrupt
|
||||
* @retval The new state of __IT__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5) == 1)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5) == 2)? \
|
||||
(__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << \
|
||||
(((uint16_t)(__IT__)) & USART_IT_MASK)))
|
||||
|
||||
|
||||
/** @brief Clears the specified USART ISR flag, in setting the proper ICR register flag.
|
||||
* @param __HANDLE__: specifies the USART Handle.
|
||||
* @param __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set
|
||||
* to clear the corresponding interrupt
|
||||
* This parameter can be one of the following values:
|
||||
* @arg USART_CLEAR_PEF: Parity Error Clear Flag
|
||||
* @arg USART_CLEAR_FEF: Framing Error Clear Flag
|
||||
* @arg USART_CLEAR_NEF: Noise detected Clear Flag
|
||||
* @arg USART_CLEAR_OREF: OverRun Error Clear Flag
|
||||
* @arg USART_CLEAR_IDLEF: IDLE line detected Clear Flag
|
||||
* @arg USART_CLEAR_TCF: Transmission Complete Clear Flag
|
||||
* @arg USART_CLEAR_CTSF: CTS Interrupt Clear Flag
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_USART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
|
||||
|
||||
/** @brief Set a specific USART request flag.
|
||||
* @param __HANDLE__: specifies the USART Handle.
|
||||
* @param __REQ__: specifies the request flag to set
|
||||
* This parameter can be one of the following values:
|
||||
* @arg USART_RXDATA_FLUSH_REQUEST: Receive Data flush Request
|
||||
* @arg USART_TXDATA_FLUSH_REQUEST: Transmit data flush Request
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_USART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
|
||||
|
||||
/** @brief Enable USART
|
||||
* @param __HANDLE__: specifies the USART Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_USART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
|
||||
|
||||
/** @brief Disable USART
|
||||
* @param __HANDLE__: specifies the USART Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_USART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Include UART HAL Extension module */
|
||||
#include "stm32f7xx_hal_usart_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup USART_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup USART_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Initialization/de-initialization functions **********************************/
|
||||
HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart);
|
||||
HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart);
|
||||
void HAL_USART_MspInit(USART_HandleTypeDef *husart);
|
||||
void HAL_USART_MspDeInit(USART_HandleTypeDef *husart);
|
||||
HAL_StatusTypeDef HAL_USART_CheckIdleState(USART_HandleTypeDef *husart);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup USART_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* IO operation functions *******************************************************/
|
||||
HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart);
|
||||
HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart);
|
||||
HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart);
|
||||
void HAL_USART_IRQHandler(USART_HandleTypeDef *husart);
|
||||
void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart);
|
||||
void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart);
|
||||
void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart);
|
||||
void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart);
|
||||
void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart);
|
||||
void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup USART_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State functions ************************************************/
|
||||
HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart);
|
||||
uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup USART_Private_Constants USART Private Constants
|
||||
* @{
|
||||
*/
|
||||
/** @brief USART interruptions flag mask
|
||||
*
|
||||
*/
|
||||
#define USART_IT_MASK ((uint16_t)0x001FU)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup USART_Private_Macros USART Private Macros
|
||||
* @{
|
||||
*/
|
||||
/** @brief Reports the USART clock source.
|
||||
* @param __HANDLE__: specifies the USART Handle
|
||||
* @param __CLOCKSOURCE__ : output variable
|
||||
* @retval the USART clocking source, written in __CLOCKSOURCE__.
|
||||
*/
|
||||
#define USART_GETCLOCKSOURCE(__HANDLE__, __CLOCKSOURCE__)\
|
||||
do { \
|
||||
if((__HANDLE__)->Instance == USART1) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART1_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART1CLKSOURCE_PCLK2: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK2; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART2) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART2_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART2CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART3) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART3_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART3CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART3CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART3CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART3CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART6) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART6_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART6CLKSOURCE_PCLK2: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK2; \
|
||||
break; \
|
||||
case RCC_USART6CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART6CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART6CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
} while(0)
|
||||
|
||||
|
||||
#define IS_USART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == USART_STOPBITS_1) || \
|
||||
((__STOPBITS__) == USART_STOPBITS_1_5) || \
|
||||
((__STOPBITS__) == USART_STOPBITS_2))
|
||||
#define IS_USART_PARITY(__PARITY__) (((__PARITY__) == USART_PARITY_NONE) || \
|
||||
((__PARITY__) == USART_PARITY_EVEN) || \
|
||||
((__PARITY__) == USART_PARITY_ODD))
|
||||
#define IS_USART_MODE(__MODE__) ((((__MODE__) & (uint32_t)0xFFFFFFF3U) == 0x00U) && ((__MODE__) != (uint32_t)0x00U))
|
||||
#define IS_USART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == USART_OVERSAMPLING_16) || \
|
||||
((__SAMPLING__) == USART_OVERSAMPLING_8))
|
||||
#define IS_USART_CLOCK(__CLOCK__) (((__CLOCK__)== USART_CLOCK_DISABLE) || \
|
||||
((__CLOCK__)== USART_CLOCK_ENABLE))
|
||||
#define IS_USART_POLARITY(__CPOL__) (((__CPOL__) == USART_POLARITY_LOW) || ((__CPOL__) == USART_POLARITY_HIGH))
|
||||
#define IS_USART_PHASE(__CPHA__) (((__CPHA__) == USART_PHASE_1EDGE) || ((__CPHA__) == USART_PHASE_2EDGE))
|
||||
#define IS_USART_LASTBIT(__LASTBIT__) (((__LASTBIT__) == USART_LASTBIT_DISABLE) || \
|
||||
((__LASTBIT__) == USART_LASTBIT_ENABLE))
|
||||
#define IS_USART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == USART_RXDATA_FLUSH_REQUEST) || \
|
||||
((__PARAM__) == USART_TXDATA_FLUSH_REQUEST))
|
||||
#define IS_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 9000001)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup USART_Private_Functions USART Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F7xx_HAL_USART_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,158 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_hal_usart_ex.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.2
|
||||
* @date 14-April-2017
|
||||
* @brief Header file of USART HAL Extension module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F7xx_HAL_USART_EX_H
|
||||
#define __STM32F7xx_HAL_USART_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup USARTEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup USARTEx_Exported_Constants USARTEx Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup USARTEx_Word_Length USARTEx Word Length
|
||||
* @{
|
||||
*/
|
||||
#define USART_WORDLENGTH_7B ((uint32_t)USART_CR1_M_1)
|
||||
#define USART_WORDLENGTH_8B ((uint32_t)0x00000000U)
|
||||
#define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M_0)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup USARTEx_Private_Macros USARTEx Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Computes the USART mask to apply to retrieve the received data
|
||||
* according to the word length and to the parity bits activation.
|
||||
* If PCE = 1, the parity bit is not included in the data extracted
|
||||
* by the reception API().
|
||||
* This masking operation is not carried out in the case of
|
||||
* DMA transfers.
|
||||
* @param __HANDLE__: specifies the USART Handle
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_USART_MASK_COMPUTATION(__HANDLE__) \
|
||||
do { \
|
||||
if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_9B) \
|
||||
{ \
|
||||
if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x01FF ; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x00FF ; \
|
||||
} \
|
||||
} \
|
||||
else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_8B) \
|
||||
{ \
|
||||
if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x00FF ; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x007F ; \
|
||||
} \
|
||||
} \
|
||||
else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_7B) \
|
||||
{ \
|
||||
if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x007F ; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x003F ; \
|
||||
} \
|
||||
} \
|
||||
} while(0)
|
||||
|
||||
#define IS_USART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == USART_WORDLENGTH_7B) || \
|
||||
((__LENGTH__) == USART_WORDLENGTH_8B) || \
|
||||
((__LENGTH__) == USART_WORDLENGTH_9B))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/* Initialization/de-initialization methods **********************************/
|
||||
/* IO operation methods *******************************************************/
|
||||
/* Peripheral Control methods ************************************************/
|
||||
/* Peripheral State methods **************************************************/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F7xx_HAL_USART_EX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,285 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_hal_wwdg.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.2
|
||||
* @date 14-April-2017
|
||||
* @brief Header file of WWDG HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F7xx_HAL_WWDG_H
|
||||
#define __STM32F7xx_HAL_WWDG_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup WWDG
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup WWDG_Exported_Types WWDG Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief WWDG Init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Prescaler; /*!< Specifies the prescaler value of the WWDG.
|
||||
This parameter can be a value of @ref WWDG_Prescaler */
|
||||
|
||||
uint32_t Window; /*!< Specifies the WWDG window value to be compared to the downcounter.
|
||||
This parameter must be a number Min_Data = 0x40 and Max_Data = 0x7F */
|
||||
|
||||
uint32_t Counter; /*!< Specifies the WWDG free-running downcounter value.
|
||||
This parameter must be a number between Min_Data = 0x40 and Max_Data = 0x7F */
|
||||
|
||||
uint32_t EWIMode ; /*!< Specifies if WWDG Early Wakeup Interupt is enable or not.
|
||||
This parameter can be a value of @ref WWDG_EWI_Mode */
|
||||
|
||||
}WWDG_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief WWDG handle Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
WWDG_TypeDef *Instance; /*!< Register base address */
|
||||
|
||||
WWDG_InitTypeDef Init; /*!< WWDG required parameters */
|
||||
|
||||
}WWDG_HandleTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup WWDG_Exported_Constants WWDG Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup WWDG_Interrupt_definition WWDG Interrupt definition
|
||||
* @{
|
||||
*/
|
||||
#define WWDG_IT_EWI WWDG_CFR_EWI /*!< Early wakeup interrupt */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup WWDG_Flag_definition WWDG Flag definition
|
||||
* @brief WWDG Flag definition
|
||||
* @{
|
||||
*/
|
||||
#define WWDG_FLAG_EWIF WWDG_SR_EWIF /*!< Early wakeup interrupt flag */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup WWDG_Prescaler WWDG Prescaler
|
||||
* @{
|
||||
*/
|
||||
#define WWDG_PRESCALER_1 0x00000000U /*!< WWDG counter clock = (PCLK1/4096)/1 */
|
||||
#define WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0 /*!< WWDG counter clock = (PCLK1/4096)/2 */
|
||||
#define WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1 /*!< WWDG counter clock = (PCLK1/4096)/4 */
|
||||
#define WWDG_PRESCALER_8 WWDG_CFR_WDGTB /*!< WWDG counter clock = (PCLK1/4096)/8 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup WWDG_EWI_Mode WWDG Early Wakeup Interrupt Mode
|
||||
* @{
|
||||
*/
|
||||
#define WWDG_EWI_DISABLE 0x00000000u /*!< EWI Disable */
|
||||
#define WWDG_EWI_ENABLE WWDG_CFR_EWI /*!< EWI Enable */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup WWDG_Private_Macros WWDG Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_WWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == WWDG_PRESCALER_1) || \
|
||||
((__PRESCALER__) == WWDG_PRESCALER_2) || \
|
||||
((__PRESCALER__) == WWDG_PRESCALER_4) || \
|
||||
((__PRESCALER__) == WWDG_PRESCALER_8))
|
||||
|
||||
#define IS_WWDG_WINDOW(__WINDOW__) (((__WINDOW__) >= WWDG_CFR_W_6) && ((__WINDOW__) <= WWDG_CFR_W))
|
||||
|
||||
#define IS_WWDG_COUNTER(__COUNTER__) (((__COUNTER__) >= WWDG_CR_T_6) && ((__COUNTER__) <= WWDG_CR_T))
|
||||
|
||||
#define IS_WWDG_EWI_MODE(__MODE__) (((__MODE__) == WWDG_EWI_ENABLE) || \
|
||||
((__MODE__) == WWDG_EWI_DISABLE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Exported macros ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup WWDG_Exported_Macros WWDG Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable the WWDG peripheral.
|
||||
* @param __HANDLE__ WWDG handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_WWDG_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, WWDG_CR_WDGA)
|
||||
|
||||
/**
|
||||
* @brief Enable the WWDG early wakeup interrupt.
|
||||
* @param __HANDLE__: WWDG handle
|
||||
* @param __INTERRUPT__ specifies the interrupt to enable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg WWDG_IT_EWI: Early wakeup interrupt
|
||||
* @note Once enabled this interrupt cannot be disabled except by a system reset.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_WWDG_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CFR, (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Check whether the selected WWDG interrupt has occurred or not.
|
||||
* @param __HANDLE__ WWDG handle
|
||||
* @param __INTERRUPT__ specifies the it to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg WWDG_FLAG_EWIF: Early wakeup interrupt IT
|
||||
* @retval The new state of WWDG_FLAG (SET or RESET).
|
||||
*/
|
||||
#define __HAL_WWDG_GET_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_GET_FLAG((__HANDLE__),(__INTERRUPT__))
|
||||
|
||||
/** @brief Clear the WWDG interrupt pending bits.
|
||||
* bits to clear the selected interrupt pending bits.
|
||||
* @param __HANDLE__ WWDG handle
|
||||
* @param __INTERRUPT__ specifies the interrupt pending bit to clear.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
|
||||
*/
|
||||
#define __HAL_WWDG_CLEAR_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_CLEAR_FLAG((__HANDLE__), (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified WWDG flag is set or not.
|
||||
* @param __HANDLE__ WWDG handle
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
|
||||
* @retval The new state of WWDG_FLAG (SET or RESET).
|
||||
*/
|
||||
#define __HAL_WWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
|
||||
|
||||
/**
|
||||
* @brief Clear the WWDG's pending flags.
|
||||
* @param __HANDLE__ WWDG handle
|
||||
* @param __FLAG__ specifies the flag to clear.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_WWDG_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
|
||||
|
||||
/** @brief Check whether the specified WWDG interrupt source is enabled or not.
|
||||
* @param __HANDLE__ WWDG Handle.
|
||||
* @param __INTERRUPT__ specifies the WWDG interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg WWDG_IT_EWI: Early Wakeup Interrupt
|
||||
* @retval state of __INTERRUPT__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_WWDG_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CFR & (__INTERRUPT__)) == (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @addtogroup WWDG_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup WWDG_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Initialization/de-initialization functions **********************************/
|
||||
HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg);
|
||||
void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup WWDG_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* I/O operation functions ******************************************************/
|
||||
HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg);
|
||||
void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg);
|
||||
void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef* hwwdg);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F7xx_HAL_WWDG_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,657 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_ll_cortex.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.2
|
||||
* @date 14-April-2017
|
||||
* @brief Header file of CORTEX LL module.
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
The LL CORTEX driver contains a set of generic APIs that can be
|
||||
used by user:
|
||||
(+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick
|
||||
functions
|
||||
(+) Low power mode configuration (SCB register of Cortex-MCU)
|
||||
(+) MPU API to configure and enable regions
|
||||
(+) API to access to MCU info (CPUID register)
|
||||
(+) API to enable fault handler (SHCSR accesses)
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F7xx_LL_CORTEX_H
|
||||
#define __STM32F7xx_LL_CORTEX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx.h"
|
||||
|
||||
/** @addtogroup STM32F7xx_LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_LL CORTEX
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source
|
||||
* @{
|
||||
*/
|
||||
#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U /*!< AHB clock divided by 8 selected as SysTick clock source.*/
|
||||
#define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick clock source. */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_LL_EC_FAULT Handler Fault type
|
||||
* @{
|
||||
*/
|
||||
#define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk /*!< Usage fault */
|
||||
#define LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk /*!< Bus fault */
|
||||
#define LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk /*!< Memory management fault */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if __MPU_PRESENT
|
||||
|
||||
/** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control
|
||||
* @{
|
||||
*/
|
||||
#define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0x00000000U /*!< Disable NMI and privileged SW access */
|
||||
#define LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */
|
||||
#define LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk /*!< Enable privileged software access to default memory map */
|
||||
#define LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_LL_EC_REGION MPU Region Number
|
||||
* @{
|
||||
*/
|
||||
#define LL_MPU_REGION_NUMBER0 0x00U /*!< REGION Number 0 */
|
||||
#define LL_MPU_REGION_NUMBER1 0x01U /*!< REGION Number 1 */
|
||||
#define LL_MPU_REGION_NUMBER2 0x02U /*!< REGION Number 2 */
|
||||
#define LL_MPU_REGION_NUMBER3 0x03U /*!< REGION Number 3 */
|
||||
#define LL_MPU_REGION_NUMBER4 0x04U /*!< REGION Number 4 */
|
||||
#define LL_MPU_REGION_NUMBER5 0x05U /*!< REGION Number 5 */
|
||||
#define LL_MPU_REGION_NUMBER6 0x06U /*!< REGION Number 6 */
|
||||
#define LL_MPU_REGION_NUMBER7 0x07U /*!< REGION Number 7 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size
|
||||
* @{
|
||||
*/
|
||||
#define LL_MPU_REGION_SIZE_32B (0x04U << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */
|
||||
#define LL_MPU_REGION_SIZE_64B (0x05U << MPU_RASR_SIZE_Pos) /*!< 64B Size of the MPU protection region */
|
||||
#define LL_MPU_REGION_SIZE_128B (0x06U << MPU_RASR_SIZE_Pos) /*!< 128B Size of the MPU protection region */
|
||||
#define LL_MPU_REGION_SIZE_256B (0x07U << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */
|
||||
#define LL_MPU_REGION_SIZE_512B (0x08U << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */
|
||||
#define LL_MPU_REGION_SIZE_1KB (0x09U << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */
|
||||
#define LL_MPU_REGION_SIZE_2KB (0x0AU << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */
|
||||
#define LL_MPU_REGION_SIZE_4KB (0x0BU << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */
|
||||
#define LL_MPU_REGION_SIZE_8KB (0x0CU << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */
|
||||
#define LL_MPU_REGION_SIZE_16KB (0x0DU << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */
|
||||
#define LL_MPU_REGION_SIZE_32KB (0x0EU << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */
|
||||
#define LL_MPU_REGION_SIZE_64KB (0x0FU << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */
|
||||
#define LL_MPU_REGION_SIZE_128KB (0x10U << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */
|
||||
#define LL_MPU_REGION_SIZE_256KB (0x11U << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */
|
||||
#define LL_MPU_REGION_SIZE_512KB (0x12U << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */
|
||||
#define LL_MPU_REGION_SIZE_1MB (0x13U << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */
|
||||
#define LL_MPU_REGION_SIZE_2MB (0x14U << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */
|
||||
#define LL_MPU_REGION_SIZE_4MB (0x15U << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */
|
||||
#define LL_MPU_REGION_SIZE_8MB (0x16U << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */
|
||||
#define LL_MPU_REGION_SIZE_16MB (0x17U << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */
|
||||
#define LL_MPU_REGION_SIZE_32MB (0x18U << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */
|
||||
#define LL_MPU_REGION_SIZE_64MB (0x19U << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */
|
||||
#define LL_MPU_REGION_SIZE_128MB (0x1AU << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */
|
||||
#define LL_MPU_REGION_SIZE_256MB (0x1BU << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */
|
||||
#define LL_MPU_REGION_SIZE_512MB (0x1CU << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */
|
||||
#define LL_MPU_REGION_SIZE_1GB (0x1DU << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */
|
||||
#define LL_MPU_REGION_SIZE_2GB (0x1EU << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */
|
||||
#define LL_MPU_REGION_SIZE_4GB (0x1FU << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges
|
||||
* @{
|
||||
*/
|
||||
#define LL_MPU_REGION_NO_ACCESS (0x00U << MPU_RASR_AP_Pos) /*!< No access*/
|
||||
#define LL_MPU_REGION_PRIV_RW (0x01U << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/
|
||||
#define LL_MPU_REGION_PRIV_RW_URO (0x02U << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user program generates a fault) */
|
||||
#define LL_MPU_REGION_FULL_ACCESS (0x03U << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */
|
||||
#define LL_MPU_REGION_PRIV_RO (0x05U << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/
|
||||
#define LL_MPU_REGION_PRIV_RO_URO (0x06U << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_LL_EC_TEX MPU TEX Level
|
||||
* @{
|
||||
*/
|
||||
#define LL_MPU_TEX_LEVEL0 (0x00U << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */
|
||||
#define LL_MPU_TEX_LEVEL1 (0x01U << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */
|
||||
#define LL_MPU_TEX_LEVEL2 (0x02U << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */
|
||||
#define LL_MPU_TEX_LEVEL4 (0x04U << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access
|
||||
* @{
|
||||
*/
|
||||
#define LL_MPU_INSTRUCTION_ACCESS_ENABLE 0x00U /*!< Instruction fetches enabled */
|
||||
#define LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk /*!< Instruction fetches disabled*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access
|
||||
* @{
|
||||
*/
|
||||
#define LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk /*!< Shareable memory attribute */
|
||||
#define LL_MPU_ACCESS_NOT_SHAREABLE 0x00U /*!< Not Shareable memory attribute */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access
|
||||
* @{
|
||||
*/
|
||||
#define LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk /*!< Cacheable memory attribute */
|
||||
#define LL_MPU_ACCESS_NOT_CACHEABLE 0x00U /*!< Not Cacheable memory attribute */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access
|
||||
* @{
|
||||
*/
|
||||
#define LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk /*!< Bufferable memory attribute */
|
||||
#define LL_MPU_ACCESS_NOT_BUFFERABLE 0x00U /*!< Not Bufferable memory attribute */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* __MPU_PRESENT */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief This function checks if the Systick counter flag is active or not.
|
||||
* @note It can be used in timeout function on application side.
|
||||
* @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)
|
||||
{
|
||||
return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures the SysTick clock source
|
||||
* @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource
|
||||
* @param Source This parameter can be one of the following values:
|
||||
* @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
|
||||
* @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)
|
||||
{
|
||||
if (Source == LL_SYSTICK_CLKSOURCE_HCLK)
|
||||
{
|
||||
SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
|
||||
}
|
||||
else
|
||||
{
|
||||
CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the SysTick clock source
|
||||
* @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
|
||||
* @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)
|
||||
{
|
||||
return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable SysTick exception request
|
||||
* @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_SYSTICK_EnableIT(void)
|
||||
{
|
||||
SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable SysTick exception request
|
||||
* @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_SYSTICK_DisableIT(void)
|
||||
{
|
||||
CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks if the SYSTICK interrupt is enabled or disabled.
|
||||
* @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)
|
||||
{
|
||||
return (READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Processor uses sleep as its low power mode
|
||||
* @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_LPM_EnableSleep(void)
|
||||
{
|
||||
/* Clear SLEEPDEEP bit of Cortex System Control Register */
|
||||
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Processor uses deep sleep as its low power mode
|
||||
* @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_LPM_EnableDeepSleep(void)
|
||||
{
|
||||
/* Set SLEEPDEEP bit of Cortex System Control Register */
|
||||
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures sleep-on-exit when returning from Handler mode to Thread mode.
|
||||
* @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an
|
||||
* empty main application.
|
||||
* @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)
|
||||
{
|
||||
/* Set SLEEPONEXIT bit of Cortex System Control Register */
|
||||
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Do not sleep when returning to Thread mode.
|
||||
* @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)
|
||||
{
|
||||
/* Clear SLEEPONEXIT bit of Cortex System Control Register */
|
||||
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the
|
||||
* processor.
|
||||
* @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_LPM_EnableEventOnPend(void)
|
||||
{
|
||||
/* Set SEVEONPEND bit of Cortex System Control Register */
|
||||
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are
|
||||
* excluded
|
||||
* @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_LPM_DisableEventOnPend(void)
|
||||
{
|
||||
/* Clear SEVEONPEND bit of Cortex System Control Register */
|
||||
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_LL_EF_HANDLER HANDLER
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable a fault in System handler control register (SHCSR)
|
||||
* @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_EnableFault
|
||||
* @param Fault This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_HANDLER_FAULT_USG
|
||||
* @arg @ref LL_HANDLER_FAULT_BUS
|
||||
* @arg @ref LL_HANDLER_FAULT_MEM
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault)
|
||||
{
|
||||
/* Enable the system handler fault */
|
||||
SET_BIT(SCB->SHCSR, Fault);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable a fault in System handler control register (SHCSR)
|
||||
* @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_DisableFault
|
||||
* @param Fault This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_HANDLER_FAULT_USG
|
||||
* @arg @ref LL_HANDLER_FAULT_BUS
|
||||
* @arg @ref LL_HANDLER_FAULT_MEM
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault)
|
||||
{
|
||||
/* Disable the system handler fault */
|
||||
CLEAR_BIT(SCB->SHCSR, Fault);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Get Implementer code
|
||||
* @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer
|
||||
* @retval Value should be equal to 0x41 for ARM
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Variant number (The r value in the rnpn product revision identifier)
|
||||
* @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant
|
||||
* @retval Value between 0 and 255 (0x0: revision 0)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Constant number
|
||||
* @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetConstant
|
||||
* @retval Value should be equal to 0xF for Cortex-M7 devices
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CPUID_GetConstant(void)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Part number
|
||||
* @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo
|
||||
* @retval Value should be equal to 0xC27 for Cortex-M7
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
|
||||
* @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision
|
||||
* @retval Value between 0 and 255 (0x1: patch 1)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if __MPU_PRESENT
|
||||
/** @defgroup CORTEX_LL_EF_MPU MPU
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable MPU with input options
|
||||
* @rmtoll MPU_CTRL ENABLE LL_MPU_Enable
|
||||
* @param Options This parameter can be one of the following values:
|
||||
* @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
|
||||
* @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
|
||||
* @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
|
||||
* @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_MPU_Enable(uint32_t Options)
|
||||
{
|
||||
/* Enable the MPU*/
|
||||
WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options));
|
||||
/* Ensure MPU settings take effects */
|
||||
__DSB();
|
||||
/* Sequence instruction fetches using update settings */
|
||||
__ISB();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable MPU
|
||||
* @rmtoll MPU_CTRL ENABLE LL_MPU_Disable
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_MPU_Disable(void)
|
||||
{
|
||||
/* Make sure outstanding transfers are done */
|
||||
__DMB();
|
||||
/* Disable MPU*/
|
||||
WRITE_REG(MPU->CTRL, 0U);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if MPU is enabled or not
|
||||
* @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_MPU_IsEnabled(void)
|
||||
{
|
||||
return (READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable a MPU region
|
||||
* @rmtoll MPU_RASR ENABLE LL_MPU_EnableRegion
|
||||
* @param Region This parameter can be one of the following values:
|
||||
* @arg @ref LL_MPU_REGION_NUMBER0
|
||||
* @arg @ref LL_MPU_REGION_NUMBER1
|
||||
* @arg @ref LL_MPU_REGION_NUMBER2
|
||||
* @arg @ref LL_MPU_REGION_NUMBER3
|
||||
* @arg @ref LL_MPU_REGION_NUMBER4
|
||||
* @arg @ref LL_MPU_REGION_NUMBER5
|
||||
* @arg @ref LL_MPU_REGION_NUMBER6
|
||||
* @arg @ref LL_MPU_REGION_NUMBER7
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region)
|
||||
{
|
||||
/* Set Region number */
|
||||
WRITE_REG(MPU->RNR, Region);
|
||||
/* Enable the MPU region */
|
||||
SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure and enable a region
|
||||
* @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n
|
||||
* MPU_RBAR REGION LL_MPU_ConfigRegion\n
|
||||
* MPU_RBAR ADDR LL_MPU_ConfigRegion\n
|
||||
* MPU_RASR XN LL_MPU_ConfigRegion\n
|
||||
* MPU_RASR AP LL_MPU_ConfigRegion\n
|
||||
* MPU_RASR S LL_MPU_ConfigRegion\n
|
||||
* MPU_RASR C LL_MPU_ConfigRegion\n
|
||||
* MPU_RASR B LL_MPU_ConfigRegion\n
|
||||
* MPU_RASR SIZE LL_MPU_ConfigRegion
|
||||
* @param Region This parameter can be one of the following values:
|
||||
* @arg @ref LL_MPU_REGION_NUMBER0
|
||||
* @arg @ref LL_MPU_REGION_NUMBER1
|
||||
* @arg @ref LL_MPU_REGION_NUMBER2
|
||||
* @arg @ref LL_MPU_REGION_NUMBER3
|
||||
* @arg @ref LL_MPU_REGION_NUMBER4
|
||||
* @arg @ref LL_MPU_REGION_NUMBER5
|
||||
* @arg @ref LL_MPU_REGION_NUMBER6
|
||||
* @arg @ref LL_MPU_REGION_NUMBER7
|
||||
* @param Address Value of region base address
|
||||
* @param SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF
|
||||
* @param Attributes This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B
|
||||
* or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB
|
||||
* or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB
|
||||
* or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB
|
||||
* or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB
|
||||
* or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB
|
||||
* @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS
|
||||
* or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO
|
||||
* @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4
|
||||
* @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
|
||||
* @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE
|
||||
* @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE
|
||||
* @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes)
|
||||
{
|
||||
/* Set Region number */
|
||||
WRITE_REG(MPU->RNR, Region);
|
||||
/* Set base address */
|
||||
WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U));
|
||||
/* Configure MPU */
|
||||
WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | SubRegionDisable << MPU_RASR_SRD_Pos));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable a region
|
||||
* @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n
|
||||
* MPU_RASR ENABLE LL_MPU_DisableRegion
|
||||
* @param Region This parameter can be one of the following values:
|
||||
* @arg @ref LL_MPU_REGION_NUMBER0
|
||||
* @arg @ref LL_MPU_REGION_NUMBER1
|
||||
* @arg @ref LL_MPU_REGION_NUMBER2
|
||||
* @arg @ref LL_MPU_REGION_NUMBER3
|
||||
* @arg @ref LL_MPU_REGION_NUMBER4
|
||||
* @arg @ref LL_MPU_REGION_NUMBER5
|
||||
* @arg @ref LL_MPU_REGION_NUMBER6
|
||||
* @arg @ref LL_MPU_REGION_NUMBER7
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region)
|
||||
{
|
||||
/* Set Region number */
|
||||
WRITE_REG(MPU->RNR, Region);
|
||||
/* Disable the MPU region */
|
||||
CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* __MPU_PRESENT */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F7xx_LL_CORTEX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,479 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_ll_crc.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.2
|
||||
* @date 14-April-2017
|
||||
* @brief Header file of CRC LL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F7xx_LL_CRC_H
|
||||
#define __STM32F7xx_LL_CRC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx.h"
|
||||
|
||||
/** @addtogroup STM32F7xx_LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(CRC)
|
||||
|
||||
/** @defgroup CRC_LL CRC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup CRC_LL_Exported_Constants CRC Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_LL_EC_POLYLENGTH Polynomial length
|
||||
* @{
|
||||
*/
|
||||
#define LL_CRC_POLYLENGTH_32B 0x00000000U /*!< 32 bits Polynomial size */
|
||||
#define LL_CRC_POLYLENGTH_16B CRC_CR_POLYSIZE_0 /*!< 16 bits Polynomial size */
|
||||
#define LL_CRC_POLYLENGTH_8B CRC_CR_POLYSIZE_1 /*!< 8 bits Polynomial size */
|
||||
#define LL_CRC_POLYLENGTH_7B (CRC_CR_POLYSIZE_1 | CRC_CR_POLYSIZE_0) /*!< 7 bits Polynomial size */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_LL_EC_INDATA_REVERSE Input Data Reverse
|
||||
* @{
|
||||
*/
|
||||
#define LL_CRC_INDATA_REVERSE_NONE 0x00000000U /*!< Input Data bit order not affected */
|
||||
#define LL_CRC_INDATA_REVERSE_BYTE CRC_CR_REV_IN_0 /*!< Input Data bit reversal done by byte */
|
||||
#define LL_CRC_INDATA_REVERSE_HALFWORD CRC_CR_REV_IN_1 /*!< Input Data bit reversal done by half-word */
|
||||
#define LL_CRC_INDATA_REVERSE_WORD (CRC_CR_REV_IN_1 | CRC_CR_REV_IN_0) /*!< Input Data bit reversal done by word */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_LL_EC_OUTDATA_REVERSE Output Data Reverse
|
||||
* @{
|
||||
*/
|
||||
#define LL_CRC_OUTDATA_REVERSE_NONE 0x00000000U /*!< Output Data bit order not affected */
|
||||
#define LL_CRC_OUTDATA_REVERSE_BIT CRC_CR_REV_OUT /*!< Output Data bit reversal done by bit */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_LL_EC_Default_Polynomial_Value Default CRC generating polynomial value
|
||||
* @brief Normal representation of this polynomial value is
|
||||
* X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2 + X + 1 .
|
||||
* @{
|
||||
*/
|
||||
#define LL_CRC_DEFAULT_CRC32_POLY 0x04C11DB7U /*!< Default CRC generating polynomial value */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_LL_EC_Default_InitValue Default CRC computation initialization value
|
||||
* @{
|
||||
*/
|
||||
#define LL_CRC_DEFAULT_CRC_INITVALUE 0xFFFFFFFFU /*!< Default CRC computation initialization value */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup CRC_LL_Exported_Macros CRC Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_LL_EM_WRITE_READ Common Write and read registers Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Write a value in CRC register
|
||||
* @param __INSTANCE__ CRC Instance
|
||||
* @param __REG__ Register to be written
|
||||
* @param __VALUE__ Value to be written in the register
|
||||
* @retval None
|
||||
*/
|
||||
#define LL_CRC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
|
||||
|
||||
/**
|
||||
* @brief Read a value in CRC register
|
||||
* @param __INSTANCE__ CRC Instance
|
||||
* @param __REG__ Register to be read
|
||||
* @retval Register value
|
||||
*/
|
||||
#define LL_CRC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup CRC_LL_Exported_Functions CRC Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_LL_EF_Configuration CRC Configuration functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Reset the CRC calculation unit.
|
||||
* @note If Programmable Initial CRC value feature
|
||||
* is available, also set the Data Register to the value stored in the
|
||||
* CRC_INIT register, otherwise, reset Data Register to its default value.
|
||||
* @rmtoll CR RESET LL_CRC_ResetCRCCalculationUnit
|
||||
* @param CRCx CRC Instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRC_ResetCRCCalculationUnit(CRC_TypeDef *CRCx)
|
||||
{
|
||||
SET_BIT(CRCx->CR, CRC_CR_RESET);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure size of the polynomial.
|
||||
* @rmtoll CR POLYSIZE LL_CRC_SetPolynomialSize
|
||||
* @param CRCx CRC Instance
|
||||
* @param PolySize This parameter can be one of the following values:
|
||||
* @arg @ref LL_CRC_POLYLENGTH_32B
|
||||
* @arg @ref LL_CRC_POLYLENGTH_16B
|
||||
* @arg @ref LL_CRC_POLYLENGTH_8B
|
||||
* @arg @ref LL_CRC_POLYLENGTH_7B
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRC_SetPolynomialSize(CRC_TypeDef *CRCx, uint32_t PolySize)
|
||||
{
|
||||
MODIFY_REG(CRCx->CR, CRC_CR_POLYSIZE, PolySize);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return size of the polynomial.
|
||||
* @rmtoll CR POLYSIZE LL_CRC_GetPolynomialSize
|
||||
* @param CRCx CRC Instance
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref LL_CRC_POLYLENGTH_32B
|
||||
* @arg @ref LL_CRC_POLYLENGTH_16B
|
||||
* @arg @ref LL_CRC_POLYLENGTH_8B
|
||||
* @arg @ref LL_CRC_POLYLENGTH_7B
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRC_GetPolynomialSize(CRC_TypeDef *CRCx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_POLYSIZE));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure the reversal of the bit order of the input data
|
||||
* @rmtoll CR REV_IN LL_CRC_SetInputDataReverseMode
|
||||
* @param CRCx CRC Instance
|
||||
* @param ReverseMode This parameter can be one of the following values:
|
||||
* @arg @ref LL_CRC_INDATA_REVERSE_NONE
|
||||
* @arg @ref LL_CRC_INDATA_REVERSE_BYTE
|
||||
* @arg @ref LL_CRC_INDATA_REVERSE_HALFWORD
|
||||
* @arg @ref LL_CRC_INDATA_REVERSE_WORD
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRC_SetInputDataReverseMode(CRC_TypeDef *CRCx, uint32_t ReverseMode)
|
||||
{
|
||||
MODIFY_REG(CRCx->CR, CRC_CR_REV_IN, ReverseMode);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return type of reversal for input data bit order
|
||||
* @rmtoll CR REV_IN LL_CRC_GetInputDataReverseMode
|
||||
* @param CRCx CRC Instance
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref LL_CRC_INDATA_REVERSE_NONE
|
||||
* @arg @ref LL_CRC_INDATA_REVERSE_BYTE
|
||||
* @arg @ref LL_CRC_INDATA_REVERSE_HALFWORD
|
||||
* @arg @ref LL_CRC_INDATA_REVERSE_WORD
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRC_GetInputDataReverseMode(CRC_TypeDef *CRCx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_REV_IN));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure the reversal of the bit order of the Output data
|
||||
* @rmtoll CR REV_OUT LL_CRC_SetOutputDataReverseMode
|
||||
* @param CRCx CRC Instance
|
||||
* @param ReverseMode This parameter can be one of the following values:
|
||||
* @arg @ref LL_CRC_OUTDATA_REVERSE_NONE
|
||||
* @arg @ref LL_CRC_OUTDATA_REVERSE_BIT
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRC_SetOutputDataReverseMode(CRC_TypeDef *CRCx, uint32_t ReverseMode)
|
||||
{
|
||||
MODIFY_REG(CRCx->CR, CRC_CR_REV_OUT, ReverseMode);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure the reversal of the bit order of the Output data
|
||||
* @rmtoll CR REV_OUT LL_CRC_GetOutputDataReverseMode
|
||||
* @param CRCx CRC Instance
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref LL_CRC_OUTDATA_REVERSE_NONE
|
||||
* @arg @ref LL_CRC_OUTDATA_REVERSE_BIT
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRC_GetOutputDataReverseMode(CRC_TypeDef *CRCx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_REV_OUT));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initialize the Programmable initial CRC value.
|
||||
* @note If the CRC size is less than 32 bits, the least significant bits
|
||||
* are used to write the correct value
|
||||
* @note LL_CRC_DEFAULT_CRC_INITVALUE could be used as value for InitCrc parameter.
|
||||
* @rmtoll INIT INIT LL_CRC_SetInitialData
|
||||
* @param CRCx CRC Instance
|
||||
* @param InitCrc Value to be programmed in Programmable initial CRC value register
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRC_SetInitialData(CRC_TypeDef *CRCx, uint32_t InitCrc)
|
||||
{
|
||||
WRITE_REG(CRCx->INIT, InitCrc);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return current Initial CRC value.
|
||||
* @note If the CRC size is less than 32 bits, the least significant bits
|
||||
* are used to read the correct value
|
||||
* @rmtoll INIT INIT LL_CRC_GetInitialData
|
||||
* @param CRCx CRC Instance
|
||||
* @retval Value programmed in Programmable initial CRC value register
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRC_GetInitialData(CRC_TypeDef *CRCx)
|
||||
{
|
||||
return (uint32_t)(READ_REG(CRCx->INIT));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initialize the Programmable polynomial value
|
||||
* (coefficients of the polynomial to be used for CRC calculation).
|
||||
* @note LL_CRC_DEFAULT_CRC32_POLY could be used as value for PolynomCoef parameter.
|
||||
* @note Please check Reference Manual and existing Errata Sheets,
|
||||
* regarding possible limitations for Polynomial values usage.
|
||||
* For example, for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65
|
||||
* @rmtoll POL POL LL_CRC_SetPolynomialCoef
|
||||
* @param CRCx CRC Instance
|
||||
* @param PolynomCoef Value to be programmed in Programmable Polynomial value register
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRC_SetPolynomialCoef(CRC_TypeDef *CRCx, uint32_t PolynomCoef)
|
||||
{
|
||||
WRITE_REG(CRCx->POL, PolynomCoef);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return current Programmable polynomial value
|
||||
* @note Please check Reference Manual and existing Errata Sheets,
|
||||
* regarding possible limitations for Polynomial values usage.
|
||||
* For example, for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65
|
||||
* @rmtoll POL POL LL_CRC_GetPolynomialCoef
|
||||
* @param CRCx CRC Instance
|
||||
* @retval Value programmed in Programmable Polynomial value register
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRC_GetPolynomialCoef(CRC_TypeDef *CRCx)
|
||||
{
|
||||
return (uint32_t)(READ_REG(CRCx->POL));
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_LL_EF_Data_Management Data_Management
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Write given 32-bit data to the CRC calculator
|
||||
* @rmtoll DR DR LL_CRC_FeedData32
|
||||
* @param CRCx CRC Instance
|
||||
* @param InData value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFFFFFFFF
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRC_FeedData32(CRC_TypeDef *CRCx, uint32_t InData)
|
||||
{
|
||||
WRITE_REG(CRCx->DR, InData);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Write given 16-bit data to the CRC calculator
|
||||
* @rmtoll DR DR LL_CRC_FeedData16
|
||||
* @param CRCx CRC Instance
|
||||
* @param InData 16 bit value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFFFF
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRC_FeedData16(CRC_TypeDef *CRCx, uint16_t InData)
|
||||
{
|
||||
*(uint16_t __IO *)(&CRCx->DR) = (uint16_t) InData;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Write given 8-bit data to the CRC calculator
|
||||
* @rmtoll DR DR LL_CRC_FeedData8
|
||||
* @param CRCx CRC Instance
|
||||
* @param InData 8 bit value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFF
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRC_FeedData8(CRC_TypeDef *CRCx, uint8_t InData)
|
||||
{
|
||||
*(uint8_t __IO *)(&CRCx->DR) = (uint8_t) InData;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return current CRC calculation result. 32 bits value is returned.
|
||||
* @rmtoll DR DR LL_CRC_ReadData32
|
||||
* @param CRCx CRC Instance
|
||||
* @retval Current CRC calculation result as stored in CRC_DR register (32 bits).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRC_ReadData32(CRC_TypeDef *CRCx)
|
||||
{
|
||||
return (uint32_t)(READ_REG(CRCx->DR));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return current CRC calculation result. 16 bits value is returned.
|
||||
* @note This function is expected to be used in a 16 bits CRC polynomial size context.
|
||||
* @rmtoll DR DR LL_CRC_ReadData16
|
||||
* @param CRCx CRC Instance
|
||||
* @retval Current CRC calculation result as stored in CRC_DR register (16 bits).
|
||||
*/
|
||||
__STATIC_INLINE uint16_t LL_CRC_ReadData16(CRC_TypeDef *CRCx)
|
||||
{
|
||||
return (uint16_t)READ_REG(CRCx->DR);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return current CRC calculation result. 8 bits value is returned.
|
||||
* @note This function is expected to be used in a 8 bits CRC polynomial size context.
|
||||
* @rmtoll DR DR LL_CRC_ReadData8
|
||||
* @param CRCx CRC Instance
|
||||
* @retval Current CRC calculation result as stored in CRC_DR register (8 bits).
|
||||
*/
|
||||
__STATIC_INLINE uint8_t LL_CRC_ReadData8(CRC_TypeDef *CRCx)
|
||||
{
|
||||
return (uint8_t)READ_REG(CRCx->DR);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return current CRC calculation result. 7 bits value is returned.
|
||||
* @note This function is expected to be used in a 7 bits CRC polynomial size context.
|
||||
* @rmtoll DR DR LL_CRC_ReadData7
|
||||
* @param CRCx CRC Instance
|
||||
* @retval Current CRC calculation result as stored in CRC_DR register (7 bits).
|
||||
*/
|
||||
__STATIC_INLINE uint8_t LL_CRC_ReadData7(CRC_TypeDef *CRCx)
|
||||
{
|
||||
return (uint8_t)(READ_REG(CRCx->DR) & 0x7FU);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return data stored in the Independent Data(IDR) register.
|
||||
* @note This register can be used as a temporary storage location for one byte.
|
||||
* @rmtoll IDR IDR LL_CRC_Read_IDR
|
||||
* @param CRCx CRC Instance
|
||||
* @retval Value stored in CRC_IDR register (General-purpose 8-bit data register).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRC_Read_IDR(CRC_TypeDef *CRCx)
|
||||
{
|
||||
return (uint32_t)(READ_REG(CRCx->IDR));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Store data in the Independent Data(IDR) register.
|
||||
* @note This register can be used as a temporary storage location for one byte.
|
||||
* @rmtoll IDR IDR LL_CRC_Write_IDR
|
||||
* @param CRCx CRC Instance
|
||||
* @param InData value to be stored in CRC_IDR register (8-bit) between between Min_Data=0 and Max_Data=0xFF
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRC_Write_IDR(CRC_TypeDef *CRCx, uint32_t InData)
|
||||
{
|
||||
*((uint8_t __IO *)(&CRCx->IDR)) = (uint8_t) InData;
|
||||
}
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined(USE_FULL_LL_DRIVER)
|
||||
/** @defgroup CRC_LL_EF_Init Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* USE_FULL_LL_DRIVER */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* defined(CRC) */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F7xx_LL_CRC_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,968 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_ll_exti.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.2
|
||||
* @date 14-April-2017
|
||||
* @brief Header file of EXTI LL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F7xx_LL_EXTI_H
|
||||
#define __STM32F7xx_LL_EXTI_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx.h"
|
||||
|
||||
/** @addtogroup STM32F7xx_LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined (EXTI)
|
||||
|
||||
/** @defgroup EXTI_LL EXTI
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/* Private Macros ------------------------------------------------------------*/
|
||||
#if defined(USE_FULL_LL_DRIVER)
|
||||
/** @defgroup EXTI_LL_Private_Macros EXTI Private Macros
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /*USE_FULL_LL_DRIVER*/
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
#if defined(USE_FULL_LL_DRIVER)
|
||||
/** @defgroup EXTI_LL_ES_INIT EXTI Exported Init structure
|
||||
* @{
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
|
||||
uint32_t Line_0_31; /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 0 to 31
|
||||
This parameter can be any combination of @ref EXTI_LL_EC_LINE */
|
||||
|
||||
FunctionalState LineCommand; /*!< Specifies the new state of the selected EXTI lines.
|
||||
This parameter can be set either to ENABLE or DISABLE */
|
||||
|
||||
uint8_t Mode; /*!< Specifies the mode for the EXTI lines.
|
||||
This parameter can be a value of @ref EXTI_LL_EC_MODE. */
|
||||
|
||||
uint8_t Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.
|
||||
This parameter can be a value of @ref EXTI_LL_EC_TRIGGER. */
|
||||
} LL_EXTI_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /*USE_FULL_LL_DRIVER*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup EXTI_LL_Exported_Constants EXTI Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_LL_EC_LINE LINE
|
||||
* @{
|
||||
*/
|
||||
#define LL_EXTI_LINE_0 EXTI_IMR_IM0 /*!< Extended line 0 */
|
||||
#define LL_EXTI_LINE_1 EXTI_IMR_IM1 /*!< Extended line 1 */
|
||||
#define LL_EXTI_LINE_2 EXTI_IMR_IM2 /*!< Extended line 2 */
|
||||
#define LL_EXTI_LINE_3 EXTI_IMR_IM3 /*!< Extended line 3 */
|
||||
#define LL_EXTI_LINE_4 EXTI_IMR_IM4 /*!< Extended line 4 */
|
||||
#define LL_EXTI_LINE_5 EXTI_IMR_IM5 /*!< Extended line 5 */
|
||||
#define LL_EXTI_LINE_6 EXTI_IMR_IM6 /*!< Extended line 6 */
|
||||
#define LL_EXTI_LINE_7 EXTI_IMR_IM7 /*!< Extended line 7 */
|
||||
#define LL_EXTI_LINE_8 EXTI_IMR_IM8 /*!< Extended line 8 */
|
||||
#define LL_EXTI_LINE_9 EXTI_IMR_IM9 /*!< Extended line 9 */
|
||||
#define LL_EXTI_LINE_10 EXTI_IMR_IM10 /*!< Extended line 10 */
|
||||
#define LL_EXTI_LINE_11 EXTI_IMR_IM11 /*!< Extended line 11 */
|
||||
#define LL_EXTI_LINE_12 EXTI_IMR_IM12 /*!< Extended line 12 */
|
||||
#define LL_EXTI_LINE_13 EXTI_IMR_IM13 /*!< Extended line 13 */
|
||||
#define LL_EXTI_LINE_14 EXTI_IMR_IM14 /*!< Extended line 14 */
|
||||
#define LL_EXTI_LINE_15 EXTI_IMR_IM15 /*!< Extended line 15 */
|
||||
#if defined(EXTI_IMR_IM16)
|
||||
#define LL_EXTI_LINE_16 EXTI_IMR_IM16 /*!< Extended line 16 */
|
||||
#endif
|
||||
#define LL_EXTI_LINE_17 EXTI_IMR_IM17 /*!< Extended line 17 */
|
||||
#if defined(EXTI_IMR_IM18)
|
||||
#define LL_EXTI_LINE_18 EXTI_IMR_IM18 /*!< Extended line 18 */
|
||||
#endif
|
||||
#define LL_EXTI_LINE_19 EXTI_IMR_IM19 /*!< Extended line 19 */
|
||||
#if defined(EXTI_IMR_IM20)
|
||||
#define LL_EXTI_LINE_20 EXTI_IMR_IM20 /*!< Extended line 20 */
|
||||
#endif
|
||||
#if defined(EXTI_IMR_IM21)
|
||||
#define LL_EXTI_LINE_21 EXTI_IMR_IM21 /*!< Extended line 21 */
|
||||
#endif
|
||||
#if defined(EXTI_IMR_IM22)
|
||||
#define LL_EXTI_LINE_22 EXTI_IMR_IM22 /*!< Extended line 22 */
|
||||
#endif
|
||||
#define LL_EXTI_LINE_23 EXTI_IMR_IM23 /*!< Extended line 23 */
|
||||
#if defined(EXTI_IMR_IM24)
|
||||
#define LL_EXTI_LINE_24 EXTI_IMR_IM24 /*!< Extended line 24 */
|
||||
#endif
|
||||
#if defined(EXTI_IMR_IM25)
|
||||
#define LL_EXTI_LINE_25 EXTI_IMR_IM25 /*!< Extended line 25 */
|
||||
#endif
|
||||
#if defined(EXTI_IMR_IM26)
|
||||
#define LL_EXTI_LINE_26 EXTI_IMR_IM26 /*!< Extended line 26 */
|
||||
#endif
|
||||
#if defined(EXTI_IMR_IM27)
|
||||
#define LL_EXTI_LINE_27 EXTI_IMR_IM27 /*!< Extended line 27 */
|
||||
#endif
|
||||
#if defined(EXTI_IMR_IM28)
|
||||
#define LL_EXTI_LINE_28 EXTI_IMR_IM28 /*!< Extended line 28 */
|
||||
#endif
|
||||
#if defined(EXTI_IMR_IM29)
|
||||
#define LL_EXTI_LINE_29 EXTI_IMR_IM29 /*!< Extended line 29 */
|
||||
#endif
|
||||
#if defined(EXTI_IMR_IM30)
|
||||
#define LL_EXTI_LINE_30 EXTI_IMR_IM30 /*!< Extended line 30 */
|
||||
#endif
|
||||
#if defined(EXTI_IMR_IM31)
|
||||
#define LL_EXTI_LINE_31 EXTI_IMR_IM31 /*!< Extended line 31 */
|
||||
#endif
|
||||
#define LL_EXTI_LINE_ALL_0_31 EXTI_IMR_IM /*!< All Extended line not reserved*/
|
||||
|
||||
|
||||
#define LL_EXTI_LINE_ALL (0xFFFFFFFFU) /*!< All Extended line */
|
||||
|
||||
#if defined(USE_FULL_LL_DRIVER)
|
||||
#define LL_EXTI_LINE_NONE (0x00000000U) /*!< None Extended line */
|
||||
#endif /*USE_FULL_LL_DRIVER*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#if defined(USE_FULL_LL_DRIVER)
|
||||
|
||||
/** @defgroup EXTI_LL_EC_MODE Mode
|
||||
* @{
|
||||
*/
|
||||
#define LL_EXTI_MODE_IT ((uint8_t)0x00U) /*!< Interrupt Mode */
|
||||
#define LL_EXTI_MODE_EVENT ((uint8_t)0x01U) /*!< Event Mode */
|
||||
#define LL_EXTI_MODE_IT_EVENT ((uint8_t)0x02U) /*!< Interrupt & Event Mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_LL_EC_TRIGGER Edge Trigger
|
||||
* @{
|
||||
*/
|
||||
#define LL_EXTI_TRIGGER_NONE ((uint8_t)0x00U) /*!< No Trigger Mode */
|
||||
#define LL_EXTI_TRIGGER_RISING ((uint8_t)0x01U) /*!< Trigger Rising Mode */
|
||||
#define LL_EXTI_TRIGGER_FALLING ((uint8_t)0x02U) /*!< Trigger Falling Mode */
|
||||
#define LL_EXTI_TRIGGER_RISING_FALLING ((uint8_t)0x03U) /*!< Trigger Rising & Falling Mode */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
#endif /*USE_FULL_LL_DRIVER*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup EXTI_LL_Exported_Macros EXTI Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_LL_EM_WRITE_READ Common Write and read registers Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Write a value in EXTI register
|
||||
* @param __REG__ Register to be written
|
||||
* @param __VALUE__ Value to be written in the register
|
||||
* @retval None
|
||||
*/
|
||||
#define LL_EXTI_WriteReg(__REG__, __VALUE__) WRITE_REG(EXTI->__REG__, (__VALUE__))
|
||||
|
||||
/**
|
||||
* @brief Read a value in EXTI register
|
||||
* @param __REG__ Register to be read
|
||||
* @retval Register value
|
||||
*/
|
||||
#define LL_EXTI_ReadReg(__REG__) READ_REG(EXTI->__REG__)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup EXTI_LL_Exported_Functions EXTI Exported Functions
|
||||
* @{
|
||||
*/
|
||||
/** @defgroup EXTI_LL_EF_IT_Management IT_Management
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable ExtiLine Interrupt request for Lines in range 0 to 31
|
||||
* @note The reset value for the direct or internal lines (see RM)
|
||||
* is set to 1 in order to enable the interrupt by default.
|
||||
* Bits are set automatically at Power on.
|
||||
* @rmtoll IMR IMx LL_EXTI_EnableIT_0_31
|
||||
* @param ExtiLine This parameter can be one of the following values:
|
||||
* @arg @ref LL_EXTI_LINE_0
|
||||
* @arg @ref LL_EXTI_LINE_1
|
||||
* @arg @ref LL_EXTI_LINE_2
|
||||
* @arg @ref LL_EXTI_LINE_3
|
||||
* @arg @ref LL_EXTI_LINE_4
|
||||
* @arg @ref LL_EXTI_LINE_5
|
||||
* @arg @ref LL_EXTI_LINE_6
|
||||
* @arg @ref LL_EXTI_LINE_7
|
||||
* @arg @ref LL_EXTI_LINE_8
|
||||
* @arg @ref LL_EXTI_LINE_9
|
||||
* @arg @ref LL_EXTI_LINE_10
|
||||
* @arg @ref LL_EXTI_LINE_11
|
||||
* @arg @ref LL_EXTI_LINE_12
|
||||
* @arg @ref LL_EXTI_LINE_13
|
||||
* @arg @ref LL_EXTI_LINE_14
|
||||
* @arg @ref LL_EXTI_LINE_15
|
||||
* @arg @ref LL_EXTI_LINE_16
|
||||
* @arg @ref LL_EXTI_LINE_17
|
||||
* @arg @ref LL_EXTI_LINE_18
|
||||
* @arg @ref LL_EXTI_LINE_19
|
||||
* @arg @ref LL_EXTI_LINE_20
|
||||
* @arg @ref LL_EXTI_LINE_21
|
||||
* @arg @ref LL_EXTI_LINE_22
|
||||
* @arg @ref LL_EXTI_LINE_23
|
||||
* @arg @ref LL_EXTI_LINE_24(*)
|
||||
* @arg @ref LL_EXTI_LINE_ALL_0_31
|
||||
* @note (*): Available in some devices
|
||||
* @note Please check each device line mapping for EXTI Line availability
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine)
|
||||
{
|
||||
SET_BIT(EXTI->IMR, ExtiLine);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable ExtiLine Interrupt request for Lines in range 0 to 31
|
||||
* @note The reset value for the direct or internal lines (see RM)
|
||||
* is set to 1 in order to enable the interrupt by default.
|
||||
* Bits are set automatically at Power on.
|
||||
* @rmtoll IMR IMx LL_EXTI_DisableIT_0_31
|
||||
* @param ExtiLine This parameter can be one of the following values:
|
||||
* @arg @ref LL_EXTI_LINE_0
|
||||
* @arg @ref LL_EXTI_LINE_1
|
||||
* @arg @ref LL_EXTI_LINE_2
|
||||
* @arg @ref LL_EXTI_LINE_3
|
||||
* @arg @ref LL_EXTI_LINE_4
|
||||
* @arg @ref LL_EXTI_LINE_5
|
||||
* @arg @ref LL_EXTI_LINE_6
|
||||
* @arg @ref LL_EXTI_LINE_7
|
||||
* @arg @ref LL_EXTI_LINE_8
|
||||
* @arg @ref LL_EXTI_LINE_9
|
||||
* @arg @ref LL_EXTI_LINE_10
|
||||
* @arg @ref LL_EXTI_LINE_11
|
||||
* @arg @ref LL_EXTI_LINE_12
|
||||
* @arg @ref LL_EXTI_LINE_13
|
||||
* @arg @ref LL_EXTI_LINE_14
|
||||
* @arg @ref LL_EXTI_LINE_15
|
||||
* @arg @ref LL_EXTI_LINE_16
|
||||
* @arg @ref LL_EXTI_LINE_17
|
||||
* @arg @ref LL_EXTI_LINE_18
|
||||
* @arg @ref LL_EXTI_LINE_19
|
||||
* @arg @ref LL_EXTI_LINE_20
|
||||
* @arg @ref LL_EXTI_LINE_21
|
||||
* @arg @ref LL_EXTI_LINE_22
|
||||
* @arg @ref LL_EXTI_LINE_23
|
||||
* @arg @ref LL_EXTI_LINE_24(*)
|
||||
* @arg @ref LL_EXTI_LINE_ALL_0_31
|
||||
* @note (*): Available in some devices
|
||||
* @note Please check each device line mapping for EXTI Line availability
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine)
|
||||
{
|
||||
CLEAR_BIT(EXTI->IMR, ExtiLine);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31
|
||||
* @note The reset value for the direct or internal lines (see RM)
|
||||
* is set to 1 in order to enable the interrupt by default.
|
||||
* Bits are set automatically at Power on.
|
||||
* @rmtoll IMR IMx LL_EXTI_IsEnabledIT_0_31
|
||||
* @param ExtiLine This parameter can be one of the following values:
|
||||
* @arg @ref LL_EXTI_LINE_0
|
||||
* @arg @ref LL_EXTI_LINE_1
|
||||
* @arg @ref LL_EXTI_LINE_2
|
||||
* @arg @ref LL_EXTI_LINE_3
|
||||
* @arg @ref LL_EXTI_LINE_4
|
||||
* @arg @ref LL_EXTI_LINE_5
|
||||
* @arg @ref LL_EXTI_LINE_6
|
||||
* @arg @ref LL_EXTI_LINE_7
|
||||
* @arg @ref LL_EXTI_LINE_8
|
||||
* @arg @ref LL_EXTI_LINE_9
|
||||
* @arg @ref LL_EXTI_LINE_10
|
||||
* @arg @ref LL_EXTI_LINE_11
|
||||
* @arg @ref LL_EXTI_LINE_12
|
||||
* @arg @ref LL_EXTI_LINE_13
|
||||
* @arg @ref LL_EXTI_LINE_14
|
||||
* @arg @ref LL_EXTI_LINE_15
|
||||
* @arg @ref LL_EXTI_LINE_16
|
||||
* @arg @ref LL_EXTI_LINE_17
|
||||
* @arg @ref LL_EXTI_LINE_18
|
||||
* @arg @ref LL_EXTI_LINE_19
|
||||
* @arg @ref LL_EXTI_LINE_20
|
||||
* @arg @ref LL_EXTI_LINE_21
|
||||
* @arg @ref LL_EXTI_LINE_22
|
||||
* @arg @ref LL_EXTI_LINE_23
|
||||
* @arg @ref LL_EXTI_LINE_24(*)
|
||||
* @arg @ref LL_EXTI_LINE_ALL_0_31
|
||||
* @note (*): Available in some devices
|
||||
* @note Please check each device line mapping for EXTI Line availability
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine)
|
||||
{
|
||||
return (READ_BIT(EXTI->IMR, ExtiLine) == (ExtiLine));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_LL_EF_Event_Management Event_Management
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable ExtiLine Event request for Lines in range 0 to 31
|
||||
* @rmtoll EMR EMx LL_EXTI_EnableEvent_0_31
|
||||
* @param ExtiLine This parameter can be one of the following values:
|
||||
* @arg @ref LL_EXTI_LINE_0
|
||||
* @arg @ref LL_EXTI_LINE_1
|
||||
* @arg @ref LL_EXTI_LINE_2
|
||||
* @arg @ref LL_EXTI_LINE_3
|
||||
* @arg @ref LL_EXTI_LINE_4
|
||||
* @arg @ref LL_EXTI_LINE_5
|
||||
* @arg @ref LL_EXTI_LINE_6
|
||||
* @arg @ref LL_EXTI_LINE_7
|
||||
* @arg @ref LL_EXTI_LINE_8
|
||||
* @arg @ref LL_EXTI_LINE_9
|
||||
* @arg @ref LL_EXTI_LINE_10
|
||||
* @arg @ref LL_EXTI_LINE_11
|
||||
* @arg @ref LL_EXTI_LINE_12
|
||||
* @arg @ref LL_EXTI_LINE_13
|
||||
* @arg @ref LL_EXTI_LINE_14
|
||||
* @arg @ref LL_EXTI_LINE_15
|
||||
* @arg @ref LL_EXTI_LINE_16
|
||||
* @arg @ref LL_EXTI_LINE_17
|
||||
* @arg @ref LL_EXTI_LINE_18
|
||||
* @arg @ref LL_EXTI_LINE_19
|
||||
* @arg @ref LL_EXTI_LINE_20
|
||||
* @arg @ref LL_EXTI_LINE_21
|
||||
* @arg @ref LL_EXTI_LINE_22
|
||||
* @arg @ref LL_EXTI_LINE_23
|
||||
* @arg @ref LL_EXTI_LINE_24(*)
|
||||
* @arg @ref LL_EXTI_LINE_ALL_0_31
|
||||
* @note (*): Available in some devices
|
||||
* @note Please check each device line mapping for EXTI Line availability
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_EXTI_EnableEvent_0_31(uint32_t ExtiLine)
|
||||
{
|
||||
SET_BIT(EXTI->EMR, ExtiLine);
|
||||
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Disable ExtiLine Event request for Lines in range 0 to 31
|
||||
* @rmtoll EMR EMx LL_EXTI_DisableEvent_0_31
|
||||
* @param ExtiLine This parameter can be one of the following values:
|
||||
* @arg @ref LL_EXTI_LINE_0
|
||||
* @arg @ref LL_EXTI_LINE_1
|
||||
* @arg @ref LL_EXTI_LINE_2
|
||||
* @arg @ref LL_EXTI_LINE_3
|
||||
* @arg @ref LL_EXTI_LINE_4
|
||||
* @arg @ref LL_EXTI_LINE_5
|
||||
* @arg @ref LL_EXTI_LINE_6
|
||||
* @arg @ref LL_EXTI_LINE_7
|
||||
* @arg @ref LL_EXTI_LINE_8
|
||||
* @arg @ref LL_EXTI_LINE_9
|
||||
* @arg @ref LL_EXTI_LINE_10
|
||||
* @arg @ref LL_EXTI_LINE_11
|
||||
* @arg @ref LL_EXTI_LINE_12
|
||||
* @arg @ref LL_EXTI_LINE_13
|
||||
* @arg @ref LL_EXTI_LINE_14
|
||||
* @arg @ref LL_EXTI_LINE_15
|
||||
* @arg @ref LL_EXTI_LINE_16
|
||||
* @arg @ref LL_EXTI_LINE_17
|
||||
* @arg @ref LL_EXTI_LINE_18
|
||||
* @arg @ref LL_EXTI_LINE_19
|
||||
* @arg @ref LL_EXTI_LINE_20
|
||||
* @arg @ref LL_EXTI_LINE_21
|
||||
* @arg @ref LL_EXTI_LINE_22
|
||||
* @arg @ref LL_EXTI_LINE_23
|
||||
* @arg @ref LL_EXTI_LINE_24(*)
|
||||
* @arg @ref LL_EXTI_LINE_ALL_0_31
|
||||
* @note (*): Available in some devices
|
||||
* @note Please check each device line mapping for EXTI Line availability
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_EXTI_DisableEvent_0_31(uint32_t ExtiLine)
|
||||
{
|
||||
CLEAR_BIT(EXTI->EMR, ExtiLine);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31
|
||||
* @rmtoll EMR EMx LL_EXTI_IsEnabledEvent_0_31
|
||||
* @param ExtiLine This parameter can be one of the following values:
|
||||
* @arg @ref LL_EXTI_LINE_0
|
||||
* @arg @ref LL_EXTI_LINE_1
|
||||
* @arg @ref LL_EXTI_LINE_2
|
||||
* @arg @ref LL_EXTI_LINE_3
|
||||
* @arg @ref LL_EXTI_LINE_4
|
||||
* @arg @ref LL_EXTI_LINE_5
|
||||
* @arg @ref LL_EXTI_LINE_6
|
||||
* @arg @ref LL_EXTI_LINE_7
|
||||
* @arg @ref LL_EXTI_LINE_8
|
||||
* @arg @ref LL_EXTI_LINE_9
|
||||
* @arg @ref LL_EXTI_LINE_10
|
||||
* @arg @ref LL_EXTI_LINE_11
|
||||
* @arg @ref LL_EXTI_LINE_12
|
||||
* @arg @ref LL_EXTI_LINE_13
|
||||
* @arg @ref LL_EXTI_LINE_14
|
||||
* @arg @ref LL_EXTI_LINE_15
|
||||
* @arg @ref LL_EXTI_LINE_16
|
||||
* @arg @ref LL_EXTI_LINE_17
|
||||
* @arg @ref LL_EXTI_LINE_18
|
||||
* @arg @ref LL_EXTI_LINE_19
|
||||
* @arg @ref LL_EXTI_LINE_20
|
||||
* @arg @ref LL_EXTI_LINE_21
|
||||
* @arg @ref LL_EXTI_LINE_22
|
||||
* @arg @ref LL_EXTI_LINE_23
|
||||
* @arg @ref LL_EXTI_LINE_24(*)
|
||||
* @arg @ref LL_EXTI_LINE_ALL_0_31
|
||||
* @note (*): Available in some devices
|
||||
* @note Please check each device line mapping for EXTI Line availability
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine)
|
||||
{
|
||||
return (READ_BIT(EXTI->EMR, ExtiLine) == (ExtiLine));
|
||||
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_LL_EF_Rising_Trigger_Management Rising_Trigger_Management
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31
|
||||
* @note The configurable wakeup lines are edge-triggered. No glitch must be
|
||||
* generated on these lines. If a rising edge on a configurable interrupt
|
||||
* line occurs during a write operation in the EXTI_RTSR register, the
|
||||
* pending bit is not set.
|
||||
* Rising and falling edge triggers can be set for
|
||||
* the same interrupt line. In this case, both generate a trigger
|
||||
* condition.
|
||||
* @rmtoll RTSR RTx LL_EXTI_EnableRisingTrig_0_31
|
||||
* @param ExtiLine This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_EXTI_LINE_0
|
||||
* @arg @ref LL_EXTI_LINE_1
|
||||
* @arg @ref LL_EXTI_LINE_2
|
||||
* @arg @ref LL_EXTI_LINE_3
|
||||
* @arg @ref LL_EXTI_LINE_4
|
||||
* @arg @ref LL_EXTI_LINE_5
|
||||
* @arg @ref LL_EXTI_LINE_6
|
||||
* @arg @ref LL_EXTI_LINE_7
|
||||
* @arg @ref LL_EXTI_LINE_8
|
||||
* @arg @ref LL_EXTI_LINE_9
|
||||
* @arg @ref LL_EXTI_LINE_10
|
||||
* @arg @ref LL_EXTI_LINE_11
|
||||
* @arg @ref LL_EXTI_LINE_12
|
||||
* @arg @ref LL_EXTI_LINE_13
|
||||
* @arg @ref LL_EXTI_LINE_14
|
||||
* @arg @ref LL_EXTI_LINE_15
|
||||
* @arg @ref LL_EXTI_LINE_16
|
||||
* @arg @ref LL_EXTI_LINE_18
|
||||
* @arg @ref LL_EXTI_LINE_19
|
||||
* @arg @ref LL_EXTI_LINE_20
|
||||
* @arg @ref LL_EXTI_LINE_21
|
||||
* @arg @ref LL_EXTI_LINE_22
|
||||
* @note Please check each device line mapping for EXTI Line availability
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine)
|
||||
{
|
||||
SET_BIT(EXTI->RTSR, ExtiLine);
|
||||
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31
|
||||
* @note The configurable wakeup lines are edge-triggered. No glitch must be
|
||||
* generated on these lines. If a rising edge on a configurable interrupt
|
||||
* line occurs during a write operation in the EXTI_RTSR register, the
|
||||
* pending bit is not set.
|
||||
* Rising and falling edge triggers can be set for
|
||||
* the same interrupt line. In this case, both generate a trigger
|
||||
* condition.
|
||||
* @rmtoll RTSR RTx LL_EXTI_DisableRisingTrig_0_31
|
||||
* @param ExtiLine This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_EXTI_LINE_0
|
||||
* @arg @ref LL_EXTI_LINE_1
|
||||
* @arg @ref LL_EXTI_LINE_2
|
||||
* @arg @ref LL_EXTI_LINE_3
|
||||
* @arg @ref LL_EXTI_LINE_4
|
||||
* @arg @ref LL_EXTI_LINE_5
|
||||
* @arg @ref LL_EXTI_LINE_6
|
||||
* @arg @ref LL_EXTI_LINE_7
|
||||
* @arg @ref LL_EXTI_LINE_8
|
||||
* @arg @ref LL_EXTI_LINE_9
|
||||
* @arg @ref LL_EXTI_LINE_10
|
||||
* @arg @ref LL_EXTI_LINE_11
|
||||
* @arg @ref LL_EXTI_LINE_12
|
||||
* @arg @ref LL_EXTI_LINE_13
|
||||
* @arg @ref LL_EXTI_LINE_14
|
||||
* @arg @ref LL_EXTI_LINE_15
|
||||
* @arg @ref LL_EXTI_LINE_16
|
||||
* @arg @ref LL_EXTI_LINE_18
|
||||
* @arg @ref LL_EXTI_LINE_19
|
||||
* @arg @ref LL_EXTI_LINE_20
|
||||
* @arg @ref LL_EXTI_LINE_21
|
||||
* @arg @ref LL_EXTI_LINE_22
|
||||
* @note Please check each device line mapping for EXTI Line availability
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine)
|
||||
{
|
||||
CLEAR_BIT(EXTI->RTSR, ExtiLine);
|
||||
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Check if rising edge trigger is enabled for Lines in range 0 to 31
|
||||
* @rmtoll RTSR RTx LL_EXTI_IsEnabledRisingTrig_0_31
|
||||
* @param ExtiLine This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_EXTI_LINE_0
|
||||
* @arg @ref LL_EXTI_LINE_1
|
||||
* @arg @ref LL_EXTI_LINE_2
|
||||
* @arg @ref LL_EXTI_LINE_3
|
||||
* @arg @ref LL_EXTI_LINE_4
|
||||
* @arg @ref LL_EXTI_LINE_5
|
||||
* @arg @ref LL_EXTI_LINE_6
|
||||
* @arg @ref LL_EXTI_LINE_7
|
||||
* @arg @ref LL_EXTI_LINE_8
|
||||
* @arg @ref LL_EXTI_LINE_9
|
||||
* @arg @ref LL_EXTI_LINE_10
|
||||
* @arg @ref LL_EXTI_LINE_11
|
||||
* @arg @ref LL_EXTI_LINE_12
|
||||
* @arg @ref LL_EXTI_LINE_13
|
||||
* @arg @ref LL_EXTI_LINE_14
|
||||
* @arg @ref LL_EXTI_LINE_15
|
||||
* @arg @ref LL_EXTI_LINE_16
|
||||
* @arg @ref LL_EXTI_LINE_18
|
||||
* @arg @ref LL_EXTI_LINE_19
|
||||
* @arg @ref LL_EXTI_LINE_20
|
||||
* @arg @ref LL_EXTI_LINE_21
|
||||
* @arg @ref LL_EXTI_LINE_22
|
||||
* @note Please check each device line mapping for EXTI Line availability
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31(uint32_t ExtiLine)
|
||||
{
|
||||
return (READ_BIT(EXTI->RTSR, ExtiLine) == (ExtiLine));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_LL_EF_Falling_Trigger_Management Falling_Trigger_Management
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31
|
||||
* @note The configurable wakeup lines are edge-triggered. No glitch must be
|
||||
* generated on these lines. If a falling edge on a configurable interrupt
|
||||
* line occurs during a write operation in the EXTI_FTSR register, the
|
||||
* pending bit is not set.
|
||||
* Rising and falling edge triggers can be set for
|
||||
* the same interrupt line. In this case, both generate a trigger
|
||||
* condition.
|
||||
* @rmtoll FTSR FTx LL_EXTI_EnableFallingTrig_0_31
|
||||
* @param ExtiLine This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_EXTI_LINE_0
|
||||
* @arg @ref LL_EXTI_LINE_1
|
||||
* @arg @ref LL_EXTI_LINE_2
|
||||
* @arg @ref LL_EXTI_LINE_3
|
||||
* @arg @ref LL_EXTI_LINE_4
|
||||
* @arg @ref LL_EXTI_LINE_5
|
||||
* @arg @ref LL_EXTI_LINE_6
|
||||
* @arg @ref LL_EXTI_LINE_7
|
||||
* @arg @ref LL_EXTI_LINE_8
|
||||
* @arg @ref LL_EXTI_LINE_9
|
||||
* @arg @ref LL_EXTI_LINE_10
|
||||
* @arg @ref LL_EXTI_LINE_11
|
||||
* @arg @ref LL_EXTI_LINE_12
|
||||
* @arg @ref LL_EXTI_LINE_13
|
||||
* @arg @ref LL_EXTI_LINE_14
|
||||
* @arg @ref LL_EXTI_LINE_15
|
||||
* @arg @ref LL_EXTI_LINE_16
|
||||
* @arg @ref LL_EXTI_LINE_18
|
||||
* @arg @ref LL_EXTI_LINE_19
|
||||
* @arg @ref LL_EXTI_LINE_20
|
||||
* @arg @ref LL_EXTI_LINE_21
|
||||
* @arg @ref LL_EXTI_LINE_22
|
||||
* @note Please check each device line mapping for EXTI Line availability
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31(uint32_t ExtiLine)
|
||||
{
|
||||
SET_BIT(EXTI->FTSR, ExtiLine);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31
|
||||
* @note The configurable wakeup lines are edge-triggered. No glitch must be
|
||||
* generated on these lines. If a Falling edge on a configurable interrupt
|
||||
* line occurs during a write operation in the EXTI_FTSR register, the
|
||||
* pending bit is not set.
|
||||
* Rising and falling edge triggers can be set for the same interrupt line.
|
||||
* In this case, both generate a trigger condition.
|
||||
* @rmtoll FTSR FTx LL_EXTI_DisableFallingTrig_0_31
|
||||
* @param ExtiLine This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_EXTI_LINE_0
|
||||
* @arg @ref LL_EXTI_LINE_1
|
||||
* @arg @ref LL_EXTI_LINE_2
|
||||
* @arg @ref LL_EXTI_LINE_3
|
||||
* @arg @ref LL_EXTI_LINE_4
|
||||
* @arg @ref LL_EXTI_LINE_5
|
||||
* @arg @ref LL_EXTI_LINE_6
|
||||
* @arg @ref LL_EXTI_LINE_7
|
||||
* @arg @ref LL_EXTI_LINE_8
|
||||
* @arg @ref LL_EXTI_LINE_9
|
||||
* @arg @ref LL_EXTI_LINE_10
|
||||
* @arg @ref LL_EXTI_LINE_11
|
||||
* @arg @ref LL_EXTI_LINE_12
|
||||
* @arg @ref LL_EXTI_LINE_13
|
||||
* @arg @ref LL_EXTI_LINE_14
|
||||
* @arg @ref LL_EXTI_LINE_15
|
||||
* @arg @ref LL_EXTI_LINE_16
|
||||
* @arg @ref LL_EXTI_LINE_18
|
||||
* @arg @ref LL_EXTI_LINE_19
|
||||
* @arg @ref LL_EXTI_LINE_20
|
||||
* @arg @ref LL_EXTI_LINE_21
|
||||
* @arg @ref LL_EXTI_LINE_22
|
||||
* @note Please check each device line mapping for EXTI Line availability
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31(uint32_t ExtiLine)
|
||||
{
|
||||
CLEAR_BIT(EXTI->FTSR, ExtiLine);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Check if falling edge trigger is enabled for Lines in range 0 to 31
|
||||
* @rmtoll FTSR FTx LL_EXTI_IsEnabledFallingTrig_0_31
|
||||
* @param ExtiLine This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_EXTI_LINE_0
|
||||
* @arg @ref LL_EXTI_LINE_1
|
||||
* @arg @ref LL_EXTI_LINE_2
|
||||
* @arg @ref LL_EXTI_LINE_3
|
||||
* @arg @ref LL_EXTI_LINE_4
|
||||
* @arg @ref LL_EXTI_LINE_5
|
||||
* @arg @ref LL_EXTI_LINE_6
|
||||
* @arg @ref LL_EXTI_LINE_7
|
||||
* @arg @ref LL_EXTI_LINE_8
|
||||
* @arg @ref LL_EXTI_LINE_9
|
||||
* @arg @ref LL_EXTI_LINE_10
|
||||
* @arg @ref LL_EXTI_LINE_11
|
||||
* @arg @ref LL_EXTI_LINE_12
|
||||
* @arg @ref LL_EXTI_LINE_13
|
||||
* @arg @ref LL_EXTI_LINE_14
|
||||
* @arg @ref LL_EXTI_LINE_15
|
||||
* @arg @ref LL_EXTI_LINE_16
|
||||
* @arg @ref LL_EXTI_LINE_18
|
||||
* @arg @ref LL_EXTI_LINE_19
|
||||
* @arg @ref LL_EXTI_LINE_20
|
||||
* @arg @ref LL_EXTI_LINE_21
|
||||
* @arg @ref LL_EXTI_LINE_22
|
||||
* @note Please check each device line mapping for EXTI Line availability
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_0_31(uint32_t ExtiLine)
|
||||
{
|
||||
return (READ_BIT(EXTI->FTSR, ExtiLine) == (ExtiLine));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_LL_EF_Software_Interrupt_Management Software_Interrupt_Management
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Generate a software Interrupt Event for Lines in range 0 to 31
|
||||
* @note If the interrupt is enabled on this line in the EXTI_IMR, writing a 1 to
|
||||
* this bit when it is at '0' sets the corresponding pending bit in EXTI_PR
|
||||
* resulting in an interrupt request generation.
|
||||
* This bit is cleared by clearing the corresponding bit in the EXTI_PR
|
||||
* register (by writing a 1 into the bit)
|
||||
* @rmtoll SWIER SWIx LL_EXTI_GenerateSWI_0_31
|
||||
* @param ExtiLine This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_EXTI_LINE_0
|
||||
* @arg @ref LL_EXTI_LINE_1
|
||||
* @arg @ref LL_EXTI_LINE_2
|
||||
* @arg @ref LL_EXTI_LINE_3
|
||||
* @arg @ref LL_EXTI_LINE_4
|
||||
* @arg @ref LL_EXTI_LINE_5
|
||||
* @arg @ref LL_EXTI_LINE_6
|
||||
* @arg @ref LL_EXTI_LINE_7
|
||||
* @arg @ref LL_EXTI_LINE_8
|
||||
* @arg @ref LL_EXTI_LINE_9
|
||||
* @arg @ref LL_EXTI_LINE_10
|
||||
* @arg @ref LL_EXTI_LINE_11
|
||||
* @arg @ref LL_EXTI_LINE_12
|
||||
* @arg @ref LL_EXTI_LINE_13
|
||||
* @arg @ref LL_EXTI_LINE_14
|
||||
* @arg @ref LL_EXTI_LINE_15
|
||||
* @arg @ref LL_EXTI_LINE_16
|
||||
* @arg @ref LL_EXTI_LINE_18
|
||||
* @arg @ref LL_EXTI_LINE_19
|
||||
* @arg @ref LL_EXTI_LINE_20
|
||||
* @arg @ref LL_EXTI_LINE_21
|
||||
* @arg @ref LL_EXTI_LINE_22
|
||||
* @note Please check each device line mapping for EXTI Line availability
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_EXTI_GenerateSWI_0_31(uint32_t ExtiLine)
|
||||
{
|
||||
SET_BIT(EXTI->SWIER, ExtiLine);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_LL_EF_Flag_Management Flag_Management
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Check if the ExtLine Flag is set or not for Lines in range 0 to 31
|
||||
* @note This bit is set when the selected edge event arrives on the interrupt
|
||||
* line. This bit is cleared by writing a 1 to the bit.
|
||||
* @rmtoll PR PIFx LL_EXTI_IsActiveFlag_0_31
|
||||
* @param ExtiLine This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_EXTI_LINE_0
|
||||
* @arg @ref LL_EXTI_LINE_1
|
||||
* @arg @ref LL_EXTI_LINE_2
|
||||
* @arg @ref LL_EXTI_LINE_3
|
||||
* @arg @ref LL_EXTI_LINE_4
|
||||
* @arg @ref LL_EXTI_LINE_5
|
||||
* @arg @ref LL_EXTI_LINE_6
|
||||
* @arg @ref LL_EXTI_LINE_7
|
||||
* @arg @ref LL_EXTI_LINE_8
|
||||
* @arg @ref LL_EXTI_LINE_9
|
||||
* @arg @ref LL_EXTI_LINE_10
|
||||
* @arg @ref LL_EXTI_LINE_11
|
||||
* @arg @ref LL_EXTI_LINE_12
|
||||
* @arg @ref LL_EXTI_LINE_13
|
||||
* @arg @ref LL_EXTI_LINE_14
|
||||
* @arg @ref LL_EXTI_LINE_15
|
||||
* @arg @ref LL_EXTI_LINE_16
|
||||
* @arg @ref LL_EXTI_LINE_18
|
||||
* @arg @ref LL_EXTI_LINE_19
|
||||
* @arg @ref LL_EXTI_LINE_20
|
||||
* @arg @ref LL_EXTI_LINE_21
|
||||
* @arg @ref LL_EXTI_LINE_22
|
||||
* @note Please check each device line mapping for EXTI Line availability
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_0_31(uint32_t ExtiLine)
|
||||
{
|
||||
return (READ_BIT(EXTI->PR, ExtiLine) == (ExtiLine));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Read ExtLine Combination Flag for Lines in range 0 to 31
|
||||
* @note This bit is set when the selected edge event arrives on the interrupt
|
||||
* line. This bit is cleared by writing a 1 to the bit.
|
||||
* @rmtoll PR PIFx LL_EXTI_ReadFlag_0_31
|
||||
* @param ExtiLine This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_EXTI_LINE_0
|
||||
* @arg @ref LL_EXTI_LINE_1
|
||||
* @arg @ref LL_EXTI_LINE_2
|
||||
* @arg @ref LL_EXTI_LINE_3
|
||||
* @arg @ref LL_EXTI_LINE_4
|
||||
* @arg @ref LL_EXTI_LINE_5
|
||||
* @arg @ref LL_EXTI_LINE_6
|
||||
* @arg @ref LL_EXTI_LINE_7
|
||||
* @arg @ref LL_EXTI_LINE_8
|
||||
* @arg @ref LL_EXTI_LINE_9
|
||||
* @arg @ref LL_EXTI_LINE_10
|
||||
* @arg @ref LL_EXTI_LINE_11
|
||||
* @arg @ref LL_EXTI_LINE_12
|
||||
* @arg @ref LL_EXTI_LINE_13
|
||||
* @arg @ref LL_EXTI_LINE_14
|
||||
* @arg @ref LL_EXTI_LINE_15
|
||||
* @arg @ref LL_EXTI_LINE_16
|
||||
* @arg @ref LL_EXTI_LINE_18
|
||||
* @arg @ref LL_EXTI_LINE_19
|
||||
* @arg @ref LL_EXTI_LINE_20
|
||||
* @arg @ref LL_EXTI_LINE_21
|
||||
* @arg @ref LL_EXTI_LINE_22
|
||||
* @note Please check each device line mapping for EXTI Line availability
|
||||
* @retval @note This bit is set when the selected edge event arrives on the interrupt
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_EXTI_ReadFlag_0_31(uint32_t ExtiLine)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(EXTI->PR, ExtiLine));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Clear ExtLine Flags for Lines in range 0 to 31
|
||||
* @note This bit is set when the selected edge event arrives on the interrupt
|
||||
* line. This bit is cleared by writing a 1 to the bit.
|
||||
* @rmtoll PR PIFx LL_EXTI_ClearFlag_0_31
|
||||
* @param ExtiLine This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_EXTI_LINE_0
|
||||
* @arg @ref LL_EXTI_LINE_1
|
||||
* @arg @ref LL_EXTI_LINE_2
|
||||
* @arg @ref LL_EXTI_LINE_3
|
||||
* @arg @ref LL_EXTI_LINE_4
|
||||
* @arg @ref LL_EXTI_LINE_5
|
||||
* @arg @ref LL_EXTI_LINE_6
|
||||
* @arg @ref LL_EXTI_LINE_7
|
||||
* @arg @ref LL_EXTI_LINE_8
|
||||
* @arg @ref LL_EXTI_LINE_9
|
||||
* @arg @ref LL_EXTI_LINE_10
|
||||
* @arg @ref LL_EXTI_LINE_11
|
||||
* @arg @ref LL_EXTI_LINE_12
|
||||
* @arg @ref LL_EXTI_LINE_13
|
||||
* @arg @ref LL_EXTI_LINE_14
|
||||
* @arg @ref LL_EXTI_LINE_15
|
||||
* @arg @ref LL_EXTI_LINE_16
|
||||
* @arg @ref LL_EXTI_LINE_18
|
||||
* @arg @ref LL_EXTI_LINE_19
|
||||
* @arg @ref LL_EXTI_LINE_20
|
||||
* @arg @ref LL_EXTI_LINE_21
|
||||
* @arg @ref LL_EXTI_LINE_22
|
||||
* @note Please check each device line mapping for EXTI Line availability
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_EXTI_ClearFlag_0_31(uint32_t ExtiLine)
|
||||
{
|
||||
WRITE_REG(EXTI->PR, ExtiLine);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined(USE_FULL_LL_DRIVER)
|
||||
/** @defgroup EXTI_LL_EF_Init Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct);
|
||||
uint32_t LL_EXTI_DeInit(void);
|
||||
void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct);
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* USE_FULL_LL_DRIVER */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* EXTI */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F7xx_LL_EXTI_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,363 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_ll_iwdg.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.2
|
||||
* @date 14-April-2017
|
||||
* @brief Header file of IWDG LL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F7xx_LL_IWDG_H
|
||||
#define __STM32F7xx_LL_IWDG_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx.h"
|
||||
|
||||
/** @addtogroup STM32F7xx_LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(IWDG)
|
||||
|
||||
/** @defgroup IWDG_LL IWDG
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup IWDG_LL_Private_Constants IWDG Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define LL_IWDG_KEY_RELOAD 0x0000AAAAU /*!< IWDG Reload Counter Enable */
|
||||
#define LL_IWDG_KEY_ENABLE 0x0000CCCCU /*!< IWDG Peripheral Enable */
|
||||
#define LL_IWDG_KEY_WR_ACCESS_ENABLE 0x00005555U /*!< IWDG KR Write Access Enable */
|
||||
#define LL_IWDG_KEY_WR_ACCESS_DISABLE 0x00000000U /*!< IWDG KR Write Access Disable */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup IWDG_LL_Exported_Constants IWDG Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_LL_EC_GET_FLAG Get Flags Defines
|
||||
* @brief Flags defines which can be used with LL_IWDG_ReadReg function
|
||||
* @{
|
||||
*/
|
||||
#define LL_IWDG_SR_PVU IWDG_SR_PVU /*!< Watchdog prescaler value update */
|
||||
#define LL_IWDG_SR_RVU IWDG_SR_RVU /*!< Watchdog counter reload value update */
|
||||
#define LL_IWDG_SR_WVU IWDG_SR_WVU /*!< Watchdog counter window value update */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_LL_EC_PRESCALER Prescaler Divider
|
||||
* @{
|
||||
*/
|
||||
#define LL_IWDG_PRESCALER_4 0x00000000U /*!< Divider by 4 */
|
||||
#define LL_IWDG_PRESCALER_8 (IWDG_PR_PR_0) /*!< Divider by 8 */
|
||||
#define LL_IWDG_PRESCALER_16 (IWDG_PR_PR_1) /*!< Divider by 16 */
|
||||
#define LL_IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< Divider by 32 */
|
||||
#define LL_IWDG_PRESCALER_64 (IWDG_PR_PR_2) /*!< Divider by 64 */
|
||||
#define LL_IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< Divider by 128 */
|
||||
#define LL_IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< Divider by 256 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup IWDG_LL_Exported_Macros IWDG Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_LL_EM_WRITE_READ Common Write and read registers Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Write a value in IWDG register
|
||||
* @param __INSTANCE__ IWDG Instance
|
||||
* @param __REG__ Register to be written
|
||||
* @param __VALUE__ Value to be written in the register
|
||||
* @retval None
|
||||
*/
|
||||
#define LL_IWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
|
||||
|
||||
/**
|
||||
* @brief Read a value in IWDG register
|
||||
* @param __INSTANCE__ IWDG Instance
|
||||
* @param __REG__ Register to be read
|
||||
* @retval Register value
|
||||
*/
|
||||
#define LL_IWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup IWDG_LL_Exported_Functions IWDG Exported Functions
|
||||
* @{
|
||||
*/
|
||||
/** @defgroup IWDG_LL_EF_Configuration Configuration
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Start the Independent Watchdog
|
||||
* @note Except if the hardware watchdog option is selected
|
||||
* @rmtoll KR KEY LL_IWDG_Enable
|
||||
* @param IWDGx IWDG Instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_IWDG_Enable(IWDG_TypeDef *IWDGx)
|
||||
{
|
||||
WRITE_REG(IWDG->KR, LL_IWDG_KEY_ENABLE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reloads IWDG counter with value defined in the reload register
|
||||
* @rmtoll KR KEY LL_IWDG_ReloadCounter
|
||||
* @param IWDGx IWDG Instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_IWDG_ReloadCounter(IWDG_TypeDef *IWDGx)
|
||||
{
|
||||
WRITE_REG(IWDG->KR, LL_IWDG_KEY_RELOAD);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers
|
||||
* @rmtoll KR KEY LL_IWDG_EnableWriteAccess
|
||||
* @param IWDGx IWDG Instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_IWDG_EnableWriteAccess(IWDG_TypeDef *IWDGx)
|
||||
{
|
||||
WRITE_REG(IWDG->KR, LL_IWDG_KEY_WR_ACCESS_ENABLE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers
|
||||
* @rmtoll KR KEY LL_IWDG_DisableWriteAccess
|
||||
* @param IWDGx IWDG Instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_IWDG_DisableWriteAccess(IWDG_TypeDef *IWDGx)
|
||||
{
|
||||
WRITE_REG(IWDG->KR, LL_IWDG_KEY_WR_ACCESS_DISABLE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Select the prescaler of the IWDG
|
||||
* @rmtoll PR PR LL_IWDG_SetPrescaler
|
||||
* @param IWDGx IWDG Instance
|
||||
* @param Prescaler This parameter can be one of the following values:
|
||||
* @arg @ref LL_IWDG_PRESCALER_4
|
||||
* @arg @ref LL_IWDG_PRESCALER_8
|
||||
* @arg @ref LL_IWDG_PRESCALER_16
|
||||
* @arg @ref LL_IWDG_PRESCALER_32
|
||||
* @arg @ref LL_IWDG_PRESCALER_64
|
||||
* @arg @ref LL_IWDG_PRESCALER_128
|
||||
* @arg @ref LL_IWDG_PRESCALER_256
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_IWDG_SetPrescaler(IWDG_TypeDef *IWDGx, uint32_t Prescaler)
|
||||
{
|
||||
WRITE_REG(IWDGx->PR, IWDG_PR_PR & Prescaler);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the selected prescaler of the IWDG
|
||||
* @rmtoll PR PR LL_IWDG_GetPrescaler
|
||||
* @param IWDGx IWDG Instance
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref LL_IWDG_PRESCALER_4
|
||||
* @arg @ref LL_IWDG_PRESCALER_8
|
||||
* @arg @ref LL_IWDG_PRESCALER_16
|
||||
* @arg @ref LL_IWDG_PRESCALER_32
|
||||
* @arg @ref LL_IWDG_PRESCALER_64
|
||||
* @arg @ref LL_IWDG_PRESCALER_128
|
||||
* @arg @ref LL_IWDG_PRESCALER_256
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_IWDG_GetPrescaler(IWDG_TypeDef *IWDGx)
|
||||
{
|
||||
return (uint32_t)(READ_REG(IWDGx->PR));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Specify the IWDG down-counter reload value
|
||||
* @rmtoll RLR RL LL_IWDG_SetReloadCounter
|
||||
* @param IWDGx IWDG Instance
|
||||
* @param Counter Value between Min_Data=0 and Max_Data=0x0FFF
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_IWDG_SetReloadCounter(IWDG_TypeDef *IWDGx, uint32_t Counter)
|
||||
{
|
||||
WRITE_REG(IWDGx->RLR, IWDG_RLR_RL & Counter);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the specified IWDG down-counter reload value
|
||||
* @rmtoll RLR RL LL_IWDG_GetReloadCounter
|
||||
* @param IWDGx IWDG Instance
|
||||
* @retval Value between Min_Data=0 and Max_Data=0x0FFF
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_IWDG_GetReloadCounter(IWDG_TypeDef *IWDGx)
|
||||
{
|
||||
return (uint32_t)(READ_REG(IWDGx->RLR));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Specify high limit of the window value to be compared to the down-counter.
|
||||
* @rmtoll WINR WIN LL_IWDG_SetWindow
|
||||
* @param IWDGx IWDG Instance
|
||||
* @param Window Value between Min_Data=0 and Max_Data=0x0FFF
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_IWDG_SetWindow(IWDG_TypeDef *IWDGx, uint32_t Window)
|
||||
{
|
||||
WRITE_REG(IWDGx->WINR, IWDG_WINR_WIN & Window);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the high limit of the window value specified.
|
||||
* @rmtoll WINR WIN LL_IWDG_GetWindow
|
||||
* @param IWDGx IWDG Instance
|
||||
* @retval Value between Min_Data=0 and Max_Data=0x0FFF
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_IWDG_GetWindow(IWDG_TypeDef *IWDGx)
|
||||
{
|
||||
return (uint32_t)(READ_REG(IWDGx->WINR));
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_LL_EF_FLAG_Management FLAG_Management
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Check if flag Prescaler Value Update is set or not
|
||||
* @rmtoll SR PVU LL_IWDG_IsActiveFlag_PVU
|
||||
* @param IWDGx IWDG Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(IWDG_TypeDef *IWDGx)
|
||||
{
|
||||
return (READ_BIT(IWDGx->SR, IWDG_SR_PVU) == (IWDG_SR_PVU));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if flag Reload Value Update is set or not
|
||||
* @rmtoll SR RVU LL_IWDG_IsActiveFlag_RVU
|
||||
* @param IWDGx IWDG Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(IWDG_TypeDef *IWDGx)
|
||||
{
|
||||
return (READ_BIT(IWDGx->SR, IWDG_SR_RVU) == (IWDG_SR_RVU));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if flag Window Value Update is set or not
|
||||
* @rmtoll SR WVU LL_IWDG_IsActiveFlag_WVU
|
||||
* @param IWDGx IWDG Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_WVU(IWDG_TypeDef *IWDGx)
|
||||
{
|
||||
return (READ_BIT(IWDGx->SR, IWDG_SR_WVU) == (IWDG_SR_WVU));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if all flags Prescaler, Reload & Window Value Update are reset or not
|
||||
* @rmtoll SR PVU LL_IWDG_IsReady\n
|
||||
* SR WVU LL_IWDG_IsReady\n
|
||||
* SR RVU LL_IWDG_IsReady
|
||||
* @param IWDGx IWDG Instance
|
||||
* @retval State of bits (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_IWDG_IsReady(IWDG_TypeDef *IWDGx)
|
||||
{
|
||||
return (READ_BIT(IWDGx->SR, IWDG_SR_PVU | IWDG_SR_RVU | IWDG_SR_WVU) == 0U);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* IWDG) */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F7xx_LL_IWDG_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,355 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_ll_rng.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.2
|
||||
* @date 14-April-2017
|
||||
* @brief Header file of RNG LL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F7xx_LL_RNG_H
|
||||
#define __STM32F7xx_LL_RNG_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx.h"
|
||||
|
||||
/** @addtogroup STM32F7xx_LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(RNG)
|
||||
|
||||
/** @defgroup RNG_LL RNG
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup RNG_LL_Exported_Constants RNG Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup RNG_LL_EC_GET_FLAG Get Flags Defines
|
||||
* @brief Flags defines which can be used with LL_RNG_ReadReg function
|
||||
* @{
|
||||
*/
|
||||
#define LL_RNG_SR_DRDY RNG_SR_DRDY /*!< Register contains valid random data */
|
||||
#define LL_RNG_SR_CECS RNG_SR_CECS /*!< Clock error current status */
|
||||
#define LL_RNG_SR_SECS RNG_SR_SECS /*!< Seed error current status */
|
||||
#define LL_RNG_SR_CEIS RNG_SR_CEIS /*!< Clock error interrupt status */
|
||||
#define LL_RNG_SR_SEIS RNG_SR_SEIS /*!< Seed error interrupt status */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RNG_LL_EC_IT IT Defines
|
||||
* @brief IT defines which can be used with LL_RNG_ReadReg and LL_RNG_WriteReg macros
|
||||
* @{
|
||||
*/
|
||||
#define LL_RNG_CR_IE RNG_CR_IE /*!< RNG Interrupt enable */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup RNG_LL_Exported_Macros RNG Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup RNG_LL_EM_WRITE_READ Common Write and read registers Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Write a value in RNG register
|
||||
* @param __INSTANCE__ RNG Instance
|
||||
* @param __REG__ Register to be written
|
||||
* @param __VALUE__ Value to be written in the register
|
||||
* @retval None
|
||||
*/
|
||||
#define LL_RNG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
|
||||
|
||||
/**
|
||||
* @brief Read a value in RNG register
|
||||
* @param __INSTANCE__ RNG Instance
|
||||
* @param __REG__ Register to be read
|
||||
* @retval Register value
|
||||
*/
|
||||
#define LL_RNG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup RNG_LL_Exported_Functions RNG Exported Functions
|
||||
* @{
|
||||
*/
|
||||
/** @defgroup RNG_LL_EF_Configuration RNG Configuration functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable Random Number Generation
|
||||
* @rmtoll CR RNGEN LL_RNG_Enable
|
||||
* @param RNGx RNG Instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_RNG_Enable(RNG_TypeDef *RNGx)
|
||||
{
|
||||
SET_BIT(RNGx->CR, RNG_CR_RNGEN);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable Random Number Generation
|
||||
* @rmtoll CR RNGEN LL_RNG_Disable
|
||||
* @param RNGx RNG Instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_RNG_Disable(RNG_TypeDef *RNGx)
|
||||
{
|
||||
CLEAR_BIT(RNGx->CR, RNG_CR_RNGEN);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if Random Number Generator is enabled
|
||||
* @rmtoll CR RNGEN LL_RNG_IsEnabled
|
||||
* @param RNGx RNG Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_RNG_IsEnabled(RNG_TypeDef *RNGx)
|
||||
{
|
||||
return (READ_BIT(RNGx->CR, RNG_CR_RNGEN) == (RNG_CR_RNGEN));
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RNG_LL_EF_FLAG_Management FLAG Management
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Indicate if the RNG Data ready Flag is set or not
|
||||
* @rmtoll SR DRDY LL_RNG_IsActiveFlag_DRDY
|
||||
* @param RNGx RNG Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_DRDY(RNG_TypeDef *RNGx)
|
||||
{
|
||||
return (READ_BIT(RNGx->SR, RNG_SR_DRDY) == (RNG_SR_DRDY));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Indicate if the Clock Error Current Status Flag is set or not
|
||||
* @rmtoll SR CECS LL_RNG_IsActiveFlag_CECS
|
||||
* @param RNGx RNG Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CECS(RNG_TypeDef *RNGx)
|
||||
{
|
||||
return (READ_BIT(RNGx->SR, RNG_SR_CECS) == (RNG_SR_CECS));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Indicate if the Seed Error Current Status Flag is set or not
|
||||
* @rmtoll SR SECS LL_RNG_IsActiveFlag_SECS
|
||||
* @param RNGx RNG Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SECS(RNG_TypeDef *RNGx)
|
||||
{
|
||||
return (READ_BIT(RNGx->SR, RNG_SR_SECS) == (RNG_SR_SECS));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Indicate if the Clock Error Interrupt Status Flag is set or not
|
||||
* @rmtoll SR CEIS LL_RNG_IsActiveFlag_CEIS
|
||||
* @param RNGx RNG Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CEIS(RNG_TypeDef *RNGx)
|
||||
{
|
||||
return (READ_BIT(RNGx->SR, RNG_SR_CEIS) == (RNG_SR_CEIS));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Indicate if the Seed Error Interrupt Status Flag is set or not
|
||||
* @rmtoll SR SEIS LL_RNG_IsActiveFlag_SEIS
|
||||
* @param RNGx RNG Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SEIS(RNG_TypeDef *RNGx)
|
||||
{
|
||||
return (READ_BIT(RNGx->SR, RNG_SR_SEIS) == (RNG_SR_SEIS));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear Clock Error interrupt Status (CEIS) Flag
|
||||
* @rmtoll SR CEIS LL_RNG_ClearFlag_CEIS
|
||||
* @param RNGx RNG Instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_RNG_ClearFlag_CEIS(RNG_TypeDef *RNGx)
|
||||
{
|
||||
WRITE_REG(RNGx->SR, ~RNG_SR_CEIS);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear Seed Error interrupt Status (SEIS) Flag
|
||||
* @rmtoll SR SEIS LL_RNG_ClearFlag_SEIS
|
||||
* @param RNGx RNG Instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_RNG_ClearFlag_SEIS(RNG_TypeDef *RNGx)
|
||||
{
|
||||
WRITE_REG(RNGx->SR, ~RNG_SR_SEIS);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RNG_LL_EF_IT_Management IT Management
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable Random Number Generator Interrupt
|
||||
* (applies for either Seed error, Clock Error or Data ready interrupts)
|
||||
* @rmtoll CR IE LL_RNG_EnableIT
|
||||
* @param RNGx RNG Instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_RNG_EnableIT(RNG_TypeDef *RNGx)
|
||||
{
|
||||
SET_BIT(RNGx->CR, RNG_CR_IE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable Random Number Generator Interrupt
|
||||
* (applies for either Seed error, Clock Error or Data ready interrupts)
|
||||
* @rmtoll CR IE LL_RNG_DisableIT
|
||||
* @param RNGx RNG Instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_RNG_DisableIT(RNG_TypeDef *RNGx)
|
||||
{
|
||||
CLEAR_BIT(RNGx->CR, RNG_CR_IE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if Random Number Generator Interrupt is enabled
|
||||
* (applies for either Seed error, Clock Error or Data ready interrupts)
|
||||
* @rmtoll CR IE LL_RNG_IsEnabledIT
|
||||
* @param RNGx RNG Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_RNG_IsEnabledIT(RNG_TypeDef *RNGx)
|
||||
{
|
||||
return (READ_BIT(RNGx->CR, RNG_CR_IE) == (RNG_CR_IE));
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RNG_LL_EF_Data_Management Data Management
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Return32-bit Random Number value
|
||||
* @rmtoll DR RNDATA LL_RNG_ReadRandData32
|
||||
* @param RNGx RNG Instance
|
||||
* @retval Generated 32-bit random value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_RNG_ReadRandData32(RNG_TypeDef *RNGx)
|
||||
{
|
||||
return (uint32_t)(READ_REG(RNGx->DR));
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined(USE_FULL_LL_DRIVER)
|
||||
/** @defgroup RNG_LL_EF_Init Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
ErrorStatus LL_RNG_DeInit(RNG_TypeDef *RNGx);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* USE_FULL_LL_DRIVER */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* defined(RNG) */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F7xx_LL_RNG_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,474 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_ll_usb.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.2
|
||||
* @date 14-April-2017
|
||||
* @brief Header file of USB Core HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F7xx_LL_USB_H
|
||||
#define __STM32F7xx_LL_USB_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F7xx_HAL
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup USB_Core
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief USB Mode definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
USB_OTG_DEVICE_MODE = 0U,
|
||||
USB_OTG_HOST_MODE = 1U,
|
||||
USB_OTG_DRD_MODE = 2U
|
||||
|
||||
}USB_OTG_ModeTypeDef;
|
||||
|
||||
/**
|
||||
* @brief URB States definition
|
||||
*/
|
||||
typedef enum {
|
||||
URB_IDLE = 0U,
|
||||
URB_DONE,
|
||||
URB_NOTREADY,
|
||||
URB_NYET,
|
||||
URB_ERROR,
|
||||
URB_STALL
|
||||
|
||||
}USB_OTG_URBStateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief Host channel States definition
|
||||
*/
|
||||
typedef enum {
|
||||
HC_IDLE = 0U,
|
||||
HC_XFRC,
|
||||
HC_HALTED,
|
||||
HC_NAK,
|
||||
HC_NYET,
|
||||
HC_STALL,
|
||||
HC_XACTERR,
|
||||
HC_BBLERR,
|
||||
HC_DATATGLERR
|
||||
|
||||
}USB_OTG_HCStateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief PCD Initialization Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t dev_endpoints; /*!< Device Endpoints number.
|
||||
This parameter depends on the used USB core.
|
||||
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
|
||||
|
||||
uint32_t Host_channels; /*!< Host Channels number.
|
||||
This parameter Depends on the used USB core.
|
||||
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
|
||||
|
||||
uint32_t speed; /*!< USB Core speed.
|
||||
This parameter can be any value of @ref USB_Core_Speed_ */
|
||||
|
||||
uint32_t dma_enable; /*!< Enable or disable of the USB embedded DMA. */
|
||||
|
||||
uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size.
|
||||
This parameter can be any value of @ref USB_EP0_MPS_ */
|
||||
|
||||
uint32_t phy_itface; /*!< Select the used PHY interface.
|
||||
This parameter can be any value of @ref USB_Core_PHY_ */
|
||||
|
||||
uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */
|
||||
|
||||
uint32_t low_power_enable; /*!< Enable or disable the low power mode. */
|
||||
|
||||
uint32_t lpm_enable; /*!< Enable or disable Link Power Management. */
|
||||
|
||||
uint32_t battery_charging_enable; /*!< Enable or disable Battery charging. */
|
||||
|
||||
uint32_t vbus_sensing_enable; /*!< Enable or disable the VBUS Sensing feature. */
|
||||
|
||||
uint32_t use_dedicated_ep1; /*!< Enable or disable the use of the dedicated EP1 interrupt. */
|
||||
|
||||
uint32_t use_external_vbus; /*!< Enable or disable the use of the external VBUS. */
|
||||
|
||||
}USB_OTG_CfgTypeDef;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint8_t num; /*!< Endpoint number
|
||||
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
|
||||
|
||||
uint8_t is_in; /*!< Endpoint direction
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
|
||||
|
||||
uint8_t is_stall; /*!< Endpoint stall condition
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
|
||||
|
||||
uint8_t type; /*!< Endpoint type
|
||||
This parameter can be any value of @ref USB_EP_Type_ */
|
||||
|
||||
uint8_t data_pid_start; /*!< Initial data PID
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
|
||||
|
||||
uint8_t even_odd_frame; /*!< IFrame parity
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
|
||||
|
||||
uint16_t tx_fifo_num; /*!< Transmission FIFO number
|
||||
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
|
||||
|
||||
uint32_t maxpacket; /*!< Endpoint Max packet size
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */
|
||||
|
||||
uint8_t *xfer_buff; /*!< Pointer to transfer buffer */
|
||||
|
||||
uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address */
|
||||
|
||||
uint32_t xfer_len; /*!< Current transfer length */
|
||||
|
||||
uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */
|
||||
|
||||
}USB_OTG_EPTypeDef;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint8_t dev_addr ; /*!< USB device address.
|
||||
This parameter must be a number between Min_Data = 1 and Max_Data = 255 */
|
||||
|
||||
uint8_t ch_num; /*!< Host channel number.
|
||||
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
|
||||
|
||||
uint8_t ep_num; /*!< Endpoint number.
|
||||
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
|
||||
|
||||
uint8_t ep_is_in; /*!< Endpoint direction
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
|
||||
|
||||
uint8_t speed; /*!< USB Host speed.
|
||||
This parameter can be any value of @ref USB_Core_Speed_ */
|
||||
|
||||
uint8_t do_ping; /*!< Enable or disable the use of the PING protocol for HS mode. */
|
||||
|
||||
uint8_t process_ping; /*!< Execute the PING protocol for HS mode. */
|
||||
|
||||
uint8_t ep_type; /*!< Endpoint Type.
|
||||
This parameter can be any value of @ref USB_EP_Type_ */
|
||||
|
||||
uint16_t max_packet; /*!< Endpoint Max packet size.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */
|
||||
|
||||
uint8_t data_pid; /*!< Initial data PID.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
|
||||
|
||||
uint8_t *xfer_buff; /*!< Pointer to transfer buffer. */
|
||||
|
||||
uint32_t xfer_len; /*!< Current transfer length. */
|
||||
|
||||
uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer. */
|
||||
|
||||
uint8_t toggle_in; /*!< IN transfer current toggle flag.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
|
||||
|
||||
uint8_t toggle_out; /*!< OUT transfer current toggle flag
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
|
||||
|
||||
uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address. */
|
||||
|
||||
uint32_t ErrCnt; /*!< Host channel error count.*/
|
||||
|
||||
USB_OTG_URBStateTypeDef urb_state; /*!< URB state.
|
||||
This parameter can be any value of @ref USB_OTG_URBStateTypeDef */
|
||||
|
||||
USB_OTG_HCStateTypeDef state; /*!< Host Channel state.
|
||||
This parameter can be any value of @ref USB_OTG_HCStateTypeDef */
|
||||
|
||||
}USB_OTG_HCTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup PCD_Exported_Constants PCD Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup USB_Core_Mode_ USB Core Mode
|
||||
* @{
|
||||
*/
|
||||
#define USB_OTG_MODE_DEVICE 0U
|
||||
#define USB_OTG_MODE_HOST 1U
|
||||
#define USB_OTG_MODE_DRD 2U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_Core_Speed_ USB Core Speed
|
||||
* @{
|
||||
*/
|
||||
#define USB_OTG_SPEED_HIGH 0U
|
||||
#define USB_OTG_SPEED_HIGH_IN_FULL 1U
|
||||
#define USB_OTG_SPEED_LOW 2U
|
||||
#define USB_OTG_SPEED_FULL 3U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_Core_PHY_ USB Core PHY
|
||||
* @{
|
||||
*/
|
||||
#define USB_OTG_ULPI_PHY 1U
|
||||
#define USB_OTG_EMBEDDED_PHY 2U
|
||||
#define USB_OTG_HS_EMBEDDED_PHY 3U
|
||||
|
||||
#if !defined (USB_HS_PHYC_TUNE_VALUE)
|
||||
#define USB_HS_PHYC_TUNE_VALUE 0x00000F13U /*!< Value of USB HS PHY Tune */
|
||||
#endif /* USB_HS_PHYC_TUNE_VALUE */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_Core_MPS_ USB Core MPS
|
||||
* @{
|
||||
*/
|
||||
#define USB_OTG_HS_MAX_PACKET_SIZE 512U
|
||||
#define USB_OTG_FS_MAX_PACKET_SIZE 64U
|
||||
#define USB_OTG_MAX_EP0_SIZE 64U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_Core_Phy_Frequency_ USB Core Phy Frequency
|
||||
* @{
|
||||
*/
|
||||
#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ (0 << 1)
|
||||
#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ (1 << 1)
|
||||
#define DSTS_ENUMSPD_LS_PHY_6MHZ (2 << 1)
|
||||
#define DSTS_ENUMSPD_FS_PHY_48MHZ (3 << 1)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_CORE_Frame_Interval_ USB CORE Frame Interval
|
||||
* @{
|
||||
*/
|
||||
#define DCFG_FRAME_INTERVAL_80 0U
|
||||
#define DCFG_FRAME_INTERVAL_85 1U
|
||||
#define DCFG_FRAME_INTERVAL_90 2U
|
||||
#define DCFG_FRAME_INTERVAL_95 3U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_EP0_MPS_ USB EP0 MPS
|
||||
* @{
|
||||
*/
|
||||
#define DEP0CTL_MPS_64 0U
|
||||
#define DEP0CTL_MPS_32 1U
|
||||
#define DEP0CTL_MPS_16 2U
|
||||
#define DEP0CTL_MPS_8 3U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_EP_Speed_ USB EP Speed
|
||||
* @{
|
||||
*/
|
||||
#define EP_SPEED_LOW 0U
|
||||
#define EP_SPEED_FULL 1U
|
||||
#define EP_SPEED_HIGH 2U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_EP_Type_ USB EP Type
|
||||
* @{
|
||||
*/
|
||||
#define EP_TYPE_CTRL 0U
|
||||
#define EP_TYPE_ISOC 1U
|
||||
#define EP_TYPE_BULK 2U
|
||||
#define EP_TYPE_INTR 3U
|
||||
#define EP_TYPE_MSK 3U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_STS_Defines_ USB STS Defines
|
||||
* @{
|
||||
*/
|
||||
#define STS_GOUT_NAK 1U
|
||||
#define STS_DATA_UPDT 2U
|
||||
#define STS_XFER_COMP 3U
|
||||
#define STS_SETUP_COMP 4U
|
||||
#define STS_SETUP_UPDT 6U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HCFG_SPEED_Defines_ HCFG SPEED Defines
|
||||
* @{
|
||||
*/
|
||||
#define HCFG_30_60_MHZ 0U
|
||||
#define HCFG_48_MHZ 1U
|
||||
#define HCFG_6_MHZ 2U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HPRT0_PRTSPD_SPEED_Defines_ HPRT0 PRTSPD SPEED Defines
|
||||
* @{
|
||||
*/
|
||||
#define HPRT0_PRTSPD_HIGH_SPEED 0U
|
||||
#define HPRT0_PRTSPD_FULL_SPEED 1U
|
||||
#define HPRT0_PRTSPD_LOW_SPEED 2U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#define HCCHAR_CTRL 0U
|
||||
#define HCCHAR_ISOC 1U
|
||||
#define HCCHAR_BULK 2U
|
||||
#define HCCHAR_INTR 3U
|
||||
|
||||
#define HC_PID_DATA0 0U
|
||||
#define HC_PID_DATA2 1U
|
||||
#define HC_PID_DATA1 2U
|
||||
#define HC_PID_SETUP 3U
|
||||
|
||||
#define GRXSTS_PKTSTS_IN 2U
|
||||
#define GRXSTS_PKTSTS_IN_XFER_COMP 3U
|
||||
#define GRXSTS_PKTSTS_DATA_TOGGLE_ERR 5U
|
||||
#define GRXSTS_PKTSTS_CH_HALTED 7U
|
||||
|
||||
#define USBx_PCGCCTL *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_PCGCCTL_BASE)
|
||||
#define USBx_HPRT0 *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_HOST_PORT_BASE)
|
||||
|
||||
#define USBx_DEVICE ((USB_OTG_DeviceTypeDef *)((uint32_t )USBx + USB_OTG_DEVICE_BASE))
|
||||
#define USBx_INEP(i) ((USB_OTG_INEndpointTypeDef *)((uint32_t)USBx + USB_OTG_IN_ENDPOINT_BASE + (i)*USB_OTG_EP_REG_SIZE))
|
||||
#define USBx_OUTEP(i) ((USB_OTG_OUTEndpointTypeDef *)((uint32_t)USBx + USB_OTG_OUT_ENDPOINT_BASE + (i)*USB_OTG_EP_REG_SIZE))
|
||||
#define USBx_DFIFO(i) *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_FIFO_BASE + (i) * USB_OTG_FIFO_SIZE)
|
||||
|
||||
#define USBx_HOST ((USB_OTG_HostTypeDef *)((uint32_t )USBx + USB_OTG_HOST_BASE))
|
||||
#define USBx_HC(i) ((USB_OTG_HostChannelTypeDef *)((uint32_t)USBx + USB_OTG_HOST_CHANNEL_BASE + (i)*USB_OTG_HOST_CHANNEL_SIZE))
|
||||
#define USBPHYC ((USBPHYC_GlobalTypeDef *)((uint32_t )USB_PHY_HS_CONTROLLER_BASE))
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
#define USB_MASK_INTERRUPT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->GINTMSK &= ~(__INTERRUPT__))
|
||||
#define USB_UNMASK_INTERRUPT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->GINTMSK |= (__INTERRUPT__))
|
||||
|
||||
#define CLEAR_IN_EP_INTR(__EPNUM__, __INTERRUPT__) (USBx_INEP(__EPNUM__)->DIEPINT = (__INTERRUPT__))
|
||||
#define CLEAR_OUT_EP_INTR(__EPNUM__, __INTERRUPT__) (USBx_OUTEP(__EPNUM__)->DOEPINT = (__INTERRUPT__))
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef Init);
|
||||
HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef Init);
|
||||
HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx);
|
||||
HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx);
|
||||
HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx , USB_OTG_ModeTypeDef mode);
|
||||
HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx , uint8_t speed);
|
||||
HAL_StatusTypeDef USB_FlushRxFifo (USB_OTG_GlobalTypeDef *USBx);
|
||||
HAL_StatusTypeDef USB_FlushTxFifo (USB_OTG_GlobalTypeDef *USBx, uint32_t num );
|
||||
HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
|
||||
HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
|
||||
HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
|
||||
HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
|
||||
HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma);
|
||||
HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma);
|
||||
HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t dma);
|
||||
void * USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len);
|
||||
HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep);
|
||||
HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep);
|
||||
HAL_StatusTypeDef USB_SetDevAddress (USB_OTG_GlobalTypeDef *USBx, uint8_t address);
|
||||
HAL_StatusTypeDef USB_DevConnect (USB_OTG_GlobalTypeDef *USBx);
|
||||
HAL_StatusTypeDef USB_DevDisconnect (USB_OTG_GlobalTypeDef *USBx);
|
||||
HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx);
|
||||
HAL_StatusTypeDef USB_ActivateSetup (USB_OTG_GlobalTypeDef *USBx);
|
||||
HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uint8_t *psetup);
|
||||
uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx);
|
||||
uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx);
|
||||
uint32_t USB_ReadInterrupts (USB_OTG_GlobalTypeDef *USBx);
|
||||
uint32_t USB_ReadDevAllOutEpInterrupt (USB_OTG_GlobalTypeDef *USBx);
|
||||
uint32_t USB_ReadDevOutEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum);
|
||||
uint32_t USB_ReadDevAllInEpInterrupt (USB_OTG_GlobalTypeDef *USBx);
|
||||
uint32_t USB_ReadDevInEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum);
|
||||
void USB_ClearInterrupts (USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt);
|
||||
|
||||
HAL_StatusTypeDef USB_HostInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg);
|
||||
HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx , uint8_t freq);
|
||||
HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx);
|
||||
HAL_StatusTypeDef USB_DriveVbus (USB_OTG_GlobalTypeDef *USBx, uint8_t state);
|
||||
uint32_t USB_GetHostSpeed (USB_OTG_GlobalTypeDef *USBx);
|
||||
uint32_t USB_GetCurrentFrame (USB_OTG_GlobalTypeDef *USBx);
|
||||
HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx,
|
||||
uint8_t ch_num,
|
||||
uint8_t epnum,
|
||||
uint8_t dev_address,
|
||||
uint8_t speed,
|
||||
uint8_t ep_type,
|
||||
uint16_t mps);
|
||||
HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc, uint8_t dma);
|
||||
uint32_t USB_HC_ReadInterrupt (USB_OTG_GlobalTypeDef *USBx);
|
||||
HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx , uint8_t hc_num);
|
||||
HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx , uint8_t ch_num);
|
||||
HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* __STM32F7xx_LL_USB_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,323 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_ll_utils.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.2
|
||||
* @date 14-April-2017
|
||||
* @brief Header file of UTILS LL module.
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
The LL UTILS driver contains a set of generic APIs that can be
|
||||
used by user:
|
||||
(+) Device electronic signature
|
||||
(+) Timing functions
|
||||
(+) PLL configuration functions
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F7xx_LL_UTILS_H
|
||||
#define __STM32F7xx_LL_UTILS_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx.h"
|
||||
|
||||
/** @addtogroup STM32F7xx_LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup UTILS_LL UTILS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup UTILS_LL_Private_Constants UTILS Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Max delay can be used in LL_mDelay */
|
||||
#define LL_MAX_DELAY 0xFFFFFFFFU
|
||||
|
||||
/**
|
||||
* @brief Unique device ID register base address
|
||||
*/
|
||||
#define UID_BASE_ADDRESS UID_BASE
|
||||
|
||||
/**
|
||||
* @brief Flash size data register base address
|
||||
*/
|
||||
#define FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE
|
||||
|
||||
/**
|
||||
* @brief Package data register base address
|
||||
*/
|
||||
#define PACKAGE_BASE_ADDRESS PACKAGE_BASE
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup UTILS_LL_Private_Macros UTILS Private Macros
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup UTILS_LL_ES_INIT UTILS Exported structures
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief UTILS PLL structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t PLLM; /*!< Division factor for PLL VCO input clock.
|
||||
This parameter can be a value of @ref RCC_LL_EC_PLLM_DIV
|
||||
|
||||
This feature can be modified afterwards using unitary function
|
||||
@ref LL_RCC_PLL_ConfigDomain_SYS(). */
|
||||
|
||||
uint32_t PLLN; /*!< Multiplication factor for PLL VCO output clock.
|
||||
This parameter must be a number between Min_Data = 50 and Max_Data = 432
|
||||
|
||||
This feature can be modified afterwards using unitary function
|
||||
@ref LL_RCC_PLL_ConfigDomain_SYS(). */
|
||||
|
||||
uint32_t PLLP; /*!< Division for the main system clock.
|
||||
This parameter can be a value of @ref RCC_LL_EC_PLLP_DIV
|
||||
|
||||
This feature can be modified afterwards using unitary function
|
||||
@ref LL_RCC_PLL_ConfigDomain_SYS(). */
|
||||
} LL_UTILS_PLLInitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief UTILS System, AHB and APB buses clock configuration structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
|
||||
This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV
|
||||
|
||||
This feature can be modified afterwards using unitary function
|
||||
@ref LL_RCC_SetAHBPrescaler(). */
|
||||
|
||||
uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
|
||||
This parameter can be a value of @ref RCC_LL_EC_APB1_DIV
|
||||
|
||||
This feature can be modified afterwards using unitary function
|
||||
@ref LL_RCC_SetAPB1Prescaler(). */
|
||||
|
||||
uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
|
||||
This parameter can be a value of @ref RCC_LL_EC_APB2_DIV
|
||||
|
||||
This feature can be modified afterwards using unitary function
|
||||
@ref LL_RCC_SetAPB2Prescaler(). */
|
||||
|
||||
} LL_UTILS_ClkInitTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation
|
||||
* @{
|
||||
*/
|
||||
#define LL_UTILS_HSEBYPASS_OFF 0x00000000U /*!< HSE Bypass is not enabled */
|
||||
#define LL_UTILS_HSEBYPASS_ON 0x00000001U /*!< HSE Bypass is enabled */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup UTILS_EC_PACKAGETYPE PACKAGE TYPE
|
||||
* @{
|
||||
*/
|
||||
#define LL_UTILS_PACKAGETYPE_LQFP100 0x00000100U /*!< LQFP100 package type */
|
||||
#define LL_UTILS_PACKAGETYPE_LQFP144_WLCSP143 0x00000200U /*!< LQFP144 or WLCSP143 package type */
|
||||
#define LL_UTILS_PACKAGETYPE_WLCSP180_LQFP176_UFBGA176 0x00000300U /*!< WLCSP180, LQFP176 or UFBGA176 package type */
|
||||
#define LL_UTILS_PACKAGETYPE_LQFP176_LQFP208_TFBGA216 0x00000400U /*!< LQFP176, LQFP208 or TFBGA216 package type */
|
||||
#define LL_UTILS_PACKAGETYPE_TFBGA216_LQFP176_LQFP208 0x00000500U /*!< LQFP176, LQFP208 or TFBGA216 package type */
|
||||
#define LL_UTILS_PACKAGETYPE_LQFP176_TFBGA216_LQFP208 0x00000600U /*!< LQFP176, LQFP208 or TFBGA216 package type */
|
||||
#define LL_UTILS_PACKAGETYPE_LQFP208_LQFP176_TFBGA216 0x00000700U /*!< LQFP176, LQFP208 or TFBGA216 package type */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Get Word0 of the unique device identifier (UID based on 96 bits)
|
||||
* @retval UID[31:0]
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_GetUID_Word0(void)
|
||||
{
|
||||
return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS)));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Word1 of the unique device identifier (UID based on 96 bits)
|
||||
* @retval UID[63:32]
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_GetUID_Word1(void)
|
||||
{
|
||||
return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U))));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Word2 of the unique device identifier (UID based on 96 bits)
|
||||
* @retval UID[95:64]
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_GetUID_Word2(void)
|
||||
{
|
||||
return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U))));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Flash memory size
|
||||
* @note This bitfield indicates the size of the device Flash memory expressed in
|
||||
* Kbytes. As an example, 0x040 corresponds to 64 Kbytes.
|
||||
* @retval FLASH_SIZE[15:0]: Flash memory size
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_GetFlashSize(void)
|
||||
{
|
||||
return (uint16_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Package type
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref LL_UTILS_PACKAGETYPE_LQFP100
|
||||
* @arg @ref LL_UTILS_PACKAGETYPE_LQFP144_WLCSP143 (*)
|
||||
* @arg @ref LL_UTILS_PACKAGETYPE_WLCSP180_LQFP176_UFBGA176 (*)
|
||||
* @arg @ref LL_UTILS_PACKAGETYPE_LQFP176_LQFP208_TFBGA216 (*)
|
||||
*
|
||||
* (*) value not defined in all devices.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_GetPackageType(void)
|
||||
{
|
||||
return (uint16_t)(READ_REG(*((uint32_t *)PACKAGE_BASE_ADDRESS)) & 0x0700U);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup UTILS_LL_EF_DELAY DELAY
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief This function configures the Cortex-M SysTick source of the time base.
|
||||
* @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
|
||||
* @note When a RTOS is used, it is recommended to avoid changing the SysTick
|
||||
* configuration by calling this function, for a delay use rather osDelay RTOS service.
|
||||
* @param Ticks Number of ticks
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
|
||||
{
|
||||
/* Configure the SysTick to have interrupt in 1ms time base */
|
||||
SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */
|
||||
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
|
||||
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
||||
SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */
|
||||
}
|
||||
|
||||
void LL_Init1msTick(uint32_t HCLKFrequency);
|
||||
void LL_mDelay(uint32_t Delay);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup UTILS_EF_SYSTEM SYSTEM
|
||||
* @{
|
||||
*/
|
||||
|
||||
void LL_SetSystemCoreClock(uint32_t HCLKFrequency);
|
||||
ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
|
||||
LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
|
||||
ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
|
||||
LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F7xx_LL_UTILS_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,342 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_ll_wwdg.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.2
|
||||
* @date 14-April-2017
|
||||
* @brief Header file of WWDG LL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F7xx_LL_WWDG_H
|
||||
#define __STM32F7xx_LL_WWDG_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx.h"
|
||||
|
||||
/** @addtogroup STM32F7xx_LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined (WWDG)
|
||||
|
||||
/** @defgroup WWDG_LL WWDG
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup WWDG_LL_Exported_Constants WWDG Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup WWDG_LL_EC_IT IT Defines
|
||||
* @brief IT defines which can be used with LL_WWDG_ReadReg and LL_WWDG_WriteReg functions
|
||||
* @{
|
||||
*/
|
||||
#define LL_WWDG_CFR_EWI WWDG_CFR_EWI
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup WWDG_LL_EC_PRESCALER PRESCALER
|
||||
* @{
|
||||
*/
|
||||
#define LL_WWDG_PRESCALER_1 0x00000000U /*!< WWDG counter clock = (PCLK1/4096)/1 */
|
||||
#define LL_WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0 /*!< WWDG counter clock = (PCLK1/4096)/2 */
|
||||
#define LL_WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1 /*!< WWDG counter clock = (PCLK1/4096)/4 */
|
||||
#define LL_WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_0 | WWDG_CFR_WDGTB_1) /*!< WWDG counter clock = (PCLK1/4096)/8 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup WWDG_LL_Exported_Macros WWDG Exported Macros
|
||||
* @{
|
||||
*/
|
||||
/** @defgroup WWDG_LL_EM_WRITE_READ Common Write and read registers macros
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Write a value in WWDG register
|
||||
* @param __INSTANCE__ WWDG Instance
|
||||
* @param __REG__ Register to be written
|
||||
* @param __VALUE__ Value to be written in the register
|
||||
* @retval None
|
||||
*/
|
||||
#define LL_WWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
|
||||
|
||||
/**
|
||||
* @brief Read a value in WWDG register
|
||||
* @param __INSTANCE__ WWDG Instance
|
||||
* @param __REG__ Register to be read
|
||||
* @retval Register value
|
||||
*/
|
||||
#define LL_WWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup WWDG_LL_Exported_Functions WWDG Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup WWDG_LL_EF_Configuration Configuration
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Enable Window Watchdog. The watchdog is always disabled after a reset.
|
||||
* @note It is enabled by setting the WDGA bit in the WWDG_CR register,
|
||||
* then it cannot be disabled again except by a reset.
|
||||
* This bit is set by software and only cleared by hardware after a reset.
|
||||
* When WDGA = 1, the watchdog can generate a reset.
|
||||
* @rmtoll CR WDGA LL_WWDG_Enable
|
||||
* @param WWDGx WWDG Instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_WWDG_Enable(WWDG_TypeDef *WWDGx)
|
||||
{
|
||||
SET_BIT(WWDGx->CR, WWDG_CR_WDGA);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks if Window Watchdog is enabled
|
||||
* @rmtoll CR WDGA LL_WWDG_IsEnabled
|
||||
* @param WWDGx WWDG Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_WWDG_IsEnabled(WWDG_TypeDef *WWDGx)
|
||||
{
|
||||
return (READ_BIT(WWDGx->CR, WWDG_CR_WDGA) == (WWDG_CR_WDGA));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the Watchdog counter value to provided value (7-bits T[6:0])
|
||||
* @note When writing to the WWDG_CR register, always write 1 in the MSB b6 to avoid generating an immediate reset
|
||||
* This counter is decremented every (4096 x 2expWDGTB) PCLK cycles
|
||||
* A reset is produced when it rolls over from 0x40 to 0x3F (bit T6 becomes cleared)
|
||||
* Setting the counter lower then 0x40 causes an immediate reset (if WWDG enabled)
|
||||
* @rmtoll CR T LL_WWDG_SetCounter
|
||||
* @param WWDGx WWDG Instance
|
||||
* @param Counter 0..0x7F (7 bit counter value)
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_WWDG_SetCounter(WWDG_TypeDef *WWDGx, uint32_t Counter)
|
||||
{
|
||||
MODIFY_REG(WWDGx->CR, WWDG_CR_T, Counter);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return current Watchdog Counter Value (7 bits counter value)
|
||||
* @rmtoll CR T LL_WWDG_GetCounter
|
||||
* @param WWDGx WWDG Instance
|
||||
* @retval 7 bit Watchdog Counter value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_WWDG_GetCounter(WWDG_TypeDef *WWDGx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(WWDGx->CR, WWDG_CR_T));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the time base of the prescaler (WDGTB).
|
||||
* @note Prescaler is used to apply ratio on PCLK clock, so that Watchdog counter
|
||||
* is decremented every (4096 x 2expWDGTB) PCLK cycles
|
||||
* @rmtoll CFR WDGTB LL_WWDG_SetPrescaler
|
||||
* @param WWDGx WWDG Instance
|
||||
* @param Prescaler This parameter can be one of the following values:
|
||||
* @arg @ref LL_WWDG_PRESCALER_1
|
||||
* @arg @ref LL_WWDG_PRESCALER_2
|
||||
* @arg @ref LL_WWDG_PRESCALER_4
|
||||
* @arg @ref LL_WWDG_PRESCALER_8
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_WWDG_SetPrescaler(WWDG_TypeDef *WWDGx, uint32_t Prescaler)
|
||||
{
|
||||
MODIFY_REG(WWDGx->CFR, WWDG_CFR_WDGTB, Prescaler);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return current Watchdog Prescaler Value
|
||||
* @rmtoll CFR WDGTB LL_WWDG_GetPrescaler
|
||||
* @param WWDGx WWDG Instance
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref LL_WWDG_PRESCALER_1
|
||||
* @arg @ref LL_WWDG_PRESCALER_2
|
||||
* @arg @ref LL_WWDG_PRESCALER_4
|
||||
* @arg @ref LL_WWDG_PRESCALER_8
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_WWDG_GetPrescaler(WWDG_TypeDef *WWDGx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(WWDGx->CFR, WWDG_CFR_WDGTB));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the Watchdog Window value to be compared to the downcounter (7-bits W[6:0]).
|
||||
* @note This window value defines when write in the WWDG_CR register
|
||||
* to program Watchdog counter is allowed.
|
||||
* Watchdog counter value update must occur only when the counter value
|
||||
* is lower than the Watchdog window register value.
|
||||
* Otherwise, a MCU reset is generated if the 7-bit Watchdog counter value
|
||||
* (in the control register) is refreshed before the downcounter has reached
|
||||
* the watchdog window register value.
|
||||
* Physically is possible to set the Window lower then 0x40 but it is not recommended.
|
||||
* To generate an immediate reset, it is possible to set the Counter lower than 0x40.
|
||||
* @rmtoll CFR W LL_WWDG_SetWindow
|
||||
* @param WWDGx WWDG Instance
|
||||
* @param Window 0x00..0x7F (7 bit Window value)
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_WWDG_SetWindow(WWDG_TypeDef *WWDGx, uint32_t Window)
|
||||
{
|
||||
MODIFY_REG(WWDGx->CFR, WWDG_CFR_W, Window);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return current Watchdog Window Value (7 bits value)
|
||||
* @rmtoll CFR W LL_WWDG_GetWindow
|
||||
* @param WWDGx WWDG Instance
|
||||
* @retval 7 bit Watchdog Window value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_WWDG_GetWindow(WWDG_TypeDef *WWDGx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(WWDGx->CFR, WWDG_CFR_W));
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup WWDG_LL_EF_FLAG_Management FLAG_Management
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Indicates if the WWDG Early Wakeup Interrupt Flag is set or not.
|
||||
* @note This bit is set by hardware when the counter has reached the value 0x40.
|
||||
* It must be cleared by software by writing 0.
|
||||
* A write of 1 has no effect. This bit is also set if the interrupt is not enabled.
|
||||
* @rmtoll SR EWIF LL_WWDG_IsActiveFlag_EWKUP
|
||||
* @param WWDGx WWDG Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_WWDG_IsActiveFlag_EWKUP(WWDG_TypeDef *WWDGx)
|
||||
{
|
||||
return (READ_BIT(WWDGx->SR, WWDG_SR_EWIF) == (WWDG_SR_EWIF));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear WWDG Early Wakeup Interrupt Flag (EWIF)
|
||||
* @rmtoll SR EWIF LL_WWDG_ClearFlag_EWKUP
|
||||
* @param WWDGx WWDG Instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_WWDG_ClearFlag_EWKUP(WWDG_TypeDef *WWDGx)
|
||||
{
|
||||
WRITE_REG(WWDGx->SR, ~WWDG_SR_EWIF);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup WWDG_LL_EF_IT_Management IT_Management
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Enable the Early Wakeup Interrupt.
|
||||
* @note When set, an interrupt occurs whenever the counter reaches value 0x40.
|
||||
* This interrupt is only cleared by hardware after a reset
|
||||
* @rmtoll CFR EWI LL_WWDG_EnableIT_EWKUP
|
||||
* @param WWDGx WWDG Instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_WWDG_EnableIT_EWKUP(WWDG_TypeDef *WWDGx)
|
||||
{
|
||||
SET_BIT(WWDGx->CFR, WWDG_CFR_EWI);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if Early Wakeup Interrupt is enabled
|
||||
* @rmtoll CFR EWI LL_WWDG_IsEnabledIT_EWKUP
|
||||
* @param WWDGx WWDG Instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_WWDG_IsEnabledIT_EWKUP(WWDG_TypeDef *WWDGx)
|
||||
{
|
||||
return (READ_BIT(WWDGx->CFR, WWDG_CFR_EWI) == (WWDG_CFR_EWI));
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* WWDG */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F7xx_LL_WWDG_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,536 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_hal.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.2
|
||||
* @date 14-April-2017
|
||||
* @brief HAL module driver.
|
||||
* This is the common part of the HAL initialization
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
The common HAL driver contains a set of generic and common APIs that can be
|
||||
used by the PPP peripheral drivers and the user to start using the HAL.
|
||||
[..]
|
||||
The HAL contains two APIs' categories:
|
||||
(+) Common HAL APIs
|
||||
(+) Services HAL APIs
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup HAL HAL
|
||||
* @brief HAL module driver.
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/** @addtogroup HAL_Private_Constants
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief STM32F7xx HAL Driver version number V1.2.2
|
||||
*/
|
||||
#define __STM32F7xx_HAL_VERSION_MAIN (0x01) /*!< [31:24] main version */
|
||||
#define __STM32F7xx_HAL_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
|
||||
#define __STM32F7xx_HAL_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */
|
||||
#define __STM32F7xx_HAL_VERSION_RC (0x00) /*!< [7:0] release candidate */
|
||||
#define __STM32F7xx_HAL_VERSION ((__STM32F7xx_HAL_VERSION_MAIN << 24)\
|
||||
|(__STM32F7xx_HAL_VERSION_SUB1 << 16)\
|
||||
|(__STM32F7xx_HAL_VERSION_SUB2 << 8 )\
|
||||
|(__STM32F7xx_HAL_VERSION_RC))
|
||||
|
||||
#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/** @addtogroup HAL_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
__IO uint32_t uwTick;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup HAL_Exported_Functions HAL Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions
|
||||
* @brief Initialization and de-initialization functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization and de-initialization functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Initializes the Flash interface the NVIC allocation and initial clock
|
||||
configuration. It initializes the systick also when timeout is needed
|
||||
and the backup domain when enabled.
|
||||
(+) de-Initializes common part of the HAL
|
||||
(+) Configure The time base source to have 1ms time base with a dedicated
|
||||
Tick interrupt priority.
|
||||
(++) Systick timer is used by default as source of time base, but user
|
||||
can eventually implement his proper time base source (a general purpose
|
||||
timer for example or other time source), keeping in mind that Time base
|
||||
duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and
|
||||
handled in milliseconds basis.
|
||||
(++) Time base configuration function (HAL_InitTick ()) is called automatically
|
||||
at the beginning of the program after reset by HAL_Init() or at any time
|
||||
when clock is configured, by HAL_RCC_ClockConfig().
|
||||
(++) Source of time base is configured to generate interrupts at regular
|
||||
time intervals. Care must be taken if HAL_Delay() is called from a
|
||||
peripheral ISR process, the Tick interrupt line must have higher priority
|
||||
(numerically lower) than the peripheral interrupt. Otherwise the caller
|
||||
ISR process will be blocked.
|
||||
(++) functions affecting time base configurations are declared as __weak
|
||||
to make override possible in case of other implementations in user file.
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief This function is used to initialize the HAL Library; it must be the first
|
||||
* instruction to be executed in the main program (before to call any other
|
||||
* HAL function), it performs the following:
|
||||
* Configure the Flash prefetch, and instruction cache through ART accelerator.
|
||||
* Configures the SysTick to generate an interrupt each 1 millisecond,
|
||||
* which is clocked by the HSI (at this stage, the clock is not yet
|
||||
* configured and thus the system is running from the internal HSI at 16 MHz).
|
||||
* Set NVIC Group Priority to 4.
|
||||
* Calls the HAL_MspInit() callback function defined in user file
|
||||
* "stm32f7xx_hal_msp.c" to do the global low level hardware initialization
|
||||
*
|
||||
* @note SysTick is used as time base for the HAL_Delay() function, the application
|
||||
* need to ensure that the SysTick time base is always set to 1 millisecond
|
||||
* to have correct HAL operation.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_Init(void)
|
||||
{
|
||||
/* Configure Flash prefetch and Instruction cache through ART accelerator */
|
||||
#if (ART_ACCLERATOR_ENABLE != 0)
|
||||
__HAL_FLASH_ART_ENABLE();
|
||||
#endif /* ART_ACCLERATOR_ENABLE */
|
||||
|
||||
/* Set Interrupt Group Priority */
|
||||
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
|
||||
|
||||
/* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
|
||||
HAL_InitTick(TICK_INT_PRIORITY);
|
||||
|
||||
/* Init the low level hardware */
|
||||
HAL_MspInit();
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function de-Initializes common part of the HAL and stops the systick.
|
||||
* This function is optional.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DeInit(void)
|
||||
{
|
||||
/* Reset of all peripherals */
|
||||
__HAL_RCC_APB1_FORCE_RESET();
|
||||
__HAL_RCC_APB1_RELEASE_RESET();
|
||||
|
||||
__HAL_RCC_APB2_FORCE_RESET();
|
||||
__HAL_RCC_APB2_RELEASE_RESET();
|
||||
|
||||
__HAL_RCC_AHB1_FORCE_RESET();
|
||||
__HAL_RCC_AHB1_RELEASE_RESET();
|
||||
|
||||
__HAL_RCC_AHB2_FORCE_RESET();
|
||||
__HAL_RCC_AHB2_RELEASE_RESET();
|
||||
|
||||
__HAL_RCC_AHB3_FORCE_RESET();
|
||||
__HAL_RCC_AHB3_RELEASE_RESET();
|
||||
|
||||
/* De-Init the low level hardware */
|
||||
HAL_MspDeInit();
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the MSP.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_MspInit(void)
|
||||
{
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_MspInit could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DeInitializes the MSP.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_MspDeInit(void)
|
||||
{
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_MspDeInit could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function configures the source of the time base.
|
||||
* The time source is configured to have 1ms time base with a dedicated
|
||||
* Tick interrupt priority.
|
||||
* @note This function is called automatically at the beginning of program after
|
||||
* reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig().
|
||||
* @note In the default implementation, SysTick timer is the source of time base.
|
||||
* It is used to generate interrupts at regular time intervals.
|
||||
* Care must be taken if HAL_Delay() is called from a peripheral ISR process,
|
||||
* The the SysTick interrupt must have higher priority (numerically lower)
|
||||
* than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
|
||||
* The function is declared as __weak to be overwritten in case of other
|
||||
* implementation in user file.
|
||||
* @param TickPriority: Tick interrupt priority.
|
||||
* @retval HAL status
|
||||
*/
|
||||
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
|
||||
{
|
||||
/*Configure the SysTick to have interrupt in 1ms time basis*/
|
||||
HAL_SYSTICK_Config(SystemCoreClock/1000);
|
||||
|
||||
/*Configure the SysTick IRQ priority */
|
||||
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority ,0);
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions
|
||||
* @brief HAL Control functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### HAL Control functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Provide a tick value in millisecond
|
||||
(+) Provide a blocking delay in millisecond
|
||||
(+) Suspend the time base source interrupt
|
||||
(+) Resume the time base source interrupt
|
||||
(+) Get the HAL API driver version
|
||||
(+) Get the device identifier
|
||||
(+) Get the device revision identifier
|
||||
(+) Enable/Disable Debug module during SLEEP mode
|
||||
(+) Enable/Disable Debug module during STOP mode
|
||||
(+) Enable/Disable Debug module during STANDBY mode
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief This function is called to increment a global variable "uwTick"
|
||||
* used as application time base.
|
||||
* @note In the default implementation, this variable is incremented each 1ms
|
||||
* in Systick ISR.
|
||||
* @note This function is declared as __weak to be overwritten in case of other
|
||||
* implementations in user file.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_IncTick(void)
|
||||
{
|
||||
uwTick++;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Provides a tick value in millisecond.
|
||||
* @note This function is declared as __weak to be overwritten in case of other
|
||||
* implementations in user file.
|
||||
* @retval tick value
|
||||
*/
|
||||
__weak uint32_t HAL_GetTick(void)
|
||||
{
|
||||
return uwTick;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function provides accurate delay (in milliseconds) based
|
||||
* on variable incremented.
|
||||
* @note In the default implementation , SysTick timer is the source of time base.
|
||||
* It is used to generate interrupts at regular time intervals where uwTick
|
||||
* is incremented.
|
||||
* @note This function is declared as __weak to be overwritten in case of other
|
||||
* implementations in user file.
|
||||
* @param Delay: specifies the delay time length, in milliseconds.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_Delay(__IO uint32_t Delay)
|
||||
{
|
||||
uint32_t tickstart = 0;
|
||||
tickstart = HAL_GetTick();
|
||||
while((HAL_GetTick() - tickstart) < Delay)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Suspend Tick increment.
|
||||
* @note In the default implementation , SysTick timer is the source of time base. It is
|
||||
* used to generate interrupts at regular time intervals. Once HAL_SuspendTick()
|
||||
* is called, the SysTick interrupt will be disabled and so Tick increment
|
||||
* is suspended.
|
||||
* @note This function is declared as __weak to be overwritten in case of other
|
||||
* implementations in user file.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_SuspendTick(void)
|
||||
{
|
||||
/* Disable SysTick Interrupt */
|
||||
SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Resume Tick increment.
|
||||
* @note In the default implementation , SysTick timer is the source of time base. It is
|
||||
* used to generate interrupts at regular time intervals. Once HAL_ResumeTick()
|
||||
* is called, the SysTick interrupt will be enabled and so Tick increment
|
||||
* is resumed.
|
||||
* @note This function is declared as __weak to be overwritten in case of other
|
||||
* implementations in user file.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_ResumeTick(void)
|
||||
{
|
||||
/* Enable SysTick Interrupt */
|
||||
SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the HAL revision
|
||||
* @retval version : 0xXYZR (8bits for each decimal, R for RC)
|
||||
*/
|
||||
uint32_t HAL_GetHalVersion(void)
|
||||
{
|
||||
return __STM32F7xx_HAL_VERSION;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the device revision identifier.
|
||||
* @retval Device revision identifier
|
||||
*/
|
||||
uint32_t HAL_GetREVID(void)
|
||||
{
|
||||
return((DBGMCU->IDCODE) >> 16U);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the device identifier.
|
||||
* @retval Device identifier
|
||||
*/
|
||||
uint32_t HAL_GetDEVID(void)
|
||||
{
|
||||
return((DBGMCU->IDCODE) & IDCODE_DEVID_MASK);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the Debug Module during SLEEP mode
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_DBGMCU_EnableDBGSleepMode(void)
|
||||
{
|
||||
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the Debug Module during SLEEP mode
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_DBGMCU_DisableDBGSleepMode(void)
|
||||
{
|
||||
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the Debug Module during STOP mode
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_DBGMCU_EnableDBGStopMode(void)
|
||||
{
|
||||
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the Debug Module during STOP mode
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_DBGMCU_DisableDBGStopMode(void)
|
||||
{
|
||||
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the Debug Module during STANDBY mode
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_DBGMCU_EnableDBGStandbyMode(void)
|
||||
{
|
||||
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the Debug Module during STANDBY mode
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_DBGMCU_DisableDBGStandbyMode(void)
|
||||
{
|
||||
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables the I/O Compensation Cell.
|
||||
* @note The I/O compensation cell can be used only when the device supply
|
||||
* voltage ranges from 2.4 to 3.6 V.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_EnableCompensationCell(void)
|
||||
{
|
||||
SYSCFG->CMPCR |= SYSCFG_CMPCR_CMP_PD;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Power-down the I/O Compensation Cell.
|
||||
* @note The I/O compensation cell can be used only when the device supply
|
||||
* voltage ranges from 2.4 to 3.6 V.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_DisableCompensationCell(void)
|
||||
{
|
||||
SYSCFG->CMPCR &= (uint32_t)~((uint32_t)SYSCFG_CMPCR_CMP_PD);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables the FMC Memory Mapping Swapping.
|
||||
*
|
||||
* @note SDRAM is accessible at 0x60000000
|
||||
* and NOR/RAM is accessible at 0xC0000000
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_EnableFMCMemorySwapping(void)
|
||||
{
|
||||
SYSCFG->MEMRMP |= SYSCFG_MEMRMP_SWP_FMC_0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables the FMC Memory Mapping Swapping
|
||||
*
|
||||
* @note SDRAM is accessible at 0xC0000000 (default mapping)
|
||||
* and NOR/RAM is accessible at 0x60000000 (default mapping)
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_DisableFMCMemorySwapping(void)
|
||||
{
|
||||
|
||||
SYSCFG->MEMRMP &= (uint32_t)~((uint32_t)SYSCFG_MEMRMP_SWP_FMC);
|
||||
}
|
||||
|
||||
#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
|
||||
/**
|
||||
* @brief Enable the Internal FLASH Bank Swapping.
|
||||
*
|
||||
* @note This function can be used only for STM32F77xx/STM32F76xx devices.
|
||||
*
|
||||
* @note Flash Bank2 mapped at 0x08000000 (AXI) (aliased at 0x00200000 (TCM))
|
||||
* and Flash Bank1 mapped at 0x08100000 (AXI) (aliased at 0x00300000 (TCM))
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_EnableMemorySwappingBank(void)
|
||||
{
|
||||
SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FB);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the Internal FLASH Bank Swapping.
|
||||
*
|
||||
* @note This function can be used only for STM32F77xx/STM32F76xx devices.
|
||||
*
|
||||
* @note The default state : Flash Bank1 mapped at 0x08000000 (AXI) (aliased at 0x00200000 (TCM))
|
||||
* and Flash Bank2 mapped at 0x08100000 (AXI)( aliased at 0x00300000 (TCM))
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_DisableMemorySwappingBank(void)
|
||||
{
|
||||
CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FB);
|
||||
}
|
||||
#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user