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This commit is contained in:
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@@ -0,0 +1,161 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file Project/STM32F4xx_StdPeriph_Templates/stm32f4xx_conf.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.7.1
|
||||
* @date 20-May-2016
|
||||
* @brief Library configuration file.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F4xx_CONF_H
|
||||
#define __STM32F4xx_CONF_H
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
/* Uncomment the line below to enable peripheral header file inclusion */
|
||||
#include "stm32f4xx_adc.h"
|
||||
#include "stm32f4xx_crc.h"
|
||||
#include "stm32f4xx_dbgmcu.h"
|
||||
#include "stm32f4xx_dma.h"
|
||||
#include "stm32f4xx_exti.h"
|
||||
#include "stm32f4xx_flash.h"
|
||||
#include "stm32f4xx_gpio.h"
|
||||
#include "stm32f4xx_i2c.h"
|
||||
#include "stm32f4xx_iwdg.h"
|
||||
#include "stm32f4xx_pwr.h"
|
||||
#include "stm32f4xx_rcc.h"
|
||||
#include "stm32f4xx_rtc.h"
|
||||
#include "stm32f4xx_sdio.h"
|
||||
#include "stm32f4xx_spi.h"
|
||||
#include "stm32f4xx_syscfg.h"
|
||||
#include "stm32f4xx_tim.h"
|
||||
#include "stm32f4xx_usart.h"
|
||||
#include "stm32f4xx_wwdg.h"
|
||||
#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
|
||||
|
||||
#if defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
|
||||
#include "stm32f4xx_cryp.h"
|
||||
#include "stm32f4xx_hash.h"
|
||||
#include "stm32f4xx_rng.h"
|
||||
#include "stm32f4xx_can.h"
|
||||
#include "stm32f4xx_dac.h"
|
||||
#include "stm32f4xx_dcmi.h"
|
||||
#include "stm32f4xx_dma2d.h"
|
||||
#include "stm32f4xx_fmc.h"
|
||||
#include "stm32f4xx_ltdc.h"
|
||||
#include "stm32f4xx_sai.h"
|
||||
#endif /* STM32F429_439xx || STM32F446xx || STM32F469_479xx */
|
||||
|
||||
#if defined(STM32F427_437xx)
|
||||
#include "stm32f4xx_cryp.h"
|
||||
#include "stm32f4xx_hash.h"
|
||||
#include "stm32f4xx_rng.h"
|
||||
#include "stm32f4xx_can.h"
|
||||
#include "stm32f4xx_dac.h"
|
||||
#include "stm32f4xx_dcmi.h"
|
||||
#include "stm32f4xx_dma2d.h"
|
||||
#include "stm32f4xx_fmc.h"
|
||||
#include "stm32f4xx_sai.h"
|
||||
#endif /* STM32F427_437xx */
|
||||
|
||||
#if defined(STM32F40_41xxx)
|
||||
#include "stm32f4xx_cryp.h"
|
||||
#include "stm32f4xx_hash.h"
|
||||
#include "stm32f4xx_rng.h"
|
||||
#include "stm32f4xx_can.h"
|
||||
#include "stm32f4xx_dac.h"
|
||||
#include "stm32f4xx_dcmi.h"
|
||||
#include "stm32f4xx_fsmc.h"
|
||||
#endif /* STM32F40_41xxx */
|
||||
|
||||
#if defined(STM32F410xx)
|
||||
#include "stm32f4xx_rng.h"
|
||||
#include "stm32f4xx_dac.h"
|
||||
#endif /* STM32F410xx */
|
||||
|
||||
#if defined(STM32F411xE)
|
||||
#include "stm32f4xx_flash_ramfunc.h"
|
||||
#endif /* STM32F411xE */
|
||||
|
||||
#if defined(STM32F446xx) || defined(STM32F469_479xx)
|
||||
#include "stm32f4xx_qspi.h"
|
||||
#endif /* STM32F446xx || STM32F469_479xx */
|
||||
|
||||
#if defined(STM32F410xx) || defined(STM32F446xx)
|
||||
#include "stm32f4xx_fmpi2c.h"
|
||||
#endif /* STM32F410xx || STM32F446xx */
|
||||
|
||||
#if defined(STM32F446xx)
|
||||
#include "stm32f4xx_spdifrx.h"
|
||||
#include "stm32f4xx_cec.h"
|
||||
#endif /* STM32F446xx */
|
||||
|
||||
#if defined(STM32F469_479xx)
|
||||
#include "stm32f4xx_dsi.h"
|
||||
#endif /* STM32F469_479xx */
|
||||
|
||||
#if defined(STM32F410xx)
|
||||
#include "stm32f4xx_lptim.h"
|
||||
#endif /* STM32F410xx */
|
||||
|
||||
#if defined(STM32F412xG)
|
||||
#include "stm32f4xx_rng.h"
|
||||
#include "stm32f4xx_can.h"
|
||||
#include "stm32f4xx_qspi.h"
|
||||
#include "stm32f4xx_rng.h"
|
||||
#include "stm32f4xx_fsmc.h"
|
||||
#include "stm32f4xx_dfsdm.h"
|
||||
#endif /* STM32F412xG */
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/* If an external clock source is used, then the value of the following define
|
||||
should be set to the value of the external clock source, else, if no external
|
||||
clock is used, keep this define commented */
|
||||
/*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */
|
||||
|
||||
|
||||
/* Uncomment the line below to expanse the "assert_param" macro in the
|
||||
Standard Peripheral Library drivers code */
|
||||
/* #define USE_FULL_ASSERT 1 */
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
#ifdef USE_FULL_ASSERT
|
||||
|
||||
/**
|
||||
* @brief The assert_param macro is used for function's parameters check.
|
||||
* @param expr: If expr is false, it calls assert_failed function
|
||||
* which reports the name of the source file and the source
|
||||
* line number of the call that failed.
|
||||
* If expr is true, it returns no value.
|
||||
* @retval None
|
||||
*/
|
||||
#define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
void assert_failed(uint8_t* file, uint32_t line);
|
||||
#else
|
||||
#define assert_param(expr) ((void)0)
|
||||
#endif /* USE_FULL_ASSERT */
|
||||
|
||||
#endif /* __STM32F4xx_CONF_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,611 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f4xx_gpio.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.7.1
|
||||
* @date 20-May-2016
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the GPIO peripheral:
|
||||
* + Initialization and Configuration
|
||||
* + GPIO Read and Write
|
||||
* + GPIO Alternate functions configuration
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### How to use this driver #####
|
||||
===============================================================================
|
||||
[..]
|
||||
(#) Enable the GPIO AHB clock using the following function
|
||||
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);
|
||||
|
||||
(#) Configure the GPIO pin(s) using GPIO_Init()
|
||||
Four possible configuration are available for each pin:
|
||||
(++) Input: Floating, Pull-up, Pull-down.
|
||||
(++) Output: Push-Pull (Pull-up, Pull-down or no Pull)
|
||||
Open Drain (Pull-up, Pull-down or no Pull). In output mode, the speed
|
||||
is configurable: 2 MHz, 25 MHz, 50 MHz or 100 MHz.
|
||||
(++) Alternate Function: Push-Pull (Pull-up, Pull-down or no Pull) Open
|
||||
Drain (Pull-up, Pull-down or no Pull).
|
||||
(++) Analog: required mode when a pin is to be used as ADC channel or DAC
|
||||
output.
|
||||
|
||||
(#) Peripherals alternate function:
|
||||
(++) For ADC and DAC, configure the desired pin in analog mode using
|
||||
GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AN;
|
||||
(+++) For other peripherals (TIM, USART...):
|
||||
(+++) Connect the pin to the desired peripherals' Alternate
|
||||
Function (AF) using GPIO_PinAFConfig() function
|
||||
(+++) Configure the desired pin in alternate function mode using
|
||||
GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF
|
||||
(+++) Select the type, pull-up/pull-down and output speed via
|
||||
GPIO_PuPd, GPIO_OType and GPIO_Speed members
|
||||
(+++) Call GPIO_Init() function
|
||||
|
||||
(#) To get the level of a pin configured in input mode use GPIO_ReadInputDataBit()
|
||||
|
||||
(#) To set/reset the level of a pin configured in output mode use
|
||||
GPIO_SetBits()/GPIO_ResetBits()
|
||||
|
||||
(#) During and just after reset, the alternate functions are not
|
||||
active and the GPIO pins are configured in input floating mode (except JTAG
|
||||
pins).
|
||||
|
||||
(#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose
|
||||
(PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has
|
||||
priority over the GPIO function.
|
||||
|
||||
(#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as
|
||||
general purpose PH0 and PH1, respectively, when the HSE oscillator is off.
|
||||
The HSE has priority over the GPIO function.
|
||||
|
||||
@endverbatim
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f4xx_gpio.h"
|
||||
#include "stm32f4xx_rcc.h"
|
||||
|
||||
/** @addtogroup STM32F4xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO
|
||||
* @brief GPIO driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup GPIO_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Group1 Initialization and Configuration
|
||||
* @brief Initialization and Configuration
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization and Configuration #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief De-initializes the GPIOx peripheral registers to their default reset values.
|
||||
* @note By default, The GPIO pins are configured in input floating mode (except JTAG pins).
|
||||
* @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
|
||||
* x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
|
||||
* x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_DeInit(GPIO_TypeDef* GPIOx)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
|
||||
if (GPIOx == GPIOA)
|
||||
{
|
||||
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOA, ENABLE);
|
||||
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOA, DISABLE);
|
||||
}
|
||||
else if (GPIOx == GPIOB)
|
||||
{
|
||||
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOB, ENABLE);
|
||||
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOB, DISABLE);
|
||||
}
|
||||
else if (GPIOx == GPIOC)
|
||||
{
|
||||
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOC, ENABLE);
|
||||
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOC, DISABLE);
|
||||
}
|
||||
else if (GPIOx == GPIOD)
|
||||
{
|
||||
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOD, ENABLE);
|
||||
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOD, DISABLE);
|
||||
}
|
||||
else if (GPIOx == GPIOE)
|
||||
{
|
||||
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOE, ENABLE);
|
||||
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOE, DISABLE);
|
||||
}
|
||||
else if (GPIOx == GPIOF)
|
||||
{
|
||||
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOF, ENABLE);
|
||||
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOF, DISABLE);
|
||||
}
|
||||
else if (GPIOx == GPIOG)
|
||||
{
|
||||
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOG, ENABLE);
|
||||
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOG, DISABLE);
|
||||
}
|
||||
else if (GPIOx == GPIOH)
|
||||
{
|
||||
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOH, ENABLE);
|
||||
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOH, DISABLE);
|
||||
}
|
||||
|
||||
else if (GPIOx == GPIOI)
|
||||
{
|
||||
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOI, ENABLE);
|
||||
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOI, DISABLE);
|
||||
}
|
||||
else if (GPIOx == GPIOJ)
|
||||
{
|
||||
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOJ, ENABLE);
|
||||
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOJ, DISABLE);
|
||||
}
|
||||
else
|
||||
{
|
||||
if (GPIOx == GPIOK)
|
||||
{
|
||||
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOK, ENABLE);
|
||||
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOK, DISABLE);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_InitStruct.
|
||||
* @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
|
||||
* x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
|
||||
* x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
|
||||
* @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that contains
|
||||
* the configuration information for the specified GPIO peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)
|
||||
{
|
||||
uint32_t pinpos = 0x00, pos = 0x00 , currentpin = 0x00;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin));
|
||||
assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode));
|
||||
assert_param(IS_GPIO_PUPD(GPIO_InitStruct->GPIO_PuPd));
|
||||
|
||||
/* ------------------------- Configure the port pins ---------------- */
|
||||
/*-- GPIO Mode Configuration --*/
|
||||
for (pinpos = 0x00; pinpos < 0x10; pinpos++)
|
||||
{
|
||||
pos = ((uint32_t)0x01) << pinpos;
|
||||
/* Get the port pins position */
|
||||
currentpin = (GPIO_InitStruct->GPIO_Pin) & pos;
|
||||
|
||||
if (currentpin == pos)
|
||||
{
|
||||
GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (pinpos * 2));
|
||||
GPIOx->MODER |= (((uint32_t)GPIO_InitStruct->GPIO_Mode) << (pinpos * 2));
|
||||
|
||||
if ((GPIO_InitStruct->GPIO_Mode == GPIO_Mode_OUT) || (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_AF))
|
||||
{
|
||||
/* Check Speed mode parameters */
|
||||
assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed));
|
||||
|
||||
/* Speed mode configuration */
|
||||
GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (pinpos * 2));
|
||||
GPIOx->OSPEEDR |= ((uint32_t)(GPIO_InitStruct->GPIO_Speed) << (pinpos * 2));
|
||||
|
||||
/* Check Output mode parameters */
|
||||
assert_param(IS_GPIO_OTYPE(GPIO_InitStruct->GPIO_OType));
|
||||
|
||||
/* Output mode configuration*/
|
||||
GPIOx->OTYPER &= ~((GPIO_OTYPER_OT_0) << ((uint16_t)pinpos)) ;
|
||||
GPIOx->OTYPER |= (uint16_t)(((uint16_t)GPIO_InitStruct->GPIO_OType) << ((uint16_t)pinpos));
|
||||
}
|
||||
|
||||
/* Pull-up Pull down resistor configuration*/
|
||||
GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << ((uint16_t)pinpos * 2));
|
||||
GPIOx->PUPDR |= (((uint32_t)GPIO_InitStruct->GPIO_PuPd) << (pinpos * 2));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Fills each GPIO_InitStruct member with its default value.
|
||||
* @param GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure which will be initialized.
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct)
|
||||
{
|
||||
/* Reset GPIO init structure parameters values */
|
||||
GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All;
|
||||
GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN;
|
||||
GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz;
|
||||
GPIO_InitStruct->GPIO_OType = GPIO_OType_PP;
|
||||
GPIO_InitStruct->GPIO_PuPd = GPIO_PuPd_NOPULL;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Locks GPIO Pins configuration registers.
|
||||
* @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
|
||||
* GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
|
||||
* @note The configuration of the locked GPIO pins can no longer be modified
|
||||
* until the next reset.
|
||||
* @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
|
||||
* x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
|
||||
* x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
|
||||
* @param GPIO_Pin: specifies the port bit to be locked.
|
||||
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
||||
{
|
||||
__IO uint32_t tmp = 0x00010000;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
||||
|
||||
tmp |= GPIO_Pin;
|
||||
/* Set LCKK bit */
|
||||
GPIOx->LCKR = tmp;
|
||||
/* Reset LCKK bit */
|
||||
GPIOx->LCKR = GPIO_Pin;
|
||||
/* Set LCKK bit */
|
||||
GPIOx->LCKR = tmp;
|
||||
/* Read LCKK bit*/
|
||||
tmp = GPIOx->LCKR;
|
||||
/* Read LCKK bit*/
|
||||
tmp = GPIOx->LCKR;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Group2 GPIO Read and Write
|
||||
* @brief GPIO Read and Write
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### GPIO Read and Write #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Reads the specified input port pin.
|
||||
* @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
|
||||
* x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
|
||||
* x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
|
||||
* @param GPIO_Pin: specifies the port bit to read.
|
||||
* This parameter can be GPIO_Pin_x where x can be (0..15).
|
||||
* @retval The input port pin value.
|
||||
*/
|
||||
uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
||||
{
|
||||
uint8_t bitstatus = 0x00;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
|
||||
|
||||
if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET)
|
||||
{
|
||||
bitstatus = (uint8_t)Bit_SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = (uint8_t)Bit_RESET;
|
||||
}
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reads the specified GPIO input data port.
|
||||
* @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
|
||||
* x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
|
||||
* x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
|
||||
* @retval GPIO input data port value.
|
||||
*/
|
||||
uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
|
||||
return ((uint16_t)GPIOx->IDR);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reads the specified output data port bit.
|
||||
* @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
|
||||
* x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
|
||||
* x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
|
||||
* @param GPIO_Pin: specifies the port bit to read.
|
||||
* This parameter can be GPIO_Pin_x where x can be (0..15).
|
||||
* @retval The output port pin value.
|
||||
*/
|
||||
uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
||||
{
|
||||
uint8_t bitstatus = 0x00;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
|
||||
|
||||
if (((GPIOx->ODR) & GPIO_Pin) != (uint32_t)Bit_RESET)
|
||||
{
|
||||
bitstatus = (uint8_t)Bit_SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = (uint8_t)Bit_RESET;
|
||||
}
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reads the specified GPIO output data port.
|
||||
* @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
|
||||
* x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
|
||||
* x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
|
||||
* @retval GPIO output data port value.
|
||||
*/
|
||||
uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
|
||||
return ((uint16_t)GPIOx->ODR);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets the selected data port bits.
|
||||
* @note This functions uses GPIOx_BSRR register to allow atomic read/modify
|
||||
* accesses. In this way, there is no risk of an IRQ occurring between
|
||||
* the read and the modify access.
|
||||
* @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
|
||||
* x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
|
||||
* x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
|
||||
* @param GPIO_Pin: specifies the port bits to be written.
|
||||
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
||||
|
||||
GPIOx->BSRRL = GPIO_Pin;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the selected data port bits.
|
||||
* @note This functions uses GPIOx_BSRR register to allow atomic read/modify
|
||||
* accesses. In this way, there is no risk of an IRQ occurring between
|
||||
* the read and the modify access.
|
||||
* @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
|
||||
* x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
|
||||
* x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
|
||||
* @param GPIO_Pin: specifies the port bits to be written.
|
||||
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
||||
|
||||
GPIOx->BSRRH = GPIO_Pin;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets or clears the selected data port bit.
|
||||
* @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
|
||||
* x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
|
||||
* x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
|
||||
* @param GPIO_Pin: specifies the port bit to be written.
|
||||
* This parameter can be one of GPIO_Pin_x where x can be (0..15).
|
||||
* @param BitVal: specifies the value to be written to the selected bit.
|
||||
* This parameter can be one of the BitAction enum values:
|
||||
* @arg Bit_RESET: to clear the port pin
|
||||
* @arg Bit_SET: to set the port pin
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
|
||||
assert_param(IS_GPIO_BIT_ACTION(BitVal));
|
||||
|
||||
if (BitVal != Bit_RESET)
|
||||
{
|
||||
GPIOx->BSRRL = GPIO_Pin;
|
||||
}
|
||||
else
|
||||
{
|
||||
GPIOx->BSRRH = GPIO_Pin ;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Writes data to the specified GPIO data port.
|
||||
* @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
|
||||
* x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
|
||||
* x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
|
||||
* @param PortVal: specifies the value to be written to the port output data register.
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
|
||||
GPIOx->ODR = PortVal;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Toggles the specified GPIO pins..
|
||||
* @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
|
||||
* x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
|
||||
* x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
|
||||
* @param GPIO_Pin: Specifies the pins to be toggled.
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_ToggleBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
|
||||
GPIOx->ODR ^= GPIO_Pin;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Group3 GPIO Alternate functions configuration function
|
||||
* @brief GPIO Alternate functions configuration function
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### GPIO Alternate functions configuration function #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Changes the mapping of the specified pin.
|
||||
* @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
|
||||
* x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
|
||||
* x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
|
||||
* @param GPIO_PinSource: specifies the pin for the Alternate function.
|
||||
* This parameter can be GPIO_PinSourcex where x can be (0..15).
|
||||
* @param GPIO_AFSelection: selects the pin to used as Alternate function.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg GPIO_AF_RTC_50Hz: Connect RTC_50Hz pin to AF0 (default after reset)
|
||||
* @arg GPIO_AF_MCO: Connect MCO pin (MCO1 and MCO2) to AF0 (default after reset)
|
||||
* @arg GPIO_AF_TAMPER: Connect TAMPER pins (TAMPER_1 and TAMPER_2) to AF0 (default after reset)
|
||||
* @arg GPIO_AF_SWJ: Connect SWJ pins (SWD and JTAG)to AF0 (default after reset)
|
||||
* @arg GPIO_AF_TRACE: Connect TRACE pins to AF0 (default after reset)
|
||||
* @arg GPIO_AF_TIM1: Connect TIM1 pins to AF1
|
||||
* @arg GPIO_AF_TIM2: Connect TIM2 pins to AF1
|
||||
* @arg GPIO_AF_TIM3: Connect TIM3 pins to AF2
|
||||
* @arg GPIO_AF_TIM4: Connect TIM4 pins to AF2
|
||||
* @arg GPIO_AF_TIM5: Connect TIM5 pins to AF2
|
||||
* @arg GPIO_AF_TIM8: Connect TIM8 pins to AF3
|
||||
* @arg GPIO_AF_TIM9: Connect TIM9 pins to AF3
|
||||
* @arg GPIO_AF_TIM10: Connect TIM10 pins to AF3
|
||||
* @arg GPIO_AF_TIM11: Connect TIM11 pins to AF3
|
||||
* @arg GPIO_AF_I2C1: Connect I2C1 pins to AF4
|
||||
* @arg GPIO_AF_I2C2: Connect I2C2 pins to AF4
|
||||
* @arg GPIO_AF_I2C3: Connect I2C3 pins to AF4
|
||||
* @arg GPIO_AF_SPI1: Connect SPI1 pins to AF5
|
||||
* @arg GPIO_AF_SPI2: Connect SPI2/I2S2 pins to AF5
|
||||
* @arg GPIO_AF_SPI4: Connect SPI4 pins to AF5
|
||||
* @arg GPIO_AF_SPI5: Connect SPI5 pins to AF5
|
||||
* @arg GPIO_AF_SPI6: Connect SPI6 pins to AF5
|
||||
* @arg GPIO_AF_SAI1: Connect SAI1 pins to AF6 for STM32F42xxx/43xxx devices.
|
||||
* @arg GPIO_AF_SPI3: Connect SPI3/I2S3 pins to AF6
|
||||
* @arg GPIO_AF_I2S3ext: Connect I2S3ext pins to AF7
|
||||
* @arg GPIO_AF_USART1: Connect USART1 pins to AF7
|
||||
* @arg GPIO_AF_USART2: Connect USART2 pins to AF7
|
||||
* @arg GPIO_AF_USART3: Connect USART3 pins to AF7
|
||||
* @arg GPIO_AF_UART4: Connect UART4 pins to AF8
|
||||
* @arg GPIO_AF_UART5: Connect UART5 pins to AF8
|
||||
* @arg GPIO_AF_USART6: Connect USART6 pins to AF8
|
||||
* @arg GPIO_AF_UART7: Connect UART7 pins to AF8
|
||||
* @arg GPIO_AF_UART8: Connect UART8 pins to AF8
|
||||
* @arg GPIO_AF_CAN1: Connect CAN1 pins to AF9
|
||||
* @arg GPIO_AF_CAN2: Connect CAN2 pins to AF9
|
||||
* @arg GPIO_AF_TIM12: Connect TIM12 pins to AF9
|
||||
* @arg GPIO_AF_TIM13: Connect TIM13 pins to AF9
|
||||
* @arg GPIO_AF_TIM14: Connect TIM14 pins to AF9
|
||||
* @arg GPIO_AF_OTG_FS: Connect OTG_FS pins to AF10
|
||||
* @arg GPIO_AF_OTG_HS: Connect OTG_HS pins to AF10
|
||||
* @arg GPIO_AF_ETH: Connect ETHERNET pins to AF11
|
||||
* @arg GPIO_AF_FSMC: Connect FSMC pins to AF12
|
||||
* @arg GPIO_AF_FMC: Connect FMC pins to AF12 for STM32F42xxx/43xxx devices.
|
||||
* @arg GPIO_AF_OTG_HS_FS: Connect OTG HS (configured in FS) pins to AF12
|
||||
* @arg GPIO_AF_SDIO: Connect SDIO pins to AF12
|
||||
* @arg GPIO_AF_DCMI: Connect DCMI pins to AF13
|
||||
* @arg GPIO_AF_LTDC: Connect LTDC pins to AF14 for STM32F429xx/439xx devices.
|
||||
* @arg GPIO_AF_EVENTOUT: Connect EVENTOUT pins to AF15
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF)
|
||||
{
|
||||
uint32_t temp = 0x00;
|
||||
uint32_t temp_2 = 0x00;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource));
|
||||
assert_param(IS_GPIO_AF(GPIO_AF));
|
||||
|
||||
temp = ((uint32_t)(GPIO_AF) << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4)) ;
|
||||
GPIOx->AFR[GPIO_PinSource >> 0x03] &= ~((uint32_t)0xF << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4)) ;
|
||||
temp_2 = GPIOx->AFR[GPIO_PinSource >> 0x03] | temp;
|
||||
GPIOx->AFR[GPIO_PinSource >> 0x03] = temp_2;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,564 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f4xx_gpio.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.7.1
|
||||
* @date 20-May-2016
|
||||
* @brief This file contains all the functions prototypes for the GPIO firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F4xx_GPIO_H
|
||||
#define __STM32F4xx_GPIO_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f4xx.h"
|
||||
|
||||
/** @addtogroup STM32F4xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup GPIO
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \
|
||||
((PERIPH) == GPIOB) || \
|
||||
((PERIPH) == GPIOC) || \
|
||||
((PERIPH) == GPIOD) || \
|
||||
((PERIPH) == GPIOE) || \
|
||||
((PERIPH) == GPIOF) || \
|
||||
((PERIPH) == GPIOG) || \
|
||||
((PERIPH) == GPIOH) || \
|
||||
((PERIPH) == GPIOI) || \
|
||||
((PERIPH) == GPIOJ) || \
|
||||
((PERIPH) == GPIOK))
|
||||
|
||||
/**
|
||||
* @brief GPIO Configuration Mode enumeration
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
GPIO_Mode_IN = 0x00, /*!< GPIO Input Mode */
|
||||
GPIO_Mode_OUT = 0x01, /*!< GPIO Output Mode */
|
||||
GPIO_Mode_AF = 0x02, /*!< GPIO Alternate function Mode */
|
||||
GPIO_Mode_AN = 0x03 /*!< GPIO Analog Mode */
|
||||
}GPIOMode_TypeDef;
|
||||
#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_IN) || ((MODE) == GPIO_Mode_OUT) || \
|
||||
((MODE) == GPIO_Mode_AF)|| ((MODE) == GPIO_Mode_AN))
|
||||
|
||||
/**
|
||||
* @brief GPIO Output type enumeration
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
GPIO_OType_PP = 0x00,
|
||||
GPIO_OType_OD = 0x01
|
||||
}GPIOOType_TypeDef;
|
||||
#define IS_GPIO_OTYPE(OTYPE) (((OTYPE) == GPIO_OType_PP) || ((OTYPE) == GPIO_OType_OD))
|
||||
|
||||
|
||||
/**
|
||||
* @brief GPIO Output Maximum frequency enumeration
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
GPIO_Low_Speed = 0x00, /*!< Low speed */
|
||||
GPIO_Medium_Speed = 0x01, /*!< Medium speed */
|
||||
GPIO_Fast_Speed = 0x02, /*!< Fast speed */
|
||||
GPIO_High_Speed = 0x03 /*!< High speed */
|
||||
}GPIOSpeed_TypeDef;
|
||||
|
||||
/* Add legacy definition */
|
||||
#define GPIO_Speed_2MHz GPIO_Low_Speed
|
||||
#define GPIO_Speed_25MHz GPIO_Medium_Speed
|
||||
#define GPIO_Speed_50MHz GPIO_Fast_Speed
|
||||
#define GPIO_Speed_100MHz GPIO_High_Speed
|
||||
|
||||
#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Low_Speed) || ((SPEED) == GPIO_Medium_Speed) || \
|
||||
((SPEED) == GPIO_Fast_Speed)|| ((SPEED) == GPIO_High_Speed))
|
||||
|
||||
/**
|
||||
* @brief GPIO Configuration PullUp PullDown enumeration
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
GPIO_PuPd_NOPULL = 0x00,
|
||||
GPIO_PuPd_UP = 0x01,
|
||||
GPIO_PuPd_DOWN = 0x02
|
||||
}GPIOPuPd_TypeDef;
|
||||
#define IS_GPIO_PUPD(PUPD) (((PUPD) == GPIO_PuPd_NOPULL) || ((PUPD) == GPIO_PuPd_UP) || \
|
||||
((PUPD) == GPIO_PuPd_DOWN))
|
||||
|
||||
/**
|
||||
* @brief GPIO Bit SET and Bit RESET enumeration
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
Bit_RESET = 0,
|
||||
Bit_SET
|
||||
}BitAction;
|
||||
#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET))
|
||||
|
||||
|
||||
/**
|
||||
* @brief GPIO Init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t GPIO_Pin; /*!< Specifies the GPIO pins to be configured.
|
||||
This parameter can be any value of @ref GPIO_pins_define */
|
||||
|
||||
GPIOMode_TypeDef GPIO_Mode; /*!< Specifies the operating mode for the selected pins.
|
||||
This parameter can be a value of @ref GPIOMode_TypeDef */
|
||||
|
||||
GPIOSpeed_TypeDef GPIO_Speed; /*!< Specifies the speed for the selected pins.
|
||||
This parameter can be a value of @ref GPIOSpeed_TypeDef */
|
||||
|
||||
GPIOOType_TypeDef GPIO_OType; /*!< Specifies the operating output type for the selected pins.
|
||||
This parameter can be a value of @ref GPIOOType_TypeDef */
|
||||
|
||||
GPIOPuPd_TypeDef GPIO_PuPd; /*!< Specifies the operating Pull-up/Pull down for the selected pins.
|
||||
This parameter can be a value of @ref GPIOPuPd_TypeDef */
|
||||
}GPIO_InitTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup GPIO_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_pins_define
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_Pin_0 ((uint16_t)0x0001) /* Pin 0 selected */
|
||||
#define GPIO_Pin_1 ((uint16_t)0x0002) /* Pin 1 selected */
|
||||
#define GPIO_Pin_2 ((uint16_t)0x0004) /* Pin 2 selected */
|
||||
#define GPIO_Pin_3 ((uint16_t)0x0008) /* Pin 3 selected */
|
||||
#define GPIO_Pin_4 ((uint16_t)0x0010) /* Pin 4 selected */
|
||||
#define GPIO_Pin_5 ((uint16_t)0x0020) /* Pin 5 selected */
|
||||
#define GPIO_Pin_6 ((uint16_t)0x0040) /* Pin 6 selected */
|
||||
#define GPIO_Pin_7 ((uint16_t)0x0080) /* Pin 7 selected */
|
||||
#define GPIO_Pin_8 ((uint16_t)0x0100) /* Pin 8 selected */
|
||||
#define GPIO_Pin_9 ((uint16_t)0x0200) /* Pin 9 selected */
|
||||
#define GPIO_Pin_10 ((uint16_t)0x0400) /* Pin 10 selected */
|
||||
#define GPIO_Pin_11 ((uint16_t)0x0800) /* Pin 11 selected */
|
||||
#define GPIO_Pin_12 ((uint16_t)0x1000) /* Pin 12 selected */
|
||||
#define GPIO_Pin_13 ((uint16_t)0x2000) /* Pin 13 selected */
|
||||
#define GPIO_Pin_14 ((uint16_t)0x4000) /* Pin 14 selected */
|
||||
#define GPIO_Pin_15 ((uint16_t)0x8000) /* Pin 15 selected */
|
||||
#define GPIO_Pin_All ((uint16_t)0xFFFF) /* All pins selected */
|
||||
|
||||
#define GPIO_PIN_MASK ((uint32_t)0x0000FFFF) /* PIN mask for assert test */
|
||||
#define IS_GPIO_PIN(PIN) (((PIN) & GPIO_PIN_MASK ) != (uint32_t)0x00)
|
||||
#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \
|
||||
((PIN) == GPIO_Pin_1) || \
|
||||
((PIN) == GPIO_Pin_2) || \
|
||||
((PIN) == GPIO_Pin_3) || \
|
||||
((PIN) == GPIO_Pin_4) || \
|
||||
((PIN) == GPIO_Pin_5) || \
|
||||
((PIN) == GPIO_Pin_6) || \
|
||||
((PIN) == GPIO_Pin_7) || \
|
||||
((PIN) == GPIO_Pin_8) || \
|
||||
((PIN) == GPIO_Pin_9) || \
|
||||
((PIN) == GPIO_Pin_10) || \
|
||||
((PIN) == GPIO_Pin_11) || \
|
||||
((PIN) == GPIO_Pin_12) || \
|
||||
((PIN) == GPIO_Pin_13) || \
|
||||
((PIN) == GPIO_Pin_14) || \
|
||||
((PIN) == GPIO_Pin_15))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup GPIO_Pin_sources
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_PinSource0 ((uint8_t)0x00)
|
||||
#define GPIO_PinSource1 ((uint8_t)0x01)
|
||||
#define GPIO_PinSource2 ((uint8_t)0x02)
|
||||
#define GPIO_PinSource3 ((uint8_t)0x03)
|
||||
#define GPIO_PinSource4 ((uint8_t)0x04)
|
||||
#define GPIO_PinSource5 ((uint8_t)0x05)
|
||||
#define GPIO_PinSource6 ((uint8_t)0x06)
|
||||
#define GPIO_PinSource7 ((uint8_t)0x07)
|
||||
#define GPIO_PinSource8 ((uint8_t)0x08)
|
||||
#define GPIO_PinSource9 ((uint8_t)0x09)
|
||||
#define GPIO_PinSource10 ((uint8_t)0x0A)
|
||||
#define GPIO_PinSource11 ((uint8_t)0x0B)
|
||||
#define GPIO_PinSource12 ((uint8_t)0x0C)
|
||||
#define GPIO_PinSource13 ((uint8_t)0x0D)
|
||||
#define GPIO_PinSource14 ((uint8_t)0x0E)
|
||||
#define GPIO_PinSource15 ((uint8_t)0x0F)
|
||||
|
||||
#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \
|
||||
((PINSOURCE) == GPIO_PinSource1) || \
|
||||
((PINSOURCE) == GPIO_PinSource2) || \
|
||||
((PINSOURCE) == GPIO_PinSource3) || \
|
||||
((PINSOURCE) == GPIO_PinSource4) || \
|
||||
((PINSOURCE) == GPIO_PinSource5) || \
|
||||
((PINSOURCE) == GPIO_PinSource6) || \
|
||||
((PINSOURCE) == GPIO_PinSource7) || \
|
||||
((PINSOURCE) == GPIO_PinSource8) || \
|
||||
((PINSOURCE) == GPIO_PinSource9) || \
|
||||
((PINSOURCE) == GPIO_PinSource10) || \
|
||||
((PINSOURCE) == GPIO_PinSource11) || \
|
||||
((PINSOURCE) == GPIO_PinSource12) || \
|
||||
((PINSOURCE) == GPIO_PinSource13) || \
|
||||
((PINSOURCE) == GPIO_PinSource14) || \
|
||||
((PINSOURCE) == GPIO_PinSource15))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Alternat_function_selection_define
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief AF 0 selection
|
||||
*/
|
||||
#define GPIO_AF_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
|
||||
#define GPIO_AF_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
|
||||
#define GPIO_AF_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
|
||||
#define GPIO_AF_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
|
||||
#define GPIO_AF_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
|
||||
#if defined(STM32F446xx)
|
||||
#define GPIO_AF0_TIM2 ((uint8_t)0x00) /* TIM2 Alternate Function mapping */
|
||||
#endif /* STM32F446xx */
|
||||
|
||||
/**
|
||||
* @brief AF 1 selection
|
||||
*/
|
||||
#define GPIO_AF_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
|
||||
#if defined(STM32F410xx)
|
||||
#define GPIO_AF_LPTIM ((uint8_t)0x01) /* LPTIM Alternate Function mapping */
|
||||
#endif /* STM32F410xx */
|
||||
/**
|
||||
* @brief AF 2 selection
|
||||
*/
|
||||
#define GPIO_AF_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
|
||||
#define GPIO_AF_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */
|
||||
#define GPIO_AF_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 3 selection
|
||||
*/
|
||||
#define GPIO_AF_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */
|
||||
#define GPIO_AF_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */
|
||||
#define GPIO_AF_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */
|
||||
#define GPIO_AF_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */
|
||||
#if defined(STM32F446xx)
|
||||
#define GPIO_AF3_CEC ((uint8_t)0x03) /* CEC Alternate Function mapping */
|
||||
#endif /* STM32F446xx */
|
||||
/**
|
||||
* @brief AF 4 selection
|
||||
*/
|
||||
#define GPIO_AF_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
|
||||
#define GPIO_AF_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
|
||||
#define GPIO_AF_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */
|
||||
#if defined(STM32F446xx)
|
||||
#define GPIO_AF4_CEC ((uint8_t)0x04) /* CEC Alternate Function mapping */
|
||||
#endif /* STM32F446xx */
|
||||
#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F446xx)
|
||||
#define GPIO_AF_FMPI2C ((uint8_t)0x04) /* FMPI2C Alternate Function mapping */
|
||||
#endif /* STM32F410xx || STM32F446xx */
|
||||
|
||||
/**
|
||||
* @brief AF 5 selection
|
||||
*/
|
||||
#define GPIO_AF_SPI1 ((uint8_t)0x05) /* SPI1/I2S1 Alternate Function mapping */
|
||||
#define GPIO_AF_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */
|
||||
#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3/I2S3 Alternate Function mapping (Only for STM32F411xE Devices) */
|
||||
#define GPIO_AF_SPI4 ((uint8_t)0x05) /* SPI4/I2S4 Alternate Function mapping */
|
||||
#define GPIO_AF_SPI5 ((uint8_t)0x05) /* SPI5 Alternate Function mapping */
|
||||
#define GPIO_AF_SPI6 ((uint8_t)0x05) /* SPI6 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 6 selection
|
||||
*/
|
||||
#define GPIO_AF_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */
|
||||
#define GPIO_AF6_SPI1 ((uint8_t)0x06) /* SPI1 Alternate Function mapping (Only for STM32F410xx Devices) */
|
||||
#define GPIO_AF6_SPI2 ((uint8_t)0x06) /* SPI2 Alternate Function mapping (Only for STM32F410xx/STM32F411xE Devices) */
|
||||
#define GPIO_AF6_SPI4 ((uint8_t)0x06) /* SPI4 Alternate Function mapping (Only for STM32F411xE Devices) */
|
||||
#define GPIO_AF6_SPI5 ((uint8_t)0x06) /* SPI5 Alternate Function mapping (Only for STM32F410xx/STM32F411xE Devices) */
|
||||
#define GPIO_AF_SAI1 ((uint8_t)0x06) /* SAI1 Alternate Function mapping */
|
||||
#define GPIO_AF_I2S2ext ((uint8_t)0x06) /* I2S2ext_SD Alternate Function mapping (only for STM32F412xG Devices) */
|
||||
#if defined(STM32F412xG)
|
||||
#define GPIO_AF6_DFSDM1 ((uint8_t)0x06) /* DFSDM Alternate Function mapping */
|
||||
#endif /* STM32F412xG */
|
||||
|
||||
/**
|
||||
* @brief AF 7 selection
|
||||
*/
|
||||
#define GPIO_AF_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
|
||||
#define GPIO_AF_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
|
||||
#define GPIO_AF_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
|
||||
#define GPIO_AF7_SPI3 ((uint8_t)0x07) /* SPI3/I2S3ext Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 7 selection Legacy
|
||||
*/
|
||||
#define GPIO_AF_I2S3ext GPIO_AF7_SPI3
|
||||
|
||||
/**
|
||||
* @brief AF 8 selection
|
||||
*/
|
||||
#define GPIO_AF_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */
|
||||
#define GPIO_AF_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */
|
||||
#define GPIO_AF_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */
|
||||
#define GPIO_AF_UART7 ((uint8_t)0x08) /* UART7 Alternate Function mapping */
|
||||
#define GPIO_AF_UART8 ((uint8_t)0x08) /* UART8 Alternate Function mapping */
|
||||
#if defined(STM32F412xG)
|
||||
#define GPIO_AF8_USART3 ((uint8_t)0x08) /* USART3 Alternate Function mapping */
|
||||
#define GPIO_AF8_DFSDM1 ((uint8_t)0x08) /* DFSDM Alternate Function mapping */
|
||||
#define GPIO_AF8_CAN1 ((uint8_t)0x08) /* CAN1 Alternate Function mapping */
|
||||
#endif /* STM32F412xG */
|
||||
#if defined(STM32F446xx)
|
||||
#define GPIO_AF8_SAI2 ((uint8_t)0x08) /* SAI2 Alternate Function mapping */
|
||||
#define GPIO_AF_SPDIF ((uint8_t)0x08) /* SPDIF Alternate Function mapping */
|
||||
#endif /* STM32F446xx */
|
||||
|
||||
/**
|
||||
* @brief AF 9 selection
|
||||
*/
|
||||
#define GPIO_AF_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */
|
||||
#define GPIO_AF_CAN2 ((uint8_t)0x09) /* CAN2 Alternate Function mapping */
|
||||
#define GPIO_AF_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */
|
||||
#define GPIO_AF_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */
|
||||
#define GPIO_AF_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */
|
||||
#define GPIO_AF9_I2C2 ((uint8_t)0x09) /* I2C2 Alternate Function mapping (Only for STM32F401xx/STM32F410xx/STM32F411xE/STM32F412xG Devices) */
|
||||
#define GPIO_AF9_I2C3 ((uint8_t)0x09) /* I2C3 Alternate Function mapping (Only for STM32F401xx/STM32F411xE/STM32F412xG Devices) */
|
||||
#if defined(STM32F446xx)
|
||||
#define GPIO_AF9_SAI2 ((uint8_t)0x09) /* SAI2 Alternate Function mapping */
|
||||
#endif /* STM32F446xx */
|
||||
#define GPIO_AF9_LTDC ((uint8_t)0x09) /* LTDC Alternate Function mapping */
|
||||
#if defined(STM32F412xG) || defined(STM32F446xx) || defined(STM32F469_479xx)
|
||||
#define GPIO_AF9_QUADSPI ((uint8_t)0x09) /* QuadSPI Alternate Function mapping */
|
||||
#endif /* STM32F412xG || STM32F446xx || STM32F469_479xx */
|
||||
#if defined(STM32F410xx) || defined(STM32F412xG)
|
||||
#define GPIO_AF9_FMPI2C ((uint8_t)0x09) /* FMPI2C Alternate Function mapping (Only for STM32F410xx Devices) */
|
||||
#endif /* STM32F410xx || STM32F412xG */
|
||||
|
||||
/**
|
||||
* @brief AF 10 selection
|
||||
*/
|
||||
#define GPIO_AF_OTG_FS ((uint8_t)0xA) /* OTG_FS Alternate Function mapping */
|
||||
#define GPIO_AF_OTG_HS ((uint8_t)0xA) /* OTG_HS Alternate Function mapping */
|
||||
#if defined(STM32F446xx)
|
||||
#define GPIO_AF10_SAI2 ((uint8_t)0x0A) /* SAI2 Alternate Function mapping */
|
||||
#endif /* STM32F446xx */
|
||||
#if defined(STM32F412xG) || defined(STM32F446xx) || defined(STM32F469_479xx)
|
||||
#define GPIO_AF10_QUADSPI ((uint8_t)0x0A) /* QuadSPI Alternate Function mapping */
|
||||
#endif /* STM32F412xG || STM32F446xx || STM32F469_479xx */
|
||||
#if defined(STM32F412xG)
|
||||
#define GPIO_AF10_FMC ((uint8_t)0xA) /* FMC Alternate Function mapping */
|
||||
#define GPIO_AF10_DFSDM ((uint8_t)0xA) /* DFSDM Alternate Function mapping */
|
||||
#endif /* STM32F412xG */
|
||||
/**
|
||||
* @brief AF 11 selection
|
||||
*/
|
||||
#define GPIO_AF_ETH ((uint8_t)0x0B) /* ETHERNET Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 12 selection
|
||||
*/
|
||||
#if defined(STM32F40_41xxx) || defined(STM32F412xG)
|
||||
#define GPIO_AF_FSMC ((uint8_t)0xC) /* FSMC Alternate Function mapping */
|
||||
#endif /* STM32F40_41xxx || STM32F412xG */
|
||||
|
||||
#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
|
||||
#define GPIO_AF_FMC ((uint8_t)0xC) /* FMC Alternate Function mapping */
|
||||
#endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */
|
||||
|
||||
#define GPIO_AF_OTG_HS_FS ((uint8_t)0xC) /* OTG HS configured in FS, Alternate Function mapping */
|
||||
#define GPIO_AF_SDIO ((uint8_t)0xC) /* SDIO Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 13 selection
|
||||
*/
|
||||
#define GPIO_AF_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */
|
||||
#if defined(STM32F469_479xx)
|
||||
#define GPIO_AF_DSI ((uint8_t)0x0D) /* DSI Alternate Function mapping */
|
||||
#endif /* STM32F469_479xx */
|
||||
/**
|
||||
* @brief AF 14 selection
|
||||
*/
|
||||
#define GPIO_AF_LTDC ((uint8_t)0x0E) /* LCD-TFT Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 15 selection
|
||||
*/
|
||||
#define GPIO_AF_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
|
||||
|
||||
#if defined(STM32F40_41xxx)
|
||||
#define IS_GPIO_AF(AF) (((AF) == GPIO_AF_RTC_50Hz) || ((AF) == GPIO_AF_TIM14) || \
|
||||
((AF) == GPIO_AF_MCO) || ((AF) == GPIO_AF_TAMPER) || \
|
||||
((AF) == GPIO_AF_SWJ) || ((AF) == GPIO_AF_TRACE) || \
|
||||
((AF) == GPIO_AF_TIM1) || ((AF) == GPIO_AF_TIM2) || \
|
||||
((AF) == GPIO_AF_TIM3) || ((AF) == GPIO_AF_TIM4) || \
|
||||
((AF) == GPIO_AF_TIM5) || ((AF) == GPIO_AF_TIM8) || \
|
||||
((AF) == GPIO_AF_I2C1) || ((AF) == GPIO_AF_I2C2) || \
|
||||
((AF) == GPIO_AF_I2C3) || ((AF) == GPIO_AF_SPI1) || \
|
||||
((AF) == GPIO_AF_SPI2) || ((AF) == GPIO_AF_TIM13) || \
|
||||
((AF) == GPIO_AF_SPI3) || ((AF) == GPIO_AF_TIM14) || \
|
||||
((AF) == GPIO_AF_USART1) || ((AF) == GPIO_AF_USART2) || \
|
||||
((AF) == GPIO_AF_USART3) || ((AF) == GPIO_AF_UART4) || \
|
||||
((AF) == GPIO_AF_UART5) || ((AF) == GPIO_AF_USART6) || \
|
||||
((AF) == GPIO_AF_CAN1) || ((AF) == GPIO_AF_CAN2) || \
|
||||
((AF) == GPIO_AF_OTG_FS) || ((AF) == GPIO_AF_OTG_HS) || \
|
||||
((AF) == GPIO_AF_ETH) || ((AF) == GPIO_AF_OTG_HS_FS) || \
|
||||
((AF) == GPIO_AF_SDIO) || ((AF) == GPIO_AF_DCMI) || \
|
||||
((AF) == GPIO_AF_EVENTOUT) || ((AF) == GPIO_AF_FSMC))
|
||||
#endif /* STM32F40_41xxx */
|
||||
|
||||
#if defined(STM32F401xx)
|
||||
#define IS_GPIO_AF(AF) (((AF) == GPIO_AF_RTC_50Hz) || ((AF) == GPIO_AF_TIM14) || \
|
||||
((AF) == GPIO_AF_MCO) || ((AF) == GPIO_AF_TAMPER) || \
|
||||
((AF) == GPIO_AF_SWJ) || ((AF) == GPIO_AF_TRACE) || \
|
||||
((AF) == GPIO_AF_TIM1) || ((AF) == GPIO_AF_TIM2) || \
|
||||
((AF) == GPIO_AF_TIM3) || ((AF) == GPIO_AF_TIM4) || \
|
||||
((AF) == GPIO_AF_TIM5) || ((AF) == GPIO_AF_TIM8) || \
|
||||
((AF) == GPIO_AF_I2C1) || ((AF) == GPIO_AF_I2C2) || \
|
||||
((AF) == GPIO_AF_I2C3) || ((AF) == GPIO_AF_SPI1) || \
|
||||
((AF) == GPIO_AF_SPI2) || ((AF) == GPIO_AF_TIM13) || \
|
||||
((AF) == GPIO_AF_SPI3) || ((AF) == GPIO_AF_TIM14) || \
|
||||
((AF) == GPIO_AF_USART1) || ((AF) == GPIO_AF_USART2) || \
|
||||
((AF) == GPIO_AF_SDIO) || ((AF) == GPIO_AF_USART6) || \
|
||||
((AF) == GPIO_AF_OTG_FS) || ((AF) == GPIO_AF_OTG_HS) || \
|
||||
((AF) == GPIO_AF_EVENTOUT) || ((AF) == GPIO_AF_SPI4))
|
||||
#endif /* STM32F401xx */
|
||||
|
||||
#if defined(STM32F411xE)
|
||||
#define IS_GPIO_AF(AF) (((AF) < 16) && ((AF) != 11) && ((AF) != 13) && ((AF) != 14))
|
||||
#endif /* STM32F411xE */
|
||||
|
||||
#if defined(STM32F410xx)
|
||||
#define IS_GPIO_AF(AF) (((AF) < 10) || ((AF) == 15))
|
||||
#endif /* STM32F410xx */
|
||||
|
||||
#if defined(STM32F427_437xx) || defined(STM32F429_439xx)
|
||||
#define IS_GPIO_AF(AF) (((AF) == GPIO_AF_RTC_50Hz) || ((AF) == GPIO_AF_TIM14) || \
|
||||
((AF) == GPIO_AF_MCO) || ((AF) == GPIO_AF_TAMPER) || \
|
||||
((AF) == GPIO_AF_SWJ) || ((AF) == GPIO_AF_TRACE) || \
|
||||
((AF) == GPIO_AF_TIM1) || ((AF) == GPIO_AF_TIM2) || \
|
||||
((AF) == GPIO_AF_TIM3) || ((AF) == GPIO_AF_TIM4) || \
|
||||
((AF) == GPIO_AF_TIM5) || ((AF) == GPIO_AF_TIM8) || \
|
||||
((AF) == GPIO_AF_I2C1) || ((AF) == GPIO_AF_I2C2) || \
|
||||
((AF) == GPIO_AF_I2C3) || ((AF) == GPIO_AF_SPI1) || \
|
||||
((AF) == GPIO_AF_SPI2) || ((AF) == GPIO_AF_TIM13) || \
|
||||
((AF) == GPIO_AF_SPI3) || ((AF) == GPIO_AF_TIM14) || \
|
||||
((AF) == GPIO_AF_USART1) || ((AF) == GPIO_AF_USART2) || \
|
||||
((AF) == GPIO_AF_USART3) || ((AF) == GPIO_AF_UART4) || \
|
||||
((AF) == GPIO_AF_UART5) || ((AF) == GPIO_AF_USART6) || \
|
||||
((AF) == GPIO_AF_CAN1) || ((AF) == GPIO_AF_CAN2) || \
|
||||
((AF) == GPIO_AF_OTG_FS) || ((AF) == GPIO_AF_OTG_HS) || \
|
||||
((AF) == GPIO_AF_ETH) || ((AF) == GPIO_AF_OTG_HS_FS) || \
|
||||
((AF) == GPIO_AF_SDIO) || ((AF) == GPIO_AF_DCMI) || \
|
||||
((AF) == GPIO_AF_EVENTOUT) || ((AF) == GPIO_AF_SPI4) || \
|
||||
((AF) == GPIO_AF_SPI5) || ((AF) == GPIO_AF_SPI6) || \
|
||||
((AF) == GPIO_AF_UART7) || ((AF) == GPIO_AF_UART8) || \
|
||||
((AF) == GPIO_AF_FMC) || ((AF) == GPIO_AF_SAI1) || \
|
||||
((AF) == GPIO_AF_LTDC))
|
||||
#endif /* STM32F427_437xx || STM32F429_439xx */
|
||||
|
||||
#if defined(STM32F412xG)
|
||||
#define IS_GPIO_AF(AF) (((AF) < 16) && ((AF) != 11) && ((AF) != 14))
|
||||
#endif /* STM32F412xG */
|
||||
|
||||
#if defined(STM32F446xx)
|
||||
#define IS_GPIO_AF(AF) (((AF) < 16) && ((AF) != 11) && ((AF) != 14))
|
||||
#endif /* STM32F446xx */
|
||||
|
||||
#if defined(STM32F469_479xx)
|
||||
#define IS_GPIO_AF(AF) ((AF) < 16)
|
||||
#endif /* STM32F469_479xx */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Legacy
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define GPIO_Mode_AIN GPIO_Mode_AN
|
||||
|
||||
#define GPIO_AF_OTG1_FS GPIO_AF_OTG_FS
|
||||
#define GPIO_AF_OTG2_HS GPIO_AF_OTG_HS
|
||||
#define GPIO_AF_OTG2_FS GPIO_AF_OTG_HS_FS
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/* Function used to set the GPIO configuration to the default reset state ****/
|
||||
void GPIO_DeInit(GPIO_TypeDef* GPIOx);
|
||||
|
||||
/* Initialization and Configuration functions *********************************/
|
||||
void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct);
|
||||
void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct);
|
||||
void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||
|
||||
/* GPIO Read and Write functions **********************************************/
|
||||
uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||
uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx);
|
||||
uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||
uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx);
|
||||
void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||
void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||
void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal);
|
||||
void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal);
|
||||
void GPIO_ToggleBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||
|
||||
/* GPIO Alternate functions configuration function ****************************/
|
||||
void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__STM32F4xx_GPIO_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,982 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f4xx_rcc.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.7.1
|
||||
* @date 20-May-2016
|
||||
* @brief This file contains all the functions prototypes for the RCC firmware library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F4xx_RCC_H
|
||||
#define __STM32F4xx_RCC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f4xx.h"
|
||||
|
||||
/** @addtogroup STM32F4xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup RCC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency expressed in Hz */
|
||||
uint32_t HCLK_Frequency; /*!< HCLK clock frequency expressed in Hz */
|
||||
uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency expressed in Hz */
|
||||
uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency expressed in Hz */
|
||||
}RCC_ClocksTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup RCC_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_HSE_configuration
|
||||
* @{
|
||||
*/
|
||||
#define RCC_HSE_OFF ((uint8_t)0x00)
|
||||
#define RCC_HSE_ON ((uint8_t)0x01)
|
||||
#define RCC_HSE_Bypass ((uint8_t)0x05)
|
||||
#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
|
||||
((HSE) == RCC_HSE_Bypass))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_LSE_Dual_Mode_Selection
|
||||
* @{
|
||||
*/
|
||||
#define RCC_LSE_LOWPOWER_MODE ((uint8_t)0x00)
|
||||
#define RCC_LSE_HIGHDRIVE_MODE ((uint8_t)0x01)
|
||||
#define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) || \
|
||||
((MODE) == RCC_LSE_HIGHDRIVE_MODE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_PLLSAIDivR_Factor
|
||||
* @{
|
||||
*/
|
||||
#define RCC_PLLSAIDivR_Div2 ((uint32_t)0x00000000)
|
||||
#define RCC_PLLSAIDivR_Div4 ((uint32_t)0x00010000)
|
||||
#define RCC_PLLSAIDivR_Div8 ((uint32_t)0x00020000)
|
||||
#define RCC_PLLSAIDivR_Div16 ((uint32_t)0x00030000)
|
||||
#define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDivR_Div2) ||\
|
||||
((VALUE) == RCC_PLLSAIDivR_Div4) ||\
|
||||
((VALUE) == RCC_PLLSAIDivR_Div8) ||\
|
||||
((VALUE) == RCC_PLLSAIDivR_Div16))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_PLL_Clock_Source
|
||||
* @{
|
||||
*/
|
||||
#define RCC_PLLSource_HSI ((uint32_t)0x00000000)
|
||||
#define RCC_PLLSource_HSE ((uint32_t)0x00400000)
|
||||
#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI) || \
|
||||
((SOURCE) == RCC_PLLSource_HSE))
|
||||
#define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63)
|
||||
#define IS_RCC_PLLN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432))
|
||||
#define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8))
|
||||
#define IS_RCC_PLLQ_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 15))
|
||||
#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F446xx) || defined(STM32F469_479xx)
|
||||
#define IS_RCC_PLLR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
|
||||
#endif /* STM32F410xx || STM32F412xG || STM32F446xx || STM32F469_479xx */
|
||||
|
||||
#define IS_RCC_PLLI2SN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432))
|
||||
#define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
|
||||
#define IS_RCC_PLLI2SM_VALUE(VALUE) ((VALUE) <= 63)
|
||||
#define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
|
||||
#if defined(STM32F446xx)
|
||||
#define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8))
|
||||
#define IS_RCC_PLLSAIM_VALUE(VALUE) ((VALUE) <= 63)
|
||||
#elif defined(STM32F412xG)
|
||||
#define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8))
|
||||
#else
|
||||
#endif /* STM32F446xx */
|
||||
#define IS_RCC_PLLSAIN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432))
|
||||
#if defined(STM32F446xx) || defined(STM32F469_479xx)
|
||||
#define IS_RCC_PLLSAIP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8))
|
||||
#endif /* STM32F446xx || STM32F469_479xx */
|
||||
#define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
|
||||
#define IS_RCC_PLLSAIR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
|
||||
|
||||
#define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
|
||||
#define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_System_Clock_Source
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(STM32F412xG) || defined(STM32F446xx)
|
||||
#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000)
|
||||
#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001)
|
||||
#define RCC_SYSCLKSource_PLLPCLK ((uint32_t)0x00000002)
|
||||
#define RCC_SYSCLKSource_PLLRCLK ((uint32_t)0x00000003)
|
||||
#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \
|
||||
((SOURCE) == RCC_SYSCLKSource_HSE) || \
|
||||
((SOURCE) == RCC_SYSCLKSource_PLLPCLK) || \
|
||||
((SOURCE) == RCC_SYSCLKSource_PLLRCLK))
|
||||
/* Add legacy definition */
|
||||
#define RCC_SYSCLKSource_PLLCLK RCC_SYSCLKSource_PLLPCLK
|
||||
#endif /* STM32F446xx */
|
||||
|
||||
#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F410xx) || defined(STM32F411xE) || defined(STM32F469_479xx)
|
||||
#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000)
|
||||
#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001)
|
||||
#define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002)
|
||||
#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \
|
||||
((SOURCE) == RCC_SYSCLKSource_HSE) || \
|
||||
((SOURCE) == RCC_SYSCLKSource_PLLCLK))
|
||||
#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F410xx || STM32F411xE || STM32F469_479xx */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_AHB_Clock_Source
|
||||
* @{
|
||||
*/
|
||||
#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000)
|
||||
#define RCC_SYSCLK_Div2 ((uint32_t)0x00000080)
|
||||
#define RCC_SYSCLK_Div4 ((uint32_t)0x00000090)
|
||||
#define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0)
|
||||
#define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0)
|
||||
#define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0)
|
||||
#define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0)
|
||||
#define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0)
|
||||
#define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0)
|
||||
#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \
|
||||
((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \
|
||||
((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \
|
||||
((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \
|
||||
((HCLK) == RCC_SYSCLK_Div512))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_APB1_APB2_Clock_Source
|
||||
* @{
|
||||
*/
|
||||
#define RCC_HCLK_Div1 ((uint32_t)0x00000000)
|
||||
#define RCC_HCLK_Div2 ((uint32_t)0x00001000)
|
||||
#define RCC_HCLK_Div4 ((uint32_t)0x00001400)
|
||||
#define RCC_HCLK_Div8 ((uint32_t)0x00001800)
|
||||
#define RCC_HCLK_Div16 ((uint32_t)0x00001C00)
|
||||
#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \
|
||||
((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \
|
||||
((PCLK) == RCC_HCLK_Div16))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_Interrupt_Source
|
||||
* @{
|
||||
*/
|
||||
#define RCC_IT_LSIRDY ((uint8_t)0x01)
|
||||
#define RCC_IT_LSERDY ((uint8_t)0x02)
|
||||
#define RCC_IT_HSIRDY ((uint8_t)0x04)
|
||||
#define RCC_IT_HSERDY ((uint8_t)0x08)
|
||||
#define RCC_IT_PLLRDY ((uint8_t)0x10)
|
||||
#define RCC_IT_PLLI2SRDY ((uint8_t)0x20)
|
||||
#define RCC_IT_PLLSAIRDY ((uint8_t)0x40)
|
||||
#define RCC_IT_CSS ((uint8_t)0x80)
|
||||
|
||||
#define IS_RCC_IT(IT) ((((IT) & (uint8_t)0x80) == 0x00) && ((IT) != 0x00))
|
||||
#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
|
||||
((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
|
||||
((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS) || \
|
||||
((IT) == RCC_IT_PLLSAIRDY) || ((IT) == RCC_IT_PLLI2SRDY))
|
||||
#define IS_RCC_CLEAR_IT(IT)((IT) != 0x00)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_LSE_Configuration
|
||||
* @{
|
||||
*/
|
||||
#define RCC_LSE_OFF ((uint8_t)0x00)
|
||||
#define RCC_LSE_ON ((uint8_t)0x01)
|
||||
#define RCC_LSE_Bypass ((uint8_t)0x04)
|
||||
#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
|
||||
((LSE) == RCC_LSE_Bypass))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_RTC_Clock_Source
|
||||
* @{
|
||||
*/
|
||||
#define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100)
|
||||
#define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200)
|
||||
#define RCC_RTCCLKSource_HSE_Div2 ((uint32_t)0x00020300)
|
||||
#define RCC_RTCCLKSource_HSE_Div3 ((uint32_t)0x00030300)
|
||||
#define RCC_RTCCLKSource_HSE_Div4 ((uint32_t)0x00040300)
|
||||
#define RCC_RTCCLKSource_HSE_Div5 ((uint32_t)0x00050300)
|
||||
#define RCC_RTCCLKSource_HSE_Div6 ((uint32_t)0x00060300)
|
||||
#define RCC_RTCCLKSource_HSE_Div7 ((uint32_t)0x00070300)
|
||||
#define RCC_RTCCLKSource_HSE_Div8 ((uint32_t)0x00080300)
|
||||
#define RCC_RTCCLKSource_HSE_Div9 ((uint32_t)0x00090300)
|
||||
#define RCC_RTCCLKSource_HSE_Div10 ((uint32_t)0x000A0300)
|
||||
#define RCC_RTCCLKSource_HSE_Div11 ((uint32_t)0x000B0300)
|
||||
#define RCC_RTCCLKSource_HSE_Div12 ((uint32_t)0x000C0300)
|
||||
#define RCC_RTCCLKSource_HSE_Div13 ((uint32_t)0x000D0300)
|
||||
#define RCC_RTCCLKSource_HSE_Div14 ((uint32_t)0x000E0300)
|
||||
#define RCC_RTCCLKSource_HSE_Div15 ((uint32_t)0x000F0300)
|
||||
#define RCC_RTCCLKSource_HSE_Div16 ((uint32_t)0x00100300)
|
||||
#define RCC_RTCCLKSource_HSE_Div17 ((uint32_t)0x00110300)
|
||||
#define RCC_RTCCLKSource_HSE_Div18 ((uint32_t)0x00120300)
|
||||
#define RCC_RTCCLKSource_HSE_Div19 ((uint32_t)0x00130300)
|
||||
#define RCC_RTCCLKSource_HSE_Div20 ((uint32_t)0x00140300)
|
||||
#define RCC_RTCCLKSource_HSE_Div21 ((uint32_t)0x00150300)
|
||||
#define RCC_RTCCLKSource_HSE_Div22 ((uint32_t)0x00160300)
|
||||
#define RCC_RTCCLKSource_HSE_Div23 ((uint32_t)0x00170300)
|
||||
#define RCC_RTCCLKSource_HSE_Div24 ((uint32_t)0x00180300)
|
||||
#define RCC_RTCCLKSource_HSE_Div25 ((uint32_t)0x00190300)
|
||||
#define RCC_RTCCLKSource_HSE_Div26 ((uint32_t)0x001A0300)
|
||||
#define RCC_RTCCLKSource_HSE_Div27 ((uint32_t)0x001B0300)
|
||||
#define RCC_RTCCLKSource_HSE_Div28 ((uint32_t)0x001C0300)
|
||||
#define RCC_RTCCLKSource_HSE_Div29 ((uint32_t)0x001D0300)
|
||||
#define RCC_RTCCLKSource_HSE_Div30 ((uint32_t)0x001E0300)
|
||||
#define RCC_RTCCLKSource_HSE_Div31 ((uint32_t)0x001F0300)
|
||||
#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_LSI) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div2) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div3) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div4) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div5) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div6) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div7) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div8) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div9) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div10) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div11) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div12) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div13) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div14) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div15) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div16) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div17) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div18) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div19) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div20) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div21) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div22) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div23) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div24) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div25) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div26) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div27) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div28) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div29) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div30) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div31))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined(STM32F410xx)
|
||||
/** @defgroup RCCEx_LPTIM1_Clock_Source RCC LPTIM1 Clock Source
|
||||
* @{
|
||||
*/
|
||||
#define RCC_LPTIM1CLKSOURCE_PCLK ((uint32_t)0x00000000)
|
||||
#define RCC_LPTIM1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0)
|
||||
#define RCC_LPTIM1CLKSOURCE_LSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_1)
|
||||
#define RCC_LPTIM1CLKSOURCE_LSE ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0 | RCC_DCKCFGR2_LPTIM1SEL_1)
|
||||
|
||||
#define IS_RCC_LPTIM1_CLOCKSOURCE(SOURCE) (((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK) || ((SOURCE) == RCC_LPTIM1CLKSOURCE_HSI) || \
|
||||
((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) || ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE))
|
||||
/* Legacy Defines */
|
||||
#define IS_RCC_LPTIM1_SOURCE IS_RCC_LPTIM1_CLOCKSOURCE
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCCEx_I2S_APB_Clock_Source RCC I2S APB Clock Source
|
||||
* @{
|
||||
*/
|
||||
#define RCC_I2SAPBCLKSOURCE_PLLR ((uint32_t)0x00000000)
|
||||
#define RCC_I2SAPBCLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2SSRC_0)
|
||||
#define RCC_I2SAPBCLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2SSRC_1)
|
||||
#define IS_RCC_I2SCLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2SAPBCLKSOURCE_PLLR) || ((SOURCE) == RCC_I2SAPBCLKSOURCE_EXT) || \
|
||||
((SOURCE) == RCC_I2SAPBCLKSOURCE_PLLSRC))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* STM32F410xx */
|
||||
|
||||
#if defined(STM32F412xG) || defined(STM32F446xx)
|
||||
/** @defgroup RCC_I2S_Clock_Source
|
||||
* @{
|
||||
*/
|
||||
#define RCC_I2SCLKSource_PLLI2S ((uint32_t)0x00)
|
||||
#define RCC_I2SCLKSource_Ext ((uint32_t)RCC_DCKCFGR_I2S1SRC_0)
|
||||
#define RCC_I2SCLKSource_PLL ((uint32_t)RCC_DCKCFGR_I2S1SRC_1)
|
||||
#define RCC_I2SCLKSource_HSI_HSE ((uint32_t)RCC_DCKCFGR_I2S1SRC_0 | RCC_DCKCFGR_I2S1SRC_1)
|
||||
|
||||
#define IS_RCC_I2SCLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2SCLKSource_PLLI2S) || ((SOURCE) == RCC_I2SCLKSource_Ext) || \
|
||||
((SOURCE) == RCC_I2SCLKSource_PLL) || ((SOURCE) == RCC_I2SCLKSource_HSI_HSE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_I2S_APBBus
|
||||
* @{
|
||||
*/
|
||||
#define RCC_I2SBus_APB1 ((uint8_t)0x00)
|
||||
#define RCC_I2SBus_APB2 ((uint8_t)0x01)
|
||||
#define IS_RCC_I2S_APBx(BUS) (((BUS) == RCC_I2SBus_APB1) || ((BUS) == RCC_I2SBus_APB2))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#if defined(STM32F446xx)
|
||||
/** @defgroup RCC_SAI_Clock_Source
|
||||
* @{
|
||||
*/
|
||||
#define RCC_SAICLKSource_PLLSAI ((uint32_t)0x00)
|
||||
#define RCC_SAICLKSource_PLLI2S ((uint32_t)RCC_DCKCFGR_SAI1SRC_0)
|
||||
#define RCC_SAICLKSource_PLL ((uint32_t)RCC_DCKCFGR_SAI1SRC_1)
|
||||
#define RCC_SAICLKSource_HSI_HSE ((uint32_t)RCC_DCKCFGR_SAI1SRC_0 | RCC_DCKCFGR_SAI1SRC_1)
|
||||
|
||||
#define IS_RCC_SAICLK_SOURCE(SOURCE) (((SOURCE) == RCC_SAICLKSource_PLLSAI) || ((SOURCE) == RCC_SAICLKSource_PLLI2S) || \
|
||||
((SOURCE) == RCC_SAICLKSource_PLL) || ((SOURCE) == RCC_SAICLKSource_HSI_HSE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_SAI_Instance
|
||||
* @{
|
||||
*/
|
||||
#define RCC_SAIInstance_SAI1 ((uint8_t)0x00)
|
||||
#define RCC_SAIInstance_SAI2 ((uint8_t)0x01)
|
||||
#define IS_RCC_SAI_INSTANCE(BUS) (((BUS) == RCC_SAIInstance_SAI1) || ((BUS) == RCC_SAIInstance_SAI2))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* STM32F446xx */
|
||||
#endif /* STM32F412xG || STM32F446xx */
|
||||
|
||||
#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE) || defined(STM32F469_479xx)
|
||||
/** @defgroup RCC_I2S_Clock_Source
|
||||
* @{
|
||||
*/
|
||||
#define RCC_I2S2CLKSource_PLLI2S ((uint8_t)0x00)
|
||||
#define RCC_I2S2CLKSource_Ext ((uint8_t)0x01)
|
||||
|
||||
#define IS_RCC_I2SCLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_PLLI2S) || ((SOURCE) == RCC_I2S2CLKSource_Ext))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_SAI_BlockA_Clock_Source
|
||||
* @{
|
||||
*/
|
||||
#define RCC_SAIACLKSource_PLLSAI ((uint32_t)0x00000000)
|
||||
#define RCC_SAIACLKSource_PLLI2S ((uint32_t)0x00100000)
|
||||
#define RCC_SAIACLKSource_Ext ((uint32_t)0x00200000)
|
||||
|
||||
#define IS_RCC_SAIACLK_SOURCE(SOURCE) (((SOURCE) == RCC_SAIACLKSource_PLLI2S) ||\
|
||||
((SOURCE) == RCC_SAIACLKSource_PLLSAI) ||\
|
||||
((SOURCE) == RCC_SAIACLKSource_Ext))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_SAI_BlockB_Clock_Source
|
||||
* @{
|
||||
*/
|
||||
#define RCC_SAIBCLKSource_PLLSAI ((uint32_t)0x00000000)
|
||||
#define RCC_SAIBCLKSource_PLLI2S ((uint32_t)0x00400000)
|
||||
#define RCC_SAIBCLKSource_Ext ((uint32_t)0x00800000)
|
||||
|
||||
#define IS_RCC_SAIBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SAIBCLKSource_PLLI2S) ||\
|
||||
((SOURCE) == RCC_SAIBCLKSource_PLLSAI) ||\
|
||||
((SOURCE) == RCC_SAIBCLKSource_Ext))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE || STM32F469_479xx */
|
||||
|
||||
/** @defgroup RCC_TIM_PRescaler_Selection
|
||||
* @{
|
||||
*/
|
||||
#define RCC_TIMPrescDesactivated ((uint8_t)0x00)
|
||||
#define RCC_TIMPrescActivated ((uint8_t)0x01)
|
||||
|
||||
#define IS_RCC_TIMCLK_PRESCALER(VALUE) (((VALUE) == RCC_TIMPrescDesactivated) || ((VALUE) == RCC_TIMPrescActivated))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined(STM32F469_479xx)
|
||||
/** @defgroup RCC_DSI_Clock_Source_Selection
|
||||
* @{
|
||||
*/
|
||||
#define RCC_DSICLKSource_PHY ((uint8_t)0x00)
|
||||
#define RCC_DSICLKSource_PLLR ((uint8_t)0x01)
|
||||
#define IS_RCC_DSI_CLOCKSOURCE(CLKSOURCE) (((CLKSOURCE) == RCC_DSICLKSource_PHY) || \
|
||||
((CLKSOURCE) == RCC_DSICLKSource_PLLR))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* STM32F469_479xx */
|
||||
|
||||
#if defined(STM32F412xG) || defined(STM32F446xx) || defined(STM32F469_479xx)
|
||||
/** @defgroup RCC_SDIO_Clock_Source_Selection
|
||||
* @{
|
||||
*/
|
||||
#define RCC_SDIOCLKSource_48MHZ ((uint8_t)0x00)
|
||||
#define RCC_SDIOCLKSource_SYSCLK ((uint8_t)0x01)
|
||||
#define IS_RCC_SDIO_CLOCKSOURCE(CLKSOURCE) (((CLKSOURCE) == RCC_SDIOCLKSource_48MHZ) || \
|
||||
((CLKSOURCE) == RCC_SDIOCLKSource_SYSCLK))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup RCC_48MHZ_Clock_Source_Selection
|
||||
* @{
|
||||
*/
|
||||
#if defined(STM32F446xx) || defined(STM32F469_479xx)
|
||||
#define RCC_48MHZCLKSource_PLL ((uint8_t)0x00)
|
||||
#define RCC_48MHZCLKSource_PLLSAI ((uint8_t)0x01)
|
||||
#define IS_RCC_48MHZ_CLOCKSOURCE(CLKSOURCE) (((CLKSOURCE) == RCC_48MHZCLKSource_PLL) || \
|
||||
((CLKSOURCE) == RCC_48MHZCLKSource_PLLSAI))
|
||||
#endif /* STM32F446xx || STM32F469_479xx */
|
||||
#if defined(STM32F412xG)
|
||||
#define RCC_CK48CLKSOURCE_PLLQ ((uint8_t)0x00)
|
||||
#define RCC_CK48CLKSOURCE_PLLI2SQ ((uint8_t)0x01) /* Only for STM32F412xG Devices */
|
||||
#define IS_RCC_48MHZ_CLOCKSOURCE(CLKSOURCE) (((CLKSOURCE) == RCC_CK48CLKSOURCE_PLLQ) || \
|
||||
((CLKSOURCE) == RCC_CK48CLKSOURCE_PLLI2SQ))
|
||||
#endif /* STM32F412xG */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* STM32F412xG || STM32F446xx || STM32F469_479xx */
|
||||
|
||||
#if defined(STM32F446xx)
|
||||
/** @defgroup RCC_SPDIFRX_Clock_Source_Selection
|
||||
* @{
|
||||
*/
|
||||
#define RCC_SPDIFRXCLKSource_PLLR ((uint8_t)0x00)
|
||||
#define RCC_SPDIFRXCLKSource_PLLI2SP ((uint8_t)0x01)
|
||||
#define IS_RCC_SPDIFRX_CLOCKSOURCE(CLKSOURCE) (((CLKSOURCE) == RCC_SPDIFRXCLKSource_PLLR) || \
|
||||
((CLKSOURCE) == RCC_SPDIFRXCLKSource_PLLI2SP))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_CEC_Clock_Source_Selection
|
||||
* @{
|
||||
*/
|
||||
#define RCC_CECCLKSource_HSIDiv488 ((uint8_t)0x00)
|
||||
#define RCC_CECCLKSource_LSE ((uint8_t)0x01)
|
||||
#define IS_RCC_CEC_CLOCKSOURCE(CLKSOURCE) (((CLKSOURCE) == RCC_CECCLKSource_HSIDiv488) || \
|
||||
((CLKSOURCE) == RCC_CECCLKSource_LSE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_AHB1_ClockGating
|
||||
* @{
|
||||
*/
|
||||
#define RCC_AHB1ClockGating_APB1Bridge ((uint32_t)0x00000001)
|
||||
#define RCC_AHB1ClockGating_APB2Bridge ((uint32_t)0x00000002)
|
||||
#define RCC_AHB1ClockGating_CM4DBG ((uint32_t)0x00000004)
|
||||
#define RCC_AHB1ClockGating_SPARE ((uint32_t)0x00000008)
|
||||
#define RCC_AHB1ClockGating_SRAM ((uint32_t)0x00000010)
|
||||
#define RCC_AHB1ClockGating_FLITF ((uint32_t)0x00000020)
|
||||
#define RCC_AHB1ClockGating_RCC ((uint32_t)0x00000040)
|
||||
|
||||
#define IS_RCC_AHB1_CLOCKGATING(PERIPH) ((((PERIPH) & 0xFFFFFF80) == 0x00) && ((PERIPH) != 0x00))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* STM32F446xx */
|
||||
|
||||
#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F446xx)
|
||||
/** @defgroup RCC_FMPI2C1_Clock_Source
|
||||
* @{
|
||||
*/
|
||||
#define RCC_FMPI2C1CLKSource_APB1 ((uint32_t)0x00)
|
||||
#define RCC_FMPI2C1CLKSource_SYSCLK ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0)
|
||||
#define RCC_FMPI2C1CLKSource_HSI ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1)
|
||||
|
||||
#define IS_RCC_FMPI2C1_CLOCKSOURCE(SOURCE) (((SOURCE) == RCC_FMPI2C1CLKSource_APB1) || ((SOURCE) == RCC_FMPI2C1CLKSource_SYSCLK) || \
|
||||
((SOURCE) == RCC_FMPI2C1CLKSource_HSI))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* STM32F410xx || STM32F412xG || STM32F446xx */
|
||||
|
||||
#if defined(STM32F412xG)
|
||||
/** @defgroup RCC_DFSDM_Clock_Source
|
||||
* @{
|
||||
*/
|
||||
#define RCC_DFSDM1CLKSource_APB ((uint8_t)0x00)
|
||||
#define RCC_DFSDM1CLKSource_SYS ((uint8_t)0x01)
|
||||
#define IS_RCC_DFSDM1CLK_SOURCE(SOURCE) (((SOURCE) == RCC_DFSDM1CLKSource_APB) || ((SOURCE) == RCC_DFSDM1CLKSource_SYS))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_DFSDM_Audio_Clock_Source RCC DFSDM Audio Clock Source
|
||||
* @{
|
||||
*/
|
||||
#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 ((uint32_t)0x00000000)
|
||||
#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 ((uint32_t)RCC_DCKCFGR_CKDFSDM1ASEL)
|
||||
#define IS_RCC_DFSDMACLK_SOURCE(SOURCE) (((SOURCE) == RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1) || ((SOURCE) == RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* STM32F412xG */
|
||||
|
||||
/** @defgroup RCC_AHB1_Peripherals
|
||||
* @{
|
||||
*/
|
||||
#define RCC_AHB1Periph_GPIOA ((uint32_t)0x00000001)
|
||||
#define RCC_AHB1Periph_GPIOB ((uint32_t)0x00000002)
|
||||
#define RCC_AHB1Periph_GPIOC ((uint32_t)0x00000004)
|
||||
#define RCC_AHB1Periph_GPIOD ((uint32_t)0x00000008)
|
||||
#define RCC_AHB1Periph_GPIOE ((uint32_t)0x00000010)
|
||||
#define RCC_AHB1Periph_GPIOF ((uint32_t)0x00000020)
|
||||
#define RCC_AHB1Periph_GPIOG ((uint32_t)0x00000040)
|
||||
#define RCC_AHB1Periph_GPIOH ((uint32_t)0x00000080)
|
||||
#define RCC_AHB1Periph_GPIOI ((uint32_t)0x00000100)
|
||||
#define RCC_AHB1Periph_GPIOJ ((uint32_t)0x00000200)
|
||||
#define RCC_AHB1Periph_GPIOK ((uint32_t)0x00000400)
|
||||
#define RCC_AHB1Periph_CRC ((uint32_t)0x00001000)
|
||||
#define RCC_AHB1Periph_FLITF ((uint32_t)0x00008000)
|
||||
#define RCC_AHB1Periph_SRAM1 ((uint32_t)0x00010000)
|
||||
#define RCC_AHB1Periph_SRAM2 ((uint32_t)0x00020000)
|
||||
#define RCC_AHB1Periph_BKPSRAM ((uint32_t)0x00040000)
|
||||
#define RCC_AHB1Periph_SRAM3 ((uint32_t)0x00080000)
|
||||
#define RCC_AHB1Periph_CCMDATARAMEN ((uint32_t)0x00100000)
|
||||
#define RCC_AHB1Periph_DMA1 ((uint32_t)0x00200000)
|
||||
#define RCC_AHB1Periph_DMA2 ((uint32_t)0x00400000)
|
||||
#define RCC_AHB1Periph_DMA2D ((uint32_t)0x00800000)
|
||||
#define RCC_AHB1Periph_ETH_MAC ((uint32_t)0x02000000)
|
||||
#define RCC_AHB1Periph_ETH_MAC_Tx ((uint32_t)0x04000000)
|
||||
#define RCC_AHB1Periph_ETH_MAC_Rx ((uint32_t)0x08000000)
|
||||
#define RCC_AHB1Periph_ETH_MAC_PTP ((uint32_t)0x10000000)
|
||||
#define RCC_AHB1Periph_OTG_HS ((uint32_t)0x20000000)
|
||||
#define RCC_AHB1Periph_OTG_HS_ULPI ((uint32_t)0x40000000)
|
||||
#if defined(STM32F410xx)
|
||||
#define RCC_AHB1Periph_RNG ((uint32_t)0x80000000)
|
||||
#endif /* STM32F410xx */
|
||||
#define IS_RCC_AHB1_CLOCK_PERIPH(PERIPH) ((((PERIPH) & 0x010BE800) == 0x00) && ((PERIPH) != 0x00))
|
||||
#define IS_RCC_AHB1_RESET_PERIPH(PERIPH) ((((PERIPH) & 0x51FE800) == 0x00) && ((PERIPH) != 0x00))
|
||||
#define IS_RCC_AHB1_LPMODE_PERIPH(PERIPH) ((((PERIPH) & 0x01106800) == 0x00) && ((PERIPH) != 0x00))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_AHB2_Peripherals
|
||||
* @{
|
||||
*/
|
||||
#define RCC_AHB2Periph_DCMI ((uint32_t)0x00000001)
|
||||
#define RCC_AHB2Periph_CRYP ((uint32_t)0x00000010)
|
||||
#define RCC_AHB2Periph_HASH ((uint32_t)0x00000020)
|
||||
#if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F469_479xx)
|
||||
#define RCC_AHB2Periph_RNG ((uint32_t)0x00000040)
|
||||
#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F469_479xx */
|
||||
#define RCC_AHB2Periph_OTG_FS ((uint32_t)0x00000080)
|
||||
#define IS_RCC_AHB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFF0E) == 0x00) && ((PERIPH) != 0x00))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_AHB3_Peripherals
|
||||
* @{
|
||||
*/
|
||||
#if defined(STM32F40_41xxx)
|
||||
#define RCC_AHB3Periph_FSMC ((uint32_t)0x00000001)
|
||||
#define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFE) == 0x00) && ((PERIPH) != 0x00))
|
||||
#endif /* STM32F40_41xxx */
|
||||
|
||||
#if defined(STM32F427_437xx) || defined(STM32F429_439xx)
|
||||
#define RCC_AHB3Periph_FMC ((uint32_t)0x00000001)
|
||||
#define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFE) == 0x00) && ((PERIPH) != 0x00))
|
||||
#endif /* STM32F427_437xx || STM32F429_439xx */
|
||||
|
||||
#if defined(STM32F446xx) || defined(STM32F469_479xx)
|
||||
#define RCC_AHB3Periph_FMC ((uint32_t)0x00000001)
|
||||
#define RCC_AHB3Periph_QSPI ((uint32_t)0x00000002)
|
||||
#define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFC) == 0x00) && ((PERIPH) != 0x00))
|
||||
#endif /* STM32F446xx || STM32F469_479xx */
|
||||
|
||||
#if defined(STM32F412xG)
|
||||
#define RCC_AHB3Periph_FSMC ((uint32_t)0x00000001)
|
||||
#define RCC_AHB3Periph_QSPI ((uint32_t)0x00000002)
|
||||
#define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFC) == 0x00) && ((PERIPH) != 0x00))
|
||||
#endif /* STM32F412xG */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_APB1_Peripherals
|
||||
* @{
|
||||
*/
|
||||
#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001)
|
||||
#define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002)
|
||||
#define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004)
|
||||
#define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008)
|
||||
#define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010)
|
||||
#define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020)
|
||||
#define RCC_APB1Periph_TIM12 ((uint32_t)0x00000040)
|
||||
#define RCC_APB1Periph_TIM13 ((uint32_t)0x00000080)
|
||||
#define RCC_APB1Periph_TIM14 ((uint32_t)0x00000100)
|
||||
#if defined(STM32F410xx)
|
||||
#define RCC_APB1Periph_LPTIM1 ((uint32_t)0x00000200)
|
||||
#endif /* STM32F410xx */
|
||||
#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800)
|
||||
#define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000)
|
||||
#define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000)
|
||||
#if defined(STM32F446xx)
|
||||
#define RCC_APB1Periph_SPDIFRX ((uint32_t)0x00010000)
|
||||
#endif /* STM32F446xx */
|
||||
#define RCC_APB1Periph_USART2 ((uint32_t)0x00020000)
|
||||
#define RCC_APB1Periph_USART3 ((uint32_t)0x00040000)
|
||||
#define RCC_APB1Periph_UART4 ((uint32_t)0x00080000)
|
||||
#define RCC_APB1Periph_UART5 ((uint32_t)0x00100000)
|
||||
#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000)
|
||||
#define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000)
|
||||
#define RCC_APB1Periph_I2C3 ((uint32_t)0x00800000)
|
||||
#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F446xx)
|
||||
#define RCC_APB1Periph_FMPI2C1 ((uint32_t)0x01000000)
|
||||
#endif /* STM32F410xx || STM32F446xx */
|
||||
#define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000)
|
||||
#define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000)
|
||||
#if defined(STM32F446xx)
|
||||
#define RCC_APB1Periph_CEC ((uint32_t)0x08000000)
|
||||
#endif /* STM32F446xx */
|
||||
#define RCC_APB1Periph_PWR ((uint32_t)0x10000000)
|
||||
#define RCC_APB1Periph_DAC ((uint32_t)0x20000000)
|
||||
#define RCC_APB1Periph_UART7 ((uint32_t)0x40000000)
|
||||
#define RCC_APB1Periph_UART8 ((uint32_t)0x80000000)
|
||||
#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x00003600) == 0x00) && ((PERIPH) != 0x00))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_APB2_Peripherals
|
||||
* @{
|
||||
*/
|
||||
#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000001)
|
||||
#define RCC_APB2Periph_TIM8 ((uint32_t)0x00000002)
|
||||
#define RCC_APB2Periph_USART1 ((uint32_t)0x00000010)
|
||||
#define RCC_APB2Periph_USART6 ((uint32_t)0x00000020)
|
||||
#define RCC_APB2Periph_ADC ((uint32_t)0x00000100)
|
||||
#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000100)
|
||||
#define RCC_APB2Periph_ADC2 ((uint32_t)0x00000200)
|
||||
#define RCC_APB2Periph_ADC3 ((uint32_t)0x00000400)
|
||||
#define RCC_APB2Periph_SDIO ((uint32_t)0x00000800)
|
||||
#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000)
|
||||
#define RCC_APB2Periph_SPI4 ((uint32_t)0x00002000)
|
||||
#define RCC_APB2Periph_SYSCFG ((uint32_t)0x00004000)
|
||||
#define RCC_APB2Periph_TIM9 ((uint32_t)0x00010000)
|
||||
#define RCC_APB2Periph_TIM10 ((uint32_t)0x00020000)
|
||||
#define RCC_APB2Periph_TIM11 ((uint32_t)0x00040000)
|
||||
#define RCC_APB2Periph_SPI5 ((uint32_t)0x00100000)
|
||||
#define RCC_APB2Periph_SPI6 ((uint32_t)0x00200000)
|
||||
#define RCC_APB2Periph_SAI1 ((uint32_t)0x00400000)
|
||||
#if defined(STM32F446xx) || defined(STM32F469_479xx)
|
||||
#define RCC_APB2Periph_SAI2 ((uint32_t)0x00800000)
|
||||
#endif /* STM32F446xx || STM32F469_479xx */
|
||||
#define RCC_APB2Periph_LTDC ((uint32_t)0x04000000)
|
||||
#if defined(STM32F469_479xx)
|
||||
#define RCC_APB2Periph_DSI ((uint32_t)0x08000000)
|
||||
#endif /* STM32F469_479xx */
|
||||
#if defined(STM32F412xG)
|
||||
#define RCC_APB2Periph_DFSDM ((uint32_t)0x01000000)
|
||||
#endif /* STM32F412xG */
|
||||
|
||||
#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xF20880CC) == 0x00) && ((PERIPH) != 0x00))
|
||||
#define IS_RCC_APB2_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xF20886CC) == 0x00) && ((PERIPH) != 0x00))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_MCO1_Clock_Source_Prescaler
|
||||
* @{
|
||||
*/
|
||||
#define RCC_MCO1Source_HSI ((uint32_t)0x00000000)
|
||||
#define RCC_MCO1Source_LSE ((uint32_t)0x00200000)
|
||||
#define RCC_MCO1Source_HSE ((uint32_t)0x00400000)
|
||||
#define RCC_MCO1Source_PLLCLK ((uint32_t)0x00600000)
|
||||
#define RCC_MCO1Div_1 ((uint32_t)0x00000000)
|
||||
#define RCC_MCO1Div_2 ((uint32_t)0x04000000)
|
||||
#define RCC_MCO1Div_3 ((uint32_t)0x05000000)
|
||||
#define RCC_MCO1Div_4 ((uint32_t)0x06000000)
|
||||
#define RCC_MCO1Div_5 ((uint32_t)0x07000000)
|
||||
#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1Source_HSI) || ((SOURCE) == RCC_MCO1Source_LSE) || \
|
||||
((SOURCE) == RCC_MCO1Source_HSE) || ((SOURCE) == RCC_MCO1Source_PLLCLK))
|
||||
|
||||
#define IS_RCC_MCO1DIV(DIV) (((DIV) == RCC_MCO1Div_1) || ((DIV) == RCC_MCO1Div_2) || \
|
||||
((DIV) == RCC_MCO1Div_3) || ((DIV) == RCC_MCO1Div_4) || \
|
||||
((DIV) == RCC_MCO1Div_5))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_MCO2_Clock_Source_Prescaler
|
||||
* @{
|
||||
*/
|
||||
#define RCC_MCO2Source_SYSCLK ((uint32_t)0x00000000)
|
||||
#define RCC_MCO2Source_PLLI2SCLK ((uint32_t)0x40000000)
|
||||
#define RCC_MCO2Source_HSE ((uint32_t)0x80000000)
|
||||
#define RCC_MCO2Source_PLLCLK ((uint32_t)0xC0000000)
|
||||
#define RCC_MCO2Div_1 ((uint32_t)0x00000000)
|
||||
#define RCC_MCO2Div_2 ((uint32_t)0x20000000)
|
||||
#define RCC_MCO2Div_3 ((uint32_t)0x28000000)
|
||||
#define RCC_MCO2Div_4 ((uint32_t)0x30000000)
|
||||
#define RCC_MCO2Div_5 ((uint32_t)0x38000000)
|
||||
#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2Source_SYSCLK) || ((SOURCE) == RCC_MCO2Source_PLLI2SCLK)|| \
|
||||
((SOURCE) == RCC_MCO2Source_HSE) || ((SOURCE) == RCC_MCO2Source_PLLCLK))
|
||||
|
||||
#define IS_RCC_MCO2DIV(DIV) (((DIV) == RCC_MCO2Div_1) || ((DIV) == RCC_MCO2Div_2) || \
|
||||
((DIV) == RCC_MCO2Div_3) || ((DIV) == RCC_MCO2Div_4) || \
|
||||
((DIV) == RCC_MCO2Div_5))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_Flag
|
||||
* @{
|
||||
*/
|
||||
#define RCC_FLAG_HSIRDY ((uint8_t)0x21)
|
||||
#define RCC_FLAG_HSERDY ((uint8_t)0x31)
|
||||
#define RCC_FLAG_PLLRDY ((uint8_t)0x39)
|
||||
#define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B)
|
||||
#define RCC_FLAG_PLLSAIRDY ((uint8_t)0x3D)
|
||||
#define RCC_FLAG_LSERDY ((uint8_t)0x41)
|
||||
#define RCC_FLAG_LSIRDY ((uint8_t)0x61)
|
||||
#define RCC_FLAG_BORRST ((uint8_t)0x79)
|
||||
#define RCC_FLAG_PINRST ((uint8_t)0x7A)
|
||||
#define RCC_FLAG_PORRST ((uint8_t)0x7B)
|
||||
#define RCC_FLAG_SFTRST ((uint8_t)0x7C)
|
||||
#define RCC_FLAG_IWDGRST ((uint8_t)0x7D)
|
||||
#define RCC_FLAG_WWDGRST ((uint8_t)0x7E)
|
||||
#define RCC_FLAG_LPWRRST ((uint8_t)0x7F)
|
||||
|
||||
#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
|
||||
((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
|
||||
((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_BORRST) || \
|
||||
((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \
|
||||
((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST)|| \
|
||||
((FLAG) == RCC_FLAG_WWDGRST) || ((FLAG) == RCC_FLAG_LPWRRST)|| \
|
||||
((FLAG) == RCC_FLAG_PLLI2SRDY)|| ((FLAG) == RCC_FLAG_PLLSAIRDY))
|
||||
|
||||
#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/* Function used to set the RCC clock configuration to the default reset state */
|
||||
void RCC_DeInit(void);
|
||||
|
||||
/* Internal/external clocks, PLL, CSS and MCO configuration functions *********/
|
||||
void RCC_HSEConfig(uint8_t RCC_HSE);
|
||||
ErrorStatus RCC_WaitForHSEStartUp(void);
|
||||
void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
|
||||
void RCC_HSICmd(FunctionalState NewState);
|
||||
void RCC_LSEConfig(uint8_t RCC_LSE);
|
||||
void RCC_LSICmd(FunctionalState NewState);
|
||||
|
||||
void RCC_PLLCmd(FunctionalState NewState);
|
||||
|
||||
#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F446xx) || defined(STM32F469_479xx)
|
||||
void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ, uint32_t PLLR);
|
||||
#endif /* STM32F410xx || STM32F412xG || STM32F446xx || STM32F469_479xx */
|
||||
|
||||
#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE)
|
||||
void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ);
|
||||
#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE */
|
||||
|
||||
void RCC_PLLI2SCmd(FunctionalState NewState);
|
||||
|
||||
#if defined(STM32F40_41xxx) || defined(STM32F401xx)
|
||||
void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR);
|
||||
#endif /* STM32F40_41xxx || STM32F401xx */
|
||||
#if defined(STM32F411xE)
|
||||
void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR, uint32_t PLLI2SM);
|
||||
#endif /* STM32F411xE */
|
||||
#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F469_479xx)
|
||||
void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SQ, uint32_t PLLI2SR);
|
||||
#endif /* STM32F427_437xx || STM32F429_439xx || STM32F469_479xx */
|
||||
#if defined(STM32F412xG) || defined(STM32F446xx)
|
||||
void RCC_PLLI2SConfig(uint32_t PLLI2SM, uint32_t PLLI2SN, uint32_t PLLI2SP, uint32_t PLLI2SQ, uint32_t PLLI2SR);
|
||||
#endif /* STM32F412xG || STM32F446xx */
|
||||
|
||||
void RCC_PLLSAICmd(FunctionalState NewState);
|
||||
#if defined(STM32F469_479xx)
|
||||
void RCC_PLLSAIConfig(uint32_t PLLSAIN, uint32_t PLLSAIP, uint32_t PLLSAIQ, uint32_t PLLSAIR);
|
||||
#endif /* STM32F469_479xx */
|
||||
#if defined(STM32F446xx)
|
||||
void RCC_PLLSAIConfig(uint32_t PLLSAIM, uint32_t PLLSAIN, uint32_t PLLSAIP, uint32_t PLLSAIQ);
|
||||
#endif /* STM32F446xx */
|
||||
#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE)
|
||||
void RCC_PLLSAIConfig(uint32_t PLLSAIN, uint32_t PLLSAIQ, uint32_t PLLSAIR);
|
||||
#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE */
|
||||
|
||||
void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
|
||||
void RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div);
|
||||
void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div);
|
||||
|
||||
/* System, AHB and APB busses clocks configuration functions ******************/
|
||||
void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
|
||||
uint8_t RCC_GetSYSCLKSource(void);
|
||||
void RCC_HCLKConfig(uint32_t RCC_SYSCLK);
|
||||
void RCC_PCLK1Config(uint32_t RCC_HCLK);
|
||||
void RCC_PCLK2Config(uint32_t RCC_HCLK);
|
||||
void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);
|
||||
|
||||
/* Peripheral clocks configuration functions **********************************/
|
||||
void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
|
||||
void RCC_RTCCLKCmd(FunctionalState NewState);
|
||||
void RCC_BackupResetCmd(FunctionalState NewState);
|
||||
|
||||
#if defined(STM32F412xG) || defined(STM32F446xx)
|
||||
void RCC_I2SCLKConfig(uint32_t RCC_I2SAPBx, uint32_t RCC_I2SCLKSource);
|
||||
#if defined(STM32F446xx)
|
||||
void RCC_SAICLKConfig(uint32_t RCC_SAIInstance, uint32_t RCC_SAICLKSource);
|
||||
#endif /* STM32F446xx */
|
||||
#endif /* STM32F412xG || STM32F446xx */
|
||||
|
||||
#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F410xx) || defined(STM32F411xE) || defined(STM32F469_479xx)
|
||||
void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource);
|
||||
#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F410xx || STM32F411xE || STM32F469_479xx */
|
||||
|
||||
#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F469_479xx)
|
||||
void RCC_SAIBlockACLKConfig(uint32_t RCC_SAIBlockACLKSource);
|
||||
void RCC_SAIBlockBCLKConfig(uint32_t RCC_SAIBlockBCLKSource);
|
||||
#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F469_479xx */
|
||||
|
||||
void RCC_SAIPLLI2SClkDivConfig(uint32_t RCC_PLLI2SDivQ);
|
||||
void RCC_SAIPLLSAIClkDivConfig(uint32_t RCC_PLLSAIDivQ);
|
||||
|
||||
void RCC_LTDCCLKDivConfig(uint32_t RCC_PLLSAIDivR);
|
||||
void RCC_TIMCLKPresConfig(uint32_t RCC_TIMCLKPrescaler);
|
||||
|
||||
void RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState);
|
||||
void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);
|
||||
void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);
|
||||
void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
|
||||
void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
|
||||
|
||||
void RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState);
|
||||
void RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);
|
||||
void RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);
|
||||
void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
|
||||
void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
|
||||
|
||||
void RCC_AHB1PeriphClockLPModeCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState);
|
||||
void RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);
|
||||
void RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);
|
||||
void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
|
||||
void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
|
||||
|
||||
/* Features available only for STM32F410xx/STM32F411xx/STM32F446xx/STM32F469_479xx devices */
|
||||
void RCC_LSEModeConfig(uint8_t RCC_Mode);
|
||||
|
||||
/* Features available only for STM32F469_479xx devices */
|
||||
#if defined(STM32F469_479xx)
|
||||
void RCC_DSIClockSourceConfig(uint8_t RCC_ClockSource);
|
||||
#endif /* STM32F469_479xx */
|
||||
|
||||
/* Features available only for STM32F412xG/STM32F446xx/STM32F469_479xx devices */
|
||||
#if defined(STM32F412xG) || defined(STM32F446xx) || defined(STM32F469_479xx)
|
||||
void RCC_48MHzClockSourceConfig(uint8_t RCC_ClockSource);
|
||||
void RCC_SDIOClockSourceConfig(uint8_t RCC_ClockSource);
|
||||
#endif /* STM32F412xG || STM32F446xx || STM32F469_479xx */
|
||||
|
||||
/* Features available only for STM32F446xx devices */
|
||||
#if defined(STM32F446xx)
|
||||
void RCC_AHB1ClockGatingCmd(uint32_t RCC_AHB1ClockGating, FunctionalState NewState);
|
||||
void RCC_SPDIFRXClockSourceConfig(uint8_t RCC_ClockSource);
|
||||
void RCC_CECClockSourceConfig(uint8_t RCC_ClockSource);
|
||||
#endif /* STM32F446xx */
|
||||
|
||||
/* Features available only for STM32F410xx/STM32F412xG/STM32F446xx devices */
|
||||
#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F446xx)
|
||||
void RCC_FMPI2C1ClockSourceConfig(uint32_t RCC_ClockSource);
|
||||
#endif /* STM32F410xx || STM32F412xG || STM32F446xx */
|
||||
|
||||
/* Features available only for STM32F410xx devices */
|
||||
#if defined(STM32F410xx)
|
||||
void RCC_LPTIM1ClockSourceConfig(uint32_t RCC_ClockSource);
|
||||
|
||||
void RCC_MCO1Cmd(FunctionalState NewState);
|
||||
void RCC_MCO2Cmd(FunctionalState NewState);
|
||||
#endif /* STM32F410xx */
|
||||
|
||||
#if defined(STM32F412xG)
|
||||
void RCC_DFSDM1CLKConfig(uint32_t RCC_DFSDM1CLKSource);
|
||||
void RCC_DFSDM1ACLKConfig(uint32_t RCC_DFSDM1ACLKSource);
|
||||
#endif /* STM32F412xG */
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
|
||||
FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
|
||||
void RCC_ClearFlag(void);
|
||||
ITStatus RCC_GetITStatus(uint8_t RCC_IT);
|
||||
void RCC_ClearITPendingBit(uint8_t RCC_IT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F4xx_RCC_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
Reference in New Issue
Block a user