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lib/main/AT32F43x/Drivers/AT32F43x_StdPeriph_Driver/src/at32f435_437_acc.c

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+/**
+  **************************************************************************
+  * @file     at32f435_437_acc.c
+  * @version  v2.1.0
+  * @date     2022-08-16
+  * @brief    contains all the functions for the acc firmware library
+  **************************************************************************
+  *                       Copyright notice & Disclaimer
+  *
+  * The software Board Support Package (BSP) that is made available to
+  * download from Artery official website is the copyrighted work of Artery.
+  * Artery authorizes customers to use, copy, and distribute the BSP
+  * software and its related documentation for the purpose of design and
+  * development in conjunction with Artery microcontrollers. Use of the
+  * software is governed by this copyright notice and the following disclaimer.
+  *
+  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+  *
+  **************************************************************************
+  */
+
+#include "at32f435_437_conf.h"
+
+/** @addtogroup AT32F435_437_periph_driver
+  * @{
+  */
+
+/** @defgroup ACC
+  * @brief ACC driver modules
+  * @{
+  */
+
+#ifdef ACC_MODULE_ENABLED
+
+/** @defgroup ACC_private_functions
+  * @{
+  */
+
+/**
+  * @brief  enable or disable the acc calibration mode.
+  * @param  acc_trim: specifies the acc calibration type.
+  *         this parameter can be one of the following values:
+  *         - ACC_CAL_HICKCAL
+  *         - ACC_CAL_HICKTRIM
+  * @param  new_state: specifies the acc calibration to be enabled or disabled.(TRUE or FALSE)
+  * @retval none
+  */
+void acc_calibration_mode_enable(uint16_t acc_trim, confirm_state new_state)
+{
+  if(acc_trim == ACC_CAL_HICKCAL)
+  {
+    ACC->ctrl1_bit.entrim = FALSE;
+  }
+  else
+  {
+    ACC->ctrl1_bit.entrim = TRUE;
+  }
+  ACC->ctrl1_bit.calon = new_state;
+}
+
+/**
+  * @brief  store calibration step data in acc's ctrl1 register.
+  * @param  step_value:  value to be stored in the acc's ctrl1 register
+  * @retval none
+  */
+void acc_step_set(uint8_t step_value)
+{
+  ACC->ctrl1_bit.step = step_value;
+}
+
+/**
+  * @brief  select sof sourse for acc in acc's ctrl1 register.
+  * @param  sof_sel:  value to be stored in the acc's ctrl1 register
+  *         this parameter can be one of the following values:
+  *         @arg ACC_SOF_OTG1
+  *         @arg ACC_SOF_OTG2
+  * @retval none
+  */
+void acc_sof_select(uint16_t sof_sel)
+{
+  ACC->ctrl1 |= sof_sel;
+}
+
+/**
+  * @brief  enable or disable the specified acc interrupts.
+  * @param  acc_int: specifies the acc interrupt sources to be enabled or disabled.
+  *         this parameter can be one of the following values:
+  *         - ACC_CALRDYIEN_INT
+  *         - ACC_EIEN_INT
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void acc_interrupt_enable(uint16_t acc_int, confirm_state new_state)
+{
+  if(acc_int == ACC_CALRDYIEN_INT)
+  {
+    ACC->ctrl1_bit.calrdyien = new_state;
+  }
+  else
+  {
+    ACC->ctrl1_bit.eien = new_state;
+  }
+}
+
+/**
+  * @brief  return the current acc hicktrim value.
+  * @param  none
+  * @retval 8-bit hicktrim value.
+  */
+uint8_t acc_hicktrim_get(void)
+{
+  return ((uint8_t)(ACC->ctrl2_bit.hicktrim));
+}
+
+/**
+  * @brief  return the current acc hickcal value.
+  * @param  none
+  * @retval 8-bit hicktrim value.
+  */
+uint8_t acc_hickcal_get(void)
+{
+  return ((uint8_t)(ACC->ctrl2_bit.hickcal));
+}
+
+/**
+  * @brief  wtire the value to  acc c1 register.
+  * @param  acc_c1_value
+  * @retval none.
+  */
+void acc_write_c1(uint16_t acc_c1_value)
+{
+  ACC->c1 = acc_c1_value;
+}
+
+/**
+  * @brief  wtire the value to  acc c2 register.
+  * @param  acc_c2_value
+  * @retval none.
+  */
+void acc_write_c2(uint16_t acc_c2_value)
+{
+  ACC->c2 = acc_c2_value;
+}
+
+/**
+  * @brief  wtire the value to  acc c3 register.
+  * @param  acc_c3_value
+  * @retval none.
+  */
+void acc_write_c3(uint16_t acc_c3_value)
+{
+  ACC->c3 = acc_c3_value;
+}
+
+/**
+  * @brief  return the current acc c1 value.
+  * @param  none
+  * @retval 16-bit c1 value.
+  */
+uint16_t acc_read_c1(void)
+{
+  return ((uint16_t)(ACC->c1));
+}
+
+/**
+  * @brief  return the current acc c2 value.
+  * @param  none
+  * @retval 16-bit c2 value.
+  */
+uint16_t acc_read_c2(void)
+{
+  return ((uint16_t)(ACC->c2));
+}
+
+/**
+  * @brief  return the current acc c3 value.
+  * @param  none
+  * @retval 16-bit c3 value.
+  */
+uint16_t acc_read_c3(void)
+{
+  return ((uint16_t)(ACC->c3));
+}
+
+/**
+  * @brief  check whether the specified acc flag is set or not.
+  * @param  acc_flag: specifies the flag to check.
+  *         this parameter can be one of the following values:
+  *         - ACC_RSLOST_FLAG
+  *         - ACC_CALRDY_FLAG
+  * @retval  flag_status (SET or RESET)
+  */
+flag_status acc_flag_get(uint16_t acc_flag)
+{
+  if(acc_flag == ACC_CALRDY_FLAG)
+    return (flag_status)(ACC->sts_bit.calrdy);
+  else
+    return (flag_status)(ACC->sts_bit.rslost);
+}
+
+/**
+  * @brief  clear the specified acc flag is set or not.
+  * @param  acc_flag: specifies the flag to check.
+  *         this parameter can be any combination of the following values:
+  *         - ACC_RSLOST_FLAG
+  *         - ACC_CALRDY_FLAG
+  * @retval  none
+  */
+void acc_flag_clear(uint16_t acc_flag)
+{
+  ACC->sts = ~acc_flag;
+}
+
+/**
+  * @}
+  */
+
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */

lib/main/AT32F43x/Drivers/AT32F43x_StdPeriph_Driver/src/at32f435_437_crc.c

@@ -0,0 +1,164 @@
+/**
+  **************************************************************************
+  * @file     at32f435_437_crc.c
+  * @version  v2.1.0
+  * @date     2022-08-16
+  * @brief    contains all the functions for the crc firmware library
+  **************************************************************************
+  *                       Copyright notice & Disclaimer
+  *
+  * The software Board Support Package (BSP) that is made available to
+  * download from Artery official website is the copyrighted work of Artery.
+  * Artery authorizes customers to use, copy, and distribute the BSP
+  * software and its related documentation for the purpose of design and
+  * development in conjunction with Artery microcontrollers. Use of the
+  * software is governed by this copyright notice and the following disclaimer.
+  *
+  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+  *
+  **************************************************************************
+  */
+
+#include "at32f435_437_conf.h"
+
+/** @addtogroup AT32F435_437_periph_driver
+  * @{
+  */
+
+/** @defgroup CRC
+  * @brief CRC driver modules
+  * @{
+  */
+
+#ifdef CRC_MODULE_ENABLED
+
+/** @defgroup CRC_private_functions
+  * @{
+  */
+
+/**
+  * @brief  reset the crc data register.
+  * @param  none
+  * @retval none
+  */
+void crc_data_reset(void)
+{
+  /* reset crc generator */
+  CRC->ctrl_bit.rst = 0x1;
+}
+
+/**
+  * @brief  compute the 32-bit crc of a given data word(32-bit).
+  * @param  data: data word(32-bit) to compute its crc
+  * @retval 32-bit crc
+  */
+uint32_t crc_one_word_calculate(uint32_t data)
+{
+  CRC->dt = data;
+  return (CRC->dt);
+}
+
+/**
+  * @brief  compute the 32-bit crc of a given buffer of data word(32-bit).
+  * @param  pbuffer: pointer to the buffer containing the data to be computed
+  * @param  length: length of the buffer to be computed
+  * @retval 32-bit crc
+  */
+uint32_t crc_block_calculate(uint32_t *pbuffer, uint32_t length)
+{
+  uint32_t index = 0;
+
+  for(index = 0; index < length; index++)
+  {
+    CRC->dt = pbuffer[index];
+  }
+
+  return (CRC->dt);
+}
+
+/**
+  * @brief  return the current crc value.
+  * @param  none
+  * @retval 32-bit crc
+  */
+uint32_t crc_data_get(void)
+{
+  return (CRC->dt);
+}
+
+/**
+  * @brief  store a 8-bit data in the common data register.
+  * @param  cdt_value: 8-bit value to be stored in the common data register
+  * @retval none
+  */
+void crc_common_data_set(uint8_t cdt_value)
+{
+  CRC->cdt_bit.cdt = cdt_value;
+}
+
+/**
+  * @brief  return the 8-bit data stored in the common data register
+  * @param  none
+  * @retval 8-bit value of the common data register
+  */
+uint8_t crc_common_data_get(void)
+{
+  return (CRC->cdt_bit.cdt);
+}
+
+/**
+  * @brief  set the 32-bit initial data of crc
+  * @param  value: initial data
+  * @retval none
+  */
+void crc_init_data_set(uint32_t value)
+{
+  CRC->idt = value;
+}
+
+/**
+  * @brief  control the reversal of the bit order in the input data
+  * @param  value
+  *         this parameter can be one of the following values:
+  *         - CRC_REVERSE_INPUT_NO_AFFECTE
+  *         - CRC_REVERSE_INPUT_BY_BYTE
+  *         - CRC_REVERSE_INPUT_BY_HALFWORD
+  *         - CRC_REVERSE_INPUT_BY_WORD
+  * @retval none.
+  */
+void crc_reverse_input_data_set(crc_reverse_input_type value)
+{
+  CRC->ctrl_bit.revid = value;
+}
+
+/**
+  * @brief  control the reversal of the bit order in the output data
+  * @param  value
+  *         this parameter can be one of the following values:
+  *         - CRC_REVERSE_OUTPUT_NO_AFFECTE
+  *         - CRC_REVERSE_OUTPUT_DATA
+  * @retval none.
+  */
+void crc_reverse_output_data_set(crc_reverse_output_type value)
+{
+  CRC->ctrl_bit.revod = value;
+}
+
+/**
+  * @}
+  */
+
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */

lib/main/AT32F43x/Drivers/AT32F43x_StdPeriph_Driver/src/at32f435_437_crm.c

@@ -0,0 +1,986 @@
+/**
+  **************************************************************************
+  * @file     at32f435_437_crm.c
+  * @version  v2.1.0
+  * @date     2022-08-16
+  * @brief    contains all the functions for the crm firmware library
+  **************************************************************************
+  *                       Copyright notice & Disclaimer
+  *
+  * The software Board Support Package (BSP) that is made available to
+  * download from Artery official website is the copyrighted work of Artery.
+  * Artery authorizes customers to use, copy, and distribute the BSP
+  * software and its related documentation for the purpose of design and
+  * development in conjunction with Artery microcontrollers. Use of the
+  * software is governed by this copyright notice and the following disclaimer.
+  *
+  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+  *
+  **************************************************************************
+  */
+
+#include "at32f435_437_conf.h"
+
+/** @addtogroup AT32F435_437_periph_driver
+  * @{
+  */
+
+/** @defgroup CRM
+  * @brief CRM driver modules
+  * @{
+  */
+
+#ifdef CRM_MODULE_ENABLED
+
+/** @defgroup CRM_private_functions
+  * @{
+  */
+
+/**
+  * @brief  reset the crm register
+  * @param  none
+  * @retval none
+  */
+void crm_reset(void)
+{
+  /* reset the crm clock configuration to the default reset state(for debug purpose) */
+  /* set hicken bit */
+  CRM->ctrl_bit.hicken = TRUE;
+
+  /* wait hick stable */
+  while(CRM->ctrl_bit.hickstbl != SET);
+
+  /* hick used as system clock */
+  CRM->cfg_bit.sclksel = CRM_SCLK_HICK;
+
+  /* wait sclk switch status */
+  while(CRM->cfg_bit.sclksts != CRM_SCLK_HICK);
+
+  /* reset hexten, hextbyps, cfden and pllen bits */
+  CRM->ctrl &= ~(0x010D0000U);
+
+  /* reset cfg register, include sclk switch, ahbdiv, apb1div, apb2div, adcdiv, clkout bits */
+  CRM->cfg = 0;
+
+  /* reset pllms pllns pllfr pllrcs bits */
+  CRM->pllcfg = 0x00033002U;
+
+  /* reset clkout[3], usbbufs, hickdiv, clkoutdiv */
+  CRM->misc1 = 0;
+
+  /* disable all interrupts enable and clear pending bits  */
+  CRM->clkint = 0x009F0000U;
+}
+
+/**
+  * @brief  enable or disable crm low speed external crystal bypass
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void crm_lext_bypass(confirm_state new_state)
+{
+  CRM->bpdc_bit.lextbyps = new_state;
+}
+
+/**
+  * @brief  enable or disable crm high speed external crystal bypass
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void crm_hext_bypass(confirm_state new_state)
+{
+  CRM->ctrl_bit.hextbyps = new_state;
+}
+
+/**
+  * @brief  get crm flag status
+  * @param  flag
+  *         this parameter can be one of the following values:
+  *         - CRM_HICK_STABLE_FLAG
+  *         - CRM_HEXT_STABLE_FLAG
+  *         - CRM_PLL_STABLE_FLAG
+  *         - CRM_LEXT_STABLE_FLAG
+  *         - CRM_LICK_STABLE_FLAG
+  *         - CRM_PIN_RESET_FLAG
+  *         - CRM_POR_RESET_FLAG
+  *         - CRM_SW_RESET_FLAG
+  *         - CRM_WDT_RESET_FLAG
+  *         - CRM_WWDT_RESET_FLAG
+  *         - CRM_LOWPOWER_RESET_FLAG
+  *         interrupt flag:
+  *         - CRM_LICK_READY_INT_FLAG
+  *         - CRM_LEXT_READY_INT_FLAG
+  *         - CRM_HICK_READY_INT_FLAG
+  *         - CRM_HEXT_READY_INT_FLAG
+  *         - CRM_PLL_READY_INT_FLAG
+  *         - CRM_CLOCK_FAILURE_INT_FLAG
+  * @retval flag_status (SET or RESET)
+  */
+flag_status crm_flag_get(uint32_t flag)
+{
+  flag_status status = RESET;
+  if((CRM_REG(flag) & CRM_REG_BIT(flag)) != CRM_REG_BIT(flag))
+  {
+    status = RESET;
+  }
+  else
+  {
+    status = SET;
+  }
+  return status;
+}
+
+/**
+  * @brief  wait for hext stable
+  * @param  none
+  * @retval error_status (ERROR or SUCCESS)
+  */
+error_status crm_hext_stable_wait(void)
+{
+  uint32_t stable_cnt = 0;
+  error_status status = ERROR;
+
+  while((crm_flag_get(CRM_HEXT_STABLE_FLAG) != SET) && (stable_cnt < HEXT_STARTUP_TIMEOUT))
+  {
+    stable_cnt ++;
+  }
+
+  if(crm_flag_get(CRM_HEXT_STABLE_FLAG) != SET)
+  {
+    status = ERROR;
+  }
+  else
+  {
+    status = SUCCESS;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  set the hick trimming value
+  * @param  trim_value (0x00~0x3F)
+  * @retval none
+  */
+void crm_hick_clock_trimming_set(uint8_t trim_value)
+{
+  CRM->ctrl_bit.hicktrim = trim_value;
+}
+
+/**
+  * @brief  set the crm calibration value
+  * @param  cali_value (0x00~0xFF)
+  * @retval none
+  */
+void crm_hick_clock_calibration_set(uint8_t cali_value)
+{
+  /* enable write hick calibration */
+  CRM->misc1_bit.hickcal_key = 0x5A;
+
+  /* write hick calibration value */
+  CRM->ctrl_bit.hickcal = cali_value;
+
+  /* disable write hick calibration */
+  CRM->misc1_bit.hickcal_key = 0x0;
+}
+
+/**
+  * @brief  enable or disable the peripheral clock
+  * @param  value
+  *         this parameter can be one of the following values:
+  *         - CRM_GPIOA_PERIPH_CLOCK        - CRM_GPIOB_PERIPH_CLOCK        - CRM_GPIOC_PERIPH_CLOCK       - CRM_GPIOD_PERIPH_CLOCK
+  *         - CRM_GPIOE_PERIPH_CLOCK        - CRM_GPIOF_PERIPH_CLOCK        - CRM_GPIOG_PERIPH_CLOCK       - CRM_GPIOH_PERIPH_CLOCK
+  *         - CRM_CRC_PERIPH_CLOCK          - CRM_EDMA_PERIPH_CLOCK         - CRM_DMA1_PERIPH_CLOCK        - CRM_DMA2_PERIPH_CLOCK
+  *         - CRM_EMAC_PERIPH_CLOCK         - CRM_EMACTX_PERIPH_CLOCK       - CRM_EMACRX_PERIPH_CLOCK      - CRM_EMACPTP_PERIPH_CLOCK
+  *         - CRM_OTGFS2_PERIPH_CLOCK       - CRM_DVP_PERIPH_CLOCK          - CRM_OTGFS1_PERIPH_CLOCK      - CRM_SDIO1_PERIPH_CLOCK
+  *         - CRM_XMC_PERIPH_CLOCK          - CRM_QSPI1_PERIPH_CLOCK        - CRM_QSPI2_PERIPH_CLOCK       - CRM_SDIO2_PERIPH_CLOCK
+  *         - CRM_TMR2_PERIPH_CLOCK         - CRM_TMR3_PERIPH_CLOCK         - CRM_TMR4_PERIPH_CLOCK        - CRM_TMR5_PERIPH_CLOCK
+  *         - CRM_TMR6_PERIPH_CLOCK         - CRM_TMR7_PERIPH_CLOCK         - CRM_TMR12_PERIPH_CLOCK       - CRM_TMR13_PERIPH_CLOCK
+  *         - CRM_TMR14_PERIPH_CLOCK        - CRM_WWDT_PERIPH_CLOCK         - CRM_SPI2_PERIPH_CLOCK        - CRM_SPI3_PERIPH_CLOCK
+  *         - CRM_USART2_PERIPH_CLOCK       - CRM_USART3_PERIPH_CLOCK       - CRM_UART4_PERIPH_CLOCK       - CRM_UART5_PERIPH_CLOCK
+  *         - CRM_I2C1_PERIPH_CLOCK         - CRM_I2C2_PERIPH_CLOCK         - CRM_I2C3_PERIPH_CLOCK        - CRM_CAN1_PERIPH_CLOCK
+  *         - CRM_CAN2_PERIPH_CLOCK         - CRM_PWC_PERIPH_CLOCK          - CRM_DAC_PERIPH_CLOCK         - CRM_UART7_PERIPH_CLOCK
+  *         - CRM_UART8_PERIPH_CLOCK        - CRM_TMR1_PERIPH_CLOCK         - CRM_TMR8_PERIPH_CLOCK        - CRM_USART1_PERIPH_CLOCK
+  *         - CRM_USART6_PERIPH_CLOCK       - CRM_ADC1_PERIPH_CLOCK         - CRM_ADC2_PERIPH_CLOCK        - CRM_ADC3_PERIPH_CLOCK
+  *         - CRM_SPI1_PERIPH_CLOCK         - CRM_SPI4_PERIPH_CLOCK         - CRM_SCFG_PERIPH_CLOCK        - CRM_TMR9_PERIPH_CLOCK
+  *         - CRM_TMR10_PERIPH_CLOCK        - CRM_TMR11_PERIPH_CLOCK        - CRM_TMR20_PERIPH_CLOCK       - CRM_ACC_PERIPH_CLOCK
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void crm_periph_clock_enable(crm_periph_clock_type value, confirm_state new_state)
+{
+  /* enable periph clock */
+  if(TRUE == new_state)
+  {
+    CRM_REG(value) |= CRM_REG_BIT(value);
+  }
+  /* disable periph clock */
+  else
+  {
+    CRM_REG(value) &= ~(CRM_REG_BIT(value));
+  }
+}
+
+/**
+  * @brief  enable or disable the peripheral reset
+  * @param  value
+  *         this parameter can be one of the following values:
+  *         - CRM_GPIOA_PERIPH_RESET        - CRM_GPIOB_PERIPH_RESET        - CRM_GPIOC_PERIPH_RESET       - CRM_GPIOD_PERIPH_RESET
+  *         - CRM_GPIOE_PERIPH_RESET        - CRM_GPIOF_PERIPH_RESET        - CRM_GPIOG_PERIPH_RESET       - CRM_GPIOH_PERIPH_RESET
+  *         - CRM_CRC_PERIPH_RESET          - CRM_EDMA_PERIPH_RESET         - CRM_DMA1_PERIPH_RESET        - CRM_DMA2_PERIPH_RESET
+  *         - CRM_EMAC_PERIPH_RESET         - CRM_OTGFS2_PERIPH_RESET       - CRM_DVP_PERIPH_RESET         - CRM_OTGFS1_PERIPH_RESET
+  *         - CRM_SDIO1_PERIPH_RESET        - CRM_XMC_PERIPH_RESET          - CRM_QSPI1_PERIPH_RESET       - CRM_QSPI2_PERIPH_RESET
+  *         - CRM_SDIO2_PERIPH_RESET        - CRM_TMR2_PERIPH_RESET         - CRM_TMR3_PERIPH_RESET        - CRM_TMR4_PERIPH_RESET
+  *         - CRM_TMR5_PERIPH_RESET         - CRM_TMR6_PERIPH_RESET         - CRM_TMR7_PERIPH_RESET        - CRM_TMR12_PERIPH_RESET
+  *         - CRM_TMR13_PERIPH_RESET        - CRM_TMR14_PERIPH_RESET        - CRM_WWDT_PERIPH_RESET        - CRM_SPI2_PERIPH_RESET
+  *         - CRM_SPI3_PERIPH_RESET         - CRM_USART2_PERIPH_RESET       - CRM_USART3_PERIPH_RESET      - CRM_UART4_PERIPH_RESET
+  *         - CRM_UART5_PERIPH_RESET        - CRM_I2C1_PERIPH_RESET         - CRM_I2C2_PERIPH_RESET        - CRM_I2C3_PERIPH_RESET
+  *         - CRM_CAN1_PERIPH_RESET         - CRM_CAN2_PERIPH_RESET         - CRM_PWC_PERIPH_RESET         - CRM_DAC_PERIPH_RESET
+  *         - CRM_UART7_PERIPH_RESET        - CRM_UART8_PERIPH_RESET        - CRM_TMR1_PERIPH_RESET        - CRM_TMR8_PERIPH_RESET
+  *         - CRM_USART1_PERIPH_RESET       - CRM_USART6_PERIPH_RESET       - CRM_ADC_PERIPH_RESET         - CRM_SPI1_PERIPH_RESET
+  *         - CRM_SPI4_PERIPH_RESET         - CRM_SCFG_PERIPH_RESET         - CRM_TMR9_PERIPH_RESET        - CRM_TMR10_PERIPH_RESET
+  *         - CRM_TMR11_PERIPH_RESET        - CRM_TMR20_PERIPH_RESET        - CRM_ACC_PERIPH_RESET
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void crm_periph_reset(crm_periph_reset_type value, confirm_state new_state)
+{
+  /* enable periph reset */
+  if(new_state == TRUE)
+  {
+    CRM_REG(value) |= (CRM_REG_BIT(value));
+  }
+  /* disable periph reset */
+  else
+  {
+    CRM_REG(value) &= ~(CRM_REG_BIT(value));
+  }
+}
+
+/**
+  * @brief  enable or disable the peripheral clock in lowpower mode
+  * @param  value
+  *         this parameter can be one of the following values:
+  *         - CRM_GPIOA_PERIPH_LOWPOWER     - CRM_GPIOB_PERIPH_LOWPOWER     - CRM_GPIOC_PERIPH_LOWPOWER    - CRM_GPIOD_PERIPH_LOWPOWER
+  *         - CRM_GPIOE_PERIPH_LOWPOWER     - CRM_GPIOF_PERIPH_LOWPOWER     - CRM_GPIOG_PERIPH_LOWPOWER    - CRM_GPIOH_PERIPH_LOWPOWER
+  *         - CRM_CRC_PERIPH_LOWPOWER       - CRM_EDMA_PERIPH_LOWPOWER      - CRM_DMA1_PERIPH_LOWPOWER     - CRM_DMA2_PERIPH_LOWPOWER
+  *         - CRM_EMAC_PERIPH_LOWPOWER      - CRM_EMACTX_PERIPH_LOWPOWER    - CRM_EMACRX_PERIPH_LOWPOWER   - CRM_EMACPTP_PERIPH_LOWPOWER
+  *         - CRM_OTGFS2_PERIPH_LOWPOWER    - CRM_DVP_PERIPH_LOWPOWER       - CRM_OTGFS1_PERIPH_LOWPOWER   - CRM_SDIO1_PERIPH_LOWPOWER
+  *         - CRM_XMC_PERIPH_LOWPOWER       - CRM_QSPI1_PERIPH_LOWPOWER     - CRM_QSPI2_PERIPH_LOWPOWER    - CRM_SDIO2_PERIPH_LOWPOWER
+  *         - CRM_TMR2_PERIPH_LOWPOWER      - CRM_TMR3_PERIPH_LOWPOWER      - CRM_TMR4_PERIPH_LOWPOWER     - CRM_TMR5_PERIPH_LOWPOWER
+  *         - CRM_TMR6_PERIPH_LOWPOWER      - CRM_TMR7_PERIPH_LOWPOWER      - CRM_TMR12_PERIPH_LOWPOWER    - CRM_TMR13_PERIPH_LOWPOWER
+  *         - CRM_TMR14_PERIPH_LOWPOWER     - CRM_WWDT_PERIPH_LOWPOWER      - CRM_SPI2_PERIPH_LOWPOWER     - CRM_SPI3_PERIPH_LOWPOWER
+  *         - CRM_USART2_PERIPH_LOWPOWER    - CRM_USART3_PERIPH_LOWPOWER    - CRM_UART4_PERIPH_LOWPOWER    - CRM_UART5_PERIPH_LOWPOWER
+  *         - CRM_I2C1_PERIPH_LOWPOWER      - CRM_I2C2_PERIPH_LOWPOWER      - CRM_I2C3_PERIPH_LOWPOWER     - CRM_CAN1_PERIPH_LOWPOWER
+  *         - CRM_CAN2_PERIPH_LOWPOWER      - CRM_PWC_PERIPH_LOWPOWER       - CRM_DAC_PERIPH_LOWPOWER      - CRM_UART7_PERIPH_LOWPOWER
+  *         - CRM_UART8_PERIPH_LOWPOWER     - CRM_TMR1_PERIPH_LOWPOWER      - CRM_TMR8_PERIPH_LOWPOWER     - CRM_USART1_PERIPH_LOWPOWER
+  *         - CRM_USART6_PERIPH_LOWPOWER    - CRM_ADC1_PERIPH_LOWPOWER      - CRM_ADC2_PERIPH_LOWPOWER     - CRM_ADC3_PERIPH_LOWPOWER
+  *         - CRM_SPI1_PERIPH_LOWPOWER      - CRM_SPI4_PERIPH_LOWPOWER      - CRM_SCFG_PERIPH_LOWPOWER     - CRM_TMR9_PERIPH_LOWPOWER
+  *         - CRM_TMR10_PERIPH_LOWPOWER     - CRM_TMR11_PERIPH_LOWPOWER     - CRM_TMR20_PERIPH_LOWPOWER    - CRM_ACC_PERIPH_LOWPOWER
+  *         - CRM_FLASH_PERIPH_LOWPOWER     - CRM_SRAM1_PERIPH_LOWPOWER     - CRM_SRAM2_PERIPH_LOWPOWER
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void crm_periph_lowpower_mode_enable(crm_periph_clock_lowpower_type value, confirm_state new_state)
+{
+  /* enable periph clock in lowpower mode */
+  if(new_state == TRUE)
+  {
+    CRM_REG(value) |= (CRM_REG_BIT(value));
+  }
+  /* disable periph clock in lowpower mode */
+  else
+  {
+    CRM_REG(value) &= ~(CRM_REG_BIT(value));
+  }
+}
+
+/**
+  * @brief  enable or disable the crm clock source
+  * @param  source
+  *         this parameter can be one of the following values:
+  *         - CRM_CLOCK_SOURCE_HICK
+  *         - CRM_CLOCK_SOURCE_HEXT
+  *         - CRM_CLOCK_SOURCE_PLL
+  *         - CRM_CLOCK_SOURCE_LEXT
+  *         - CRM_CLOCK_SOURCE_LICK
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void crm_clock_source_enable(crm_clock_source_type source, confirm_state new_state)
+{
+  switch(source)
+  {
+    case CRM_CLOCK_SOURCE_HICK:
+      CRM->ctrl_bit.hicken = new_state;
+      break;
+    case CRM_CLOCK_SOURCE_HEXT:
+      CRM->ctrl_bit.hexten = new_state;
+      break;
+    case CRM_CLOCK_SOURCE_PLL:
+      CRM->ctrl_bit.pllen = new_state;
+      break;
+    case CRM_CLOCK_SOURCE_LEXT:
+      CRM->bpdc_bit.lexten = new_state;
+      break;
+    case CRM_CLOCK_SOURCE_LICK:
+      CRM->ctrlsts_bit.licken = new_state;
+      break;
+    default: break;
+  }
+}
+
+/**
+  * @brief  clear the crm reset flags
+  * @param  flag
+  *         this parameter can be one of the following values:
+  *         reset flag:
+  *         - CRM_PIN_RESET_FLAG
+  *         - CRM_POR_RESET_FLAG
+  *         - CRM_SW_RESET_FLAG
+  *         - CRM_WDT_RESET_FLAG
+  *         - CRM_WWDT_RESET_FLAG
+  *         - CRM_LOWPOWER_RESET_FLAG
+  *         - CRM_ALL_RESET_FLAG
+  *         interrupt flag:
+  *         - CRM_LICK_READY_INT_FLAG
+  *         - CRM_LEXT_READY_INT_FLAG
+  *         - CRM_HICK_READY_INT_FLAG
+  *         - CRM_HEXT_READY_INT_FLAG
+  *         - CRM_PLL_READY_INT_FLAG
+  *         - CRM_CLOCK_FAILURE_INT_FLAG
+  * @retval none
+  */
+void crm_flag_clear(uint32_t flag)
+{
+  switch(flag)
+  {
+    case CRM_NRST_RESET_FLAG:
+    case CRM_POR_RESET_FLAG:
+    case CRM_SW_RESET_FLAG:
+    case CRM_WDT_RESET_FLAG:
+    case CRM_WWDT_RESET_FLAG:
+    case CRM_LOWPOWER_RESET_FLAG:
+    case CRM_ALL_RESET_FLAG:
+      CRM->ctrlsts_bit.rstfc = TRUE;
+      while(CRM->ctrlsts_bit.rstfc == TRUE);
+      break;
+    case CRM_LICK_READY_INT_FLAG:
+      CRM->clkint_bit.lickstblfc = TRUE;
+      break;
+    case CRM_LEXT_READY_INT_FLAG:
+      CRM->clkint_bit.lextstblfc = TRUE;
+      break;
+    case CRM_HICK_READY_INT_FLAG:
+      CRM->clkint_bit.hickstblfc = TRUE;
+      break;
+    case CRM_HEXT_READY_INT_FLAG:
+      CRM->clkint_bit.hextstblfc = TRUE;
+      break;
+    case CRM_PLL_READY_INT_FLAG:
+      CRM->clkint_bit.pllstblfc = TRUE;
+      break;
+    case CRM_CLOCK_FAILURE_INT_FLAG:
+      CRM->clkint_bit.cfdfc = TRUE;
+      break;
+    default:
+      break;
+  }
+}
+
+/**
+  * @brief  select ertc clock
+  * @param  value
+  *         this parameter can be one of the following values:
+  *         - CRM_ERTC_CLOCK_NOCLK
+  *         - CRM_ERTC_CLOCK_LEXT
+  *         - CRM_ERTC_CLOCK_LICK
+  *         - CRM_ERTC_CLOCK_HEXT_DIV_2
+  *         - CRM_ERTC_CLOCK_HEXT_DIV_3
+  *         - CRM_ERTC_CLOCK_HEXT_DIV_4
+  *         - CRM_ERTC_CLOCK_HEXT_DIV_5
+  *         - CRM_ERTC_CLOCK_HEXT_DIV_6
+  *         - CRM_ERTC_CLOCK_HEXT_DIV_7
+  *         - CRM_ERTC_CLOCK_HEXT_DIV_8
+  *         - CRM_ERTC_CLOCK_HEXT_DIV_9
+  *         - CRM_ERTC_CLOCK_HEXT_DIV_10
+  *         - CRM_ERTC_CLOCK_HEXT_DIV_11
+  *         - CRM_ERTC_CLOCK_HEXT_DIV_12
+  *         - CRM_ERTC_CLOCK_HEXT_DIV_13
+  *         - CRM_ERTC_CLOCK_HEXT_DIV_14
+  *         - CRM_ERTC_CLOCK_HEXT_DIV_15
+  *         - CRM_ERTC_CLOCK_HEXT_DIV_16
+  *         - CRM_ERTC_CLOCK_HEXT_DIV_17
+  *         - CRM_ERTC_CLOCK_HEXT_DIV_18
+  *         - CRM_ERTC_CLOCK_HEXT_DIV_19
+  *         - CRM_ERTC_CLOCK_HEXT_DIV_20
+  *         - CRM_ERTC_CLOCK_HEXT_DIV_21
+  *         - CRM_ERTC_CLOCK_HEXT_DIV_22
+  *         - CRM_ERTC_CLOCK_HEXT_DIV_23
+  *         - CRM_ERTC_CLOCK_HEXT_DIV_24
+  *         - CRM_ERTC_CLOCK_HEXT_DIV_25
+  *         - CRM_ERTC_CLOCK_HEXT_DIV_26
+  *         - CRM_ERTC_CLOCK_HEXT_DIV_27
+  *         - CRM_ERTC_CLOCK_HEXT_DIV_28
+  *         - CRM_ERTC_CLOCK_HEXT_DIV_29
+  *         - CRM_ERTC_CLOCK_HEXT_DIV_30
+  *         - CRM_ERTC_CLOCK_HEXT_DIV_31
+  * @retval none
+  */
+void crm_ertc_clock_select(crm_ertc_clock_type value)
+{
+  CRM->cfg_bit.ertcdiv = ((value & 0x1F0) >> 4);
+  CRM->bpdc_bit.ertcsel = (value & 0xF);
+}
+
+/**
+  * @brief  enable or disable ertc
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void crm_ertc_clock_enable(confirm_state new_state)
+{
+  CRM->bpdc_bit.ertcen = new_state;
+}
+
+/**
+  * @brief  set crm ahb division
+  * @param  value
+  *         this parameter can be one of the following values:
+  *         - CRM_AHB_DIV_1
+  *         - CRM_AHB_DIV_2
+  *         - CRM_AHB_DIV_4
+  *         - CRM_AHB_DIV_8
+  *         - CRM_AHB_DIV_16
+  *         - CRM_AHB_DIV_64
+  *         - CRM_AHB_DIV_128
+  *         - CRM_AHB_DIV_256
+  *         - CRM_AHB_DIV_512
+  * @retval none
+  */
+void crm_ahb_div_set(crm_ahb_div_type value)
+{
+  CRM->cfg_bit.ahbdiv = value;
+}
+
+/**
+  * @brief  set crm apb1 division
+  * @param  value
+  *         this parameter can be one of the following values:
+  *         - CRM_APB1_DIV_1
+  *         - CRM_APB1_DIV_2
+  *         - CRM_APB1_DIV_4
+  *         - CRM_APB1_DIV_8
+  *         - CRM_APB1_DIV_16
+  * @retval none
+  */
+void crm_apb1_div_set(crm_apb1_div_type value)
+{
+  CRM->cfg_bit.apb1div = value;
+}
+
+/**
+  * @brief  set crm apb2 division
+  * @param  value
+  *         this parameter can be one of the following values:
+  *         - CRM_APB2_DIV_1
+  *         - CRM_APB2_DIV_2
+  *         - CRM_APB2_DIV_4
+  *         - CRM_APB2_DIV_8
+  *         - CRM_APB2_DIV_16
+  * @retval none
+  */
+void crm_apb2_div_set(crm_apb2_div_type value)
+{
+  CRM->cfg_bit.apb2div = value;
+}
+
+/**
+  * @brief  set usb division
+  * @param  value
+  *         this parameter can be one of the following values:
+  *         - CRM_USB_DIV_1_5
+  *         - CRM_USB_DIV_1
+  *         - CRM_USB_DIV_2_5
+  *         - CRM_USB_DIV_2
+  *         - CRM_USB_DIV_3_5
+  *         - CRM_USB_DIV_3
+  *         - CRM_USB_DIV_4_5
+  *         - CRM_USB_DIV_4
+  *         - CRM_USB_DIV_5_5
+  *         - CRM_USB_DIV_5
+  *         - CRM_USB_DIV_6_5
+  *         - CRM_USB_DIV_6
+  *         - CRM_USB_DIV_7
+  * @retval none
+  */
+void crm_usb_clock_div_set(crm_usb_div_type value)
+{
+    CRM->misc2_bit.usbdiv = value;
+}
+
+/**
+  * @brief  enable or disable clock failure detection
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void crm_clock_failure_detection_enable(confirm_state new_state)
+{
+  CRM->ctrl_bit.cfden = new_state;
+}
+
+/**
+  * @brief  battery powered domain software reset
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void crm_battery_powered_domain_reset(confirm_state new_state)
+{
+  CRM->bpdc_bit.bpdrst = new_state;
+}
+
+/**
+  * @brief  auto step clock switch enable
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void crm_auto_step_mode_enable(confirm_state new_state)
+{
+  if(new_state == TRUE)
+    CRM->misc2_bit.auto_step_en = CRM_AUTO_STEP_MODE_ENABLE;
+  else
+    CRM->misc2_bit.auto_step_en = CRM_AUTO_STEP_MODE_DISABLE;
+}
+
+/**
+  * @brief  config hick divider select
+  * @param  value
+  *         this parameter can be one of the following values:
+  *         - CRM_HICK48_DIV6
+  *         - CRM_HICK48_NODIV
+  * @retval none
+  */
+void crm_hick_divider_select(crm_hick_div_6_type value)
+{
+  CRM->misc1_bit.hickdiv = value;
+}
+
+/**
+  * @brief  hick as system clock frequency select
+  * @param  value
+  *         this parameter can be one of the following values:
+  *         - CRM_HICK_SCLK_8MHZ
+  *         - CRM_HICK_SCLK_48MHZ
+  * @retval none
+  */
+void crm_hick_sclk_frequency_select(crm_hick_sclk_frequency_type value)
+{
+  crm_hick_divider_select(CRM_HICK48_NODIV);
+  CRM->misc1_bit.hick_to_sclk = value;
+}
+
+/**
+  * @brief  usb 48 mhz clock source select
+  * @param  value
+  *         this parameter can be one of the following values:
+  *         - CRM_USB_CLOCK_SOURCE_PLL
+  *         - CRM_USB_CLOCK_SOURCE_HICK
+  * @retval none
+  */
+void crm_usb_clock_source_select(crm_usb_clock_source_type value)
+{
+  if(value == CRM_USB_CLOCK_SOURCE_HICK)
+  {
+    crm_hick_sclk_frequency_select(CRM_HICK_SCLK_48MHZ);
+  }
+  CRM->misc1_bit.hick_to_usb = value;
+}
+
+/**
+  * @brief  enable or disable clkout direct to tmr10 channel 1
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void crm_clkout_to_tmr10_enable(confirm_state new_state)
+{
+  CRM->misc2_bit.clk_to_tmr = new_state;
+}
+
+/**
+  * @brief  config crm pll
+  *                        pll_rcs_freq * pll_ns
+  *         pll clock = --------------------------------
+  *                           pll_ms * pll_fr_n
+  *         attemtion:
+  *                  31 <= pll_ns <= 500
+  *                  1  <= pll_ms <= 15
+  *
+  *                       pll_rcs_freq
+  *         2mhz <=  ---------------------- <= 16mhz
+  *                          pll_ms
+  *
+  *                       pll_rcs_freq * pll_ns
+  *         500mhz <=  -------------------------------- <= 1000mhz
+  *                               pll_ms
+  * @param  clock_source
+  *         this parameter can be one of the following values:
+  *         - CRM_PLL_SOURCE_HICK
+  *         - CRM_PLL_SOURCE_HEXT
+  * @param  pll_ns (31~500)
+  * @param  pll_ms (1~15)
+  * @param  pll_fr
+  *         this parameter can be one of the following values:
+  *         - CRM_PLL_FR_1
+  *         - CRM_PLL_FR_2
+  *         - CRM_PLL_FR_4
+  *         - CRM_PLL_FR_8
+  *         - CRM_PLL_FR_16
+  *         - CRM_PLL_FR_32
+  * @retval none
+  */
+void crm_pll_config(crm_pll_clock_source_type clock_source, uint16_t pll_ns, \
+                    uint16_t pll_ms, crm_pll_fr_type pll_fr)
+{
+  /* config pll clock source */
+  CRM->pllcfg_bit.pllrcs = clock_source;
+
+  /* config pll multiplication factor */
+  CRM->pllcfg_bit.pllns = pll_ns;
+  CRM->pllcfg_bit.pllms = pll_ms;
+  CRM->pllcfg_bit.pllfr = pll_fr;
+}
+
+/**
+  * @brief  select system clock source
+  * @param  value
+  *         this parameter can be one of the following values:
+  *         - CRM_SCLK_HICK
+  *         - CRM_SCLK_HEXT
+  *         - CRM_SCLK_PLL
+  * @retval none
+  */
+void crm_sysclk_switch(crm_sclk_type value)
+{
+  CRM->cfg_bit.sclksel = value;
+}
+
+/**
+  * @brief  indicate which clock source is used as system clock
+  * @param  none
+  * @retval crm_sclk
+  *         this return can be one of the following values:
+  *         - CRM_SCLK_HICK
+  *         - CRM_SCLK_HEXT
+  *         - CRM_SCLK_PLL
+  */
+crm_sclk_type crm_sysclk_switch_status_get(void)
+{
+  return (crm_sclk_type)CRM->cfg_bit.sclksts;
+}
+
+/**
+  * @brief  get crm clocks freqency
+  * @param  clocks_struct
+  *         - pointer to the crm_clocks_freq_type structure
+  * @retval none
+  */
+void crm_clocks_freq_get(crm_clocks_freq_type *clocks_struct)
+{
+  uint32_t pll_ns = 0, pll_ms = 0, pll_fr = 0, pll_clock_source = 0, pllrcsfreq = 0;
+  uint32_t temp = 0, div_value = 0;
+  crm_sclk_type sclk_source;
+
+  static const uint8_t sclk_ahb_div_table[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+  static const uint8_t ahb_apb1_div_table[8] = {0, 0, 0, 0, 1, 2, 3, 4};
+  static const uint8_t ahb_apb2_div_table[8] = {0, 0, 0, 0, 1, 2, 3, 4};
+  static const uint8_t pll_fr_table[6] = {1, 2, 4, 8, 16, 32};
+
+  /* get sclk source */
+  sclk_source = crm_sysclk_switch_status_get();
+
+  switch(sclk_source)
+  {
+    case CRM_SCLK_HICK:
+      if(((CRM->misc1_bit.hick_to_sclk) != RESET) && ((CRM->misc1_bit.hickdiv) != RESET))
+        clocks_struct->sclk_freq = HICK_VALUE * 6;
+      else
+        clocks_struct->sclk_freq = HICK_VALUE;
+      break;
+    case CRM_SCLK_HEXT:
+      clocks_struct->sclk_freq = HEXT_VALUE;
+      break;
+    case CRM_SCLK_PLL:
+      /* get pll clock source */
+      pll_clock_source = CRM->pllcfg_bit.pllrcs;
+
+      /* get multiplication factor */
+      pll_ns = CRM->pllcfg_bit.pllns;
+      pll_ms = CRM->pllcfg_bit.pllms;
+      pll_fr = pll_fr_table[CRM->pllcfg_bit.pllfr];
+
+      if (pll_clock_source == CRM_PLL_SOURCE_HICK)
+      {
+        /* hick selected as pll clock entry */
+        pllrcsfreq = HICK_VALUE;
+      }
+      else
+      {
+        /* hext selected as pll clock entry */
+        pllrcsfreq = HEXT_VALUE;
+      }
+
+      clocks_struct->sclk_freq = (uint32_t)(((uint64_t)pllrcsfreq * pll_ns) / (pll_ms * pll_fr));
+      break;
+    default:
+      clocks_struct->sclk_freq = HICK_VALUE;
+      break;
+  }
+
+  /* compute sclk, ahbclk, abp1clk and apb2clk frequencies */
+  /* get ahb division */
+  temp = CRM->cfg_bit.ahbdiv;
+  div_value = sclk_ahb_div_table[temp];
+  /* ahbclk frequency */
+  clocks_struct->ahb_freq = clocks_struct->sclk_freq >> div_value;
+
+  /* get apb1 division */
+  temp = CRM->cfg_bit.apb1div;
+  div_value = ahb_apb1_div_table[temp];
+  /* apb1clk frequency */
+  clocks_struct->apb1_freq = clocks_struct->ahb_freq >> div_value;
+
+  /* get apb2 division */
+  temp = CRM->cfg_bit.apb2div;
+  div_value = ahb_apb2_div_table[temp];
+  /* apb2clk frequency */
+  clocks_struct->apb2_freq = clocks_struct->ahb_freq >> div_value;
+}
+
+/**
+  * @brief  set crm clkout1
+  * @param  clkout
+  *         this parameter can be one of the following values:
+  *         - CRM_CLKOUT1_HICK
+  *         - CRM_CLKOUT1_LEXT
+  *         - CRM_CLKOUT1_HEXT
+  *         - CRM_CLKOUT1_PLL
+  * @retval none
+  */
+void crm_clock_out1_set(crm_clkout1_select_type clkout)
+{
+    CRM->cfg_bit.clkout1_sel = clkout;
+}
+
+/**
+  * @brief  set crm clkout2
+  * @param  clkout
+  *         this parameter can be one of the following values:
+  *         - CRM_CLKOUT2_SCLK
+  *         - CRM_CLKOUT2_HEXT
+  *         - CRM_CLKOUT2_PLL
+  *         - CRM_CLKOUT2_USB
+  *         - CRM_CLKOUT2_ADC
+  *         - CRM_CLKOUT2_HICK
+  *         - CRM_CLKOUT2_LICK
+  *         - CRM_CLKOUT2_LEXT
+  * @retval none
+  */
+void crm_clock_out2_set(crm_clkout2_select_type clkout)
+{
+  if(clkout < 0x10)
+  {
+    CRM->cfg_bit.clkout2_sel1 = (clkout & 0x3);
+  }
+  else
+  {
+    CRM->cfg_bit.clkout2_sel1 = 0x1;
+    CRM->misc1_bit.clkout2_sel2 = (clkout & 0xF);
+  }
+}
+
+/**
+  * @brief  set crm clkout1 division1
+  * @param  div1
+  *         this parameter can be one of the following values:
+  *         - CRM_CLKOUT_INDEX_1
+  *         - CRM_CLKOUT_INDEX_2
+  * @param  div1
+  *         this parameter can be one of the following values:
+  *         - CRM_CLKOUT_DIV1_1
+  *         - CRM_CLKOUT_DIV1_2
+  *         - CRM_CLKOUT_DIV1_3
+  *         - CRM_CLKOUT_DIV1_4
+  *         - CRM_CLKOUT_DIV1_5
+  * @param  div2
+  *         this parameter can be one of the following values:
+  *         - CRM_CLKOUT_DIV2_1
+  *         - CRM_CLKOUT_DIV2_2
+  *         - CRM_CLKOUT_DIV2_4
+  *         - CRM_CLKOUT_DIV2_8
+  *         - CRM_CLKOUT_DIV2_16
+  *         - CRM_CLKOUT_DIV2_64
+  *         - CRM_CLKOUT_DIV2_128
+  *         - CRM_CLKOUT_DIV2_256
+  *         - CRM_CLKOUT_DIV2_512
+  * @retval none
+  */
+void crm_clkout_div_set(crm_clkout_index_type index, crm_clkout_div1_type div1, crm_clkout_div2_type div2)
+{
+  if(index == CRM_CLKOUT_INDEX_1)
+  {
+    CRM->cfg_bit.clkout1div1 = div1;
+    CRM->misc1_bit.clkout1div2 = div2;
+  }
+  else
+  {
+    CRM->cfg_bit.clkout2div1 = div1;
+    CRM->misc1_bit.clkout2div2 = div2;
+  }
+}
+
+/**
+  * @brief  set emac output pulse width
+  * @param  width
+  *         this parameter can be one of the following values:
+  *         - CRM_EMAC_PULSE_125MS
+  *         - CRM_EMAC_PULSE_1SCLK
+  * @retval none
+  */
+void crm_emac_output_pulse_set(crm_emac_output_pulse_type width)
+{
+  CRM->misc2_bit.emac_pps_sel = width;
+}
+
+/**
+  * @brief  config crm interrupt
+  * @param  int
+  *         this parameter can be any combination of the following values:
+  *         - CRM_LICK_STABLE_INT
+  *         - CRM_LEXT_STABLE_INT
+  *         - CRM_HICK_STABLE_INT
+  *         - CRM_HEXT_STABLE_INT
+  *         - CRM_PLL_STABLE_INT
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void crm_interrupt_enable(uint32_t crm_int, confirm_state new_state)
+{
+  if(TRUE == new_state)
+    CRM->clkint |= crm_int;
+  else
+    CRM->clkint &= ~crm_int;
+}
+
+/**
+  * @brief  calculate the pll parameters with pll reference clock and target pll output frequency.
+  *                        pll_rcs_freq * pll_ns
+  *         pll clock = --------------------------------
+  *                           pll_ms * pll_fr_n
+  *         attemtion:
+  *                  31 <= pll_ns <= 500
+  *                  1  <= pll_ms <= 15
+  *
+  *                       pll_rcs_freq
+  *         2mhz <=  ---------------------- <= 16mhz
+  *                          pll_ms
+  *
+  *                       pll_rcs_freq * pll_ns
+  *         500mhz <=  -------------------------------- <= 1000mhz
+  *                               pll_ms
+  * @param  pll_rcs
+  *         this parameter can be one of the following values:
+  *         - CRM_PLL_SOURCE_HICK
+  *         - CRM_PLL_SOURCE_HEXT
+  * @param  target_sclk_freq: target pll output frequency, such as 200 mhz (target_sclk_freq: 200000000)
+  * @param  ret_ms: pointer to ms value, return the pll_ms of pll parameters
+  * @param  ret_ns: pointer to ns value, return the pll_ns of pll parameters
+  * @param  ret_fr: pointer to fr value, return the pll_fr of pll parameters
+  * @retval error_status (SUCCESS or ERROR)
+  */
+error_status crm_pll_parameter_calculate(crm_pll_clock_source_type pll_rcs, uint32_t target_sclk_freq, \
+                                         uint16_t *ret_ms, uint16_t *ret_ns, uint16_t *ret_fr)
+{
+  uint32_t pll_rcs_freq = 0, ns = 0, ms = 0, fr = 0;
+  uint32_t ms_min = 0, ms_max = 0, error_min = 0xFFFFFFFF;
+  uint32_t result = 0, absolute_value = 0;
+
+  /* reduce calculate accuracy, target_sclk_freq accuracy with khz */
+  target_sclk_freq = target_sclk_freq / 1000;
+
+  /* get pll reference clock frequency, accuracy with khz */
+  if(pll_rcs == CRM_PLL_SOURCE_HICK)
+    pll_rcs_freq = HICK_VALUE / 1000;
+  else
+    pll_rcs_freq = HEXT_VALUE / 1000;
+
+  /* polling ms range, accuracy with khz */
+  for(ms = 1; ms <= 15; ms ++)
+  {
+    result = pll_rcs_freq / ms;
+    if((result >= 2000U) && (result <= 16000U))
+    {
+      if(ms_min == 0)
+        ms_min = ms;
+
+      ms_max = ms;
+    }
+  }
+
+  /* polling pll parameters */
+  for(ms = ms_min; ms <= ms_max; ms ++)
+  {
+    for(fr = 0; fr <= 5; fr ++)
+    {
+      for(ns = 31; ns <= 500; ns ++)
+      {
+        result = (pll_rcs_freq * ns) / (ms);
+        /* check vco frequency range, accuracy with khz */
+        if((result < 500000U) || (result > 1000000U))
+        {
+          continue;
+        }
+        /* calculate pll output frequency */
+        result = result / (0x1 << fr);
+        /* check frequency */
+        if(target_sclk_freq == result)
+        {
+          *ret_ms = ms;
+          *ret_ns = ns;
+          *ret_fr = fr;
+          /* the pll parameters that is equal to target_sclk_freq */
+          return SUCCESS;
+        }
+        /* calculate error range, accuracy with khz */
+        absolute_value = (result > target_sclk_freq) ? (result - target_sclk_freq) : (target_sclk_freq - result);
+        if(absolute_value < error_min)
+        {
+          error_min = absolute_value;
+          *ret_ms = ms;
+          *ret_ns = ns;
+          *ret_fr = fr;
+        }
+      }
+    }
+  }
+  /* the pll parameters that is the closest approach to target_sclk_freq */
+  return ERROR;
+}
+
+/**
+  * @}
+  */
+
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */

lib/main/AT32F43x/Drivers/AT32F43x_StdPeriph_Driver/src/at32f435_437_dac.c

@@ -0,0 +1,454 @@
+/**
+  **************************************************************************
+  * @file     at32f435_437_dac.c
+  * @version  v2.1.0
+  * @date     2022-08-16
+  * @brief    contains all the functions for the dac firmware library
+  **************************************************************************
+  *                       Copyright notice & Disclaimer
+  *
+  * The software Board Support Package (BSP) that is made available to
+  * download from Artery official website is the copyrighted work of Artery.
+  * Artery authorizes customers to use, copy, and distribute the BSP
+  * software and its related documentation for the purpose of design and
+  * development in conjunction with Artery microcontrollers. Use of the
+  * software is governed by this copyright notice and the following disclaimer.
+  *
+  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+  *
+  **************************************************************************
+  */
+
+#include "at32f435_437_conf.h"
+
+/** @addtogroup AT32F435_437_periph_driver
+  * @{
+  */
+
+/** @defgroup DAC
+  * @brief DAC driver modules
+  * @{
+  */
+
+#ifdef DAC_MODULE_ENABLED
+
+/** @defgroup DAC_private_functions
+  * @{
+  */
+
+/**
+  * @brief  dac reset
+  * @param  none
+  * @retval none
+  */
+void dac_reset(void)
+{
+  crm_periph_reset(CRM_DAC_PERIPH_RESET, TRUE);
+  crm_periph_reset(CRM_DAC_PERIPH_RESET, FALSE);
+}
+
+/**
+  * @brief  enable or disable dac
+  * @param  dac_select
+  *         this parameter can be one of the following values:
+  *         - DAC1_SELECT
+  *         - DAC2_SELECT
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void dac_enable(dac_select_type dac_select, confirm_state new_state)
+{
+  switch(dac_select)
+  {
+    case DAC1_SELECT:
+      DAC->ctrl_bit.d1en = new_state;
+      break;
+    case DAC2_SELECT:
+      DAC->ctrl_bit.d2en = new_state;
+      break;
+    default:
+      break;
+  }
+}
+
+/**
+  * @brief  enable or disable dac output buffer
+  * @param  dac_select
+  *         this parameter can be one of the following values:
+  *         - DAC1_SELECT
+  *         - DAC2_SELECT
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void dac_output_buffer_enable(dac_select_type dac_select, confirm_state new_state)
+{
+  new_state = (confirm_state)!new_state;
+  switch(dac_select)
+  {
+    case DAC1_SELECT:
+      DAC->ctrl_bit.d1obdis = new_state;
+      break;
+    case DAC2_SELECT:
+      DAC->ctrl_bit.d2obdis = new_state;
+      break;
+    default:
+      break;
+  }
+}
+
+/**
+  * @brief  enable or disable dac trigger
+  * @param  dac_select
+  *         this parameter can be one of the following values:
+  *         - DAC1_SELECT
+  *         - DAC2_SELECT
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void dac_trigger_enable(dac_select_type dac_select, confirm_state new_state)
+{
+  switch(dac_select)
+  {
+    case DAC1_SELECT:
+      DAC->ctrl_bit.d1trgen = new_state;
+      break;
+    case DAC2_SELECT:
+      DAC->ctrl_bit.d2trgen = new_state;
+      break;
+    default:
+      break;
+  }
+}
+
+/**
+  * @brief  select dac trigger
+  * @param  dac_select
+  *         this parameter can be one of the following values:
+  *         - DAC1_SELECT
+  *         - DAC2_SELECT
+  * @param  dac_trigger_source
+  *         this parameter can be one of the following values:
+  *         - DAC_TMR6_TRGOUT_EVENT
+  *         - DAC_TMR8_TRGOUT_EVENT
+  *         - DAC_TMR7_TRGOUT_EVENT
+  *         - DAC_TMR5_TRGOUT_EVENT
+  *         - DAC_TMR2_TRGOUT_EVENT
+  *         - DAC_TMR4_TRGOUT_EVENT
+  *         - DAC_EXTERNAL_INTERRUPT_LINE_9
+  *         - DAC_SOFTWARE_TRIGGER
+  * @retval none
+  */
+void dac_trigger_select(dac_select_type dac_select, dac_trigger_type dac_trigger_source)
+{
+  switch(dac_select)
+  {
+    case DAC1_SELECT:
+      DAC->ctrl_bit.d1trgsel = dac_trigger_source;
+      break;
+    case DAC2_SELECT:
+      DAC->ctrl_bit.d2trgsel = dac_trigger_source;
+      break;
+    default:
+      break;
+  }
+}
+
+/**
+  * @brief  generate dac software trigger
+  * @param  dac_select
+  *         this parameter can be one of the following values:
+  *         - DAC1_SELECT
+  *         - DAC2_SELECT
+  * @retval none
+  */
+void dac_software_trigger_generate(dac_select_type dac_select)
+{
+  switch(dac_select)
+  {
+    case DAC1_SELECT:
+      DAC->swtrg_bit.d1swtrg = TRUE;
+      break;
+    case DAC2_SELECT:
+      DAC->swtrg_bit.d2swtrg = TRUE;
+      break;
+    default:
+      break;
+  }
+}
+
+/**
+  * @brief  generate dac dual software trigger synchronously
+  * @param  none
+  * @retval none
+  */
+void dac_dual_software_trigger_generate(void)
+{
+  DAC->swtrg |= 0x03;
+}
+
+/**
+  * @brief  generate dac wave
+  * @param  dac_select
+  *         this parameter can be one of the following values:
+  *         - DAC1_SELECT
+  *         - DAC2_SELECT
+  * @param  dac_wave
+  *         this parameter can be one of the following values:
+  *         - DAC_WAVE_GENERATE_NONE
+  *         - DAC_WAVE_GENERATE_NOISE
+  *         - DAC_WAVE_GENERATE_TRIANGLE
+  * @retval none
+  */
+void dac_wave_generate(dac_select_type dac_select, dac_wave_type dac_wave)
+{
+  switch(dac_select)
+  {
+    case DAC1_SELECT:
+      DAC->ctrl_bit.d1nm = dac_wave;
+      break;
+    case DAC2_SELECT:
+      DAC->ctrl_bit.d2nm = dac_wave;
+      break;
+    default:
+      break;
+  }
+}
+
+/**
+  * @brief  select dac mask amplitude
+  * @param  dac_select
+  *         this parameter can be one of the following values:
+  *         - DAC1_SELECT
+  *         - DAC2_SELECT
+  * @param  dac_mask_amplitude
+  *         this parameter can be one of the following values:
+  *         - DAC_LSFR_BIT0_AMPLITUDE_1
+  *         - DAC_LSFR_BIT10_AMPLITUDE_3
+  *         - DAC_LSFR_BIT20_AMPLITUDE_7
+  *         - DAC_LSFR_BIT30_AMPLITUDE_15
+  *         - DAC_LSFR_BIT40_AMPLITUDE_31
+  *         - DAC_LSFR_BIT50_AMPLITUDE_63
+  *         - DAC_LSFR_BIT60_AMPLITUDE_127
+  *         - DAC_LSFR_BIT70_AMPLITUDE_255
+  *         - DAC_LSFR_BIT80_AMPLITUDE_511
+  *         - DAC_LSFR_BIT90_AMPLITUDE_1023
+  *         - DAC_LSFR_BITA0_AMPLITUDE_2047
+  *         - DAC_LSFR_BITB0_AMPLITUDE_4095
+  * @retval none
+  */
+void dac_mask_amplitude_select(dac_select_type dac_select, dac_mask_amplitude_type dac_mask_amplitude)
+{
+  switch(dac_select)
+  {
+    case DAC1_SELECT:
+      DAC->ctrl_bit.d1nbsel = dac_mask_amplitude;
+      break;
+    case DAC2_SELECT:
+      DAC->ctrl_bit.d2nbsel = dac_mask_amplitude;
+      break;
+    default:
+      break;
+  }
+}
+
+/**
+  * @brief  enable or disable dac dma
+  * @param  dac_select
+  *         this parameter can be one of the following values:
+  *         - DAC1_SELECT
+  *         - DAC2_SELECT
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void dac_dma_enable(dac_select_type dac_select, confirm_state new_state)
+{
+  switch(dac_select)
+  {
+    case DAC1_SELECT:
+      DAC->ctrl_bit.d1dmaen = new_state;
+      break;
+    case DAC2_SELECT:
+      DAC->ctrl_bit.d2dmaen = new_state;
+      break;
+    default:
+      break;
+  }
+}
+
+/**
+  * @brief  get dac data output
+  * @param  dac_select
+  *         this parameter can be one of the following values:
+  *         - DAC1_SELECT
+  *         - DAC2_SELECT
+  * @retval dac channel data output
+  */
+uint16_t dac_data_output_get(dac_select_type dac_select)
+{
+  uint16_t data_output =0;
+  switch(dac_select)
+  {
+    case DAC1_SELECT:
+      data_output = DAC->d1odt_bit.d1odt;
+      break;
+    case DAC2_SELECT:
+      data_output = DAC->d2odt_bit.d2odt;
+      break;
+    default:
+      break;
+  }
+  return data_output;
+}
+
+/**
+  * @brief  set dac1 data
+  * @param  dac1_aligned
+  *         this parameter can be one of the following values:
+  *         DAC1_12BIT_RIGHT
+  *         DAC1_12BIT_LEFT
+  *         DAC1_8BIT_RIGHT
+  * @param  dac1_data :indecate from selected data holding register
+  * @retval none
+  */
+void dac_1_data_set(dac1_aligned_data_type dac1_aligned, uint16_t dac1_data)
+{
+  *(__IO uint32_t *) dac1_aligned = dac1_data;
+}
+
+/**
+  * @brief  set dac2 data
+  * @param  dac2_aligned
+  *         this parameter can be one of the following values:
+  *         DAC2_12BIT_RIGHT
+  *         DAC2_12BIT_LEFT
+  *         DAC2_8BIT_RIGHT
+  * @param  dac2_data :indecate from selected data holding register
+  * @retval none
+  */
+void dac_2_data_set(dac2_aligned_data_type dac2_aligned, uint16_t dac2_data)
+{
+  *(__IO uint32_t *) dac2_aligned = dac2_data;
+}
+
+/**
+  * @brief  set dac dual data
+  * @param  dac_dual
+  *         this parameter can be one of the following values:
+  *         DAC_DUAL_12BIT_RIGHT
+  *         DAC_DUAL_12BIT_LEFT
+  *         DAC_DUAL_8BIT_RIGHT
+  * @param  data1 :dac1 channel indecate from selected data holding register
+  * @param  data2 :dac1 channel indecate from selected data holding register
+  * @retval none
+  */
+void dac_dual_data_set(dac_dual_data_type dac_dual, uint16_t data1, uint16_t data2)
+{
+  switch(dac_dual)
+  {
+    case DAC_DUAL_12BIT_RIGHT:
+      *(__IO uint32_t *) dac_dual = (uint32_t)(data1 | (data2 << 16));
+      break;
+    case DAC_DUAL_12BIT_LEFT:
+      *(__IO uint32_t *) dac_dual = (uint32_t)(data1 | (data2 << 16));
+      break;
+    case DAC_DUAL_8BIT_RIGHT:
+      *(__IO uint32_t *) dac_dual = (uint32_t)(data1 | (data2 << 8));
+      break;
+    default:
+      break;
+  }
+}
+
+/**
+  * @brief  enable/disable dac dma udr interrupt
+  * @param  dac_select
+  *         this parameter can be one of the following values:
+  *         - DAC1_SELECT
+  *         - DAC2_SELECT
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void dac_udr_enable(dac_select_type dac_select, confirm_state new_state)
+{
+  switch(dac_select)
+  {
+    case DAC1_SELECT:
+      DAC->ctrl_bit.d1dmaudrien = new_state;
+      break;
+    case DAC2_SELECT:
+      DAC->ctrl_bit.d2dmaudrien = new_state;
+      break;
+    default:
+      break;
+  }
+}
+
+/**
+  * @brief  get flag of the dac udr flag.
+  * @param  dac_select
+  *         this parameter can be one of the following values:
+  *         - DAC1_SELECT
+  *         - DAC2_SELECT
+  * @retval the new state of dac udr flag status(SET or RESET).
+  */
+flag_status dac_udr_flag_get(dac_select_type dac_select)
+{
+  flag_status status = RESET;
+
+  switch(dac_select)
+  {
+    case DAC1_SELECT:
+      if(DAC->sts_bit.d1dmaudrf != 0)
+        status = SET;
+      break;
+    case DAC2_SELECT:
+      if(DAC->sts_bit.d2dmaudrf != 0)
+        status = SET;
+      break;
+    default:
+      break;
+  }
+  return status;
+}
+
+/**
+  * @brief  clear the dac udr flag.
+  * @param  dac_select
+  *         this parameter can be one of the following values:
+  *         - DAC1_SELECT
+  *         - DAC2_SELECT
+  * @retval none
+  */
+void dac_udr_flag_clear(dac_select_type dac_select)
+{
+  switch(dac_select)
+  {
+    case DAC1_SELECT:
+      DAC->sts = DAC1_D1DMAUDRF;
+      break;
+    case DAC2_SELECT:
+      DAC->sts = DAC2_D2DMAUDRF;
+      break;
+    default:
+      break;
+  }
+}
+
+/**
+  * @}
+  */
+
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */

lib/main/AT32F43x/Drivers/AT32F43x_StdPeriph_Driver/src/at32f435_437_debug.c

@@ -0,0 +1,135 @@
+/**
+  **************************************************************************
+  * @file     at32f435_437_mcudbg.c
+  * @version  v2.1.0
+  * @date     2022-08-16
+  * @brief    contains all the functions for the mcudbg firmware library
+  **************************************************************************
+  *                       Copyright notice & Disclaimer
+  *
+  * The software Board Support Package (BSP) that is made available to
+  * download from Artery official website is the copyrighted work of Artery.
+  * Artery authorizes customers to use, copy, and distribute the BSP
+  * software and its related documentation for the purpose of design and
+  * development in conjunction with Artery microcontrollers. Use of the
+  * software is governed by this copyright notice and the following disclaimer.
+  *
+  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+  *
+  **************************************************************************
+  */
+
+#include "at32f435_437_conf.h"
+
+/** @addtogroup AT32F435_437_periph_driver
+  * @{
+  */
+
+/** @defgroup DEBUG
+  * @brief DEBUG driver modules
+  * @{
+  */
+
+#ifdef DEBUG_MODULE_ENABLED
+
+/** @defgroup DEBUG_private_functions
+  * @{
+  */
+
+/**
+  * @brief  get debug device id
+  * @param  none
+  * @retval the debug device id
+  */
+uint32_t debug_device_id_get(void)
+{
+  return DEBUGMCU->pid;
+}
+/**
+  * @brief  set periph debug mode
+  * @param  periph_debug_mode
+  *         this parameter can be one of the following values:
+  *         - DEBUG_SLEEP
+  *         - DEBUG_DEEPSLEEP
+  *         - DEBUG_STANDBY
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void debug_low_power_mode_set(uint32_t low_power_mode, confirm_state new_state)
+{
+  if(new_state != FALSE)
+  {
+    DEBUGMCU->ctrl |= low_power_mode;
+  }
+  else
+  {
+    DEBUGMCU->ctrl &= ~low_power_mode;
+  }
+}
+/**
+  * @brief  set apb1 periph debug mode
+  * @param  periph_debug_mode
+  *         this parameter can be any combination of the following values:
+  *         - DEBUG_TMR2_PAUSE                      - DEBUG_TMR3_PAUSE
+  *         - DEBUG_TMR4_PAUSE                      - DEBUG_TMR5_PAUSE
+  *         - DEBUG_TMR6_PAUSE                      - DEBUG_TMR7_PAUSE
+  *         - DEBUG_TMR12_PAUSE                     - DEBUG_TMR13_PAUSE
+  *         - DEBUG_TMR14_PAUSE                     - DEBUG_ERTC_PAUSE
+  *         - DEBUG_WWDT_PAUSE                      - DEBUG_WDT_PAUSE
+  *         - DEBUG_ERTC_512_PAUSE                  - DEBUG_I2C1_SMBUS_TIMEOUT
+  *         - DEBUG_I2C2_SMBUS_TIMEOUT              - DEBUG_I2C3_SMBUS_TIMEOUT
+  *         - DEBUG_CAN1_PAUSE                      - DEBUG_CAN2_PAUSE
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void debug_apb1_periph_mode_set(uint32_t apb1_periph, confirm_state new_state)
+{
+  if(new_state != FALSE)
+  {
+    DEBUGMCU->apb1_frz |= apb1_periph;
+  }
+  else
+  {
+    DEBUGMCU->apb1_frz &= ~apb1_periph;
+  }
+}
+/**
+  * @brief  set apb2 periph debug mode
+  * @param  periph_debug_mode
+  *         this parameter can be any combination of the following values:
+  *         - DEBUG_TMR1_PAUSE                      - DEBUG_TMR8_PAUSE
+  *         - DEBUG_TMR20_PAUSE                     - DEBUG_TMR9_PAUSE
+  *         - DEBUG_TMR10_PAUSE                     - DEBUG_TMR11_PAUSE
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void debug_apb2_periph_mode_set(uint32_t apb2_periph, confirm_state new_state)
+{
+  if(new_state != FALSE)
+  {
+    DEBUGMCU->apb2_frz |= apb2_periph;
+  }
+  else
+  {
+    DEBUGMCU->apb2_frz &= ~apb2_periph;
+  }
+}
+
+/**
+  * @}
+  */
+
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */

lib/main/AT32F43x/Drivers/AT32F43x_StdPeriph_Driver/src/at32f435_437_dma.c

@@ -0,0 +1,683 @@
+/**
+  **************************************************************************
+  * @file     at32f435_437_dma.c
+  * @version  v2.1.0
+  * @date     2022-08-16
+  * @brief    contains all the functions for the dma firmware library
+  **************************************************************************
+  *                       Copyright notice & Disclaimer
+  *
+  * The software Board Support Package (BSP) that is made available to
+  * download from Artery official website is the copyrighted work of Artery.
+  * Artery authorizes customers to use, copy, and distribute the BSP
+  * software and its related documentation for the purpose of design and
+  * development in conjunction with Artery microcontrollers. Use of the
+  * software is governed by this copyright notice and the following disclaimer.
+  *
+  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+  *
+  **************************************************************************
+  */
+
+#include "at32f435_437_conf.h"
+
+/** @addtogroup AT32F435_437_periph_driver
+  * @{
+  */
+
+/** @defgroup DMA
+  * @brief DMA driver modules
+  * @{
+  */
+
+#ifdef DMA_MODULE_ENABLED
+
+/** @defgroup DMA_private_functions
+  * @{
+  */
+
+/**
+  * @brief  reset dmax channely register.
+  * @param  dmax_channely:
+  *         this parameter can be one of the following values:
+  *         - DMA1_CHANNEL1
+  *         - DMA1_CHANNEL2
+  *         - DMA1_CHANNEL3
+  *         - DMA1_CHANNEL4
+  *         - DMA1_CHANNEL5
+  *         - DMA1_CHANNEL6
+  *         - DMA1_CHANNEL7
+  *         - DMA2_CHANNEL1
+  *         - DMA2_CHANNEL2
+  *         - DMA2_CHANNEL3
+  *         - DMA2_CHANNEL4
+  *         - DMA2_CHANNEL5
+  *         - DMA2_CHANNEL6
+  *         - DMA2_CHANNEL7
+  * @retval none.
+  */
+void dma_reset(dma_channel_type *dmax_channely)
+{
+  uint32_t temp = 0;
+  dmax_channely->ctrl_bit.chen = FALSE;
+  dmax_channely->ctrl = 0;
+  dmax_channely->dtcnt = 0;
+  dmax_channely->paddr = 0;
+  dmax_channely->maddr = 0;
+
+  temp = (uint32_t)dmax_channely;
+
+  if((temp & 0x6FF) < 0x608)
+  {
+    /* dma1 channel */
+    DMA1->clr |= (uint32_t)(0x0F << ((((temp & 0xFF) - 0x08) / 0x14) * 4));
+  }
+  else if((temp & 0x6FF) < 0x688)
+  {
+    /* dma2 channel */
+    DMA2->clr |= (uint32_t)(0x0F << ((((temp & 0xFF) - 0x08) / 0x14) * 4));
+  }
+}
+
+/**
+  * @brief  set the number of data to be transferred.
+  * @param  dmax_channely:
+  *         this parameter can be one of the following values:
+  *         - DMA1_CHANNEL1
+  *         - DMA1_CHANNEL2
+  *         - DMA1_CHANNEL3
+  *         - DMA1_CHANNEL4
+  *         - DMA1_CHANNEL5
+  *         - DMA1_CHANNEL6
+  *         - DMA1_CHANNEL7
+  *         - DMA2_CHANNEL1
+  *         - DMA2_CHANNEL2
+  *         - DMA2_CHANNEL3
+  *         - DMA2_CHANNEL4
+  *         - DMA2_CHANNEL5
+  *         - DMA2_CHANNEL6
+  *         - DMA2_CHANNEL7
+  * @param  data_number: the number of data to be transferred (0x0000~0xFFFF).
+  * @retval none.
+  */
+void dma_data_number_set(dma_channel_type *dmax_channely, uint16_t data_number)
+{
+  dmax_channely->dtcnt = data_number;
+}
+
+/**
+  * @brief  get the number of data to be transferred.
+  * @param  dmax_channely:
+  *         this parameter can be one of the following values:
+  *         - DMA1_CHANNEL1
+  *         - DMA1_CHANNEL2
+  *         - DMA1_CHANNEL3
+  *         - DMA1_CHANNEL4
+  *         - DMA1_CHANNEL5
+  *         - DMA1_CHANNEL6
+  *         - DMA1_CHANNEL7
+  *         - DMA2_CHANNEL1
+  *         - DMA2_CHANNEL2
+  *         - DMA2_CHANNEL3
+  *         - DMA2_CHANNEL4
+  *         - DMA2_CHANNEL5
+  *         - DMA2_CHANNEL6
+  *         - DMA2_CHANNEL7
+  * @retval the number value.
+  */
+uint16_t dma_data_number_get(dma_channel_type *dmax_channely)
+{
+  return (uint16_t)dmax_channely->dtcnt;
+}
+
+/**
+  * @brief  enable or disable dma interrupt.
+  * @param  dmax_channely:
+  *         this parameter can be one of the following values:
+  *         - DMA1_CHANNEL1
+  *         - DMA1_CHANNEL2
+  *         - DMA1_CHANNEL3
+  *         - DMA1_CHANNEL4
+  *         - DMA1_CHANNEL5
+  *         - DMA1_CHANNEL6
+  *         - DMA1_CHANNEL7
+  *         - DMA2_CHANNEL1
+  *         - DMA2_CHANNEL2
+  *         - DMA2_CHANNEL3
+  *         - DMA2_CHANNEL4
+  *         - DMA2_CHANNEL5
+  *         - DMA2_CHANNEL6
+  *         - DMA2_CHANNEL7
+  * @param  dma_int:
+  *         this parameter can be any combination of the following values:
+  *         - DMA_FDT_INT
+  *         - DMA_HDT_INT
+  *         - DMA_DTERR_INT
+  * @param  new_state (TRUE or FALSE)
+  * @retval none.
+  */
+void dma_interrupt_enable(dma_channel_type *dmax_channely, uint32_t dma_int, confirm_state new_state)
+{
+  if(new_state != FALSE)
+  {
+    dmax_channely->ctrl |= dma_int;
+  }
+  else
+  {
+    dmax_channely->ctrl &= ~dma_int;
+  }
+}
+
+/**
+  * @brief  enable or disable dma channel.
+  * @param  dmax_channely:
+  *         this parameter can be one of the following values:
+  *         - DMA1_CHANNEL1
+  *         - DMA1_CHANNEL2
+  *         - DMA1_CHANNEL3
+  *         - DMA1_CHANNEL4
+  *         - DMA1_CHANNEL5
+  *         - DMA1_CHANNEL6
+  *         - DMA1_CHANNEL7
+  *         - DMA2_CHANNEL1
+  *         - DMA2_CHANNEL2
+  *         - DMA2_CHANNEL3
+  *         - DMA2_CHANNEL4
+  *         - DMA2_CHANNEL5
+  *         - DMA2_CHANNEL6
+  *         - DMA2_CHANNEL7
+  * @param  new_state (TRUE or FALSE).
+  * @retval none.
+  */
+void dma_channel_enable(dma_channel_type *dmax_channely, confirm_state new_state)
+{
+  dmax_channely->ctrl_bit.chen = new_state;
+}
+
+/**
+  * @brief  dma flag get.
+  * @param  dma_flag
+  *         - DMA1_GL1_FLAG        - DMA1_FDT1_FLAG        - DMA1_HDT1_FLAG        - DMA1_DTERR1_FLAG
+  *         - DMA1_GL2_FLAG        - DMA1_FDT2_FLAG        - DMA1_HDT2_FLAG        - DMA1_DTERR2_FLAG
+  *         - DMA1_GL3_FLAG        - DMA1_FDT3_FLAG        - DMA1_HDT3_FLAG        - DMA1_DTERR3_FLAG
+  *         - DMA1_GL4_FLAG        - DMA1_FDT4_FLAG        - DMA1_HDT4_FLAG        - DMA1_DTERR4_FLAG
+  *         - DMA1_GL5_FLAG        - DMA1_FDT5_FLAG        - DMA1_HDT5_FLAG        - DMA1_DTERR5_FLAG
+  *         - DMA1_GL6_FLAG        - DMA1_FDT6_FLAG        - DMA1_HDT6_FLAG        - DMA1_DTERR6_FLAG
+  *         - DMA1_GL7_FLAG        - DMA1_FDT7_FLAG        - DMA1_HDT7_FLAG        - DMA1_DTERR7_FLAG
+  *         - DMA2_GL1_FLAG        - DMA2_FDT1_FLAG        - DMA2_HDT1_FLAG        - DMA2_DTERR1_FLAG
+  *         - DMA2_GL2_FLAG        - DMA2_FDT2_FLAG        - DMA2_HDT2_FLAG        - DMA2_DTERR2_FLAG
+  *         - DMA2_GL3_FLAG        - DMA2_FDT3_FLAG        - DMA2_HDT3_FLAG        - DMA2_DTERR3_FLAG
+  *         - DMA2_GL4_FLAG        - DMA2_FDT4_FLAG        - DMA2_HDT4_FLAG        - DMA2_DTERR4_FLAG
+  *         - DMA2_GL5_FLAG        - DMA2_FDT5_FLAG        - DMA2_HDT5_FLAG        - DMA2_DTERR5_FLAG
+  *         - DMA2_GL6_FLAG        - DMA2_FDT6_FLAG        - DMA2_HDT6_FLAG        - DMA2_DTERR6_FLAG
+  *         - DMA2_GL7_FLAG        - DMA2_FDT7_FLAG        - DMA2_HDT7_FLAG        - DMA2_DTERR7_FLAG
+  * @retval state of dma flag.
+  */
+flag_status dma_flag_get(uint32_t dmax_flag)
+{
+  uint32_t temp = 0;
+
+  if(dmax_flag > 0x10000000)
+  {
+    temp = DMA2->sts;
+  }
+  else
+  {
+    temp = DMA1->sts;
+  }
+
+  if((temp & dmax_flag) != RESET)
+  {
+    return SET;
+  }
+  else
+  {
+    return RESET;
+  }
+}
+
+/**
+  * @brief  dma flag clear.
+  * @param  dma_flag
+  *         this parameter can be one of the following values:
+  *         - DMA1_GL1_FLAG        - DMA1_FDT1_FLAG        - DMA1_HDT1_FLAG        - DMA1_DTERR1_FLAG
+  *         - DMA1_GL2_FLAG        - DMA1_FDT2_FLAG        - DMA1_HDT2_FLAG        - DMA1_DTERR2_FLAG
+  *         - DMA1_GL3_FLAG        - DMA1_FDT3_FLAG        - DMA1_HDT3_FLAG        - DMA1_DTERR3_FLAG
+  *         - DMA1_GL4_FLAG        - DMA1_FDT4_FLAG        - DMA1_HDT4_FLAG        - DMA1_DTERR4_FLAG
+  *         - DMA1_GL5_FLAG        - DMA1_FDT5_FLAG        - DMA1_HDT5_FLAG        - DMA1_DTERR5_FLAG
+  *         - DMA1_GL6_FLAG        - DMA1_FDT6_FLAG        - DMA1_HDT6_FLAG        - DMA1_DTERR6_FLAG
+  *         - DMA1_GL7_FLAG        - DMA1_FDT7_FLAG        - DMA1_HDT7_FLAG        - DMA1_DTERR7_FLAG
+  *         - DMA2_GL1_FLAG        - DMA2_FDT1_FLAG        - DMA2_HDT1_FLAG        - DMA2_DTERR1_FLAG
+  *         - DMA2_GL2_FLAG        - DMA2_FDT2_FLAG        - DMA2_HDT2_FLAG        - DMA2_DTERR2_FLAG
+  *         - DMA2_GL3_FLAG        - DMA2_FDT3_FLAG        - DMA2_HDT3_FLAG        - DMA2_DTERR3_FLAG
+  *         - DMA2_GL4_FLAG        - DMA2_FDT4_FLAG        - DMA2_HDT4_FLAG        - DMA2_DTERR4_FLAG
+  *         - DMA2_GL5_FLAG        - DMA2_FDT5_FLAG        - DMA2_HDT5_FLAG        - DMA2_DTERR5_FLAG
+  *         - DMA2_GL6_FLAG        - DMA2_FDT6_FLAG        - DMA2_HDT6_FLAG        - DMA2_DTERR6_FLAG
+  *         - DMA2_GL7_FLAG        - DMA2_FDT7_FLAG        - DMA2_HDT7_FLAG        - DMA2_DTERR7_FLAG
+  * @retval none.
+  */
+void dma_flag_clear(uint32_t dmax_flag)
+{
+  if(dmax_flag > ((uint32_t)0x10000000))
+  {
+    DMA2->clr = (uint32_t)(dmax_flag & 0x0FFFFFFF);
+  }
+  else
+  {
+    DMA1->clr = dmax_flag;
+  }
+}
+
+/**
+  * @brief  dma init config with its default value.
+  * @param  dma_init_struct: pointer to a dma_init_type structure which will be initialized.
+  * @retval none.
+  */
+void dma_default_para_init(dma_init_type *dma_init_struct)
+{
+  dma_init_struct->peripheral_base_addr = 0;
+  dma_init_struct->memory_base_addr = 0;
+  dma_init_struct->direction = DMA_DIR_PERIPHERAL_TO_MEMORY;
+  dma_init_struct->buffer_size = 0;
+  dma_init_struct->peripheral_inc_enable = FALSE;
+  dma_init_struct->memory_inc_enable = FALSE;
+  dma_init_struct->peripheral_data_width = DMA_PERIPHERAL_DATA_WIDTH_BYTE;
+  dma_init_struct->memory_data_width = DMA_MEMORY_DATA_WIDTH_BYTE;
+  dma_init_struct->loop_mode_enable = FALSE;
+  dma_init_struct->priority = DMA_PRIORITY_LOW;
+}
+
+/**
+  * @brief  dma init.
+  * @param  dmax_channely:
+  *         this parameter can be one of the following values:
+  *         - DMA1_CHANNEL1
+  *         - DMA1_CHANNEL2
+  *         - DMA1_CHANNEL3
+  *         - DMA1_CHANNEL4
+  *         - DMA1_CHANNEL5
+  *         - DMA1_CHANNEL6
+  *         - DMA1_CHANNEL7
+  *         - DMA2_CHANNEL1
+  *         - DMA2_CHANNEL2
+  *         - DMA2_CHANNEL3
+  *         - DMA2_CHANNEL4
+  *         - DMA2_CHANNEL5
+  *         - DMA2_CHANNEL6
+  *         - DMA2_CHANNEL7
+  * @param  dma_init_struct: pointer to a dma_init_type structure.
+  * @retval none.
+  */
+void dma_init(dma_channel_type *dmax_channely, dma_init_type *dma_init_struct)
+{
+  /* clear ctrl register dtd bit and m2m bit */
+  dmax_channely->ctrl &= 0xbfef;
+  dmax_channely->ctrl |= dma_init_struct->direction;
+
+  dmax_channely->ctrl_bit.chpl = dma_init_struct->priority;
+  dmax_channely->ctrl_bit.mwidth = dma_init_struct->memory_data_width;
+  dmax_channely->ctrl_bit.pwidth = dma_init_struct->peripheral_data_width;
+  dmax_channely->ctrl_bit.mincm = dma_init_struct->memory_inc_enable;
+  dmax_channely->ctrl_bit.pincm = dma_init_struct->peripheral_inc_enable;
+  dmax_channely->ctrl_bit.lm = dma_init_struct->loop_mode_enable;
+  dmax_channely->dtcnt_bit.cnt = dma_init_struct->buffer_size;
+  dmax_channely->paddr = dma_init_struct->peripheral_base_addr;
+  dmax_channely->maddr = dma_init_struct->memory_base_addr;
+}
+/**
+  * @brief  dmamux init.
+  * @param  dma_x: pointer to a dma_type structure, can be DMA1 or DMA2.
+  * @param  dmamux_channelx:
+  *         this parameter can be one of the following values:
+  *         - DMA1MUX_CHANNEL1
+  *         - DMA1MUX_CHANNEL2
+  *         - DMA1MUX_CHANNEL3
+  *         - DMA1MUX_CHANNEL4
+  *         - DMA1MUX_CHANNEL5
+  *         - DMA1MUX_CHANNEL6
+  *         - DMA1MUX_CHANNEL7
+  *         - DMA2MUX_CHANNEL1
+  *         - DMA2MUX_CHANNEL2
+  *         - DMA2MUX_CHANNEL3
+  *         - DMA2MUX_CHANNEL4
+  *         - DMA2MUX_CHANNEL5
+  *         - DMA2MUX_CHANNEL6
+  *         - DMA2MUX_CHANNEL7
+  * @param  dmamux_req_sel:
+  *         this parameter can be one of the following values:
+  *         - DMAMUX_DMAREQ_ID_REQ_G1       - DMAMUX_DMAREQ_ID_REQ_G2       - DMAMUX_DMAREQ_ID_REQ_G3       - DMAMUX_DMAREQ_ID_REQ_G4
+  *         - DMAMUX_DMAREQ_ID_ADC1         - DMAMUX_DMAREQ_ID_ADC2         - DMAMUX_DMAREQ_ID_ADC3         - DMAMUX_DMAREQ_ID_DAC1
+  *         - DMAMUX_DMAREQ_ID_DAC2         - DMAMUX_DMAREQ_ID_TMR6_OVERFLOW- DMAMUX_DMAREQ_ID_TMR7_OVERFLOW- DMAMUX_DMAREQ_ID_SPI1_RX
+  *         - DMAMUX_DMAREQ_ID_SPI1_TX      - DMAMUX_DMAREQ_ID_SPI2_RX      - DMAMUX_DMAREQ_ID_SPI2_TX      - DMAMUX_DMAREQ_ID_SPI3_RX
+  *         - DMAMUX_DMAREQ_ID_SPI3_TX      - DMAMUX_DMAREQ_ID_SPI4_RX      - DMAMUX_DMAREQ_ID_SPI4_TX      - DMAMUX_DMAREQ_ID_I2S2_EXT_RX
+  *         - DMAMUX_DMAREQ_ID_I2S2_EXT_TX  - DMAMUX_DMAREQ_ID_I2S3_EXT_RX  - DMAMUX_DMAREQ_ID_I2S3_EXT_TX  - DMAMUX_DMAREQ_ID_I2C1_RX
+  *         - DMAMUX_DMAREQ_ID_I2C1_TX      - DMAMUX_DMAREQ_ID_I2C2_RX      - DMAMUX_DMAREQ_ID_I2C2_TX      - DMAMUX_DMAREQ_ID_I2C3_RX
+  *         - DMAMUX_DMAREQ_ID_I2C3_TX      - DMAMUX_DMAREQ_ID_USART1_RX    - DMAMUX_DMAREQ_ID_USART1_TX    - DMAMUX_DMAREQ_ID_USART2_RX
+  *         - DMAMUX_DMAREQ_ID_USART2_TX    - DMAMUX_DMAREQ_ID_USART3_RX    - DMAMUX_DMAREQ_ID_USART3_TX    - DMAMUX_DMAREQ_ID_UART4_RX
+  *         - DMAMUX_DMAREQ_ID_UART4_TX     - DMAMUX_DMAREQ_ID_UART5_RX     - DMAMUX_DMAREQ_ID_UART5_TX     - DMAMUX_DMAREQ_ID_USART6_RX
+  *         - DMAMUX_DMAREQ_ID_USART6_TX    - DMAMUX_DMAREQ_ID_UART7_RX     - DMAMUX_DMAREQ_ID_UART7_TX     - DMAMUX_DMAREQ_ID_UART8_RX
+  *         - DMAMUX_DMAREQ_ID_UART8_TX     - DMAMUX_DMAREQ_ID_SDIO1        - DMAMUX_DMAREQ_ID_SDIO2        - DMAMUX_DMAREQ_ID_QSPI1
+  *         - DMAMUX_DMAREQ_ID_QSPI2        - DMAMUX_DMAREQ_ID_TMR1_CH1     - DMAMUX_DMAREQ_ID_TMR1_CH2     - DMAMUX_DMAREQ_ID_TMR1_CH3
+  *         - DMAMUX_DMAREQ_ID_TMR1_CH4     - DMAMUX_DMAREQ_ID_TMR1_OVERFLOW- DMAMUX_DMAREQ_ID_TMR1_TRIG    - DMAMUX_DMAREQ_ID_TMR1_COM
+  *         - DMAMUX_DMAREQ_ID_TMR8_CH1     - DMAMUX_DMAREQ_ID_TMR8_CH2     - DMAMUX_DMAREQ_ID_TMR8_CH3     - DMAMUX_DMAREQ_ID_TMR8_CH4
+  *         - DMAMUX_DMAREQ_ID_TMR8_UP      - DMAMUX_DMAREQ_ID_TMR8_TRIG    - DMAMUX_DMAREQ_ID_TMR8_COM     - DMAMUX_DMAREQ_ID_TMR2_CH1
+  *         - DMAMUX_DMAREQ_ID_TMR2_CH2     - DMAMUX_DMAREQ_ID_TMR2_CH3     - DMAMUX_DMAREQ_ID_TMR2_CH4     - DMAMUX_DMAREQ_ID_TMR2_OVERFLOW
+  *         - DMAMUX_DMAREQ_ID_TMR2_TRIG    - DMAMUX_DMAREQ_ID_TMR3_CH1     - DMAMUX_DMAREQ_ID_TMR3_CH2     - DMAMUX_DMAREQ_ID_TMR3_CH3
+  *         - DMAMUX_DMAREQ_ID_TMR3_CH4     - DMAMUX_DMAREQ_ID_TMR3_OVERFLOW- DMAMUX_DMAREQ_ID_TMR3_TRIG    - DMAMUX_DMAREQ_ID_TMR4_CH1
+  *         - DMAMUX_DMAREQ_ID_TMR4_CH2     - DMAMUX_DMAREQ_ID_TMR4_CH3     - DMAMUX_DMAREQ_ID_TMR4_CH4     - DMAMUX_DMAREQ_ID_TMR4_OVERFLOW
+  *         - DMAMUX_DMAREQ_ID_TMR4_TRIG    - DMAMUX_DMAREQ_ID_TMR5_CH1     - DMAMUX_DMAREQ_ID_TMR5_CH2     - DMAMUX_DMAREQ_ID_TMR5_CH3
+  *         - DMAMUX_DMAREQ_ID_TMR5_CH4     - DMAMUX_DMAREQ_ID_TMR5_OVERFLOW- DMAMUX_DMAREQ_ID_TMR5_TRIG    - DMAMUX_DMAREQ_ID_TMR20_CH1
+  *         - DMAMUX_DMAREQ_ID_TMR20_CH2    - DMAMUX_DMAREQ_ID_TMR20_CH3    - DMAMUX_DMAREQ_ID_TMR20_CH4    - DMAMUX_DMAREQ_ID_TMR20_OVERFLOW
+  *         - DMAMUX_DMAREQ_ID_TMR20_TRIG   - DMAMUX_DMAREQ_ID_TMR20_HALL   - DMAMUX_DMAREQ_ID_DVP
+  * @retval none.
+  */
+void dma_flexible_config(dma_type* dma_x, dmamux_channel_type *dmamux_channelx, dmamux_requst_id_sel_type dmamux_req_sel)
+{
+  dma_x->muxsel_bit.tblsel = TRUE;
+  dmamux_channelx->muxctrl_bit.reqsel = dmamux_req_sel;
+}
+
+/**
+  * @brief  enable or disable the dmamux.
+  * @param  dma_x: pointer to a dma_type structure, can be DMA1 or DMA2.
+  * @param  new_state (TRUE or FALSE) .
+  * @retval none.
+  */
+void dmamux_enable(dma_type *dma_x, confirm_state new_state)
+{
+  dma_x->muxsel_bit.tblsel = new_state;
+}
+
+/**
+  * @brief  dmamux init.
+  * @param  dmamux_channelx:
+  *         this parameter can be one of the following values:
+  *         - DMA1MUX_CHANNEL1
+  *         - DMA1MUX_CHANNEL2
+  *         - DMA1MUX_CHANNEL3
+  *         - DMA1MUX_CHANNEL4
+  *         - DMA1MUX_CHANNEL5
+  *         - DMA1MUX_CHANNEL6
+  *         - DMA1MUX_CHANNEL7
+  *         - DMA2MUX_CHANNEL1
+  *         - DMA2MUX_CHANNEL2
+  *         - DMA2MUX_CHANNEL3
+  *         - DMA2MUX_CHANNEL4
+  *         - DMA2MUX_CHANNEL5
+  *         - DMA2MUX_CHANNEL6
+  *         - DMA2MUX_CHANNEL7
+  * @param  dmamux_req_sel:
+  *         this parameter can be one of the following values:
+  *         - DMAMUX_DMAREQ_ID_REQ_G1       - DMAMUX_DMAREQ_ID_REQ_G2       - DMAMUX_DMAREQ_ID_REQ_G3       - DMAMUX_DMAREQ_ID_REQ_G4
+  *         - DMAMUX_DMAREQ_ID_ADC1         - DMAMUX_DMAREQ_ID_ADC2         - DMAMUX_DMAREQ_ID_ADC3         - DMAMUX_DMAREQ_ID_DAC1
+  *         - DMAMUX_DMAREQ_ID_DAC2         - DMAMUX_DMAREQ_ID_TMR6_OVERFLOW- DMAMUX_DMAREQ_ID_TMR7_OVERFLOW- DMAMUX_DMAREQ_ID_SPI1_RX
+  *         - DMAMUX_DMAREQ_ID_SPI1_TX      - DMAMUX_DMAREQ_ID_SPI2_RX      - DMAMUX_DMAREQ_ID_SPI2_TX      - DMAMUX_DMAREQ_ID_SPI3_RX
+  *         - DMAMUX_DMAREQ_ID_SPI3_TX      - DMAMUX_DMAREQ_ID_SPI4_RX      - DMAMUX_DMAREQ_ID_SPI4_TX      - DMAMUX_DMAREQ_ID_I2S2_EXT_RX
+  *         - DMAMUX_DMAREQ_ID_I2S2_EXT_TX  - DMAMUX_DMAREQ_ID_I2S3_EXT_RX  - DMAMUX_DMAREQ_ID_I2S3_EXT_TX  - DMAMUX_DMAREQ_ID_I2C1_RX
+  *         - DMAMUX_DMAREQ_ID_I2C1_TX      - DMAMUX_DMAREQ_ID_I2C2_RX      - DMAMUX_DMAREQ_ID_I2C2_TX      - DMAMUX_DMAREQ_ID_I2C3_RX
+  *         - DMAMUX_DMAREQ_ID_I2C3_TX      - DMAMUX_DMAREQ_ID_USART1_RX    - DMAMUX_DMAREQ_ID_USART1_TX    - DMAMUX_DMAREQ_ID_USART2_RX
+  *         - DMAMUX_DMAREQ_ID_USART2_TX    - DMAMUX_DMAREQ_ID_USART3_RX    - DMAMUX_DMAREQ_ID_USART3_TX    - DMAMUX_DMAREQ_ID_UART4_RX
+  *         - DMAMUX_DMAREQ_ID_UART4_TX     - DMAMUX_DMAREQ_ID_UART5_RX     - DMAMUX_DMAREQ_ID_UART5_TX     - DMAMUX_DMAREQ_ID_USART6_RX
+  *         - DMAMUX_DMAREQ_ID_USART6_TX    - DMAMUX_DMAREQ_ID_UART7_RX     - DMAMUX_DMAREQ_ID_UART7_TX     - DMAMUX_DMAREQ_ID_UART8_RX
+  *         - DMAMUX_DMAREQ_ID_UART8_TX     - DMAMUX_DMAREQ_ID_SDIO1        - DMAMUX_DMAREQ_ID_SDIO2        - DMAMUX_DMAREQ_ID_QSPI1
+  *         - DMAMUX_DMAREQ_ID_QSPI2        - DMAMUX_DMAREQ_ID_TMR1_CH1     - DMAMUX_DMAREQ_ID_TMR1_CH2     - DMAMUX_DMAREQ_ID_TMR1_CH3
+  *         - DMAMUX_DMAREQ_ID_TMR1_CH4     - DMAMUX_DMAREQ_ID_TMR1_OVERFLOW- DMAMUX_DMAREQ_ID_TMR1_TRIG    - DMAMUX_DMAREQ_ID_TMR1_COM
+  *         - DMAMUX_DMAREQ_ID_TMR8_CH1     - DMAMUX_DMAREQ_ID_TMR8_CH2     - DMAMUX_DMAREQ_ID_TMR8_CH3     - DMAMUX_DMAREQ_ID_TMR8_CH4
+  *         - DMAMUX_DMAREQ_ID_TMR8_UP      - DMAMUX_DMAREQ_ID_TMR8_TRIG    - DMAMUX_DMAREQ_ID_TMR8_COM     - DMAMUX_DMAREQ_ID_TMR2_CH1
+  *         - DMAMUX_DMAREQ_ID_TMR2_CH2     - DMAMUX_DMAREQ_ID_TMR2_CH3     - DMAMUX_DMAREQ_ID_TMR2_CH4     - DMAMUX_DMAREQ_ID_TMR2_OVERFLOW
+  *         - DMAMUX_DMAREQ_ID_TMR2_TRIG    - DMAMUX_DMAREQ_ID_TMR3_CH1     - DMAMUX_DMAREQ_ID_TMR3_CH2     - DMAMUX_DMAREQ_ID_TMR3_CH3
+  *         - DMAMUX_DMAREQ_ID_TMR3_CH4     - DMAMUX_DMAREQ_ID_TMR3_OVERFLOW- DMAMUX_DMAREQ_ID_TMR3_TRIG    - DMAMUX_DMAREQ_ID_TMR4_CH1
+  *         - DMAMUX_DMAREQ_ID_TMR4_CH2     - DMAMUX_DMAREQ_ID_TMR4_CH3     - DMAMUX_DMAREQ_ID_TMR4_CH4     - DMAMUX_DMAREQ_ID_TMR4_OVERFLOW
+  *         - DMAMUX_DMAREQ_ID_TMR4_TRIG    - DMAMUX_DMAREQ_ID_TMR5_CH1     - DMAMUX_DMAREQ_ID_TMR5_CH2     - DMAMUX_DMAREQ_ID_TMR5_CH3
+  *         - DMAMUX_DMAREQ_ID_TMR5_CH4     - DMAMUX_DMAREQ_ID_TMR5_OVERFLOW- DMAMUX_DMAREQ_ID_TMR5_TRIG    - DMAMUX_DMAREQ_ID_TMR20_CH1
+  *         - DMAMUX_DMAREQ_ID_TMR20_CH2    - DMAMUX_DMAREQ_ID_TMR20_CH3    - DMAMUX_DMAREQ_ID_TMR20_CH4    - DMAMUX_DMAREQ_ID_TMR20_OVERFLOW
+  *         - DMAMUX_DMAREQ_ID_TMR20_TRIG   - DMAMUX_DMAREQ_ID_TMR20_HALL   - DMAMUX_DMAREQ_ID_DVP
+  * @retval none.
+  */
+void dmamux_init(dmamux_channel_type *dmamux_channelx, dmamux_requst_id_sel_type dmamux_req_sel)
+{
+  dmamux_channelx->muxctrl_bit.reqsel = dmamux_req_sel;
+}
+
+/**
+  * @brief  dmamux sync init struct config with its default value.
+  * @param  dmamux_sync_init_struct: pointer to a dmamux_sync_init_type structure which will be initialized.
+  * @retval none.
+  */
+void dmamux_sync_default_para_init(dmamux_sync_init_type *dmamux_sync_init_struct)
+{
+  dmamux_sync_init_struct->sync_enable = FALSE;
+  dmamux_sync_init_struct->sync_event_enable = FALSE;
+  dmamux_sync_init_struct->sync_polarity = DMAMUX_SYNC_POLARITY_DISABLE;
+  dmamux_sync_init_struct->sync_request_number = 0x0;
+  dmamux_sync_init_struct->sync_signal_sel = (dmamux_sync_id_sel_type)0;
+}
+
+/**
+  * @brief  dmamux synchronization config.
+  * @param  dmamux_channelx:
+  *         this parameter can be one of the following values:
+  *         - DMA1MUX_CHANNEL1
+  *         - DMA1MUX_CHANNEL2
+  *         - DMA1MUX_CHANNEL3
+  *         - DMA1MUX_CHANNEL4
+  *         - DMA1MUX_CHANNEL5
+  *         - DMA1MUX_CHANNEL6
+  *         - DMA1MUX_CHANNEL7
+  *         - DMA2MUX_CHANNEL1
+  *         - DMA2MUX_CHANNEL2
+  *         - DMA2MUX_CHANNEL3
+  *         - DMA2MUX_CHANNEL4
+  *         - DMA2MUX_CHANNEL5
+  *         - DMA2MUX_CHANNEL6
+  *         - DMA2MUX_CHANNEL7
+  * @param  dmamux_sync_init_struct: ointer to a dmamux_sync_init_type structure.
+  * @retval none.
+  */
+void dmamux_sync_config(dmamux_channel_type *dmamux_channelx, dmamux_sync_init_type *dmamux_sync_init_struct)
+{
+  dmamux_channelx->muxctrl_bit.syncsel = dmamux_sync_init_struct->sync_signal_sel;
+  dmamux_channelx->muxctrl_bit.syncpol = dmamux_sync_init_struct->sync_polarity;
+  dmamux_channelx->muxctrl_bit.reqcnt  = dmamux_sync_init_struct->sync_request_number;
+  dmamux_channelx->muxctrl_bit.evtgen  = dmamux_sync_init_struct->sync_event_enable;
+  dmamux_channelx->muxctrl_bit.syncen  = dmamux_sync_init_struct->sync_enable;
+}
+
+/**
+  * @brief  dmamux request generator init struct config with its default value.
+  * @param  dmamux_gen_init_struct: pointer to a dmamux_gen_init_type structure which will be initialized.
+  * @retval none.
+  */
+void dmamux_generator_default_para_init(dmamux_gen_init_type *dmamux_gen_init_struct)
+{
+  dmamux_gen_init_struct->gen_enable         = FALSE;
+  dmamux_gen_init_struct->gen_polarity       = DMAMUX_GEN_POLARITY_DISABLE;
+  dmamux_gen_init_struct->gen_request_number = 0x0;
+  dmamux_gen_init_struct->gen_signal_sel     = (dmamux_gen_id_sel_type)0x0;
+}
+
+/**
+  * @brief  dmamux request generator init.
+  * @param  dmamux_gen_x :
+  *         this parameter can be one of the following values:
+  *         - DMA1MUX_GENERATOR1
+  *         - DMA1MUX_GENERATOR2
+  *         - DMA1MUX_GENERATOR3
+  *         - DMA1MUX_GENERATOR4
+  *         - DMA2MUX_GENERATOR1
+  *         - DMA2MUX_GENERATOR2
+  *         - DMA2MUX_GENERATOR3
+  *         - DMA2MUX_GENERATOR4
+  * @param  dmamux_gen_init_struct: pointer to a dmamux_gen_init_type structure which will be initialized.
+  * @retval none.
+  */
+void dmamux_generator_config(dmamux_generator_type *dmamux_gen_x, dmamux_gen_init_type *dmamux_gen_init_struct)
+{
+  dmamux_gen_x->gctrl_bit.sigsel  = dmamux_gen_init_struct->gen_signal_sel;
+  dmamux_gen_x->gctrl_bit.gpol    = dmamux_gen_init_struct->gen_polarity;
+  dmamux_gen_x->gctrl_bit.greqcnt = dmamux_gen_init_struct->gen_request_number;
+  dmamux_gen_x->gctrl_bit.gen     = dmamux_gen_init_struct->gen_enable;
+}
+
+/**
+  * @brief  enable or disable the dmamux sync interrupts.
+  * @param  dmamux_channelx:
+  *         this parameter can be one of the following values:
+  *         - DMA1MUX_CHANNEL1
+  *         - DMA1MUX_CHANNEL2
+  *         - DMA1MUX_CHANNEL3
+  *         - DMA1MUX_CHANNEL4
+  *         - DMA1MUX_CHANNEL5
+  *         - DMA1MUX_CHANNEL6
+  *         - DMA1MUX_CHANNEL7
+  *         - DMA2MUX_CHANNEL1
+  *         - DMA2MUX_CHANNEL2
+  *         - DMA2MUX_CHANNEL3
+  *         - DMA2MUX_CHANNEL4
+  *         - DMA2MUX_CHANNEL5
+  *         - DMA2MUX_CHANNEL6
+  *         - DMA2MUX_CHANNEL7
+  * @param  new_state (TRUE or FALSE).
+  * @retval none.
+  */
+void dmamux_sync_interrupt_enable(dmamux_channel_type *dmamux_channelx, confirm_state new_state)
+{
+  if(new_state != FALSE)
+  {
+    dmamux_channelx->muxctrl_bit.syncovien = TRUE;
+  }
+  else
+  {
+    dmamux_channelx->muxctrl_bit.syncovien = FALSE;
+  }
+}
+
+/**
+  * @brief  enable or disable the dmamux request generator interrupts.
+  * @param  dmamux_gen_x : pointer to a dmamux_generator_type structure.
+  *         this parameter can be one of the following values:
+  *         - DMA1MUX_GENERATOR1
+  *         - DMA1MUX_GENERATOR2
+  *         - DMA1MUX_GENERATOR3
+  *         - DMA1MUX_GENERATOR4
+  *         - DMA2MUX_GENERATOR1
+  *         - DMA2MUX_GENERATOR2
+  *         - DMA2MUX_GENERATOR3
+  *         - DMA2MUX_GENERATOR4
+  * @param  new_state (TRUE or FALSE).
+  * @retval none.
+  */
+void dmamux_generator_interrupt_enable(dmamux_generator_type *dmamux_gen_x, confirm_state new_state)
+{
+  if(new_state != FALSE)
+  {
+    dmamux_gen_x->gctrl_bit.trgovien = TRUE;
+  }
+  else
+  {
+    dmamux_gen_x->gctrl_bit.trgovien = FALSE;
+  }
+}
+
+/**
+  * @brief  dmamux sync flag get.
+  * @param  dma_x : pointer to a dma_type structure, can be DMA1 or DMA2.
+  * @param  flag
+  *         this parameter can be any combination of the following values:
+  *         - DMAMUX_SYNC_OV1_FLAG
+  *         - DMAMUX_SYNC_OV2_FLAG
+  *         - DMAMUX_SYNC_OV3_FLAG
+  *         - DMAMUX_SYNC_OV4_FLAG
+  *         - DMAMUX_SYNC_OV5_FLAG
+  *         - DMAMUX_SYNC_OV6_FLAG
+  *         - DMAMUX_SYNC_OV7_FLAG
+  * @retval state of dmamux sync flag.
+  */
+flag_status dmamux_sync_flag_get(dma_type *dma_x, uint32_t flag)
+{
+  if((dma_x->muxsyncsts & flag) != RESET)
+  {
+    return SET;
+  }
+  else
+  {
+    return RESET;
+  }
+}
+
+/**
+  * @brief  dmamux sync flag clear.
+  * @param  dma_x : pointer to a dma_type structure, can be DMA1 or DMA2.
+  * @param  flag
+  *         this parameter can be any combination of the following values:
+  *         - DMAMUX_SYNC_OV1_FLAG
+  *         - DMAMUX_SYNC_OV2_FLAG
+  *         - DMAMUX_SYNC_OV3_FLAG
+  *         - DMAMUX_SYNC_OV4_FLAG
+  *         - DMAMUX_SYNC_OV5_FLAG
+  *         - DMAMUX_SYNC_OV6_FLAG
+  *         - DMAMUX_SYNC_OV7_FLAG
+  * @retval none.
+  */
+void dmamux_sync_flag_clear(dma_type *dma_x, uint32_t flag)
+{
+  dma_x->muxsyncclr = flag;
+}
+
+/**
+  * @brief  dmamux request generator flag get.
+  * @param  dma_x : pointer to a dma_type structure, can be DMA1 or DMA2.
+  * @param  flag
+  *         this parameter can be any combination of the following values:
+  *         - DMAMUX_GEN_TRIG_OV1_FLAG
+  *         - DMAMUX_GEN_TRIG_OV2_FLAG
+  *         - DMAMUX_GEN_TRIG_OV3_FLAG
+  *         - DMAMUX_GEN_TRIG_OV4_FLAG
+  * @retval state of dmamux sync flag.
+  */
+flag_status dmamux_generator_flag_get(dma_type *dma_x, uint32_t flag)
+{
+  if((dma_x->muxgsts & flag) != RESET)
+  {
+    return SET;
+  }
+  else
+  {
+    return RESET;
+  }
+}
+
+/**
+  * @brief  dmamux request generator flag clear.
+  * @param  dma_x : pointer to a dma_type structure, can be DMA1 or DMA2.
+  * @param  flag
+  *         this parameter can be any combination of the following values:
+  *         - DMAMUX_GEN_TRIG_OV1_FLAG
+  *         - DMAMUX_GEN_TRIG_OV2_FLAG
+  *         - DMAMUX_GEN_TRIG_OV3_FLAG
+  *         - DMAMUX_GEN_TRIG_OV4_FLAG
+  * @retval none.
+  */
+void dmamux_generator_flag_clear(dma_type *dma_x, uint32_t flag)
+{
+  dma_x->muxgclr = flag;
+}
+
+/**
+  * @}
+  */
+
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */

lib/main/AT32F43x/Drivers/AT32F43x_StdPeriph_Driver/src/at32f435_437_dvp.c

@@ -0,0 +1,528 @@
+/**
+  **************************************************************************
+  * @file     at32f435_437_dvp.c
+  * @version  v2.1.0
+  * @date     2022-08-16
+  * @brief    contains all the functions for the dvp firmware library
+  **************************************************************************
+  *                       Copyright notice & Disclaimer
+  *
+  * The software Board Support Package (BSP) that is made available to
+  * download from Artery official website is the copyrighted work of Artery.
+  * Artery authorizes customers to use, copy, and distribute the BSP
+  * software and its related documentation for the purpose of design and
+  * development in conjunction with Artery microcontrollers. Use of the
+  * software is governed by this copyright notice and the following disclaimer.
+  *
+  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+  *
+  **************************************************************************
+  */
+
+#include "at32f435_437_conf.h"
+
+/** @addtogroup AT32F435_437_periph_driver
+  * @{
+  */
+
+/** @defgroup DVP
+  * @brief DVP driver modules
+  * @{
+  */
+
+#ifdef DVP_MODULE_ENABLED
+
+/** @defgroup DVP_private_functions
+  * @{
+  */
+
+/**
+  * @brief  reset the dvp register
+  * @param  none
+  * @retval none
+  */
+void dvp_reset(void)
+{
+  crm_periph_reset(CRM_DVP_PERIPH_RESET, TRUE);
+  crm_periph_reset(CRM_DVP_PERIPH_RESET, FALSE);
+}
+
+/**
+  * @brief  enable or disable dvp capture
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void dvp_capture_enable(confirm_state new_state)
+{
+  DVP->ctrl_bit.cap = new_state;
+}
+
+/**
+  * @brief  set dvp capture mode
+  * @param  cap_mode
+  *         this parameter can be one of the following values:
+  *         - DVP_CAP_FUNC_MODE_CONTINUOUS
+  *         - DVP_CAP_FUNC_MODE_SINGLE
+  * @retval none
+  */
+void dvp_capture_mode_set(dvp_cfm_type cap_mode)
+{
+  DVP->ctrl_bit.cfm = cap_mode;
+}
+
+/**
+  * @brief  set dvp cropping window enable
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void dvp_window_crop_enable(confirm_state new_state)
+{
+  DVP->ctrl_bit.crp = new_state;
+}
+
+/**
+  * @brief  set dvp cropping window configuration
+  * @param  crop_x: cropping window horizontal start pixel
+  * @param  crop_y: cropping window vertical start line
+  * @param  crop_w: cropping window horizontal pixel number
+  * @param  crop_h: cropping window vertical line number
+  * @param  bytes: the number of bytes corresponding to one pixel
+  *         eg. y8:bytes = 1, rgb565:bytes = 2
+  * @retval none
+  */
+void dvp_window_crop_set(uint16_t crop_x, uint16_t crop_y, uint16_t crop_w, uint16_t crop_h, uint8_t bytes)
+{
+  DVP->cwst = ((crop_x * bytes) | (crop_y << 16));
+  DVP->cwsz = ((crop_w * bytes - 1) | ((crop_h - 1) << 16));
+}
+
+/**
+  * @brief  enable or disable dvp jpeg
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void dvp_jpeg_enable(confirm_state new_state)
+{
+  DVP->ctrl_bit.jpeg = new_state;
+}
+
+/**
+  * @brief  set dvp synchronization mode
+  * @param  sync_mode
+  *         this parameter can be one of the following values:
+  *         - DVP_SYNC_MODE_HARDWARE
+  *         - DVP_SYNC_MODE_EMBEDDED
+  * @retval none
+  */
+void dvp_sync_mode_set(dvp_sm_type sync_mode)
+{
+  DVP->ctrl_bit.sm = sync_mode;
+}
+
+/**
+  * @brief  set dvp synchronization code configuration
+  * @param  fmsc(0x00~0xFF): frame start code
+  * @param  fmec(0x00~0xFF): frame end code
+  * @param  lnsc(0x00~0xFF): line start code
+  * @param  lnec(0x00~0xFF): line end code
+  * @retval none
+  */
+void dvp_sync_code_set(uint8_t fmsc, uint8_t fmec, uint8_t lnsc, uint8_t lnec)
+{
+  DVP->scr = (fmsc | (lnsc << 8) | (lnec << 16) | (fmec << 24));
+}
+
+/**
+  * @brief  set dvp synchronization unmask configuration
+  * @param  fmsu(0x00~0xFF): frame start unmask
+  * @param  fmeu(0x00~0xFF): frame end unmask
+  * @param  lnsu(0x00~0xFF): line start unmask
+  * @param  lneu(0x00~0xFF): line end unmask
+  * @retval none
+  */
+void dvp_sync_unmask_set(uint8_t fmsu, uint8_t fmeu, uint8_t lnsu, uint8_t lneu)
+{
+  DVP->sur = (fmsu | (lnsu << 8) | (lneu << 16) | (fmeu << 24));
+}
+
+/**
+  * @brief  set dvp pixel clock polarity
+  * @param  edge
+  *         this parameter can be one of the following values:
+  *         - DVP_CLK_POLARITY_RISING
+  *         - DVP_CLK_POLARITY_FALLING
+  * @retval none
+  */
+void dvp_pclk_polarity_set(dvp_ckp_type edge)
+{
+  DVP->ctrl_bit.ckp = edge;
+}
+
+/**
+  * @brief  set dvp horizontal synchronization polarity
+  * @param  hsync_pol
+  *         this parameter can be one of the following values:
+  *         - DVP_HSYNC_POLARITY_HIGH
+  *         - DVP_HSYNC_POLARITY_LOW
+  * @retval none
+  */
+void dvp_hsync_polarity_set(dvp_hsp_type hsync_pol)
+{
+  DVP->ctrl_bit.hsp = hsync_pol;
+}
+
+/**
+  * @brief  set dvp vertical synchronization polarity
+  * @param  vsync_pol
+  *         this parameter can be one of the following values:
+  *         - DVP_VSYNC_POLARITY_LOW
+  *         - DVP_VSYNC_POLARITY_HIGH
+  * @retval none
+  */
+void dvp_vsync_polarity_set(dvp_vsp_type vsync_pol)
+{
+  DVP->ctrl_bit.vsp = vsync_pol;
+}
+
+/**
+  * @brief  config dvp basic frame rate control
+  * @note   this function only work in continuous fire mode(ctrl_bit.cfm = 0)
+  * @param  dvp_bfrc
+  *         this parameter can be one of the following values:
+  *         - DVP_BFRC_ALL
+  *         - DVP_BFRC_HALF
+  *         - DVP_BFRC_QUARTER
+  * @retval none
+  */
+void dvp_basic_frame_rate_control_set(dvp_bfrc_type dvp_bfrc)
+{
+  DVP->ctrl_bit.bfrc = dvp_bfrc;
+}
+
+/**
+  * @brief  config dvp pixel data length
+  * @param  dvp_pdl
+  *         this parameter can be one of the following values:
+  *         - DVP_PIXEL_DATA_LENGTH_8
+  *         - DVP_PIXEL_DATA_LENGTH_10
+  *         - DVP_PIXEL_DATA_LENGTH_12
+  *         - DVP_PIXEL_DATA_LENGTH_14
+  * @retval none
+  */
+void dvp_pixel_data_length_set(dvp_pdl_type dvp_pdl)
+{
+  DVP->ctrl_bit.pdl = dvp_pdl;
+}
+
+/**
+  * @brief  enable or disable dvp function
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void dvp_enable(confirm_state new_state)
+{
+  DVP->ctrl_bit.ena = new_state;
+}
+
+/**
+  * @brief  set dvp zoomout select
+  * @param  dvp_pcdes: pixel capture/drop selection extension (Only work when pcdc = 2)
+  *         this parameter can be one of the following values:
+  *         - DVP_PCDES_CAP_FIRST
+  *         - DVP_PCDES_DROP_FIRST
+  * @retval none
+  */
+void dvp_zoomout_select(dvp_pcdes_type dvp_pcdes)
+{
+  DVP->actrl_bit.pcdes = dvp_pcdes;
+}
+
+/**
+  * @brief  set dvp zoomout configuration
+  * @param  dvp_pcdc: basic pixel capture/drop control
+  *         this parameter can be one of the following values:
+  *         - DVP_PCDC_ALL
+  *         - DVP_PCDC_ONE_IN_TWO
+  *         - DVP_PCDC_ONE_IN_FOUR
+  *         - DVP_PCDC_TWO_IN_FOUR
+  * @param  dvp_pcds: pixel capture/drop selection
+  *         this parameter can be one of the following values:
+  *         - DVP_PCDS_CAP_FIRST
+  *         - DVP_PCDS_DROP_FIRST
+  * @param  dvp_lcdc: line capture/drop control
+  *         this parameter can be one of the following values:
+  *         - DVP_LCDC_ALL
+  *         - DVP_LCDC_ONE_IN_TWO
+  * @param  dvp_lcds: line capture/drop selection
+  *         this parameter can be one of the following values:
+  *         - DVP_LCDS_CAP_FIRST
+  *         - DVP_LCDS_DROP_FIRST
+  * @retval none
+  */
+void dvp_zoomout_set(dvp_pcdc_type dvp_pcdc, dvp_pcds_type dvp_pcds, dvp_lcdc_type dvp_lcdc, dvp_lcds_type dvp_lcds)
+{
+  DVP->ctrl_bit.pcdc = dvp_pcdc;
+  DVP->ctrl_bit.pcds = dvp_pcds;
+  DVP->ctrl_bit.lcdc = dvp_lcdc;
+  DVP->ctrl_bit.lcds = dvp_lcds;
+}
+
+/**
+  * @brief  get dvp basic status
+  * @param  dvp_status_basic_type:
+  *         this parameter can be one of the following values:
+  *         - DVP_STATUS_HSYN
+  *         - DVP_STATUS_VSYN
+  *         - DVP_STATUS_OFNE
+  * @retval flag_status (SET or RESET)
+  */
+flag_status dvp_basic_status_get(dvp_status_basic_type dvp_status_basic)
+{
+  flag_status status = RESET;
+
+  if ((DVP->sts & (0x1 << dvp_status_basic)) != (uint16_t)RESET)
+  {
+    status = SET;
+  }
+  else
+  {
+    status = RESET;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  enable or disable dvp interrupt
+  * @param  dvp_int:
+  *         this parameter can be any combination of the following values:
+  *         - DVP_CFD_INT
+  *         - DVP_OVR_INT
+  *         - DVP_ESE_INT
+  *         - DVP_VS_INT
+  *         - DVP_HS_INT
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void dvp_interrupt_enable(uint32_t dvp_int, confirm_state new_state)
+{
+  if(new_state == TRUE)
+  {
+    DVP->ier |= dvp_int;
+  }
+  else
+  {
+    DVP->ier &= ~dvp_int;
+  }
+}
+
+/**
+  * @brief  get dvp event/interrupt flag status
+  * @param  flag
+  *         this parameter can be one of the following values:
+  *         event flag:
+  *         - DVP_CFD_EVT_FLAG
+  *         - DVP_OVR_EVT_FLAG
+  *         - DVP_ESE_EVT_FLAG
+  *         - DVP_VS_EVT_FLAG
+  *         - DVP_HS_EVT_FLAG
+  *         interrupt flag:
+  *         - DVP_CFD_INT_FLAG
+  *         - DVP_OVR_INT_FLAG
+  *         - DVP_ESE_INT_FLAG
+  *         - DVP_VS_INT_FLAG
+  *         - DVP_HS_INT_FLAG
+  * @retval flag_status (SET or RESET)
+  */
+flag_status dvp_flag_get(uint32_t flag)
+{
+  flag_status status = RESET;
+  if(flag & 0x80000000)
+  {
+    if((DVP->ists & flag) != RESET)
+    {
+      status = SET;
+    }
+    else
+    {
+      status = RESET;
+    }
+  }
+  else
+  {
+    if((DVP->ests & flag) != RESET)
+    {
+      status = SET;
+    }
+    else
+    {
+      status = RESET;
+    }
+  }
+  return status;
+}
+
+/**
+  * @brief  clear dvp's pending flags
+  * @param  flag
+  *         this parameter can be one of the following values:
+  *         event flag:
+  *         - DVP_CFD_EVT_FLAG
+  *         - DVP_OVR_EVT_FLAG
+  *         - DVP_ESE_EVT_FLAG
+  *         - DVP_VS_EVT_FLAG
+  *         - DVP_HS_EVT_FLAG
+  *         interrupt flag:
+  *         - DVP_CFD_INT_FLAG
+  *         - DVP_OVR_INT_FLAG
+  *         - DVP_ESE_INT_FLAG
+  *         - DVP_VS_INT_FLAG
+  *         - DVP_HS_INT_FLAG
+  * @retval none
+  */
+void dvp_flag_clear(uint32_t flag)
+{
+  flag &= ~0x80000000;
+  DVP->iclr = flag;
+}
+
+/**
+  * @brief  set dvp enhanced image scaling resize enable
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void dvp_enhanced_scaling_resize_enable(confirm_state new_state)
+{
+  DVP->actrl_bit.eisre = new_state;
+}
+/**
+  * @brief  set dvp enhanced image scaling resize configuration
+  * @param  src_w(0x0001~0x1FFF): horizontal scaling resize source size (source image width)
+  * @param  des_w(0x0001~0x1FFF): horizontal scaling resize target size (target image width)
+  * @param  src_h(0x0001~0x1FFF): vertical scaling resize source size (source image height)
+  * @param  des_h(0x0001~0x1FFF): vertical scaling resize target size (target image height)
+  * @retval none
+  */
+void dvp_enhanced_scaling_resize_set(uint16_t src_w, uint16_t des_w, uint16_t src_h, uint16_t des_h)
+{
+  if((!DVP->ctrl_bit.pcdc) && (!DVP->ctrl_bit.lcdc) && DVP->actrl_bit.efdf)
+  {
+    DVP->hscf = (src_w | (des_w << 16));
+    DVP->vscf = (src_h | (des_h << 16));
+  }
+}
+
+/**
+  * @brief  set enhanced frame rate control configuration
+  * @param  efrcsf(0x00~0x1F): original frame rate contorl factor
+  * @param  efrctf(0x00~0x1F): enhanced frame rate contorl factor
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void dvp_enhanced_framerate_set(uint16_t efrcsf, uint16_t efrctf, confirm_state new_state)
+{
+  if((!DVP->ctrl_bit.cfm) && (!DVP->ctrl_bit.bfrc) && (efrctf <= efrcsf))
+  {
+    DVP->frf = (efrcsf | (efrctf << 8));
+  }
+
+  DVP->actrl_bit.efrce = new_state;
+}
+
+/**
+  * @brief  set dvp monochrome image binarization configuration
+  * @param  mibthd(0x00~0xFF): monochrome image binarization threshold
+  * @param  new_state: (TRUE or FALSE)
+  * @retval none
+  */
+void dvp_monochrome_image_binarization_set(uint8_t mibthd, confirm_state new_state)
+{
+  DVP->bth_bit.mibthd = mibthd;
+  DVP->actrl_bit.mibe = new_state;
+}
+
+/**
+  * @brief  set dvp enhanced function data format configuration
+  * @param  dvp_efdf: enhanced function data format
+  *         this parameter can be one of the following values:
+  *         - DVP_EFDF_BYPASS
+  *         - DVP_EFDF_YUV422_UYVY
+  *         - DVP_EFDF_YUV422_YUYV
+  *         - DVP_EFDF_RGB565_555
+  *         - DVP_EFDF_Y8
+  * @retval none
+  */
+void dvp_enhanced_data_format_set(dvp_efdf_type dvp_efdf)
+{
+  DVP->actrl_bit.efdf = dvp_efdf;
+}
+
+/**
+  * @brief  set dvp input data un-used condition/number configuration
+  * @param  dvp_idus: input data un-used condition
+  *         this parameter can be one of the following values:
+  *         - DVP_IDUS_MSB
+  *         - DVP_IDUS_LSB
+  * @param  dvp_idun: input data un-used number
+  *         this parameter can be one of the following values:
+  *         - DVP_IDUN_0
+  *         - DVP_IDUN_2
+  *         - DVP_IDUN_4
+  *         - DVP_IDUN_6
+  * @retval none
+  */
+void dvp_input_data_unused_set(dvp_idus_type dvp_idus, dvp_idun_type dvp_idun)
+{
+  DVP->actrl_bit.idus = dvp_idus;
+  DVP->actrl_bit.idun = dvp_idun;
+}
+
+/**
+  * @brief  set dvp dma burst transfer configuration
+  * @param  dvp_dmabt: dma burst transfer configuration
+  *         this parameter can be one of the following values:
+  *         - DVP_DMABT_SINGLE
+  *         - DVP_DMABT_BURST
+  * @retval none
+  */
+void dvp_dma_burst_set(dvp_dmabt_type dvp_dmabt)
+{
+  DVP->actrl_bit.dmabt = dvp_dmabt;
+}
+
+/**
+  * @brief  set dvp hsync/vsync event interrupt strategy configuration
+  * @param  dvp_hseid: hsync event interrupt strategy
+  *         this parameter can be one of the following values:
+  *         - DVP_HSEID_LINE_END
+  *         - DVP_HSEID_LINE_START
+  * @param  dvp_vseid: vsync event interrupt strategy
+  *         this parameter can be one of the following values:
+  *         - DVP_VSEID_FRAME_END
+  *         - DVP_VSEID_FRMAE_START
+  * @retval none
+  */
+void dvp_sync_event_interrupt_set(dvp_hseid_type dvp_hseid, dvp_vseid_type dvp_vseid)
+{
+  DVP->actrl_bit.hseid = dvp_hseid;
+  DVP->actrl_bit.vseid = dvp_vseid;
+}
+
+/**
+  * @}
+  */
+
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */

lib/main/AT32F43x/Drivers/AT32F43x_StdPeriph_Driver/src/at32f435_437_edma.c

@@ -0,0 +1,931 @@
+/**
+  **************************************************************************
+  * @file     at32f435_437_edma.c
+  * @version  v2.1.0
+  * @date     2022-08-16
+  * @brief    contains all the functions for the edma firmware library
+  **************************************************************************
+  *                       Copyright notice & Disclaimer
+  *
+  * The software Board Support Package (BSP) that is made available to
+  * download from Artery official website is the copyrighted work of Artery.
+  * Artery authorizes customers to use, copy, and distribute the BSP
+  * software and its related documentation for the purpose of design and
+  * development in conjunction with Artery microcontrollers. Use of the
+  * software is governed by this copyright notice and the following disclaimer.
+  *
+  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+  *
+  **************************************************************************
+  */
+
+#include "at32f435_437_conf.h"
+
+/** @addtogroup AT32F435_437_periph_driver
+  * @{
+  */
+
+/** @defgroup EDMA
+  * @brief EDMA driver modules
+  * @{
+  */
+
+#ifdef EDMA_MODULE_ENABLED
+
+/** @defgroup EDMA_private_functions
+  * @{
+  */
+
+/**
+  * @brief  reset edma_streamx channely register.
+  * @param  edma_streamx:
+  *         this parameter can be one of the following values:
+  *         - EDMA_STREAM1
+  *         - EDMA_STREAM2
+  *         - EDMA_STREAM3
+  *         - EDMA_STREAM4
+  *         - EDMA_STREAM5
+  *         - EDMA_STREAM6
+  *         - EDMA_STREAM7
+  *         - EDMA_STREAM8
+  * @retval none.
+  */
+void edma_reset(edma_stream_type *edma_streamx)
+{
+  /* reset registers for the selected stream */
+  edma_streamx->ctrl_bit.sen = FALSE;
+  edma_streamx->ctrl = 0x0;
+  edma_streamx->dtcnt = 0x0;
+  edma_streamx->paddr = 0x0;
+  edma_streamx->m0addr = 0x0;
+  edma_streamx->m1addr = 0x0;
+  edma_streamx->fctrl = (uint32_t)0x00000021;
+
+  /* reset interrupt pending bits for the selected stream */
+  switch((uint32_t)edma_streamx)
+  {
+    case EDMA_STREAM1_BASE:
+      EDMA->clr1 = EDMA_STREAM1_INT_MASK;
+      break;
+    case EDMA_STREAM2_BASE:
+      EDMA->clr1 = EDMA_STREAM2_INT_MASK;
+      break;
+    case EDMA_STREAM3_BASE:
+      EDMA->clr1 = EDMA_STREAM3_INT_MASK;
+      break;
+    case EDMA_STREAM4_BASE:
+      EDMA->clr1 = EDMA_STREAM4_INT_MASK;
+      break;
+    case EDMA_STREAM5_BASE:
+      EDMA->clr2 = EDMA_STREAM5_INT_MASK;
+      break;
+    case EDMA_STREAM6_BASE:
+      EDMA->clr2 = EDMA_STREAM6_INT_MASK;
+      break;
+    case EDMA_STREAM7_BASE:
+      EDMA->clr2 = EDMA_STREAM7_INT_MASK;
+      break;
+    case EDMA_STREAM8_BASE:
+      EDMA->clr2 = EDMA_STREAM8_INT_MASK;
+      break;
+    default: break;
+  }
+}
+
+/**
+  * @brief  edma init.
+  * @param  edma_streamx:
+  *         this parameter can be one of the following values:
+  *         - EDMA_STREAM1
+  *         - EDMA_STREAM2
+  *         - EDMA_STREAM3
+  *         - EDMA_STREAM4
+  *         - EDMA_STREAM5
+  *         - EDMA_STREAM6
+  *         - EDMA_STREAM7
+  *         - EDMA_STREAM8
+  * @param  edma_init_struct: pointer to a edma_init_type structure.
+  * @retval none.
+  */
+void edma_init(edma_stream_type *edma_streamx, edma_init_type *edma_init_struct)
+{
+  /* config dtd bits */
+  edma_streamx->ctrl_bit.dtd = edma_init_struct->direction;
+
+  /* config pincm bit */
+  edma_streamx->ctrl_bit.pincm = edma_init_struct->peripheral_inc_enable;
+
+  /* config mincm bit*/
+  edma_streamx->ctrl_bit.mincm = edma_init_struct->memory_inc_enable;
+
+  /* config pwidth bits */
+  edma_streamx->ctrl_bit.pwidth = edma_init_struct->peripheral_data_width;
+
+  /* config mwidth bits */
+  edma_streamx->ctrl_bit.mwidth = edma_init_struct->memory_data_width;
+
+  /* config lm bit */
+  edma_streamx->ctrl_bit.lm = edma_init_struct->loop_mode_enable;
+
+  /* config spl bits */
+  edma_streamx->ctrl_bit.spl = edma_init_struct->priority;
+
+  /* config mct bits */
+  edma_streamx->ctrl_bit.mct = edma_init_struct->memory_burst_mode;
+
+  /* config pct bits */
+  edma_streamx->ctrl_bit.pct = edma_init_struct->peripheral_burst_mode;
+
+  /* config fen bits */
+  edma_streamx->fctrl_bit.fen = edma_init_struct->fifo_mode_enable;
+
+  /* config fthsel bits*/
+  edma_streamx->fctrl_bit.fthsel = edma_init_struct->fifo_threshold;
+
+  /* config dtcnt */
+  edma_streamx->dtcnt = edma_init_struct->buffer_size;
+
+  /* config paddr */
+  edma_streamx->paddr = edma_init_struct->peripheral_base_addr;
+
+  /* config m0addr */
+  edma_streamx->m0addr = edma_init_struct->memory0_base_addr;
+}
+
+/**
+  * @brief  edma init struct config with its default value.
+  * @param  edma_init_struct: pointer to a edma_init_type structure which will be initialized.
+  * @retval none.
+  */
+void edma_default_para_init(edma_init_type *edma_init_struct)
+{
+  edma_init_struct->buffer_size = 0;
+  edma_init_struct->loop_mode_enable = FALSE;
+  edma_init_struct->direction = EDMA_DIR_PERIPHERAL_TO_MEMORY;
+  edma_init_struct->fifo_threshold = EDMA_FIFO_THRESHOLD_1QUARTER;
+  edma_init_struct->fifo_mode_enable = FALSE;
+  edma_init_struct->memory0_base_addr = 0;
+  edma_init_struct->memory_burst_mode = EDMA_MEMORY_SINGLE;
+  edma_init_struct->memory_data_width = EDMA_MEMORY_DATA_WIDTH_BYTE;
+  edma_init_struct->memory_inc_enable = FALSE;
+  edma_init_struct->peripheral_base_addr = 0;
+  edma_init_struct->peripheral_burst_mode = EDMA_PERIPHERAL_SINGLE;
+  edma_init_struct->peripheral_data_width = EDMA_PERIPHERAL_DATA_WIDTH_BYTE;
+  edma_init_struct->peripheral_inc_enable = FALSE;
+  edma_init_struct->priority = EDMA_PRIORITY_LOW;
+}
+
+/**
+  * @brief  enable or disable the edma streamx.
+  * @param  edma_streamx:
+  *         this parameter can be one of the following values:
+  *         - EDMA_STREAM1
+  *         - EDMA_STREAM2
+  *         - EDMA_STREAM3
+  *         - EDMA_STREAM4
+  *         - EDMA_STREAM5
+  *         - EDMA_STREAM6
+  *         - EDMA_STREAM7
+  *         - EDMA_STREAM8
+  * @param  new_state (TRUE or FALSE).
+  * @retval none.
+  */
+void edma_stream_enable(edma_stream_type *edma_streamx, confirm_state new_state)
+{
+  edma_streamx->ctrl_bit.sen = new_state;
+}
+
+/**
+  * @brief  enable or disable the edma streamx interrupts.
+  * @param  edma_streamx:
+  *         this parameter can be one of the following values:
+  *         - EDMA_STREAM1
+  *         - EDMA_STREAM2
+  *         - EDMA_STREAM3
+  *         - EDMA_STREAM4
+  *         - EDMA_STREAM5
+  *         - EDMA_STREAM6
+  *         - EDMA_STREAM7
+  *         - EDMA_STREAM8
+  * @param  edma_int:
+  *         this parameter can be one of the following values:
+  *         - EDMA_FDT_INT
+  *         - EDMA_HDT_INT
+  *         - EDMA_DTERR_INT
+  *         - EDMA_DMERR_INT
+  *         - EDMA_FERR_INT
+  * @param  new_state (TRUE or FALSE).
+  * @retval none.
+  */
+void edma_interrupt_enable(edma_stream_type *edma_streamx, uint32_t edma_int, confirm_state new_state)
+{
+  if((edma_int & EDMA_FERR_INT) != 0)
+  {
+    if(new_state != FALSE)
+    {
+      edma_streamx->fctrl |= (uint32_t)EDMA_FERR_INT;
+    }
+    else
+    {
+      edma_streamx->fctrl &= ~(uint32_t)EDMA_FERR_INT;
+    }
+  }
+
+  if(edma_int != EDMA_FERR_INT)
+  {
+    if(new_state != FALSE)
+    {
+      edma_streamx->ctrl |= (uint32_t)edma_int;
+    }
+    else
+    {
+      edma_streamx->ctrl &= ~(uint32_t)edma_int;
+    }
+  }
+}
+
+/**
+  * @brief  config the edma peripheral increment offset size mode.
+  * @param  edma_streamx:
+  *         this parameter can be one of the following values:
+  *         - EDMA_STREAM1
+  *         - EDMA_STREAM2
+  *         - EDMA_STREAM3
+  *         - EDMA_STREAM4
+  *         - EDMA_STREAM5
+  *         - EDMA_STREAM6
+  *         - EDMA_STREAM7
+  *         - EDMA_STREAM8
+  * @param  offset: peripheral increment offset size.
+  *         this parameter can be one of the following values:
+  *         - EDMA_PERIPHERAL_INC_PSIZE
+  *         - EDMA_PERIPHERAL_INC_4_BYTE
+  * @retval none.
+  */
+void edma_peripheral_inc_offset_set(edma_stream_type *edma_streamx, edma_peripheral_inc_offset_type offset)
+{
+  edma_streamx->ctrl_bit.pincos = offset;
+}
+
+/**
+  * @brief  enable or disable the edma streamx flow controller.
+  * @param  edma_streamx:
+  *         this parameter can be one of the following values:
+  *         - EDMA_STREAM1
+  *         - EDMA_STREAM2
+  *         - EDMA_STREAM3
+  *         - EDMA_STREAM4
+  *         - EDMA_STREAM5
+  *         - EDMA_STREAM6
+  *         - EDMA_STREAM7
+  *         - EDMA_STREAM8
+  * @param  new_state (TRUE or FALSE).
+  * @retval none.
+  */
+void edma_flow_controller_enable(edma_stream_type *edma_streamx, confirm_state new_state)
+{
+  edma_streamx->ctrl_bit.pfctrl = new_state;
+}
+
+/**
+  * @brief  set the number of data to be transferred.
+  * @param  edma_streamx:
+  *         this parameter can be one of the following values:
+  *         - EDMA_STREAM1
+  *         - EDMA_STREAM2
+  *         - EDMA_STREAM3
+  *         - EDMA_STREAM4
+  *         - EDMA_STREAM5
+  *         - EDMA_STREAM6
+  *         - EDMA_STREAM7
+  *         - EDMA_STREAM8
+  * @param  data_number: the number of data to be transferred (0x0000~0xFFFF).
+  * @retval none.
+  */
+void edma_data_number_set(edma_stream_type *edma_streamx, uint16_t data_number)
+{
+  /* write the number of data units to be transferred */
+  edma_streamx->dtcnt = data_number;
+}
+
+/**
+  * @brief  get the number of data to be transferred.
+  * @param  edma_streamx:
+  *         this parameter can be one of the following values:
+  *         - EDMA_STREAM1
+  *         - EDMA_STREAM2
+  *         - EDMA_STREAM3
+  *         - EDMA_STREAM4
+  *         - EDMA_STREAM5
+  *         - EDMA_STREAM6
+  *         - EDMA_STREAM7
+  *         - EDMA_STREAM8
+  * @retval the number value.
+  */
+uint16_t edma_data_number_get(edma_stream_type *edma_streamx)
+{
+  return ((uint16_t)(edma_streamx->dtcnt));
+}
+
+/**
+  * @brief  config the the double buffer mode.
+  * @param  edma_streamx:
+  *         this parameter can be one of the following values:
+  *         - EDMA_STREAM1
+  *         - EDMA_STREAM2
+  *         - EDMA_STREAM3
+  *         - EDMA_STREAM4
+  *         - EDMA_STREAM5
+  *         - EDMA_STREAM6
+  *         - EDMA_STREAM7
+  *         - EDMA_STREAM8
+  * @param  memory1_addr: the address of the second buffer.
+  * @param  current_memory: specifies the target area of the first transfer.
+  *         this parameter can be one of the following values:
+  *         - EDMA_MEMORY_0
+  *         - EDMA_MEMORY_1
+  * @retval none.
+  */
+void edma_double_buffer_mode_init(edma_stream_type *edma_streamx, uint32_t memory1_addr, edma_memory_type current_memory)
+{
+  if(current_memory != EDMA_MEMORY_0)
+  {
+    edma_streamx->ctrl_bit.cm = 1;
+  }
+  else
+  {
+    edma_streamx->ctrl_bit.cm = 0;
+  }
+
+  edma_streamx->m1addr = memory1_addr;
+}
+
+/**
+  * @brief  enable or disable the double memory mode.
+  * @param  edma_streamx:
+  *         this parameter can be one of the following values:
+  *         - EDMA_STREAM1
+  *         - EDMA_STREAM2
+  *         - EDMA_STREAM3
+  *         - EDMA_STREAM4
+  *         - EDMA_STREAM5
+  *         - EDMA_STREAM6
+  *         - EDMA_STREAM7
+  *         - EDMA_STREAM8
+  * @param  new_state (TRUE or FALSE).
+  * @retval none.
+  */
+void edma_double_buffer_mode_enable(edma_stream_type *edma_streamx, confirm_state new_state)
+{
+  if(new_state != FALSE)
+  {
+    edma_streamx->ctrl_bit.dmm = 1;
+  }
+  else
+  {
+    edma_streamx->ctrl_bit.dmm = 0;
+  }
+}
+
+/**
+  * @brief  config the memory address in double buffer mode.
+  * @param  edma_streamx:
+  *         this parameter can be one of the following values:
+  *         - EDMA_STREAM1
+  *         - EDMA_STREAM2
+  *         - EDMA_STREAM3
+  *         - EDMA_STREAM4
+  *         - EDMA_STREAM5
+  *         - EDMA_STREAM6
+  *         - EDMA_STREAM7
+  *         - EDMA_STREAM8
+  * @param  memory_addr: the address of the buffer.
+  * @param  memory_target: indicates the which memory addr register will be config.
+  *         this parameter can be one of the following values:
+  *         - EDMA_MEMORY_0
+  *         - EDMA_MEMORY_1
+  * @retval none.
+  */
+void edma_memory_addr_set(edma_stream_type *edma_streamx, uint32_t memory_addr, uint32_t memory_target)
+{
+  if(memory_target != EDMA_MEMORY_0)
+  {
+    edma_streamx->m1addr = memory_addr;
+  }
+  else
+  {
+    edma_streamx->m0addr = memory_addr;
+  }
+}
+
+/**
+  * @brief  get the current memory target.
+  * @param  edma_streamx:
+  *         this parameter can be one of the following values:
+  *         - EDMA_STREAM1
+  *         - EDMA_STREAM2
+  *         - EDMA_STREAM3
+  *         - EDMA_STREAM4
+  *         - EDMA_STREAM5
+  *         - EDMA_STREAM6
+  *         - EDMA_STREAM7
+  *         - EDMA_STREAM8
+  * @retval the memory target
+  *         - EDMA_MEMORY_0
+  *         - EDMA_MEMORY_1
+  */
+edma_memory_type edma_memory_target_get(edma_stream_type *edma_streamx)
+{
+  return (edma_memory_type)(edma_streamx->ctrl_bit.cm);
+}
+
+/**
+  * @brief  get the enable status of edma streamx.
+  * @param  edma_streamx:
+  *         this parameter can be one of the following values:
+  *         - EDMA_STREAM1
+  *         - EDMA_STREAM2
+  *         - EDMA_STREAM3
+  *         - EDMA_STREAM4
+  *         - EDMA_STREAM5
+  *         - EDMA_STREAM6
+  *         - EDMA_STREAM7
+  *         - EDMA_STREAM8
+  * @retval current state of the edma streamx (SET or RESET).
+  */
+flag_status edma_stream_status_get(edma_stream_type *edma_streamx)
+{
+  if((edma_streamx->ctrl_bit.sen) != RESET)
+  {
+    return SET;
+  }
+  else
+  {
+    return RESET;
+  }
+}
+
+/**
+  * @brief  get the fifo level status.
+  * @param  edma_streamx:
+  *         this parameter can be one of the following values:
+  *         - EDMA_STREAM1
+  *         - EDMA_STREAM2
+  *         - EDMA_STREAM3
+  *         - EDMA_STREAM4
+  *         - EDMA_STREAM5
+  *         - EDMA_STREAM6
+  *         - EDMA_STREAM7
+  *         - EDMA_STREAM8
+  * @retval the fifo filling state.
+  *         - EDMA_FIFO_STATUS_LESS_1QUARTER: (0)   <  fifo level < (1/4).
+  *         - EDMA_FIFO_STATUS_1QUARTER:      (1/4) <= fifo level < (1/2) .
+  *         - EDMA_FIFO_STATUS_HALF:          (1/2) <= fifo level < (3/4).
+  *         - EDMA_FIFO_STATUS_3QUARTER:      (3/4) <= fifo level < (1).
+  *         - EDMA_FIFO_STATUS_EMPTY: fifo is empty.
+  *         - EDMA_FIFO_STATUS_FULL: fifo is full.
+  */
+uint8_t edma_fifo_status_get(edma_stream_type *edma_streamx)
+{
+  return (uint8_t)(edma_streamx->fctrl_bit.fsts);
+}
+
+/**
+  * @brief  get the edma flag.
+  * @param  edma_flag:
+  *         this parameter can be one of the following values:
+  *         - EDMA_FERR1_FLAG   - EDMA_DMERR1_FLAG  - EDMA_DTERR1_FLAG  - EDMA_HDT1_FLAG   - EDMA_FDT1_FLAG
+  *         - EDMA_FERR2_FLAG   - EDMA_DMERR2_FLAG  - EDMA_DTERR2_FLAG  - EDMA_HDT2_FLAG   - EDMA_FDT2_FLAG
+  *         - EDMA_FERR3_FLAG   - EDMA_DMERR3_FLAG  - EDMA_DTERR3_FLAG  - EDMA_HDT3_FLAG   - EDMA_FDT3_FLAG
+  *         - EDMA_FERR4_FLAG   - EDMA_DMERR4_FLAG  - EDMA_DTERR4_FLAG  - EDMA_HDT4_FLAG   - EDMA_FDT4_FLAG
+  *         - EDMA_FERR5_FLAG   - EDMA_DMERR5_FLAG  - EDMA_DTERR5_FLAG  - EDMA_HDT5_FLAG   - EDMA_FDT5_FLAG
+  *         - EDMA_FERR6_FLAG   - EDMA_DMERR6_FLAG  - EDMA_DTERR6_FLAG  - EDMA_HDT6_FLAG   - EDMA_FDT6_FLAG
+  *         - EDMA_FERR7_FLAG   - EDMA_DMERR7_FLAG  - EDMA_DTERR7_FLAG  - EDMA_HDT7_FLAG   - EDMA_FDT7_FLAG
+  *         - EDMA_FERR8_FLAG   - EDMA_DMERR8_FLAG  - EDMA_DTERR8_FLAG  - EDMA_HDT8_FLAG   - EDMA_FDT8_FLAG
+  * @retval the new state of edma flag (SET or RESET).
+  */
+flag_status edma_flag_get(uint32_t edma_flag)
+{
+  uint32_t status;
+
+  if(edma_flag > ((uint32_t)0x20000000))
+  {
+    status = EDMA->sts2;
+  }
+  else
+  {
+    status = EDMA->sts1;
+  }
+
+  if((status & edma_flag) != ((uint32_t)RESET))
+  {
+    return SET;
+  }
+  else
+  {
+    return RESET;
+  }
+}
+
+/**
+  * @brief  clear the edma flag.
+  * @param  edma_flag:
+  *         this parameter can be one of the following values:
+  *         - EDMA_FERR1_FLAG   - EDMA_DMERR1_FLAG  - EDMA_DTERR1_FLAG  - EDMA_HDT1_FLAG   - EDMA_FDT1_FLAG
+  *         - EDMA_FERR2_FLAG   - EDMA_DMERR2_FLAG  - EDMA_DTERR2_FLAG  - EDMA_HDT2_FLAG   - EDMA_FDT2_FLAG
+  *         - EDMA_FERR3_FLAG   - EDMA_DMERR3_FLAG  - EDMA_DTERR3_FLAG  - EDMA_HDT3_FLAG   - EDMA_FDT3_FLAG
+  *         - EDMA_FERR4_FLAG   - EDMA_DMERR4_FLAG  - EDMA_DTERR4_FLAG  - EDMA_HDT4_FLAG   - EDMA_FDT4_FLAG
+  *         - EDMA_FERR5_FLAG   - EDMA_DMERR5_FLAG  - EDMA_DTERR5_FLAG  - EDMA_HDT5_FLAG   - EDMA_FDT5_FLAG
+  *         - EDMA_FERR6_FLAG   - EDMA_DMERR6_FLAG  - EDMA_DTERR6_FLAG  - EDMA_HDT6_FLAG   - EDMA_FDT6_FLAG
+  *         - EDMA_FERR7_FLAG   - EDMA_DMERR7_FLAG  - EDMA_DTERR7_FLAG  - EDMA_HDT7_FLAG   - EDMA_FDT7_FLAG
+  *         - EDMA_FERR8_FLAG   - EDMA_DMERR8_FLAG  - EDMA_DTERR8_FLAG  - EDMA_HDT8_FLAG   - EDMA_FDT8_FLAG
+  * @retval none.
+  */
+void edma_flag_clear(uint32_t edma_flag)
+{
+  if(edma_flag > ((uint32_t)0x20000000))
+  {
+    EDMA->clr2 = (uint32_t)(edma_flag & 0x0FFFFFFF);
+  }
+  else
+  {
+    EDMA->clr1 = edma_flag;
+  }
+}
+
+/**
+  * @brief  initialize the edma 2d mode.
+  * @param  edma_streamx_2d:
+  *         this parameter can be one of the following values:
+  *         - EDMA_STREAM1_2D
+  *         - EDMA_STREAM2_2D
+  *         - EDMA_STREAM3_2D
+  *         - EDMA_STREAM4_2D
+  *         - EDMA_STREAM5_2D
+  *         - EDMA_STREAM6_2D
+  *         - EDMA_STREAM7_2D
+  *         - EDMA_STREAM8_2D
+  * @param  src_stride: source stride(-32768 ~ 32767).
+  * @param  dst_stride: destination stride(-32768 ~ 32767).
+  * @param  xcnt: x dimension transfer count(0x0000~ 0xFFFF).
+  * @param  ycnt: y dimension transfer count(0x0000~ 0xFFFF).
+  * @retval none.
+  */
+void edma_2d_init(edma_stream_2d_type *edma_streamx_2d, int16_t src_stride, int16_t dst_stride, uint16_t xcnt, uint16_t ycnt)
+{
+  edma_streamx_2d->s2dcnt = (uint32_t)((ycnt << 16) | (xcnt));
+
+  edma_streamx_2d->stride = (uint32_t)((dst_stride << 16) | (src_stride));
+}
+
+/**
+  * @brief  enable or disable the edma 2d mode.
+  * @param  edma_streamx_2d:
+  *         this parameter can be one of the following values:
+  *         - EDMA_STREAM1_2D
+  *         - EDMA_STREAM2_2D
+  *         - EDMA_STREAM3_2D
+  *         - EDMA_STREAM4_2D
+  *         - EDMA_STREAM5_2D
+  *         - EDMA_STREAM6_2D
+  *         - EDMA_STREAM7_2D
+  *         - EDMA_STREAM8_2D
+  * @param  new_state (TRUE or FALSE).
+  * @retval none.
+  */
+void edma_2d_enable(edma_stream_2d_type *edma_streamx_2d, confirm_state new_state)
+{
+  uint32_t offset;
+
+  offset = ((uint32_t)edma_streamx_2d - EDMA_STREAM1_2D_BASE) / 4;
+
+  if(new_state != FALSE)
+  {
+    EDMA->s2dctrl |= (uint16_t)0x0001 << offset;
+  }
+  else
+  {
+    EDMA->s2dctrl &= ~((uint16_t)0x0001 << offset);
+  }
+}
+
+/**
+  * @brief  initialize the edma link list.
+  * @param  edma_streamx_ll:
+  *         this parameter can be one of the following values:
+  *         - EDMA_STREAM1_LL
+  *         - EDMA_STREAM2_LL
+  *         - EDMA_STREAM3_LL
+  *         - EDMA_STREAM4_LL
+  *         - EDMA_STREAM5_LL
+  *         - EDMA_STREAM6_LL
+  *         - EDMA_STREAM7_LL
+  *         - EDMA_STREAM8_LL
+  * @param  pointer: link list pointer.
+  * @retval none.
+  */
+void edma_link_list_init(edma_stream_link_list_type *edma_streamx_ll, uint32_t pointer)
+{
+  edma_streamx_ll->llp = pointer;
+}
+
+/**
+  * @brief  enable or disable the edma stream link list mode.
+  * @param  edma_streamx_ll:
+  *         this parameter can be any combination of the following values:
+  *         - EDMA_STREAM1_LL
+  *         - EDMA_STREAM2_LL
+  *         - EDMA_STREAM3_LL
+  *         - EDMA_STREAM4_LL
+  *         - EDMA_STREAM5_LL
+  *         - EDMA_STREAM6_LL
+  *         - EDMA_STREAM7_LL
+  *         - EDMA_STREAM8_LL
+  * @param  new_state (TRUE or FALSE).
+  * @retval none.
+  */
+void edma_link_list_enable(edma_stream_link_list_type *edma_streamx_ll, confirm_state new_state)
+{
+  uint32_t offset;
+
+  offset = ((uint32_t)edma_streamx_ll - EDMA_STREAM1_LL_BASE) / 4;
+
+  if(new_state != FALSE)
+  {
+    EDMA->llctrl |= (uint16_t)0x0001 << offset;
+  }
+  else
+  {
+    EDMA->llctrl &= ~((uint16_t)0x0001 << offset);
+  }
+}
+
+/**
+  * @brief  enable or disable the edma edmamux.
+  * @param  new_state (TRUE or FALSE).
+  * @retval none.
+  */
+void edmamux_enable(confirm_state new_state)
+{
+  EDMA->muxsel_bit.tblsel = new_state;
+}
+
+/**
+  * @brief  edmamux init.
+  * @param  edmamux_channelx:
+  *         this parameter can be one of the following values:
+  *         - EDMAMUX_CHANNEL1
+  *         - EDMAMUX_CHANNEL2
+  *         - EDMAMUX_CHANNEL3
+  *         - EDMAMUX_CHANNEL4
+  *         - EDMAMUX_CHANNEL5
+  *         - EDMAMUX_CHANNEL6
+  *         - EDMAMUX_CHANNEL7
+  *         - EDMAMUX_CHANNEL8
+  * @param  edmamux_req_id:
+  *         this parameter can be one of the following values:
+  *         - EDMAMUX_DMAREQ_ID_REQ_G1       - EDMAMUX_DMAREQ_ID_REQ_G2       - EDMAMUX_DMAREQ_ID_REQ_G3       - EDMAMUX_DMAREQ_ID_REQ_G4
+  *         - EDMAMUX_DMAREQ_ID_ADC1         - EDMAMUX_DMAREQ_ID_ADC2         - EDMAMUX_DMAREQ_ID_ADC3         - EDMAMUX_DMAREQ_ID_DAC1
+  *         - EDMAMUX_DMAREQ_ID_DAC2         - EDMAMUX_DMAREQ_ID_TMR6_OVERFLOW- EDMAMUX_DMAREQ_ID_TMR7_OVERFLOW- EDMAMUX_DMAREQ_ID_SPI1_RX
+  *         - EDMAMUX_DMAREQ_ID_SPI1_TX      - EDMAMUX_DMAREQ_ID_SPI2_RX      - EDMAMUX_DMAREQ_ID_SPI2_TX      - EDMAMUX_DMAREQ_ID_SPI3_RX
+  *         - EDMAMUX_DMAREQ_ID_SPI3_TX      - EDMAMUX_DMAREQ_ID_SPI4_RX      - EDMAMUX_DMAREQ_ID_SPI4_TX      - EDMAMUX_DMAREQ_ID_I2S2_EXT_RX
+  *         - EDMAMUX_DMAREQ_ID_I2S2_EXT_TX  - EDMAMUX_DMAREQ_ID_I2S3_EXT_RX  - EDMAMUX_DMAREQ_ID_I2S3_EXT_TX  - EDMAMUX_DMAREQ_ID_I2C1_RX
+  *         - EDMAMUX_DMAREQ_ID_I2C1_TX      - EDMAMUX_DMAREQ_ID_I2C2_RX      - EDMAMUX_DMAREQ_ID_I2C2_TX      - EDMAMUX_DMAREQ_ID_I2C3_RX
+  *         - EDMAMUX_DMAREQ_ID_I2C3_TX      - EDMAMUX_DMAREQ_ID_USART1_RX    - EDMAMUX_DMAREQ_ID_USART1_TX    - EDMAMUX_DMAREQ_ID_USART2_RX
+  *         - EDMAMUX_DMAREQ_ID_USART2_TX    - EDMAMUX_DMAREQ_ID_USART3_RX    - EDMAMUX_DMAREQ_ID_USART3_TX    - EDMAMUX_DMAREQ_ID_UART4_RX
+  *         - EDMAMUX_DMAREQ_ID_UART4_TX     - EDMAMUX_DMAREQ_ID_UART5_RX     - EDMAMUX_DMAREQ_ID_UART5_TX     - EDMAMUX_DMAREQ_ID_USART6_RX
+  *         - EDMAMUX_DMAREQ_ID_USART6_TX    - EDMAMUX_DMAREQ_ID_UART7_RX     - EDMAMUX_DMAREQ_ID_UART7_TX     - EDMAMUX_DMAREQ_ID_UART8_RX
+  *         - EDMAMUX_DMAREQ_ID_UART8_TX     - EDMAMUX_DMAREQ_ID_SDIO1        - EDMAMUX_DMAREQ_ID_SDIO2        - EDMAMUX_DMAREQ_ID_QSPI1
+  *         - EDMAMUX_DMAREQ_ID_QSPI2        - EDMAMUX_DMAREQ_ID_TMR1_CH1     - EDMAMUX_DMAREQ_ID_TMR1_CH2     - EDMAMUX_DMAREQ_ID_TMR1_CH3
+  *         - EDMAMUX_DMAREQ_ID_TMR1_CH4     - EDMAMUX_DMAREQ_ID_TMR1_OVERFLOW- EDMAMUX_DMAREQ_ID_TMR1_TRIG    - EDMAMUX_DMAREQ_ID_TMR1_COM
+  *         - EDMAMUX_DMAREQ_ID_TMR8_CH1     - EDMAMUX_DMAREQ_ID_TMR8_CH2     - EDMAMUX_DMAREQ_ID_TMR8_CH3     - EDMAMUX_DMAREQ_ID_TMR8_CH4
+  *         - EDMAMUX_DMAREQ_ID_TMR8_UP      - EDMAMUX_DMAREQ_ID_TMR8_TRIG    - EDMAMUX_DMAREQ_ID_TMR8_COM     - EDMAMUX_DMAREQ_ID_TMR2_CH1
+  *         - EDMAMUX_DMAREQ_ID_TMR2_CH2     - EDMAMUX_DMAREQ_ID_TMR2_CH3     - EDMAMUX_DMAREQ_ID_TMR2_CH4     - EDMAMUX_DMAREQ_ID_TMR2_OVERFLOW
+  *         - EDMAMUX_DMAREQ_ID_TMR2_TRIG    - EDMAMUX_DMAREQ_ID_TMR3_CH1     - EDMAMUX_DMAREQ_ID_TMR3_CH2     - EDMAMUX_DMAREQ_ID_TMR3_CH3
+  *         - EDMAMUX_DMAREQ_ID_TMR3_CH4     - EDMAMUX_DMAREQ_ID_TMR3_OVERFLOW- EDMAMUX_DMAREQ_ID_TMR3_TRIG    - EDMAMUX_DMAREQ_ID_TMR4_CH1
+  *         - EDMAMUX_DMAREQ_ID_TMR4_CH2     - EDMAMUX_DMAREQ_ID_TMR4_CH3     - EDMAMUX_DMAREQ_ID_TMR4_CH4     - EDMAMUX_DMAREQ_ID_TMR4_OVERFLOW
+  *         - EDMAMUX_DMAREQ_ID_TMR4_TRIG    - EDMAMUX_DMAREQ_ID_TMR5_CH1     - EDMAMUX_DMAREQ_ID_TMR5_CH2     - EDMAMUX_DMAREQ_ID_TMR5_CH3
+  *         - EDMAMUX_DMAREQ_ID_TMR5_CH4     - EDMAMUX_DMAREQ_ID_TMR5_OVERFLOW- EDMAMUX_DMAREQ_ID_TMR5_TRIG    - EDMAMUX_DMAREQ_ID_TMR20_CH1
+  *         - EDMAMUX_DMAREQ_ID_TMR20_CH2    - EDMAMUX_DMAREQ_ID_TMR20_CH3    - EDMAMUX_DMAREQ_ID_TMR20_CH4    - EDMAMUX_DMAREQ_ID_TMR20_OVERFLOW
+  *         - EDMAMUX_DMAREQ_ID_TMR20_TRIG   - EDMAMUX_DMAREQ_ID_TMR20_HALL   - EDMAMUX_DMAREQ_ID_DVP
+  * @retval none.
+  */
+void edmamux_init(edmamux_channel_type *edmamux_channelx, edmamux_requst_id_sel_type edmamux_req_id)
+{
+  edmamux_channelx->muxctrl_bit.reqsel = edmamux_req_id;
+}
+
+/**
+  * @brief  edmamux sync init struct config with its default value.
+  * @param  edmamux_sync_init_struct: pointer to a edmamux_sync_init_type structure which will be initialized.
+  * @retval none.
+  */
+void edmamux_sync_default_para_init(edmamux_sync_init_type *edmamux_sync_init_struct)
+{
+  edmamux_sync_init_struct->sync_enable = FALSE;
+  edmamux_sync_init_struct->sync_event_enable = FALSE;
+  edmamux_sync_init_struct->sync_polarity = EDMAMUX_SYNC_POLARITY_DISABLE;
+  edmamux_sync_init_struct->sync_request_number = 0x0;
+  edmamux_sync_init_struct->sync_signal_sel = EDMAMUX_SYNC_ID_EXINT0;
+}
+
+/**
+  * @brief  edmamux synchronization config.
+  * @param  edmamux_channelx:
+  *         this parameter can be one of the following values:
+  *         - EDMAMUX_CHANNEL1
+  *         - EDMAMUX_CHANNEL2
+  *         - EDMAMUX_CHANNEL3
+  *         - EDMAMUX_CHANNEL4
+  *         - EDMAMUX_CHANNEL5
+  *         - EDMAMUX_CHANNEL6
+  *         - EDMAMUX_CHANNEL7
+  *         - EDMAMUX_CHANNEL8
+  * @param  edmamux_sync_init_struct: ointer to a edmamux_sync_init_type structure.
+  * @retval none.
+  */
+void edmamux_sync_config(edmamux_channel_type *edmamux_channelx, edmamux_sync_init_type *edmamux_sync_init_struct)
+{
+  edmamux_channelx->muxctrl_bit.syncsel = edmamux_sync_init_struct->sync_signal_sel;
+  edmamux_channelx->muxctrl_bit.syncpol = edmamux_sync_init_struct->sync_polarity;
+  edmamux_channelx->muxctrl_bit.reqcnt  = edmamux_sync_init_struct->sync_request_number;
+  edmamux_channelx->muxctrl_bit.evtgen  = edmamux_sync_init_struct->sync_event_enable;
+  edmamux_channelx->muxctrl_bit.syncen  = edmamux_sync_init_struct->sync_enable;
+}
+
+/**
+  * @brief  edmamux request generator init struct config with its default value.
+  * @param  edmamux_gen_init_struct: pointer to a edmamux_gen_init_type structure which will be initialized.
+  * @retval none.
+  */
+void edmamux_generator_default_para_init(edmamux_gen_init_type *edmamux_gen_init_struct)
+{
+  edmamux_gen_init_struct->gen_enable         = FALSE;
+  edmamux_gen_init_struct->gen_polarity       = EDMAMUX_GEN_POLARITY_DISABLE;
+  edmamux_gen_init_struct->gen_request_number = 0x0;
+  edmamux_gen_init_struct->gen_signal_sel     = EDMAMUX_GEN_ID_EXINT0;
+}
+
+/**
+  * @brief  edmamux request generator init.
+  * @param  edmamux_gen_init_struct: pointer to a edmamux_gen_init_type structure which will be initialized.
+  * @retval none.
+  */
+void edmamux_generator_config(edmamux_generator_type *edmamux_gen_x, edmamux_gen_init_type *edmamux_gen_init_struct)
+{
+  edmamux_gen_x->gctrl_bit.sigsel  = edmamux_gen_init_struct->gen_signal_sel;
+  edmamux_gen_x->gctrl_bit.gpol    = edmamux_gen_init_struct->gen_polarity;
+  edmamux_gen_x->gctrl_bit.greqcnt = edmamux_gen_init_struct->gen_request_number;
+  edmamux_gen_x->gctrl_bit.gen     = edmamux_gen_init_struct->gen_enable;
+}
+
+/**
+  * @brief  enable or disable the edmamux sync interrupts.
+  * @param  edmamux_channelx:
+  *         this parameter can be one of the following values:
+  *         - EDMAMUX_CHANNEL1
+  *         - EDMAMUX_CHANNEL2
+  *         - EDMAMUX_CHANNEL3
+  *         - EDMAMUX_CHANNEL4
+  *         - EDMAMUX_CHANNEL5
+  *         - EDMAMUX_CHANNEL6
+  *         - EDMAMUX_CHANNEL7
+  *         - EDMAMUX_CHANNEL8
+  * @param  new_state (TRUE or FALSE).
+  * @retval none.
+  */
+void edmamux_sync_interrupt_enable(edmamux_channel_type *edmamux_channelx, confirm_state new_state)
+{
+  if(new_state != FALSE)
+  {
+    edmamux_channelx->muxctrl_bit.syncovien = TRUE;
+  }
+  else
+  {
+    edmamux_channelx->muxctrl_bit.syncovien = FALSE;
+  }
+}
+
+/**
+  * @brief  enable or disable the edmamux request generator interrupts.
+  * @param  edmamux_gen_x: pointer to a edmamux_generator_type structure.
+  *         this parameter can be one of the following values:
+  *         - EDMAMUX_GENERATOR1
+  *         - EDMAMUX_GENERATOR2
+  *         - EDMAMUX_GENERATOR3
+  *         - EDMAMUX_GENERATOR4
+  * @param  new_state (TRUE or FALSE).
+  * @retval none.
+  */
+void edmamux_generator_interrupt_enable(edmamux_generator_type *edmamux_gen_x, confirm_state new_state)
+{
+  if(new_state != FALSE)
+  {
+    edmamux_gen_x->gctrl_bit.trgovien = TRUE;
+  }
+  else
+  {
+    edmamux_gen_x->gctrl_bit.trgovien = FALSE;
+  }
+}
+
+/**
+  * @brief  edmamux sync flag get.
+  * @param  flag
+  *         this parameter can be any combination of the following values:
+  *         - EDMAMUX_SYNC_OV1_FLAG
+  *         - EDMAMUX_SYNC_OV2_FLAG
+  *         - EDMAMUX_SYNC_OV3_FLAG
+  *         - EDMAMUX_SYNC_OV4_FLAG
+  *         - EDMAMUX_SYNC_OV5_FLAG
+  *         - EDMAMUX_SYNC_OV6_FLAG
+  *         - EDMAMUX_SYNC_OV7_FLAG
+  *         - EDMAMUX_SYNC_OV8_FLAG
+  * @retval state of edmamux sync flag.
+  */
+flag_status edmamux_sync_flag_get(uint32_t flag)
+{
+  if((EDMA->muxsyncsts & flag) != RESET)
+  {
+    return SET;
+  }
+  else
+  {
+    return RESET;
+  }
+}
+
+/**
+  * @brief  edmamux sync flag clear.
+  * @param  flag
+  *         this parameter can be any combination of the following values:
+  *         - EDMAMUX_SYNC_OV1_FLAG
+  *         - EDMAMUX_SYNC_OV2_FLAG
+  *         - EDMAMUX_SYNC_OV3_FLAG
+  *         - EDMAMUX_SYNC_OV4_FLAG
+  *         - EDMAMUX_SYNC_OV5_FLAG
+  *         - EDMAMUX_SYNC_OV6_FLAG
+  *         - EDMAMUX_SYNC_OV7_FLAG
+  *         - EDMAMUX_SYNC_OV8_FLAG
+  * @retval none.
+  */
+void edmamux_sync_flag_clear(uint32_t flag)
+{
+  EDMA->muxsyncclr = flag;
+}
+
+/**
+  * @brief  edmamux request generator flag get.
+  * @param  flag
+  *         this parameter can be any combination of the following values:
+  *         - EDMAMUX_GEN_TRIG_OV1_FLAG
+  *         - EDMAMUX_GEN_TRIG_OV2_FLAG
+  *         - EDMAMUX_GEN_TRIG_OV3_FLAG
+  *         - EDMAMUX_GEN_TRIG_OV4_FLAG
+  * @retval state of edmamux sync flag.
+  */
+flag_status edmamux_generator_flag_get(uint32_t flag)
+{
+  if((EDMA->muxgsts & flag) != RESET)
+  {
+    return SET;
+  }
+  else
+  {
+    return RESET;
+  }
+}
+
+/**
+  * @brief  edmamux request generator flag clear.
+  * @param  flag
+  *         this parameter can be any combination of the following values:
+  *         - EDMAMUX_GEN_TRIG_OV1_FLAG
+  *         - EDMAMUX_GEN_TRIG_OV2_FLAG
+  *         - EDMAMUX_GEN_TRIG_OV3_FLAG
+  *         - EDMAMUX_GEN_TRIG_OV4_FLAG
+  * @retval none.
+  */
+void edmamux_generator_flag_clear(uint32_t flag)
+{
+  EDMA->muxgclr = flag;
+}
+
+/**
+  * @}
+  */
+
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */

lib/main/AT32F43x/Drivers/AT32F43x_StdPeriph_Driver/src/at32f435_437_exint.c

@@ -0,0 +1,236 @@
+/**
+  **************************************************************************
+  * @file     at32f435_437_exint.c
+  * @version  v2.1.0
+  * @date     2022-08-16
+  * @brief    contains all the functions for the exint firmware library
+  **************************************************************************
+  *                       Copyright notice & Disclaimer
+  *
+  * The software Board Support Package (BSP) that is made available to
+  * download from Artery official website is the copyrighted work of Artery.
+  * Artery authorizes customers to use, copy, and distribute the BSP
+  * software and its related documentation for the purpose of design and
+  * development in conjunction with Artery microcontrollers. Use of the
+  * software is governed by this copyright notice and the following disclaimer.
+  *
+  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+  *
+  **************************************************************************
+  */
+
+#include "at32f435_437_conf.h"
+
+/** @addtogroup AT32F435_437_periph_driver
+  * @{
+  */
+
+/** @defgroup EXINT
+  * @brief EXINT driver modules
+  * @{
+  */
+
+#ifdef EXINT_MODULE_ENABLED
+
+/** @defgroup EXINT_private_functions
+  * @{
+  */
+
+/**
+  * @brief  exint reset
+  * @param  none
+  * @retval none
+  */
+void exint_reset(void)
+{
+  EXINT->inten = 0x00000000;
+  EXINT->polcfg1 = 0x00000000;
+  EXINT->polcfg2 = 0x00000000;
+  EXINT->evten = 0x00000000;
+  EXINT->intsts = 0x007FFFFF;
+}
+
+/**
+  * @brief  exint default para init
+  * @param  exint_struct
+  *         - to the structure of exint_init_type
+  * @retval none
+  */
+void exint_default_para_init(exint_init_type *exint_struct)
+{
+  exint_struct->line_enable = FALSE;
+  exint_struct->line_select = EXINT_LINE_NONE;
+  exint_struct->line_polarity = EXINT_TRIGGER_FALLING_EDGE;
+  exint_struct->line_mode = EXINT_LINE_EVENT;
+}
+
+/**
+  * @brief  exint init
+  * @param  exint_struct
+  *         - to the structure of exint_init_type
+  * @retval none
+  */
+void exint_init(exint_init_type *exint_struct)
+{
+  uint32_t line_index = 0;
+  line_index = exint_struct->line_select;
+
+  EXINT->inten &= ~line_index;
+  EXINT->evten &= ~line_index;
+
+  if(exint_struct->line_enable != FALSE)
+  {
+    if(exint_struct->line_mode == EXINT_LINE_INTERRUPUT)
+    {
+      EXINT->inten |= line_index;
+    }
+    else
+    {
+      EXINT->evten |= line_index;
+    }
+
+    EXINT->polcfg1 &= ~line_index;
+    EXINT->polcfg2 &= ~line_index;
+    if(exint_struct->line_polarity == EXINT_TRIGGER_RISING_EDGE)
+    {
+      EXINT->polcfg1 |= line_index;
+    }
+    else if(exint_struct->line_polarity == EXINT_TRIGGER_FALLING_EDGE)
+    {
+      EXINT->polcfg2 |= line_index;
+    }
+    else
+    {
+      EXINT->polcfg1 |= line_index;
+      EXINT->polcfg2 |= line_index;
+    }
+  }
+}
+
+/**
+  * @brief  clear exint flag
+  * @param  exint_line
+  *         this parameter can be any combination of the following values:
+  *         - EXINT_LINE_0
+  *         - EXINT_LINE_1
+  *         ...
+  *         - EXINT_LINE_21
+  *         - EXINT_LINE_22
+  * @retval none
+  */
+void exint_flag_clear(uint32_t exint_line)
+{
+  EXINT->intsts = exint_line;
+}
+
+/**
+  * @brief  get exint flag
+  * @param  exint_line
+  *         this parameter can be one of the following values:
+  *         - EXINT_LINE_0
+  *         - EXINT_LINE_1
+  *         ...
+  *         - EXINT_LINE_21
+  *         - EXINT_LINE_22
+  * @retval the new state of exint flag(SET or RESET).
+  */
+flag_status exint_flag_get(uint32_t exint_line)
+{
+  flag_status status = RESET;
+  uint32_t exint_flag =0;
+  exint_flag = EXINT->intsts & exint_line;
+  if((exint_flag != (uint16_t)RESET))
+  {
+    status = SET;
+  }
+  else
+  {
+    status = RESET;
+  }
+  return status;
+}
+
+/**
+  * @brief  generate exint software interrupt event
+  * @param  exint_line
+  *         this parameter can be one of the following values:
+  *         - EXINT_LINE_0
+  *         - EXINT_LINE_1
+  *         ...
+  *         - EXINT_LINE_21
+  *         - EXINT_LINE_22
+  * @retval none
+  */
+void exint_software_interrupt_event_generate(uint32_t exint_line)
+{
+  EXINT->swtrg |= exint_line;
+}
+
+/**
+  * @brief  enable or disable exint interrupt
+  * @param  exint_line
+  *         this parameter can be any combination of the following values:
+  *         - EXINT_LINE_0
+  *         - EXINT_LINE_1
+  *         ...
+  *         - EXINT_LINE_21
+  *         - EXINT_LINE_22
+  * @param  new_state: new state of exint interrupt.
+  *         this parameter can be: TRUE or FALSE.
+  * @retval none
+  */
+void exint_interrupt_enable(uint32_t exint_line, confirm_state new_state)
+{
+  if(new_state == TRUE)
+  {
+    EXINT->inten |= exint_line;
+  }
+  else
+  {
+    EXINT->inten &= ~exint_line;
+  }
+}
+
+/**
+  * @brief  enable or disable exint event
+  * @param  exint_line
+  *         this parameter can be any combination of the following values:
+  *         - EXINT_LINE_0
+  *         - EXINT_LINE_1
+  *         ...
+  *         - EXINT_LINE_21
+  *         - EXINT_LINE_22
+  * @param  new_state: new state of exint event.
+  *         this parameter can be: TRUE or FALSE.
+  * @retval none
+  */
+void exint_event_enable(uint32_t exint_line, confirm_state new_state)
+{
+  if(new_state == TRUE)
+  {
+    EXINT->evten |= exint_line;
+  }
+  else
+  {
+    EXINT->evten &= ~exint_line;
+  }
+}
+
+/**
+  * @}
+  */
+
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */

lib/main/AT32F43x/Drivers/AT32F43x_StdPeriph_Driver/src/at32f435_437_gpio.c

@@ -0,0 +1,523 @@
+/**
+  **************************************************************************
+  * @file     at32f435_437_gpio.c
+  * @version  v2.1.0
+  * @date     2022-08-16
+  * @brief    contains all the functions for the gpio firmware library
+  **************************************************************************
+  *                       Copyright notice & Disclaimer
+  *
+  * The software Board Support Package (BSP) that is made available to
+  * download from Artery official website is the copyrighted work of Artery.
+  * Artery authorizes customers to use, copy, and distribute the BSP
+  * software and its related documentation for the purpose of design and
+  * development in conjunction with Artery microcontrollers. Use of the
+  * software is governed by this copyright notice and the following disclaimer.
+  *
+  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+  *
+  **************************************************************************
+  */
+
+#include "at32f435_437_conf.h"
+
+/** @addtogroup AT32F435_437_periph_driver
+  * @{
+  */
+
+/** @defgroup GPIO
+  * @brief GPIO driver modules
+  * @{
+  */
+
+#ifdef GPIO_MODULE_ENABLED
+
+/** @defgroup GPIO_private_functions
+  * @{
+  */
+
+/**
+  * @brief  reset the gpio register
+  * @param  gpio_x: to select the gpio peripheral.
+  *         this parameter can be one of the following values:
+  *         GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH.
+  * @retval none
+  */
+void gpio_reset(gpio_type *gpio_x)
+{
+  if(gpio_x == GPIOA)
+  {
+    crm_periph_reset(CRM_GPIOA_PERIPH_RESET, TRUE);
+    crm_periph_reset(CRM_GPIOA_PERIPH_RESET, FALSE);
+  }
+  else if(gpio_x == GPIOB)
+  {
+    crm_periph_reset(CRM_GPIOB_PERIPH_RESET, TRUE);
+    crm_periph_reset(CRM_GPIOB_PERIPH_RESET, FALSE);
+  }
+  else if(gpio_x == GPIOC)
+  {
+    crm_periph_reset(CRM_GPIOC_PERIPH_RESET, TRUE);
+    crm_periph_reset(CRM_GPIOC_PERIPH_RESET, FALSE);
+  }
+  else if(gpio_x == GPIOD)
+  {
+    crm_periph_reset(CRM_GPIOD_PERIPH_RESET, TRUE);
+    crm_periph_reset(CRM_GPIOD_PERIPH_RESET, FALSE);
+  }
+  else if(gpio_x == GPIOE)
+  {
+    crm_periph_reset(CRM_GPIOE_PERIPH_RESET, TRUE);
+    crm_periph_reset(CRM_GPIOE_PERIPH_RESET, FALSE);
+  }
+  else if(gpio_x == GPIOF)
+  {
+    crm_periph_reset(CRM_GPIOF_PERIPH_RESET, TRUE);
+    crm_periph_reset(CRM_GPIOF_PERIPH_RESET, FALSE);
+  }
+  else if(gpio_x == GPIOG)
+  {
+    crm_periph_reset(CRM_GPIOG_PERIPH_RESET, TRUE);
+    crm_periph_reset(CRM_GPIOG_PERIPH_RESET, FALSE);
+  }
+  else if(gpio_x == GPIOH)
+  {
+    crm_periph_reset(CRM_GPIOH_PERIPH_RESET, TRUE);
+    crm_periph_reset(CRM_GPIOH_PERIPH_RESET, FALSE);
+  }
+}
+
+/**
+  * @brief  initialize the gpio peripheral.
+  * @param  gpio_x: to select the gpio peripheral.
+  *         this parameter can be one of the following values:
+  *         GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH.
+  * @param  gpio_init_struct: pointer to gpio init structure.
+  * @retval none
+  */
+void gpio_init(gpio_type *gpio_x, gpio_init_type *gpio_init_struct)
+{
+  uint16_t pinx_value, pin_index = 0;
+
+  pinx_value = (uint16_t)gpio_init_struct->gpio_pins;
+
+  while(pinx_value > 0)
+  {
+    if(pinx_value & 0x01)
+    {
+      gpio_x->cfgr  &= (uint32_t)~(0x03 << (pin_index * 2));
+      gpio_x->cfgr  |= (uint32_t)(gpio_init_struct->gpio_mode << (pin_index * 2));
+
+      gpio_x->omode &= (uint32_t)~(0x01 << (pin_index));
+      gpio_x->omode |= (uint32_t)(gpio_init_struct->gpio_out_type << (pin_index));
+
+      gpio_x->odrvr &= (uint32_t)~(0x03 << (pin_index * 2));
+      gpio_x->odrvr |= (uint32_t)(gpio_init_struct->gpio_drive_strength << (pin_index * 2));
+
+      gpio_x->pull  &= (uint32_t)~(0x03 << (pin_index * 2));
+      gpio_x->pull  |= (uint32_t)(gpio_init_struct->gpio_pull << (pin_index * 2));
+    }
+    pinx_value >>= 1;
+    pin_index++;
+  }
+}
+
+/**
+  * @brief  fill each gpio_init_type member with its default value.
+  * @param  gpio_init_struct : pointer to a gpio_init_type structure which will be initialized.
+  * @retval none
+  */
+void gpio_default_para_init(gpio_init_type *gpio_init_struct)
+{
+  /* reset gpio init structure parameters values */
+  gpio_init_struct->gpio_pins  = GPIO_PINS_ALL;
+  gpio_init_struct->gpio_mode = GPIO_MODE_INPUT;
+  gpio_init_struct->gpio_out_type = GPIO_OUTPUT_PUSH_PULL;
+  gpio_init_struct->gpio_pull = GPIO_PULL_NONE;
+  gpio_init_struct->gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
+}
+
+/**
+  * @brief  read the specified input port pin.
+  * @param  gpio_x: to select the gpio peripheral.
+  *         this parameter can be one of the following values:
+  *         GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH.
+  * @param  pins: gpio pin number
+  *         this parameter can be one of the following values:
+  *         - GPIO_PINS_0
+  *         - GPIO_PINS_1
+  *         - GPIO_PINS_2
+  *         - GPIO_PINS_3
+  *         - GPIO_PINS_4
+  *         - GPIO_PINS_5
+  *         - GPIO_PINS_6
+  *         - GPIO_PINS_7
+  *         - GPIO_PINS_8
+  *         - GPIO_PINS_9
+  *         - GPIO_PINS_10
+  *         - GPIO_PINS_11
+  *         - GPIO_PINS_12
+  *         - GPIO_PINS_13
+  *         - GPIO_PINS_14
+  *         - GPIO_PINS_15
+  * @retval flag_status (SET or RESET)
+  */
+flag_status gpio_input_data_bit_read(gpio_type *gpio_x, uint16_t pins)
+{
+  flag_status status = RESET;
+
+  if(pins != (pins & gpio_x->idt))
+  {
+    status = RESET;
+  }
+  else
+  {
+    status = SET;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  read the specified gpio input data port.
+  * @param  gpio_x: to select the gpio peripheral.
+  *         this parameter can be one of the following values:
+  *         GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH.
+  * @retval gpio input data port value.
+  */
+uint16_t gpio_input_data_read(gpio_type *gpio_x)
+{
+  return ((uint16_t)(gpio_x->idt));
+}
+
+/**
+  * @brief  read the specified output port pin.
+  * @param  gpio_x: to select the gpio peripheral.
+  *         this parameter can be one of the following values:
+  *         GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH.
+  * @param  pins: gpio pin number
+  *         this parameter can be one of the following values:
+  *         - GPIO_PINS_0
+  *         - GPIO_PINS_1
+  *         - GPIO_PINS_2
+  *         - GPIO_PINS_3
+  *         - GPIO_PINS_4
+  *         - GPIO_PINS_5
+  *         - GPIO_PINS_6
+  *         - GPIO_PINS_7
+  *         - GPIO_PINS_8
+  *         - GPIO_PINS_9
+  *         - GPIO_PINS_10
+  *         - GPIO_PINS_11
+  *         - GPIO_PINS_12
+  *         - GPIO_PINS_13
+  *         - GPIO_PINS_14
+  *         - GPIO_PINS_15
+  * @retval flag_status (SET or RESET)
+  */
+flag_status gpio_output_data_bit_read(gpio_type *gpio_x, uint16_t pins)
+{
+  flag_status status = RESET;
+
+  if((gpio_x->odt & pins) != RESET)
+  {
+    status = SET;
+  }
+  else
+  {
+    status = RESET;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  read the specified gpio ouput data port.
+  * @param  gpio_x: to select the gpio peripheral.
+  *         this parameter can be one of the following values:
+  *         GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH.
+  * @retval gpio input data port value.
+  */
+uint16_t gpio_output_data_read(gpio_type *gpio_x)
+{
+  return ((uint16_t)(gpio_x->odt));
+}
+
+/**
+  * @brief  set the selected data port bits.
+  * @param  gpio_x: to select the gpio peripheral.
+  *         this parameter can be one of the following values:
+  *         GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH.
+  * @param  pins: gpio pin number
+  *         parameter can be any combination of gpio_pin_x, gpio_pin_x as following values:
+  *         - GPIO_PINS_0
+  *         - GPIO_PINS_1
+  *         - GPIO_PINS_2
+  *         - GPIO_PINS_3
+  *         - GPIO_PINS_4
+  *         - GPIO_PINS_5
+  *         - GPIO_PINS_6
+  *         - GPIO_PINS_7
+  *         - GPIO_PINS_8
+  *         - GPIO_PINS_9
+  *         - GPIO_PINS_10
+  *         - GPIO_PINS_11
+  *         - GPIO_PINS_12
+  *         - GPIO_PINS_13
+  *         - GPIO_PINS_14
+  *         - GPIO_PINS_15
+  *         - GPIO_PINS_ALL
+  * @retval none
+  */
+void gpio_bits_set(gpio_type *gpio_x, uint16_t pins)
+{
+  gpio_x->scr = pins;
+}
+
+/**
+  * @brief  clear the selected data port bits.
+  * @param  gpio_x: to select the gpio peripheral.
+  *         this parameter can be one of the following values:
+  *         GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH.
+  * @param  pins: gpio pin number
+  *         parameter can be any combination of gpio_pin_x, gpio_pin_x as following values:
+  *         - GPIO_PINS_0
+  *         - GPIO_PINS_1
+  *         - GPIO_PINS_2
+  *         - GPIO_PINS_3
+  *         - GPIO_PINS_4
+  *         - GPIO_PINS_5
+  *         - GPIO_PINS_6
+  *         - GPIO_PINS_7
+  *         - GPIO_PINS_8
+  *         - GPIO_PINS_9
+  *         - GPIO_PINS_10
+  *         - GPIO_PINS_11
+  *         - GPIO_PINS_12
+  *         - GPIO_PINS_13
+  *         - GPIO_PINS_14
+  *         - GPIO_PINS_15
+  *         - GPIO_PINS_ALL
+  * @retval none
+  */
+void gpio_bits_reset(gpio_type *gpio_x, uint16_t pins)
+{
+  gpio_x->clr = pins;
+}
+
+/**
+  * @brief  set or clear the selected data port bit.
+  * @param  gpio_x: to select the gpio peripheral.
+  *         this parameter can be one of the following values:
+  *         GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH.
+  * @param  pins: gpio pin number
+  *         parameter can be any combination of gpio_pin_x, gpio_pin_x as following values:
+  *         - GPIO_PINS_0
+  *         - GPIO_PINS_1
+  *         - GPIO_PINS_2
+  *         - GPIO_PINS_3
+  *         - GPIO_PINS_4
+  *         - GPIO_PINS_5
+  *         - GPIO_PINS_6
+  *         - GPIO_PINS_7
+  *         - GPIO_PINS_8
+  *         - GPIO_PINS_9
+  *         - GPIO_PINS_10
+  *         - GPIO_PINS_11
+  *         - GPIO_PINS_12
+  *         - GPIO_PINS_13
+  *         - GPIO_PINS_14
+  *         - GPIO_PINS_15
+  *         - GPIO_PINS_ALL
+  * @param  bit_state: specifies the value to be written to the selected bit (TRUE or FALSE).
+  * @retval none
+  */
+void gpio_bits_write(gpio_type *gpio_x, uint16_t pins, confirm_state bit_state)
+{
+  if(bit_state != FALSE)
+  {
+    gpio_x->scr = pins;
+  }
+  else
+  {
+    gpio_x->clr = pins;
+  }
+}
+
+/**
+  * @brief  write data to the specified gpio data port.
+  * @param  gpio_x: to select the gpio peripheral.
+  *         this parameter can be one of the following values:
+  *         GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH.
+  * @param  port_value: specifies the value to be written to the port output data register.
+  * @retval none
+  */
+void gpio_port_write(gpio_type *gpio_x, uint16_t port_value)
+{
+  gpio_x->odt = port_value;
+}
+
+/**
+  * @brief  write protect gpio pins configuration registers.
+  * @param  gpio_x: to select the gpio peripheral.
+  *         this parameter can be one of the following values:
+  *         GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH.
+  * @param  pins: gpio pin number
+  *         this parameter can be any combination of the following:
+  *         - GPIO_PINS_0
+  *         - GPIO_PINS_1
+  *         - GPIO_PINS_2
+  *         - GPIO_PINS_3
+  *         - GPIO_PINS_4
+  *         - GPIO_PINS_5
+  *         - GPIO_PINS_6
+  *         - GPIO_PINS_7
+  *         - GPIO_PINS_8
+  *         - GPIO_PINS_9
+  *         - GPIO_PINS_10
+  *         - GPIO_PINS_11
+  *         - GPIO_PINS_12
+  *         - GPIO_PINS_13
+  *         - GPIO_PINS_14
+  *         - GPIO_PINS_15
+  *         - GPIO_PINS_ALL
+  * @retval none
+  */
+void gpio_pin_wp_config(gpio_type *gpio_x, uint16_t pins)
+{
+  uint32_t temp = 0x00010000;
+
+  temp |= pins;
+  /* set wpen bit */
+  gpio_x->wpr = temp;
+  /* reset wpen bit */
+  gpio_x->wpr =  pins;
+  /* set wpen bit */
+  gpio_x->wpr = temp;
+  /* read wpen bit*/
+  temp = gpio_x->wpr;
+  /* read wpen bit*/
+  temp = gpio_x->wpr;
+}
+
+/**
+  * @brief  enable or disable gpio pins huge driven.
+  * @param  gpio_x: to select the gpio peripheral.
+  *         this parameter can be one of the following values:
+  *         GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH.
+  * @param  pins: gpio pin number
+  *         parameter can be any combination of gpio_pin_x, gpio_pin_x as following values:
+  *         - GPIO_PINS_0
+  *         - GPIO_PINS_1
+  *         - GPIO_PINS_2
+  *         - GPIO_PINS_3
+  *         - GPIO_PINS_4
+  *         - GPIO_PINS_5
+  *         - GPIO_PINS_6
+  *         - GPIO_PINS_7
+  *         - GPIO_PINS_8
+  *         - GPIO_PINS_9
+  *         - GPIO_PINS_10
+  *         - GPIO_PINS_11
+  *         - GPIO_PINS_12
+  *         - GPIO_PINS_13
+  *         - GPIO_PINS_14
+  *         - GPIO_PINS_15
+  *         - GPIO_PINS_ALL
+  * @param  new_state: new state of the slew rate.
+  *         this parameter can be: true or false.
+  * @retval none
+  */
+void gpio_pins_huge_driven_config(gpio_type *gpio_x, uint16_t pins, confirm_state new_state)
+{
+  if(new_state != FALSE)
+  {
+    gpio_x->hdrv |= pins;
+  }
+  else
+  {
+    gpio_x->hdrv &= ~pins;
+  }
+}
+
+/**
+  * @brief  configure the pin's muxing function.
+  * @param  gpio_x: to select the gpio peripheral.
+  *         this parameter can be one of the following values:
+  *         GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH.
+  * @param  gpio_pin_source: specifies the pin for the muxing function.
+  *         this parameter can be one of the following values:
+  *         - GPIO_PINS_SOURCE0
+  *         - GPIO_PINS_SOURCE1
+  *         - GPIO_PINS_SOURCE2
+  *         - GPIO_PINS_SOURCE3
+  *         - GPIO_PINS_SOURCE4
+  *         - GPIO_PINS_SOURCE5
+  *         - GPIO_PINS_SOURCE6
+  *         - GPIO_PINS_SOURCE7
+  *         - GPIO_PINS_SOURCE8
+  *         - GPIO_PINS_SOURCE9
+  *         - GPIO_PINS_SOURCE10
+  *         - GPIO_PINS_SOURCE11
+  *         - GPIO_PINS_SOURCE12
+  *         - GPIO_PINS_SOURCE13
+  *         - GPIO_PINS_SOURCE14
+  *         - GPIO_PINS_SOURCE15
+  * @param  gpio_mux: select the pin to used as muxing function.
+  *         this parameter can be one of the following values:
+  *         - GPIO_MUX_0
+  *         - GPIO_MUX_1
+  *         - GPIO_MUX_2
+  *         - GPIO_MUX_3
+  *         - GPIO_MUX_4
+  *         - GPIO_MUX_5
+  *         - GPIO_MUX_6
+  *         - GPIO_MUX_7
+  *         - GPIO_MUX_8
+  *         - GPIO_MUX_9
+  *         - GPIO_MUX_10
+  *         - GPIO_MUX_11
+  *         - GPIO_MUX_12
+  *         - GPIO_MUX_13
+  *         - GPIO_MUX_14
+  *         - GPIO_MUX_15
+  * @retval none
+  */
+void gpio_pin_mux_config(gpio_type *gpio_x, gpio_pins_source_type gpio_pin_source, gpio_mux_sel_type gpio_mux)
+{
+  uint32_t temp = 0x00;
+  uint32_t temp_2 = 0x00;
+
+  temp = ((uint32_t)(gpio_mux) << ((uint32_t)((uint32_t)gpio_pin_source & (uint32_t)0x07) * 4));
+  if(gpio_pin_source >> 0x03)
+  {
+    gpio_x->muxh &= ~((uint32_t)0xF << ((uint32_t)((uint32_t)gpio_pin_source & (uint32_t)0x07) * 4));
+    temp_2 = gpio_x->muxh | temp;
+    gpio_x->muxh = temp_2;
+  }
+  else
+  {
+    gpio_x->muxl &= ~((uint32_t)0xF << ((uint32_t)((uint32_t)gpio_pin_source & (uint32_t)0x07) * 4));
+    temp_2 = gpio_x->muxl | temp;
+    gpio_x->muxl = temp_2;
+  }
+}
+
+/**
+  * @}
+  */
+
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */

lib/main/AT32F43x/Drivers/AT32F43x_StdPeriph_Driver/src/at32f435_437_i2c.c

@@ -0,0 +1,748 @@
+/**
+  **************************************************************************
+  * @file     at32f435_437_i2c.c
+  * @version  v2.1.0
+  * @date     2022-08-16
+  * @brief    contains all the functions for the i2c firmware library
+  **************************************************************************
+  *                       Copyright notice & Disclaimer
+  *
+  * The software Board Support Package (BSP) that is made available to
+  * download from Artery official website is the copyrighted work of Artery.
+  * Artery authorizes customers to use, copy, and distribute the BSP
+  * software and its related documentation for the purpose of design and
+  * development in conjunction with Artery microcontrollers. Use of the
+  * software is governed by this copyright notice and the following disclaimer.
+  *
+  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+  *
+  **************************************************************************
+  */
+
+#include "at32f435_437_conf.h"
+
+/** @addtogroup AT32F435_437_periph_driver
+  * @{
+  */
+
+/** @defgroup I2C
+  * @brief I2C driver modules
+  * @{
+  */
+
+#ifdef I2C_MODULE_ENABLED
+
+/** @defgroup I2C_private_functions
+  * @{
+  */
+
+/**
+  * @brief  reset the i2c register
+  * @param  i2c_x: to select the i2c peripheral.
+  *         this parameter can be one of the following values:
+  *         I2C1, I2C2, I2C3.
+  * @retval none
+  */
+void i2c_reset(i2c_type *i2c_x)
+{
+  if(i2c_x == I2C1)
+  {
+    crm_periph_reset(CRM_I2C1_PERIPH_RESET, TRUE);
+    crm_periph_reset(CRM_I2C1_PERIPH_RESET, FALSE);
+  }
+  else if(i2c_x == I2C2)
+  {
+    crm_periph_reset(CRM_I2C2_PERIPH_RESET, TRUE);
+    crm_periph_reset(CRM_I2C2_PERIPH_RESET, FALSE);
+  }
+  else if(i2c_x == I2C3)
+  {
+    crm_periph_reset(CRM_I2C3_PERIPH_RESET, TRUE);
+    crm_periph_reset(CRM_I2C3_PERIPH_RESET, FALSE);
+  }
+}
+
+/**
+  * @brief  init i2c digit filters and clock control register.
+  * @param  i2c_x: to select the i2c peripheral.
+  *         this parameter can be one of the following values:
+  *         I2C1, I2C2, I2C3.
+  * @param  dfilters: number of digit filters (0x00~0x0F).
+  * @param  clk: i2c clock control register (0x00000000~0xFFFFFFFF).
+  * @retval none
+  */
+void i2c_init(i2c_type *i2c_x, uint8_t dfilters, uint32_t clk)
+{
+  /* disable i2c peripheral */
+  i2c_x->ctrl1_bit.i2cen = FALSE;
+
+  /* write clkctrl register*/
+  i2c_x->clkctrl = clk;
+
+  /* write digital filter register*/
+  i2c_x->ctrl1_bit.dflt = dfilters;
+}
+
+/**
+  * @brief  config i2c own address 1.
+  * @param  i2c_x: to select the i2c peripheral.
+  *         this parameter can be one of the following values:
+  *         I2C1, I2C2, I2C3.
+  * @param  mode: i2c address mode.
+  *         this parameter can be one of the following values:
+  *         - I2C_ADDRESS_MODE_7BIT: 7bit address.
+  *         - I2C_ADDRESS_MODE_10BIT: 10bit address.
+  * @param  address: own address 1, such as 0xB0.
+  * @retval none
+  */
+void i2c_own_address1_set(i2c_type *i2c_x, i2c_address_mode_type mode, uint16_t address)
+{
+  /* config address mode */
+  i2c_x->oaddr1_bit.addr1mode = mode;
+
+  /* config address */
+  i2c_x->oaddr1_bit.addr1 = address & 0x03FF;
+
+  /* enable address */
+  i2c_x->oaddr1_bit.addr1en = TRUE;
+}
+
+/**
+  * @brief  config i2c own address 2 and mask.
+  * @param  i2c_x: to select the i2c peripheral.
+  *         this parameter can be one of the following values:
+  *         I2C1, I2C2, I2C3.
+  * @param  address: own address 1, such as 0xC0.
+  * @param  mask: own address 2 mask.
+  *         this parameter can be one of the following values:
+  *         - I2C_ADDR2_NOMASK: compare bit      [7:1].
+  *         - I2C_ADDR2_MASK01: only compare bit [7:2].
+  *         - I2C_ADDR2_MASK02: only compare bit [7:2].
+  *         - I2C_ADDR2_MASK03: only compare bit [7:3].
+  *         - I2C_ADDR2_MASK04: only compare bit [7:4].
+  *         - I2C_ADDR2_MASK05: only compare bit [7:5].
+  *         - I2C_ADDR2_MASK06: only compare bit [7:6].
+  *         - I2C_ADDR2_MASK07: only compare bit [7].
+  * @retval none
+  */
+void i2c_own_address2_set(i2c_type *i2c_x, uint8_t address, i2c_addr2_mask_type mask)
+{
+  i2c_x->oaddr2_bit.addr2mask = mask;
+
+  i2c_x->oaddr2_bit.addr2 = (address >> 1) & 0x7F;
+}
+
+/**
+  * @brief  enable or disable own address 2.
+  * @param  i2c_x: to select the i2c peripheral.
+  *         this parameter can be one of the following values:
+  *         I2C1, I2C2, I2C3.
+  * @param  new_state (TRUE or FALSE).
+  * @retval none
+  */
+void i2c_own_address2_enable(i2c_type *i2c_x, confirm_state new_state)
+{
+  i2c_x->oaddr2_bit.addr2en = new_state;
+}
+
+/**
+  * @brief  enable or disable smbus mode.
+  * @param  i2c_x: to select the i2c peripheral.
+  *         this parameter can be one of the following values:
+  *         I2C1, I2C2, I2C3.
+  * @param  mode: smbus device mode.
+  *         this parameter can be one of the following values:
+  *         - I2C_SMBUS_MODE_DEVICE: smbus device.
+  *         - I2C_SMBUS_MODE_HOST: smbus host.
+  * @param  new_state (TRUE or FALSE).
+  * @retval none
+  */
+void i2c_smbus_enable(i2c_type *i2c_x, i2c_smbus_mode_type mode, confirm_state new_state)
+{
+  switch (mode)
+  {
+    case I2C_SMBUS_MODE_DEVICE:
+      i2c_x->ctrl1_bit.devaddren = new_state;
+      break;
+    case I2C_SMBUS_MODE_HOST:
+       i2c_x->ctrl1_bit.haddren = new_state;
+      break;
+    default:
+      break;
+  }
+}
+
+/**
+  * @brief  enable or disable peripheral.
+  * @param  i2c_x: to select the i2c peripheral.
+  *         this parameter can be one of the following values:
+  *         I2C1, I2C2, I2C3.
+  * @param  new_state (TRUE or FALSE).
+  * @retval none
+  */
+void i2c_enable(i2c_type *i2c_x, confirm_state new_state)
+{
+  i2c_x->ctrl1_bit.i2cen = new_state;
+}
+
+/**
+  * @brief  enable or disable clock stretch.
+  * @param  i2c_x: to select the i2c peripheral.
+  *         this parameter can be one of the following values:
+  *         I2C1, I2C2, I2C3.
+  * @param  new_state (TRUE or FALSE).
+  * @retval none
+  */
+void i2c_clock_stretch_enable(i2c_type *i2c_x, confirm_state new_state)
+{
+  i2c_x->ctrl1_bit.stretch = (!new_state);
+}
+
+/**
+  * @brief  enable or disable ack.
+  * @param  i2c_x: to select the i2c peripheral.
+  *         this parameter can be one of the following values:
+  *         I2C1, I2C2, I2C3.
+  * @param  new_state (TRUE or FALSE).
+  * @retval none.
+  */
+void i2c_ack_enable(i2c_type *i2c_x, confirm_state new_state)
+{
+  i2c_x->ctrl2_bit.nacken  = (!new_state);
+}
+
+/**
+  * @brief  enable or disable 10-bit address mode (master transfer).
+  * @param  i2c_x: to select the i2c peripheral.
+  *         this parameter can be one of the following values:
+  *         I2C1, I2C2, I2C3.
+  * @param  new_state (TRUE or FALSE).
+  * @retval none
+  */
+void i2c_addr10_mode_enable(i2c_type *i2c_x, confirm_state new_state)
+{
+  i2c_x->ctrl2_bit.addr10 = new_state;
+}
+
+/**
+  * @brief  config the slave address to be transmitted.
+  * @param  i2c_x: to select the i2c peripheral.
+  *         this parameter can be one of the following values:
+  *         I2C1, I2C2, I2C3.
+  * @param  address: slave address.
+  * @retval none
+  */
+void i2c_transfer_addr_set(i2c_type *i2c_x, uint16_t address)
+{
+  i2c_x->ctrl2_bit.saddr = address & 0x03FF;
+}
+
+/**
+  * @brief  get the slave address to be transmitted.
+  * @param  i2c_x: to select the i2c peripheral.
+  *         this parameter can be one of the following values:
+  *         I2C1, I2C2, I2C3.
+  * @retval slave address
+  */
+uint16_t i2c_transfer_addr_get(i2c_type *i2c_x)
+{
+  return i2c_x->ctrl2_bit.saddr;
+}
+
+/**
+  * @brief  config the master transfer direction.
+  * @param  i2c_x: to select the i2c peripheral.
+  *         this parameter can be one of the following values:
+  *         I2C1, I2C2, I2C3.
+  * @param  i2c_direction: transfer request direction.
+  *         this parameter can be one of the following values:
+  *         - I2C_DIR_TRANSMIT: master request a write transfer.
+  *         - I2C_DIR_RECEIVE: master request a read transfer.
+  * @retval none
+  */
+void i2c_transfer_dir_set(i2c_type *i2c_x, i2c_transfer_dir_type i2c_direction)
+{
+  i2c_x->ctrl2_bit.dir = i2c_direction;
+}
+
+/**
+  * @brief  slave get the i2c transfer direction.
+  * @param  i2c_x: to select the i2c peripheral.
+  *         this parameter can be one of the following values:
+  *         I2C1, I2C2, I2C3.
+  * @retval the value of the slave direction
+  *         - I2C_DIR_TRANSMIT: master request a write transfer, slave enters receiver mode.
+  *         - I2C_DIR_RECEIVE: master request a read transfer, slave enters transmitter mode.
+  */
+i2c_transfer_dir_type i2c_transfer_dir_get(i2c_type *i2c_x)
+{
+  if (i2c_x->sts_bit.sdir == 0)
+  {
+    return I2C_DIR_TRANSMIT;
+  }
+  else
+  {
+    return I2C_DIR_RECEIVE;
+  }
+}
+
+/**
+  * @brief  get the i2c slave matched address.
+  * @param  i2c_x: to select the i2c peripheral.
+  *         this parameter can be one of the following values:
+  *         I2C1, I2C2, I2C3.
+  * @retval slave matched address.
+  */
+uint8_t i2c_matched_addr_get(i2c_type *i2c_x)
+{
+  return (i2c_x->sts_bit.addr << 1);
+}
+
+/**
+  * @brief  enable or disable auto send stop mode.
+  * @param  i2c_x: to select the i2c peripheral.
+  *         this parameter can be one of the following values:
+  *         I2C1, I2C2, I2C3.
+  * @param  new_state (TRUE or FALSE).
+  * @retval none
+  */
+void i2c_auto_stop_enable(i2c_type *i2c_x, confirm_state new_state)
+{
+  i2c_x->ctrl2_bit.astopen = new_state;
+}
+
+/**
+  * @brief  enable or disable cnt reload mode.
+  * @param  i2c_x: to select the i2c peripheral.
+  *         this parameter can be one of the following values:
+  *         I2C1, I2C2, I2C3.
+  * @param  new_state (TRUE or FALSE).
+  * @retval none
+  */
+void i2c_reload_enable(i2c_type *i2c_x, confirm_state new_state)
+{
+  i2c_x->ctrl2_bit.rlden = new_state;
+}
+
+/**
+  * @brief  config the transfer cnt .
+  * @param  i2c_x: to select the i2c peripheral.
+  *         this parameter can be one of the following values:
+  *         I2C1, I2C2, I2C3.
+  * @param  cnt: transfer cnt.
+  * @retval none
+  */
+void i2c_cnt_set(i2c_type *i2c_x, uint8_t cnt)
+{
+  i2c_x->ctrl2_bit.cnt = cnt;
+}
+
+/**
+  * @brief  enable or disable read 10-bit header, this mode
+  *         only used in 10-bit address mode read.
+  * @param  i2c_x: to select the i2c peripheral.
+  *         this parameter can be one of the following values:
+  *         I2C1, I2C2, I2C3.
+  * @param  new_state (TRUE or FALSE).
+  * @retval none
+  */
+void i2c_addr10_header_enable(i2c_type *i2c_x, confirm_state new_state)
+{
+  i2c_x->ctrl2_bit.readh10 = new_state;
+}
+
+/**
+  * @brief  enable or disable general call mode.
+  * @param  i2c_x: to select the i2c peripheral.
+  *         this parameter can be one of the following values:
+  *         I2C1, I2C2, I2C3.
+  * @param  new_state (TRUE or FALSE).
+  * @retval none
+  */
+void i2c_general_call_enable(i2c_type *i2c_x, confirm_state new_state)
+{
+  i2c_x->ctrl1_bit.gcaen = new_state;
+}
+
+/**
+  * @brief  drives the smbus alert pin high or low.
+  * @param  i2c_x: to select the i2c peripheral.
+  *         this parameter can be one of the following values:
+  *         I2C1, I2C2, I2C3.
+  * @param  level
+  *         this parameter can be one of the following values:
+  *         - I2C_SMBUS_ALERT_LOW: smbus alert set low.
+  *         - I2C_SMBUS_ALERT_HIGH: smbus alert set high.
+  * @retval none
+  */
+void i2c_smbus_alert_set(i2c_type *i2c_x, i2c_smbus_alert_set_type level)
+{
+  i2c_x->ctrl1_bit.smbalert = level;
+}
+
+/**
+  * @brief  enable or disable slave data control.
+  * @param  i2c_x: to select the i2c peripheral.
+  *         this parameter can be one of the following values:
+  *         I2C1, I2C2, I2C3.
+  * @param  new_state (TRUE or FALSE).
+  * @retval none
+  */
+void i2c_slave_data_ctrl_enable(i2c_type *i2c_x, confirm_state new_state)
+{
+  i2c_x->ctrl1_bit.sctrl = new_state;
+}
+
+/**
+  * @brief  enable or disable pec calculate.
+  * @param  i2c_x: to select the i2c peripheral.
+  *         this parameter can be one of the following values:
+  *         I2C1, I2C2, I2C3.
+  * @param  new_state (TRUE or FALSE).
+  * @retval none
+  */
+void i2c_pec_calculate_enable(i2c_type *i2c_x, confirm_state new_state)
+{
+  i2c_x->ctrl1_bit.pecen = new_state;
+}
+
+/**
+  * @brief  enable or disable pec transfer.
+  * @param  i2c_x: to select the i2c peripheral.
+  *         this parameter can be one of the following values:
+  *         I2C1, I2C2, I2C3.
+  * @param  new_state (TRUE or FALSE).
+  * @retval none
+  */
+void i2c_pec_transmit_enable(i2c_type *i2c_x, confirm_state new_state)
+{
+  i2c_x->ctrl2_bit.pecten = new_state;
+}
+
+/**
+  * @brief  get the i2c pec value.
+  * @param  i2c_x: to select the i2c peripheral.
+  *         this parameter can be one of the following values:
+  *         I2C1, I2C2, I2C3.
+  * @retval the value of the pec.
+  */
+uint8_t i2c_pec_value_get(i2c_type *i2c_x)
+{
+  return (uint8_t)(i2c_x->pec_bit.pecval);
+}
+
+/**
+  * @brief  config the i2c bus timeout.
+  * @param  i2c_x: to select the i2c peripheral.
+  *         this parameter can be one of the following values:
+  *         I2C1, I2C2, I2C3.
+  * @param  timeout: timeout (0x0000~0x0FFF).
+  * @retval none
+  */
+void i2c_timeout_set(i2c_type *i2c_x, uint16_t timeout)
+{
+  i2c_x->timeout_bit.totime = timeout;
+}
+
+/**
+  * @brief  config the bus timeout detcet level.
+  * @param  i2c_x: to select the i2c peripheral.
+  *         this parameter can be one of the following values:
+  *         I2C1, I2C2, I2C3.
+  * @param  level
+  *         this parameter can be one of the following values:
+  *         - I2C_TIMEOUT_DETCET_HIGH: detect high level timeout.
+  *         - I2C_TIMEOUT_DETCET_LOW: detect low level timeout.
+  * @retval none
+  */
+void i2c_timeout_detcet_set(i2c_type *i2c_x, i2c_timeout_detcet_type mode)
+{
+  i2c_x->timeout_bit.tomode = mode;
+}
+
+/**
+  * @brief  enable or disable bus timeout.
+  * @param  i2c_x: to select the i2c peripheral.
+  *         this parameter can be one of the following values:
+  *         I2C1, I2C2, I2C3.
+  * @param  new_state (TRUE or FALSE).
+  * @retval none
+  */
+void i2c_timeout_enable(i2c_type *i2c_x, confirm_state new_state)
+{
+  i2c_x->timeout_bit.toen = new_state;
+}
+
+/**
+  * @brief  config the i2c extend bus timeout.
+  * @param  i2c_x: to select the i2c peripheral.
+  *         this parameter can be one of the following values:
+  *         I2C1, I2C2, I2C3.
+  * @param  timeout: extend timeout (0x0000~0x0FFF).
+  * @retval none
+  */
+void i2c_ext_timeout_set(i2c_type *i2c_x, uint16_t timeout)
+{
+  i2c_x->timeout_bit.exttime = timeout;
+}
+
+/**
+  * @brief  enable or disable extend bus timeout.
+  * @param  i2c_x: to select the i2c peripheral.
+  *         this parameter can be one of the following values:
+  *         I2C1, I2C2, I2C3.
+  * @param  new_state (TRUE or FALSE).
+  * @retval none
+  */
+void i2c_ext_timeout_enable(i2c_type *i2c_x, confirm_state new_state)
+{
+  i2c_x->timeout_bit.exten = new_state;
+}
+
+/**
+  * @brief  enable or disable interrupts.
+  * @param  i2c_x: to select the i2c peripheral.
+  *         this parameter can be one of the following values:
+  *         I2C1, I2C2, I2C3.
+  * @param  i2c_int: interrupts sources.
+  *         this parameter can be one of the following values:
+  *         - I2C_TD_INT: transmit data interrupt.
+  *         - I2C_RD_INT: receive data interrupt.
+  *         - I2C_ADDR_INT: address match interrupt.
+  *         - I2C_ACKFIAL_INT: ack fail interrupt.
+  *         - I2C_STOP_INT: stop detect interrupt.
+  *         - I2C_TDC_INT:  transmit data complete interrupt.
+  *         - I2C_ERR_INT: bus error interrupt.
+  * @param  new_state (TRUE or FALSE).
+  * @retval none
+  */
+void i2c_interrupt_enable(i2c_type *i2c_x, uint32_t source, confirm_state new_state)
+{
+  if (new_state != FALSE)
+  {
+    i2c_x->ctrl1 |= source;
+  }
+  else
+  {
+    i2c_x->ctrl1 &= (uint32_t)~source;
+  }
+}
+
+/**
+  * @brief  get interrupt status
+  * @param  i2c_x: to select the i2c peripheral.
+  *         this parameter can be one of the following values:
+  *         I2C1, I2C2, I2C3.
+  * @param  source
+  *         this parameter can be one of the following values:
+  *         - I2C_TD_INT: transmit data interrupt.
+  *         - I2C_RD_INT: receive data interrupt.
+  *         - I2C_ADDR_INT: address match interrupt.
+  *         - I2C_ACKFIAL_INT: ack fail interrupt.
+  *         - I2C_STOP_INT: stop detect interrupt.
+  *         - I2C_TDC_INT:  transmit data complete interrupt.
+  *         - I2C_ERR_INT: bus error interrupt.
+  * @retval flag_status (SET or RESET)
+  */
+flag_status i2c_interrupt_get(i2c_type *i2c_x, uint16_t source)
+{
+  if((i2c_x->ctrl1 & source) != RESET)
+  {
+    return SET;
+  }
+  else
+  {
+    return RESET;
+  }
+}
+
+/**
+  * @brief  enable or disable dma requests.
+  * @param  i2c_x: to select the i2c peripheral.
+  *         this parameter can be one of the following values:
+  *         I2C1, I2C2, I2C3.
+  * @param  dma_req: dma transfer request.
+  *         this parameter can be one of the following values:
+  *         - I2C_DMA_REQUEST_TX: dma transmit request.
+  *         - I2C_DMA_REQUEST_RX: dma receive request.
+  * @param  new_state (TRUE or FALSE).
+  * @retval none
+  */
+void i2c_dma_enable(i2c_type *i2c_x, i2c_dma_request_type dma_req, confirm_state new_state)
+{
+  if(dma_req == I2C_DMA_REQUEST_TX)
+  {
+    i2c_x->ctrl1_bit.dmaten = new_state;
+  }
+  else
+  {
+    i2c_x->ctrl1_bit.dmaren = new_state;
+  }
+}
+
+/**
+  * @brief  config data transfer.
+  * @param  i2c_x: to select the i2c peripheral.
+  *         this parameter can be one of the following values:
+  *         I2C1, I2C2, I2C3.
+  * @param  address: slave address.
+  * @param  cnt: transfer conuter(0~255)
+  * @param  rld_stop: config reload and gen stop condition mode.
+  *         this parameter can be one of the following values:
+  *         - I2C_AUTO_STOP_MODE: auto generate stop mode.
+  *         - I2C_SOFT_STOP_MODE: soft generate stop mode.
+  *         - I2C_RELOAD_MODE:  reload mode.
+  * @param  start: config gen start condition mode.
+  *         this parameter can be one of the following values:
+  *         - I2C_WITHOUT_START: transfer data without start condition.
+  *         - I2C_GEN_START_READ: read data and generate start.
+  *         - I2C_GEN_START_WRITE: send data and generate start.
+  * @retval none
+  */
+void i2c_transmit_set(i2c_type *i2c_x, uint16_t address, uint8_t cnt, i2c_reload_stop_mode_type rld_stop, i2c_start_mode_type start)
+{
+  uint32_t temp;
+
+  /* copy ctrl2 value to temp */
+  temp = i2c_x->ctrl2;
+
+  /* clear ctrl2_bit specific bits */
+  temp &= ~0x03FF67FF;
+
+  /* transfer mode and address set */
+  temp |= address | rld_stop | start;
+
+  /* transfer counter set */
+  temp |= (uint32_t)cnt << 16;
+
+  /* update ctrl2 value */
+  i2c_x->ctrl2 = temp;
+}
+
+/**
+  * @brief  generate start condition.
+  * @param  i2c_x: to select the i2c peripheral.
+  *         this parameter can be one of the following values:
+  *         I2C1, I2C2, I2C3.
+  * @retval none
+  */
+void i2c_start_generate(i2c_type *i2c_x)
+{
+  i2c_x->ctrl2_bit.genstart = TRUE;
+}
+
+/**
+  * @brief  generate stop condition.
+  * @param  i2c_x: to select the i2c peripheral.
+  *         this parameter can be one of the following values:
+  *         I2C1, I2C2, I2C3.
+  * @retval none
+  */
+void i2c_stop_generate(i2c_type *i2c_x)
+{
+  i2c_x->ctrl2_bit.genstop = TRUE;
+}
+
+/**
+  * @brief  send a byte through the i2c periph.
+  * @param  i2c_x: to select the i2c peripheral.
+  *         this parameter can be one of the following values:
+  *         I2C1, I2C2, I2C3.
+  * @param  data: byte to be transmitted.
+  * @retval none
+  */
+void i2c_data_send(i2c_type *i2c_x, uint8_t data)
+{
+  i2c_x->txdt = data;
+}
+
+/**
+  * @brief  receive a byte through the i2c periph.
+  * @param  i2c_x: to select the i2c peripheral.
+  *         this parameter can be one of the following values:
+  *         I2C1, I2C2, I2C3.
+  * @retval the value of the received data.
+  */
+uint8_t i2c_data_receive(i2c_type *i2c_x)
+{
+  return (uint8_t)i2c_x->rxdt;
+}
+
+/**
+  * @brief  get flag status.
+  * @param  i2c_x: to select the i2c peripheral.
+  *         this parameter can be one of the following values:
+  *         I2C1, I2C2, I2C3.
+  * @param  flag: specifies the flag to check.
+  *         this parameter can be one of the following values:
+  *         - I2C_TDBE_FLAG: transmit data buffer empty flag.
+  *         - I2C_TDIS_FLAG: send interrupt status.
+  *         - I2C_RDBF_FLAG: receive data buffer full flag.
+  *         - I2C_ADDRF_FLAG: 0~7 bit address match flag.
+  *         - I2C_ACKFAIL_FLAG: acknowledge failure flag.
+  *         - I2C_STOPF_FLAG: stop condition generation complete flag.
+  *         - I2C_TDC_FLAG: transmit data complete flag.
+  *         - I2C_TCRLD_FLAG: transmission is complete, waiting to load data.
+  *         - I2C_BUSERR_FLAG: bus error flag.
+  *         - I2C_ARLOST_FLAG: arbitration lost flag.
+  *         - I2C_OUF_FLAG: overflow or underflow flag.
+  *         - I2C_PECERR_FLAG: pec receive error flag.
+  *         - I2C_TMOUT_FLAG: smbus timeout flag.
+  *         - I2C_ALERTF_FLAG: smbus alert flag.
+  *         - I2C_BUSYF_FLAG: bus busy flag transmission mode.
+  *         - I2C_SDIR_FLAG: slave data transmit direction.
+  * @retval the new state of flag (SET or RESET).
+  */
+flag_status i2c_flag_get(i2c_type *i2c_x, uint32_t flag)
+{
+  if((i2c_x->sts & flag) != RESET)
+  {
+    return SET;
+  }
+  else
+  {
+    return RESET;
+  }
+}
+
+/**
+  * @brief  clear flag status
+  * @param  i2c_x: to select the i2c peripheral.
+  *         this parameter can be one of the following values:
+  *         I2C1, I2C2, I2C3.
+  * @param  flag: specifies the flag to clear.
+  *         this parameter can be any combination of the following values:
+  *         - I2C_ADDRF_FLAG: 0~7 bit address match flag.
+  *         - I2C_ACKFAIL_FLAG: acknowledge failure flag.
+  *         - I2C_STOPF_FLAG: stop condition generation complete flag.
+  *         - I2C_BUSERR_FLAG: bus error flag.
+  *         - I2C_ARLOST_FLAG: arbitration lost flag.
+  *         - I2C_OUF_FLAG: overflow or underflow flag.
+  *         - I2C_PECERR_FLAG: pec receive error flag.
+  *         - I2C_TMOUT_FLAG: smbus timeout flag.
+  *         - I2C_ALERTF_FLAG: smbus alert flag.
+  * @retval none
+  */
+void i2c_flag_clear(i2c_type *i2c_x, uint32_t flag)
+{
+  i2c_x->clr = flag;
+}
+
+/**
+  * @}
+  */
+
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */

lib/main/AT32F43x/Drivers/AT32F43x_StdPeriph_Driver/src/at32f435_437_misc.c

@@ -0,0 +1,173 @@
+/**
+  **************************************************************************
+  * @file     at32f435_437_misc.c
+  * @version  v2.1.0
+  * @date     2022-08-16
+  * @brief    contains all the functions for the misc firmware library
+  **************************************************************************
+  *                       Copyright notice & Disclaimer
+  *
+  * The software Board Support Package (BSP) that is made available to
+  * download from Artery official website is the copyrighted work of Artery.
+  * Artery authorizes customers to use, copy, and distribute the BSP
+  * software and its related documentation for the purpose of design and
+  * development in conjunction with Artery microcontrollers. Use of the
+  * software is governed by this copyright notice and the following disclaimer.
+  *
+  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+  *
+  **************************************************************************
+  */
+
+/* includes ------------------------------------------------------------------*/
+#include "at32f435_437_conf.h"
+
+/** @addtogroup AT32F435_437_periph_driver
+  * @{
+  */
+
+/** @defgroup MISC
+  * @brief MISC driver modules
+  * @{
+  */
+
+#ifdef MISC_MODULE_ENABLED
+
+/** @defgroup MISC_private_functions
+  * @{
+  */
+
+#define AIRCR_VECTKEY_MASK    ((uint32_t)0x05FA0000)
+
+/**
+  * @brief  system reset
+  * @param  none
+  * @retval none
+  */
+void nvic_system_reset(void)
+{
+  NVIC_SystemReset();
+}
+
+/**
+  * @brief  enable nvic irq
+  * @param  irqn (IRQn_Type number)
+  * @param  preempt_priority: preemptive priority value (starting from 0)
+  * @param  sub_priority: subpriority value (starting from 0)
+  * @retval none
+  */
+void nvic_irq_enable(IRQn_Type irqn, uint32_t preempt_priority, uint32_t sub_priority)
+{
+  uint32_t temp_priority = 0;
+
+  /* encode priority */
+  temp_priority = NVIC_EncodePriority(NVIC_GetPriorityGrouping(), preempt_priority, sub_priority);
+  /* set priority */
+  NVIC_SetPriority(irqn, temp_priority);
+  /* enable irqn */
+  NVIC_EnableIRQ(irqn);
+}
+
+/**
+  * @brief  disable nvic irq number
+  * @param  irqn (IRQn_Type number)
+  * @retval none
+  */
+void nvic_irq_disable(IRQn_Type irqn)
+{
+  NVIC_DisableIRQ(irqn);
+}
+
+/**
+  * @brief  config nvic priority group
+  * @param  priority_group
+  *         this parameter can be one of the following values:
+  *         - NVIC_PRIORITY_GROUP_0
+  *         - NVIC_PRIORITY_GROUP_1
+  *         - NVIC_PRIORITY_GROUP_2
+  *         - NVIC_PRIORITY_GROUP_3
+  *         - NVIC_PRIORITY_GROUP_4
+  * @retval none
+  */
+void nvic_priority_group_config(nvic_priority_group_type priority_group)
+{
+  /* set the prigroup[10:8] bits according to nvic_prioritygroup value */
+  NVIC_SetPriorityGrouping(priority_group);
+}
+
+/**
+  * @brief  set the vector table location and offset.
+  * @param  base
+  *         this parameter can be one of the following values:
+  *         - NVIC_VECTTAB_RAM
+  *         - NVIC_VECTTAB_FLASH
+  * @param  offset (vector table base offset field. this value must be a multiple of 0x200)
+  * @retval none
+  */
+void nvic_vector_table_set(uint32_t base, uint32_t offset)
+{
+  SCB->VTOR = base | (offset & (uint32_t)0x1FFFFF80);
+}
+
+/**
+  * @brief  config nvic lowpower mode
+  * @param  lp_mode
+  *         this parameter can be one of the following values:
+  *         - NVIC_LP_SEVONPEND
+  *         - NVIC_LP_SLEEPDEEP
+  *         - NVIC_LP_SLEEPONEXIT
+  * @param  new_state (new state of lp condition. ENABLE or DISABLE)
+  * @retval none
+  */
+void nvic_lowpower_mode_config(nvic_lowpower_mode_type lp_mode, confirm_state new_state)
+{
+  if(new_state != FALSE)
+  {
+    SCB->SCR |= lp_mode;
+  }
+  else
+  {
+    SCB->SCR &= (uint32_t)(~(uint32_t)lp_mode);
+  }
+}
+
+/**
+  * @brief  config systick clock source
+  * @param  source
+  *         this parameter can be one of the following values:
+  *         - SYSTICK_CLOCK_SOURCE_AHBCLK_DIV8
+  *         - SYSTICK_CLOCK_SOURCE_AHBCLK_NODIV
+  * @retval none
+  */
+void systick_clock_source_config(systick_clock_source_type source)
+{
+  if(source == SYSTICK_CLOCK_SOURCE_AHBCLK_NODIV)
+  {
+    SysTick->CTRL |= SYSTICK_CLOCK_SOURCE_AHBCLK_NODIV;
+  }
+  else
+  {
+    SysTick->CTRL &= ~(uint32_t)SYSTICK_CLOCK_SOURCE_AHBCLK_NODIV;
+  }
+}
+
+/**
+  * @}
+  */
+
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+

lib/main/AT32F43x/Drivers/AT32F43x_StdPeriph_Driver/src/at32f435_437_pwc.c

@@ -0,0 +1,250 @@
+/**
+  **************************************************************************
+  * @file     at32f435_437_pwc.c
+  * @version  v2.1.0
+  * @date     2022-08-16
+  * @brief    contains all the functions for the pwc firmware library
+  **************************************************************************
+  *                       Copyright notice & Disclaimer
+  *
+  * The software Board Support Package (BSP) that is made available to
+  * download from Artery official website is the copyrighted work of Artery.
+  * Artery authorizes customers to use, copy, and distribute the BSP
+  * software and its related documentation for the purpose of design and
+  * development in conjunction with Artery microcontrollers. Use of the
+  * software is governed by this copyright notice and the following disclaimer.
+  *
+  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+  *
+  **************************************************************************
+  */
+
+#include "at32f435_437_conf.h"
+
+/** @addtogroup AT32F435_437_periph_driver
+  * @{
+  */
+
+/** @defgroup PWC
+  * @brief PWC driver modules
+  * @{
+  */
+
+#ifdef PWC_MODULE_ENABLED
+
+/** @defgroup PWC_private_functions
+  * @{
+  */
+
+/**
+  * @brief  deinitialize the pwc peripheral registers to their default reset values.
+  * @param  none
+  * @retval none
+  */
+void pwc_reset(void)
+{
+  crm_periph_reset(CRM_PWC_PERIPH_RESET, TRUE);
+  crm_periph_reset(CRM_PWC_PERIPH_RESET, FALSE);
+}
+
+/**
+  * @brief  enable or disable access to the battery powered domain.
+  * @param  new_state: new state of battery powered domain access.
+  *         this parameter can be: TRUE or FALSE.
+  * @retval none
+  */
+void pwc_battery_powered_domain_access(confirm_state new_state)
+{
+  PWC->ctrl_bit.bpwen= new_state;
+}
+
+/**
+  * @brief  select the voltage threshold detected by the power voltage detector.
+  * @param  pvm_voltage: select pwc pvm voltage
+  *         this parameter can be one of the following values:
+  *         - PWC_PVM_VOLTAGE_2V3
+  *         - PWC_PVM_VOLTAGE_2V4
+  *         - PWC_PVM_VOLTAGE_2V5
+  *         - PWC_PVM_VOLTAGE_2V6
+  *         - PWC_PVM_VOLTAGE_2V7
+  *         - PWC_PVM_VOLTAGE_2V8
+  *         - PWC_PVM_VOLTAGE_2V9
+  * @retval none
+  */
+void pwc_pvm_level_select(pwc_pvm_voltage_type pvm_voltage)
+{
+  PWC->ctrl_bit.pvmsel= pvm_voltage;
+}
+
+/**
+  * @brief  enable or disable pwc power voltage monitor (pvm)
+  * @param  new_state: new state of pvm.
+  *         this parameter can be: TRUE or FALSE.
+  * @retval none
+  */
+void pwc_power_voltage_monitor_enable(confirm_state new_state)
+{
+  PWC->ctrl_bit.pvmen= new_state;
+}
+
+/**
+  * @brief  enable or disable pwc standby wakeup pin
+  * @param  pin_num: choose the wakeup pin.
+  *         this parameter can be be any combination of the following values:
+  *         - PWC_WAKEUP_PIN_1
+  *         - PWC_WAKEUP_PIN_2
+  * @param  new_state: new state of the standby wakeup pin.
+  *         this parameter can be one of the following values:
+  *         - TRUE <wakeup pin is used for wake up cpu from standby mode>
+  *         - FALSE <wakeup pin is used for general purpose I/O>
+  * @retval none
+  */
+void pwc_wakeup_pin_enable(uint32_t pin_num, confirm_state new_state)
+{
+  if(new_state == TRUE)
+  {
+    PWC->ctrlsts |= pin_num;
+  }
+  else
+  {
+    PWC->ctrlsts &= ~pin_num;
+  }
+}
+
+/**
+  * @brief  clear flag of pwc
+  * @param  pwc_flag: select the pwc flag.
+  *         this parameter can be any combination of the following values:
+  *         - PWC_WAKEUP_FLAG
+  *         - PWC_STANDBY_FLAG
+  *         - note:"PWC_PVM_OUTPUT_FLAG" cannot be choose!this bit is readonly bit,it means the voltage monitoring output state
+  * @retval none
+  */
+void pwc_flag_clear(uint32_t pwc_flag)
+{
+  if(pwc_flag & PWC_STANDBY_FLAG)
+    PWC->ctrl_bit.clsef = TRUE;
+  if(pwc_flag & PWC_WAKEUP_FLAG)
+    PWC->ctrl_bit.clswef = TRUE;
+}
+
+/**
+  * @brief  get flag of pwc
+  * @param  pwc_flag: select the pwc flag.
+  *         this parameter can be one of the following values:
+  *         - PWC_WAKEUP_FLAG
+  *         - PWC_STANDBY_FLAG
+  *         - PWC_PVM_OUTPUT_FLAG
+  * @retval state of select flag(SET or RESET).
+  */
+flag_status pwc_flag_get(uint32_t pwc_flag)
+{
+  flag_status status = RESET;
+  if ((PWC->ctrlsts & pwc_flag) == RESET)
+  {
+    status = RESET;
+  }
+  else
+  {
+    status = SET;
+  }
+  return status;
+}
+
+/**
+  * @brief  enter pwc sleep mode
+  * @param  sleep_mode_enter: choose the instruction to enter sleep mode.
+  *         this parameter can be one of the following values:
+  *         - PWC_SLEEP_ENTER_WFI
+  *         - PWC_SLEEP_ENTER_WFE
+  * @retval none
+  */
+void pwc_sleep_mode_enter(pwc_sleep_enter_type pwc_sleep_enter)
+{
+  SCB->SCR &= (uint32_t)~0x4;
+  if(pwc_sleep_enter == PWC_SLEEP_ENTER_WFE)
+  {
+    __SEV();
+    __WFE();
+    __WFE();
+  }
+  else if(pwc_sleep_enter == PWC_SLEEP_ENTER_WFI)
+  {
+    __WFI();
+  }
+}
+
+/**
+  * @brief  enter pwc deep-sleep mode
+  * @param  pwc_deep_sleep_enter: choose the instruction to enter deep sleep mode.
+  *         this parameter can be one of the following values:
+  *         - PWC_DEEP_SLEEP_ENTER_WFI
+  *         - PWC_DEEP_SLEEP_ENTER_WFE
+  * @retval none
+  */
+void pwc_deep_sleep_mode_enter(pwc_deep_sleep_enter_type pwc_deep_sleep_enter)
+{
+  SCB->SCR |= 0x04;
+  if(pwc_deep_sleep_enter == PWC_DEEP_SLEEP_ENTER_WFE)
+  {
+    __SEV();
+    __WFE();
+    __WFE();
+  }
+  else if(pwc_deep_sleep_enter == PWC_DEEP_SLEEP_ENTER_WFI)
+  {
+    __WFI();
+  }
+  SCB->SCR &= (uint32_t)~0x4;
+}
+
+/**
+  * @brief  regulate low power consumption in the deep sleep mode
+  * @param  pwc_regulator: set the regulator state.
+  *         this parameter can be one of the following values:
+  *         - PWC_REGULATOR_ON
+  *         - PWC_REGULATOR_LOW_POWER
+  * @retval none
+  */
+void pwc_voltage_regulate_set(pwc_regulator_type pwc_regulator)
+{
+  PWC->ctrl_bit.vrsel = pwc_regulator;
+}
+
+/**
+  * @brief  enter pwc standby mode
+  * @param  none
+  * @retval none
+  */
+void pwc_standby_mode_enter(void)
+{
+  PWC->ctrl_bit.clswef = TRUE;
+  PWC->ctrl_bit.lpsel = TRUE;
+  SCB->SCR |= 0x04;
+#if defined (__CC_ARM)
+  __force_stores();
+#endif
+  while(1)
+  {
+    __WFI();
+  }
+}
+
+/**
+  * @}
+  */
+
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */

lib/main/AT32F43x/Drivers/AT32F43x_StdPeriph_Driver/src/at32f435_437_qspi.c

@@ -0,0 +1,430 @@
+/**
+  **************************************************************************
+  * @file     at32f435_437_qspi.c
+  * @version  v2.1.0
+  * @date     2022-08-16
+  * @brief    contain all the functions for qspi firmware library
+  **************************************************************************
+  *                       Copyright notice & Disclaimer
+  *
+  * The software Board Support Package (BSP) that is made available to
+  * download from Artery official website is the copyrighted work of Artery.
+  * Artery authorizes customers to use, copy, and distribute the BSP
+  * software and its related documentation for the purpose of design and
+  * development in conjunction with Artery microcontrollers. Use of the
+  * software is governed by this copyright notice and the following disclaimer.
+  *
+  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+  *
+  **************************************************************************
+  */
+
+#include "at32f435_437_conf.h"
+
+/** @addtogroup AT32F435_437_periph_driver
+  * @{
+  */
+
+/** @defgroup QSPI
+  * @brief QSPI driver modules
+  * @{
+  */
+
+#ifdef QSPI_MODULE_ENABLED
+
+/** @defgroup QSPI_private_functions
+  * @{
+  */
+
+/**
+  * @brief  enable/disable encryption for qspi.
+  * @note   the function must be configured only when qspi in command-port mode!!!
+  * @param  qspi_x: select the qspi peripheral.
+  *         this parameter can be one of the following values:
+  *         QSPI1,QSPI2.
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void qspi_encryption_enable(qspi_type* qspi_x, confirm_state new_state)
+{
+  qspi_x->ctrl_bit.keyen = new_state;
+}
+
+/**
+  * @brief  set qspi sck mode.
+  * @note   the function must be configured only when qspi in command-port mode!!!
+  * @param  qspi_x: select the qspi peripheral.
+  *         this parameter can be one of the following values:
+  *         QSPI1,QSPI2.
+  * @param  new_mode: new state to be set
+  *         this parameter can be one of the following values:
+  *         - QSPI_SCK_MODE_0
+  *         - QSPI_SCK_MODE_3
+  * @retval none
+  */
+void qspi_sck_mode_set(qspi_type* qspi_x, qspi_clk_mode_type new_mode)
+{
+  qspi_x->ctrl_bit.sckmode = new_mode;
+}
+
+/**
+  * @brief  set qspi clock division
+  * @note   the function must be configured only when qspi in command-port mode!!!
+  * @param  qspi_x: select the qspi peripheral.
+  *         this parameter can be one of the following values:
+  *         QSPI1,QSPI2.
+  * @param  new_clkdiv: new division value
+  *         this parameter can be one of the following values:
+  *         - QSPI_CLK_DIV_2
+  *         - QSPI_CLK_DIV_4
+  *         - QSPI_CLK_DIV_6
+  *         - QSPI_CLK_DIV_8
+  *         - QSPI_CLK_DIV_3
+  *         - QSPI_CLK_DIV_5
+  *         - QSPI_CLK_DIV_10
+  *         - QSPI_CLK_DIV_12
+  * @retval none
+  */
+void qspi_clk_division_set(qspi_type* qspi_x, qspi_clk_div_type new_clkdiv)
+{
+  qspi_x->ctrl_bit.clkdiv = new_clkdiv;
+}
+
+/**
+  * @brief  enable/disable cache in xip mode
+  * @note   the function must be configured only when qspi in command-port mode!!!
+  * @param  qspi_x: select the qspi peripheral.
+  *         this parameter can be one of the following values:
+  *         QSPI1,QSPI2.
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void qspi_xip_cache_bypass_set(qspi_type* qspi_x, confirm_state new_state)
+{
+  qspi_x->xip_cmd_w3_bit.bypassc = new_state;
+}
+
+/**
+  * @brief  enable/disable interrupt when command is completed
+  * @note   the function must be configured only when qspi in command-port mode!!!
+  * @param  qspi_x: select the qspi peripheral.
+  *         this parameter can be one of the following values:
+  *         QSPI1,QSPI2.
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void qspi_interrupt_enable(qspi_type* qspi_x, confirm_state new_state)
+{
+  qspi_x->ctrl2_bit.cmdie = new_state;
+}
+
+/**
+  * @brief  get status flags.
+  * @param  qspi_x: select the qspi peripheral.
+  *         this parameter can be one of the following values:
+  *         QSPI1,QSPI2.
+  * @param  flag: specifies the flag to check.
+  *         this parameter can be one of the following values:
+  *         - QSPI_RXFIFORDY_FLAG
+  *         - QSPI_TXFIFORDY_FLAG
+  *         - QSPI_CMDSTS_FLAG
+  * @retval the new state of usart_flag (SET or RESET).
+  */
+flag_status qspi_flag_get(qspi_type* qspi_x, uint32_t flag)
+{
+  flag_status bit_status = RESET;
+  switch(flag)
+  {
+    case QSPI_RXFIFORDY_FLAG:
+      bit_status = (flag_status)qspi_x->fifosts_bit.rxfifordy;
+      break;
+    case QSPI_TXFIFORDY_FLAG:
+      bit_status = (flag_status)qspi_x->fifosts_bit.txfifordy;
+      break;
+    case QSPI_CMDSTS_FLAG:
+      bit_status = (flag_status)qspi_x->cmdsts_bit.cmdsts;
+      break;
+    default:
+      break;
+  }
+  return bit_status;
+}
+
+/**
+  * @brief  clear flags
+  * @param  qspi_x: select the qspi peripheral.
+  *         this parameter can be one of the following values:
+  *         QSPI1,QSPI2.
+  * @param  flag: flags to be clear
+  *         this parameter can be one of the following values:
+  *         - QSPI_CMDSTS_FLAG
+  * @retval none
+  */
+void qspi_flag_clear(qspi_type* qspi_x, uint32_t flag)
+{
+  UNUSED(flag);
+  qspi_x->cmdsts = QSPI_CMDSTS_FLAG;
+}
+
+/**
+  * @brief  set dma threshold for dma rx
+  * @note   the function must be configured only when qspi in command-port mode!!!
+  * @param  qspi_x: select the qspi peripheral.
+  *         this parameter can be one of the following values:
+  *         QSPI1,QSPI2.
+  * @param  new_threshold: value to set
+  *         this parameter can be one of the following values:
+  *         - QSPI_DMA_FIFO_THOD_WORD08
+  *         - QSPI_DMA_FIFO_THOD_WORD16
+  *         - QSPI_DMA_FIFO_THOD_WORD32
+  * @retval none
+  */
+void qspi_dma_rx_threshold_set(qspi_type* qspi_x, qspi_dma_fifo_thod_type new_threshold)
+{
+  qspi_x->ctrl2_bit.rxfifo_thod = new_threshold;
+}
+
+/**
+  * @brief  set dma threshold for dma tx
+  * @note   the function must be configured only when qspi in command-port mode!!!
+  * @param  qspi_x: select the qspi peripheral.
+  *         this parameter can be one of the following values:
+  *         QSPI1,QSPI2.
+  * @param  new_threshold: value to set
+  *         this parameter can be one of the following values:
+  *         - QSPI_DMA_FIFO_THOD_WORD08
+  *         - QSPI_DMA_FIFO_THOD_WORD16
+  *         - QSPI_DMA_FIFO_THOD_WORD32
+  * @retval none
+  */
+void qspi_dma_tx_threshold_set(qspi_type* qspi_x, qspi_dma_fifo_thod_type new_threshold)
+{
+  qspi_x->ctrl2_bit.txfifo_thod = new_threshold;
+}
+
+/**
+  * @brief  enable/disable dma transfer
+  * @note   the function must be configured only when qspi in command-port mode!!!
+  * @param  qspi_x: select the qspi peripheral.
+  *         this parameter can be one of the following values:
+  *         QSPI1,QSPI2.
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void qspi_dma_enable(qspi_type* qspi_x, confirm_state new_state)
+{
+  qspi_x->ctrl2_bit.dmaen = new_state;
+}
+
+/**
+  * @brief  set wip position in status register of flash
+  * @note   the function must be configured only when qspi in command-port mode!!!
+  * @param  qspi_x: select the qspi peripheral.
+  *         this parameter can be one of the following values:
+  *         QSPI1,QSPI2.
+  * @param  busy_pos: value to set
+  *         this parameter can be one of the following values:
+  *         - QSPI_BUSY_OFFSET_0
+  *         - QSPI_BUSY_OFFSET_1
+  *         - QSPI_BUSY_OFFSET_2
+  *         - QSPI_BUSY_OFFSET_3
+  *         - QSPI_BUSY_OFFSET_4
+  *         - QSPI_BUSY_OFFSET_5
+  *         - QSPI_BUSY_OFFSET_6
+  *         - QSPI_BUSY_OFFSET_7
+  * @retval none
+  */
+void qspi_busy_config(qspi_type* qspi_x, qspi_busy_pos_type busy_pos)
+{
+  qspi_x->ctrl_bit.busy = busy_pos;
+}
+
+/**
+  * @brief  enable xip mode or command-port mode.
+  * @param  qspi_x: select the qspi peripheral.
+  *         this parameter can be one of the following values:
+  *         QSPI1,QSPI2.
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void qspi_xip_enable(qspi_type* qspi_x, confirm_state new_state)
+{
+  /* skip if state is no change */
+  if(new_state == (confirm_state)(qspi_x->ctrl_bit.xipsel))
+  {
+    return;
+  }
+
+  /* wait until tx fifo emoty*/
+  while(qspi_x->fifosts_bit.txfifordy == 0);
+
+  /* flush and reset qspi state */
+  qspi_x->ctrl_bit.xiprcmdf = 1;
+
+  /* wait until action is finished */
+  while(qspi_x->ctrl_bit.abort);
+
+  /* set xip mode to new state */
+  qspi_x->ctrl_bit.xipsel = new_state;
+
+  /* wait until abort is not set */
+  while(qspi_x->ctrl_bit.abort);
+
+  /* wait until cache status valid*/
+  if(new_state == TRUE)
+  {
+    while( qspi_x->xip_cmd_w3_bit.csts );
+  }
+}
+
+/**
+  * @brief  set command-port and qspi_x will start to work
+  * @param  qspi_x: select the qspi peripheral.
+  *         this parameter can be one of the following values:
+  *         QSPI1,QSPI2.
+  * @param  qspi_cmd_struct: pointer to qspi cmd structure
+  * @retval none
+  */
+void qspi_cmd_operation_kick(qspi_type* qspi_x, qspi_cmd_type* qspi_cmd_struct)
+{
+  uint32_t w1_val = 0, w3_val = 0;
+
+  /* config analyse cmd_w0 register */
+  qspi_x->cmd_w0 = (uint32_t)qspi_cmd_struct->address_code;
+
+  /* config analyse cmd_w1 register */
+  w1_val = (uint32_t)qspi_cmd_struct->address_length;
+  w1_val |= (uint32_t)(qspi_cmd_struct->second_dummy_cycle_num << 16);
+  w1_val |= (uint32_t)(qspi_cmd_struct->instruction_length << 24);
+  w1_val |= (uint32_t)(qspi_cmd_struct->pe_mode_enable << 28);
+  qspi_x->cmd_w1 = w1_val;
+
+  /* config analyse cmd_w2 register */
+  qspi_x->cmd_w2 = (uint32_t)qspi_cmd_struct->data_counter;
+
+  /* config analyse cmd_w3 register */
+  w3_val = (uint32_t)(qspi_cmd_struct->write_data_enable << 1);
+  w3_val |= (uint32_t)(qspi_cmd_struct->read_status_enable << 2);
+  w3_val |= (uint32_t)(qspi_cmd_struct->read_status_config << 3);
+  w3_val |= (uint32_t)(qspi_cmd_struct->operation_mode << 5);
+  w3_val |= (uint32_t)(qspi_cmd_struct->pe_mode_operate_code << 16);
+  w3_val |= (uint32_t)(qspi_cmd_struct->instruction_code << 24);
+  qspi_x->cmd_w3 = w3_val;
+}
+
+/**
+  * @brief  initial xip mode for qspi_x
+  * @param  qspi_x: select the qspi peripheral.
+  *         this parameter can be one of the following values:
+  *         QSPI1,QSPI2.
+  * @param  xip_init_struct: pointer to xip init structure.
+  * @retval none.
+  */
+void qspi_xip_init(qspi_type* qspi_x, qspi_xip_type* xip_init_struct)
+{
+  uint32_t xc0_val = 0, xc1_val = 0, xc2_val = 0;
+  /* config analyse xip_cmd_w0 register */
+  xc0_val = (uint32_t)xip_init_struct->read_second_dummy_cycle_num;
+  xc0_val |= (uint32_t)(xip_init_struct->read_operation_mode << 8);
+  xc0_val |= (uint32_t)(xip_init_struct->read_address_length << 11);
+  xc0_val |= (uint32_t)(xip_init_struct->read_instruction_code << 12);
+  qspi_x->xip_cmd_w0 = xc0_val;
+
+  /* config analyse xip_cmd_w1 register */
+  xc1_val = (uint32_t)xip_init_struct->write_second_dummy_cycle_num;
+  xc1_val |= (uint32_t)(xip_init_struct->write_operation_mode << 8);
+  xc1_val |= (uint32_t)(xip_init_struct->write_address_length << 11);
+  xc1_val |= (uint32_t)(xip_init_struct->write_instruction_code << 12);
+  qspi_x->xip_cmd_w1 = xc1_val;
+
+  /* config analyse xip_cmd_w2 register */
+  xc2_val = (uint32_t)xip_init_struct->read_data_counter;
+  xc2_val |= (uint32_t)(xip_init_struct->read_time_counter << 8);
+  xc2_val |= (uint32_t)(xip_init_struct->read_select_mode << 15);
+  xc2_val |= (uint32_t)(xip_init_struct->write_data_counter << 16);
+  xc2_val |= (uint32_t)(xip_init_struct->write_time_counter << 24);
+  xc2_val |= (uint32_t)(xip_init_struct->write_select_mode << 31);
+  qspi_x->xip_cmd_w2 = xc2_val;
+}
+
+/**
+  * @brief  read one byte from qspi device in command mode
+  * @param  qspi_x: select the qspi peripheral.
+  * @retval 8-bit data.
+  */
+uint8_t qspi_byte_read(qspi_type* qspi_x)
+{
+  return qspi_x->dt_u8;
+}
+
+/**
+  * @brief  read one half-word from qspi device in command mode
+  * @param  qspi_x: select the qspi peripheral.
+  * @retval 16-bit data.
+  */
+uint16_t qspi_half_word_read(qspi_type* qspi_x)
+{
+  return qspi_x->dt_u16;
+}
+
+/**
+  * @brief  read one word from qspi device in command mode
+  * @param  qspi_x: select the qspi peripheral.
+  * @retval 32-bit data.
+  */
+uint32_t qspi_word_read(qspi_type* qspi_x)
+{
+  return qspi_x->dt;
+}
+
+/**
+  * @brief  write one byte to qspi device in command mode
+  * @param  qspi_x: select the qspi peripheral.
+  * @param  value:  8-bit data.
+  * @retval none.
+  */
+void qspi_byte_write(qspi_type* qspi_x, uint8_t value)
+{
+  qspi_x->dt_u8 = value;
+}
+
+/**
+  * @brief  write one half-word to qspi device in command mode
+  * @param  qspi_x: select the qspi peripheral.
+  * @param  value:  16-bit data.
+  * @retval none.
+  */
+void qspi_half_word_write(qspi_type* qspi_x, uint16_t value)
+{
+  qspi_x->dt_u16 = value;
+}
+
+/**
+  * @brief  write one word to qspi device in command mode
+  * @param  qspi_x: select the qspi peripheral.
+  * @param  value:  32-bit data.
+  * @retval none.
+  */
+void qspi_word_write(qspi_type* qspi_x, uint32_t value)
+{
+  qspi_x->dt = value;
+}
+
+/**
+  * @}
+  */
+
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */

lib/main/AT32F43x/Drivers/AT32F43x_StdPeriph_Driver/src/at32f435_437_scfg.c

@@ -0,0 +1,220 @@
+/**
+  **************************************************************************
+  * @file     at32f435_437_scfg.c
+  * @version  v2.1.0
+  * @date     2022-08-16
+  * @brief    contains all the functions for the system config firmware library
+  **************************************************************************
+  *                       Copyright notice & Disclaimer
+  *
+  * The software Board Support Package (BSP) that is made available to
+  * download from Artery official website is the copyrighted work of Artery.
+  * Artery authorizes customers to use, copy, and distribute the BSP
+  * software and its related documentation for the purpose of design and
+  * development in conjunction with Artery microcontrollers. Use of the
+  * software is governed by this copyright notice and the following disclaimer.
+  *
+  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+  *
+  **************************************************************************
+  */
+
+#include "at32f435_437_conf.h"
+
+/** @addtogroup AT32F435_437_periph_driver
+  * @{
+  */
+
+/** @defgroup SCFG
+  * @brief SCFG driver modules
+  * @{
+  */
+
+#ifdef SCFG_MODULE_ENABLED
+
+/** @defgroup SCFG_private_functions
+  * @{
+  */
+
+/**
+  * @brief  scfg reset
+  * @param  none
+  * @retval none
+  */
+void scfg_reset(void)
+{
+  crm_periph_reset(CRM_SCFG_PERIPH_RESET, TRUE);
+  crm_periph_reset(CRM_SCFG_PERIPH_RESET, FALSE);
+}
+
+/**
+  * @brief  scfg xmc address mapping swap set
+  * @param  xmc_swap
+  *         this parameter can be one of the following values:
+  *         - SCFG_XMC_SWAP_NONE
+  *         - SCFG_XMC_SWAP_MODE1
+  *         - SCFG_XMC_SWAP_MODE2
+  *         - SCFG_XMC_SWAP_MODE3
+  * @retval none
+  */
+void scfg_xmc_mapping_swap_set(scfg_xmc_swap_type xmc_swap)
+{
+  SCFG->cfg1_bit.swap_xmc = xmc_swap;
+}
+
+/**
+  * @brief  scfg infrared config
+  * @param  source
+  *         this parameter can be one of the following values:
+  *         - SCFG_IR_SOURCE_TMR10
+  *         - SCFG_IR_SOURCE_USART1
+  *         - SCFG_IR_SOURCE_USART2
+  * @param  polarity
+  *         this parameter can be one of the following values:
+  *         - SCFG_IR_POLARITY_NO_AFFECTE
+  *         - SCFG_IR_POLARITY_REVERSE
+  * @retval none
+  */
+void scfg_infrared_config(scfg_ir_source_type source, scfg_ir_polarity_type polarity)
+{
+  SCFG->cfg1_bit.ir_src_sel = source;
+  SCFG->cfg1_bit.ir_pol = polarity;
+}
+
+/**
+  * @brief  scfg memory address mapping set
+  * @param  mem_map
+  *         this parameter can be one of the following values:
+  *         - SCFG_MEM_MAP_MAIN_MEMORY
+  *         - SCFG_MEM_MAP_BOOT_MEMORY
+  *         - SCFG_MEM_MAP_XMC_BANK1
+  *         - SCFG_MEM_MAP_INTERNAL_SRAM
+  *         - SCFG_MEM_MAP_XMC_SDRAM_BANK1
+  * @retval none
+  */
+void scfg_mem_map_set(scfg_mem_map_type mem_map)
+{
+  SCFG->cfg1_bit.mem_map_sel = mem_map;
+}
+
+/**
+  * @brief  scfg emac interface set
+  * @param  mode
+  *         this parameter can be one of the following values:
+  *         - SCFG_EMAC_SELECT_MII
+  *         - SCFG_EMAC_SELECT_RMII
+  * @retval none
+  */
+void scfg_emac_interface_set(scfg_emac_interface_type mode)
+{
+  SCFG->cfg2_bit.mii_rmii_sel = mode;
+}
+
+/**
+  * @brief  select the gpio pin used as exint line.
+  * @param  port_source:
+  *         select the gpio port to be used as source for exint lines.
+  *         this parameter can be one of the following values:
+  *         - SCFG_PORT_SOURCE_GPIOA
+  *         - SCFG_PORT_SOURCE_GPIOB
+  *         - SCFG_PORT_SOURCE_GPIOC
+  *         - SCFG_PORT_SOURCE_GPIOD
+  *         - SCFG_PORT_SOURCE_GPIOE
+  *         - SCFG_PORT_SOURCE_GPIOF
+  *         - SCFG_PORT_SOURCE_GPIOG
+  *         - SCFG_PORT_SOURCE_GPIOH
+  * @param  pin_source:
+  *         specifies the exint line to be configured.
+  *         this parameter can be one of the following values:
+  *         - SCFG_PINS_SOURCE0
+  *         - SCFG_PINS_SOURCE1
+  *         - SCFG_PINS_SOURCE2
+  *         - SCFG_PINS_SOURCE3
+  *         - SCFG_PINS_SOURCE4
+  *         - SCFG_PINS_SOURCE5
+  *         - SCFG_PINS_SOURCE6
+  *         - SCFG_PINS_SOURCE7
+  *         - SCFG_PINS_SOURCE8
+  *         - SCFG_PINS_SOURCE9
+  *         - SCFG_PINS_SOURCE10
+  *         - SCFG_PINS_SOURCE11
+  *         - SCFG_PINS_SOURCE12
+  *         - SCFG_PINS_SOURCE13
+  *         - SCFG_PINS_SOURCE14
+  *         - SCFG_PINS_SOURCE15
+  * @retval none
+  */
+void scfg_exint_line_config(scfg_port_source_type port_source, scfg_pins_source_type pin_source)
+{
+  uint32_t tmp = 0x00;
+  tmp = ((uint32_t)0x0F) << (0x04 * (pin_source & (uint8_t)0x03));
+
+  switch (pin_source >> 0x02)
+  {
+    case 0:
+      SCFG->exintc1 &= ~tmp;
+      SCFG->exintc1 |= (((uint32_t)port_source) << (0x04 * (pin_source & (uint8_t)0x03)));
+      break;
+    case 1:
+      SCFG->exintc2 &= ~tmp;
+      SCFG->exintc2 |= (((uint32_t)port_source) << (0x04 * (pin_source & (uint8_t)0x03)));
+      break;
+    case 2:
+      SCFG->exintc3 &= ~tmp;
+      SCFG->exintc3 |= (((uint32_t)port_source) << (0x04 * (pin_source & (uint8_t)0x03)));
+      break;
+    case 3:
+      SCFG->exintc4 &= ~tmp;
+      SCFG->exintc4 |= (((uint32_t)port_source) << (0x04 * (pin_source & (uint8_t)0x03)));
+      break;
+    default:
+      break;
+  }
+}
+
+/**
+  * @brief  enable or disable gpio pins ultra driven.
+  * @param  value:
+  *         this parameter can be one of the following values:
+  *         - SCFG_ULTRA_DRIVEN_PB3
+  *         - SCFG_ULTRA_DRIVEN_PB9
+  *         - SCFG_ULTRA_DRIVEN_PB10
+  *         - SCFG_ULTRA_DRIVEN_PD12
+  *         - SCFG_ULTRA_DRIVEN_PD13
+  *         - SCFG_ULTRA_DRIVEN_PD14
+  *         - SCFG_ULTRA_DRIVEN_PD15
+  *         - SCFG_ULTRA_DRIVEN_PF14
+  *         - SCFG_ULTRA_DRIVEN_PF15
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void scfg_pins_ultra_driven_enable(scfg_ultra_driven_pins_type value, confirm_state new_state)
+{
+  if(TRUE == new_state)
+  {
+    SCFG_REG(value) |= SCFG_REG_BIT(value);
+  }
+  else
+  {
+    SCFG_REG(value) &= ~(SCFG_REG_BIT(value));
+  }
+}
+
+/**
+  * @}
+  */
+
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */

lib/main/AT32F43x/Drivers/AT32F43x_StdPeriph_Driver/src/at32f435_437_sdio.c

@@ -0,0 +1,575 @@
+/**
+  **************************************************************************
+  * @file     at32f435_437_sdio.c
+  * @version  v2.1.0
+  * @date     2022-08-16
+  * @brief    contains all the functions for the sdio firmware library
+  **************************************************************************
+  *                       Copyright notice & Disclaimer
+  *
+  * The software Board Support Package (BSP) that is made available to
+  * download from Artery official website is the copyrighted work of Artery.
+  * Artery authorizes customers to use, copy, and distribute the BSP
+  * software and its related documentation for the purpose of design and
+  * development in conjunction with Artery microcontrollers. Use of the
+  * software is governed by this copyright notice and the following disclaimer.
+  *
+  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+  *
+  **************************************************************************
+  */
+
+#include "at32f435_437_conf.h"
+
+/** @addtogroup AT32F435_437_periph_driver
+  * @{
+  */
+
+/** @defgroup SDIO
+  * @brief SDIO driver modules
+  * @{
+  */
+
+#ifdef SDIO_MODULE_ENABLED
+
+/** @defgroup SDIO_private_functions
+  * @{
+  */
+
+/**
+  * @brief  reset the sdio register
+  * @param  sdio_x: to select the sdio peripheral.
+  *         this parameter can be one of the following values:
+  *         SDIO1, SDIO2.
+  * @retval none
+  */
+void sdio_reset(sdio_type *sdio_x)
+{
+  sdio_x->pwrctrl = 0x0;
+  sdio_x->clkctrl = 0x0;
+  sdio_x->argu = 0x0;
+  sdio_x->cmdctrl = 0x0;
+  sdio_x->dttmr = 0x0;
+  sdio_x->dtlen = 0x0;
+  sdio_x->dtctrl = 0x0;
+  sdio_x->inten = 0x0;
+  sdio_x->intclr = 0x004007FF;
+}
+
+/**
+  * @brief  set the power status of the controller
+  * @param  sdio_x: to select the sdio peripheral.
+  *         this parameter can be one of the following values:
+  *         SDIO1, SDIO2.
+  * @param  power_state
+  *         this parameter can be one of the following values:
+  *         - SDIO_POWER_OFF
+  *         - SDIO_POWER_ON
+  * @retval none
+  */
+void sdio_power_set(sdio_type *sdio_x, sdio_power_state_type power_state)
+{
+  sdio_x->pwrctrl_bit.ps = power_state;
+}
+
+/**
+  * @brief  get power status.
+  * @param  sdio_x: to select the sdio peripheral.
+  *         this parameter can be one of the following values:
+  *         SDIO1, SDIO2.
+  * @retval sdio_power_state_type (SDIO_POWER_ON or SDIO_POWER_OFF)
+  */
+sdio_power_state_type sdio_power_status_get(sdio_type *sdio_x)
+{
+  return (sdio_power_state_type)(sdio_x->pwrctrl_bit.ps);
+}
+
+/**
+  * @brief  config sdio clock
+  * @param  sdio_x: to select the sdio peripheral.
+  *         this parameter can be one of the following values:
+  *         SDIO1, SDIO2.
+  * @param  clk_div: sdio clock divide factor(frequency = sdio_clk / [clk_psc + 2]).
+  * @param  clk_edg
+  *         this parameter can be one of the following values:
+  *         - SDIO_CLOCK_EDGE_RISING
+  *         - SDIO_CLOCK_EDGE_FALLING
+  * @retval none
+  */
+void sdio_clock_config(sdio_type *sdio_x, uint16_t clk_div, sdio_edge_phase_type clk_edg)
+{
+  /* config clock edge */
+  sdio_x->clkctrl_bit.clkegs = clk_edg;
+
+  /* config clock divide [7:0] */
+  sdio_x->clkctrl_bit.clkdiv_l = (clk_div & 0xFF);
+
+  /* config clock divide [9:8] */
+  sdio_x->clkctrl_bit.clkdiv_h = ((clk_div & 0x300) >> 8);
+}
+
+/**
+  * @brief  config sdio bus width
+  * @param  sdio_x: to select the sdio peripheral.
+  *         this parameter can be one of the following values:
+  *         SDIO1, SDIO2.
+  * @param  width
+  *         this parameter can be one of the following values:
+  *         - SDIO_BUS_WIDTH_D1
+  *         - SDIO_BUS_WIDTH_D4
+  *         - SDIO_BUS_WIDTH_D8
+  * @retval none
+  */
+void sdio_bus_width_config(sdio_type *sdio_x, sdio_bus_width_type width)
+{
+  sdio_x->clkctrl_bit.busws = width;
+}
+
+/**
+  * @brief  enable or disable clock divider bypss
+  * @param  sdio_x: to select the sdio peripheral.
+  *         this parameter can be one of the following values:
+  *         SDIO1, SDIO2.
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void sdio_clock_bypass(sdio_type *sdio_x, confirm_state new_state)
+{
+  sdio_x->clkctrl_bit.bypsen = new_state;
+}
+
+/**
+  * @brief  enable or disable power saving mode, config sdio_ck clock output
+  *         when the bus is idle.
+  * @param  sdio_x: to select the sdio peripheral.
+  *         this parameter can be one of the following values:
+  *         SDIO1, SDIO2.
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void sdio_power_saving_mode_enable(sdio_type *sdio_x, confirm_state new_state)
+{
+  sdio_x->clkctrl_bit.pwrsven = new_state;
+}
+
+/**
+  * @brief  enable or disable hardware flow control.
+  * @param  sdio_x: to select the sdio peripheral.
+  *         this parameter can be one of the following values:
+  *         SDIO1, SDIO2.
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void sdio_flow_control_enable(sdio_type *sdio_x, confirm_state new_state)
+{
+  sdio_x->clkctrl_bit.hfcen = new_state;
+}
+
+/**
+  * @brief  enable or disable sdio_ck output.
+  * @param  sdio_x: to select the sdio peripheral.
+  *         this parameter can be one of the following values:
+  *         SDIO1, SDIO2.
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void sdio_clock_enable(sdio_type *sdio_x, confirm_state new_state)
+{
+  sdio_x->clkctrl_bit.clkoen = new_state;
+}
+
+/**
+  * @brief  enable or disable dma.
+  * @param  sdio_x: to select the sdio peripheral.
+  *         this parameter can be one of the following values:
+  *         SDIO1, SDIO2.
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void sdio_dma_enable(sdio_type *sdio_x, confirm_state new_state)
+{
+  sdio_x->dtctrl_bit.dmaen = new_state;
+}
+
+/**
+  * @brief  config corresponding interrupt.
+  * @param  sdio_x: to select the sdio peripheral.
+  *         this parameter can be one of the following values:
+  *         SDIO1, SDIO2.
+  * @param  int_opt
+  *         this parameter can be one of the following values:
+  *         - SDIO_CMDFAIL_INT
+  *         - SDIO_DTFAIL_INT
+  *         - SDIO_CMDTIMEOUT_INT
+  *         - SDIO_DTTIMEOUT_INT
+  *         - SDIO_TXERRU_INT
+  *         - SDIO_RXERRO_INT
+  *         - SDIO_CMDRSPCMPL_INT
+  *         - SDIO_CMDCMPL_INT
+  *         - SDIO_DTCMP_INT
+  *         - SDIO_SBITERR_INT
+  *         - SDIO_DTBLKCMPL_INT
+  *         - SDIO_DOCMD_INT
+  *         - SDIO_DOTX_INT
+  *         - SDIO_DORX_INT
+  *         - SDIO_TXBUFH_INT
+  *         - SDIO_RXBUFH_INT
+  *         - SDIO_TXBUFF_INT
+  *         - SDIO_RXBUFF_INT
+  *         - SDIO_TXBUFE_INT
+  *         - SDIO_RXBUFE_INT
+  *         - SDIO_TXBUF_INT
+  *         - SDIO_RXBUF_INT
+  *         - SDIO_SDIOIF_INT
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void sdio_interrupt_enable(sdio_type *sdio_x, uint32_t int_opt,  confirm_state new_state)
+{
+  /* enable interrupt */
+  if(TRUE == new_state)
+  {
+    sdio_x->inten |= int_opt;
+  }
+  /* disable interrupt */
+  else
+  {
+    sdio_x->inten &= ~(int_opt);
+  }
+}
+
+/**
+  * @brief  get sdio flag.
+  * @param  sdio_x: to select the sdio peripheral.
+  *         this parameter can be one of the following values:
+  *         SDIO1, SDIO2.
+  * @param  flag
+  *         this parameter can be one of the following values:
+  *         - SDIO_CMDFAIL_FLAG
+  *         - SDIO_DTFAIL_FLAG
+  *         - SDIO_CMDTIMEOUT_FLAG
+  *         - SDIO_DTTIMEOUT_FLAG
+  *         - SDIO_TXERRU_FLAG
+  *         - SDIO_RXERRO_FLAG
+  *         - SDIO_CMDRSPCMPL_FLAG
+  *         - SDIO_CMDCMPL_FLAG
+  *         - SDIO_DTCMPL_FLAG
+  *         - SDIO_SBITERR_FLAG
+  *         - SDIO_DTBLKCMPL_FLAG
+  *         - SDIO_DOCMD_FLAG
+  *         - SDIO_DOTX_FLAG
+  *         - SDIO_DORX_FLAG
+  *         - SDIO_TXBUFH_FLAG
+  *         - SDIO_RXBUFH_FLAG
+  *         - SDIO_TXBUFF_FLAG
+  *         - SDIO_RXBUFF_FLAG
+  *         - SDIO_TXBUFE_FLAG
+  *         - SDIO_RXBUFE_FLAG
+  *         - SDIO_TXBUF_FLAG
+  *         - SDIO_RXBUF_FLAG
+  *         - SDIO_SDIOIF_FLAG
+  * @retval flag_status (SET or RESET)
+  */
+flag_status sdio_flag_get(sdio_type *sdio_x, uint32_t flag)
+{
+  flag_status status = RESET;
+
+  if((sdio_x->sts & flag) == flag)
+  {
+    status = SET;
+  }
+  else
+  {
+    status = RESET;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  clear sdio flag.
+  * @param  sdio_x: to select the sdio peripheral.
+  *         this parameter can be one of the following values:
+  *         SDIO1, SDIO2.
+  * @param  int_opt
+  *         this parameter can be any combination of the following values:
+  *         - SDIO_CMDFAIL_FLAG
+  *         - SDIO_DTFAIL_FLAG
+  *         - SDIO_CMDTIMEOUT_FLAG
+  *         - SDIO_DTTIMEOUT_FLAG
+  *         - SDIO_TXERRU_FLAG
+  *         - SDIO_RXERRO_FLAG
+  *         - SDIO_CMDRSPCMPL_FLAG
+  *         - SDIO_CMDCMPL_FLAG
+  *         - SDIO_DTCMPL_FLAG
+  *         - SDIO_SBITERR_FLAG
+  *         - SDIO_DTBLKCMPL_FLAG
+  *         - SDIO_SDIOIF_FLAG
+  * @retval none
+  */
+void sdio_flag_clear(sdio_type *sdio_x, uint32_t flag)
+{
+  sdio_x->intclr = flag;
+}
+
+/**
+  * @brief  config sdio command.
+  * @param  sdio_x: to select the sdio peripheral.
+  *         this parameter can be one of the following values:
+  *         SDIO1, SDIO2.
+  * @param  command_struct : pointer to a sdio_command_struct_type structure
+  *         that contains the configuration information for the sdio command.
+  * @retval none
+  */
+void sdio_command_config(sdio_type *sdio_x, sdio_command_struct_type *command_struct)
+{
+  /* disable command path state machine */
+  sdio_x->cmdctrl_bit.ccsmen = FALSE;
+
+  /* config command argument */
+  sdio_x->argu = command_struct->argument;
+
+  /* config command register */
+  sdio_x->cmdctrl_bit.cmdidx = command_struct->cmd_index;
+  sdio_x->cmdctrl_bit.rspwt = command_struct->rsp_type;
+  sdio_x->cmdctrl_bit.intwt = (command_struct->wait_type & 0x1); /* [1:0] -> [0] */
+  sdio_x->cmdctrl_bit.pndwt = (command_struct->wait_type & 0x2)>>1; /* [1:0] -> [1] */
+}
+
+/**
+  * @brief  enable or disable command path state machine(CPSM).
+  * @param  sdio_x: to select the sdio peripheral.
+  *         this parameter can be one of the following values:
+  *         SDIO1, SDIO2.
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void sdio_command_state_machine_enable(sdio_type *sdio_x, confirm_state new_state)
+{
+  sdio_x->cmdctrl_bit.ccsmen = new_state;
+}
+
+/**
+  * @brief  get command index of last command for which response received.
+  * @param  sdio_x: to select the sdio peripheral.
+  *         this parameter can be one of the following values:
+  *         SDIO1, SDIO2.
+  * @param  new_state (TRUE or FALSE)
+  * @retval uint8_t: command index
+  */
+uint8_t sdio_command_response_get(sdio_type *sdio_x)
+{
+  return sdio_x->rspcmd_bit.rspcmd;
+}
+
+/**
+  * @brief  get response received from the card for the last command.
+  * @param  sdio_x: to select the sdio peripheral.
+  *         this parameter can be one of the following values:
+  *         SDIO1, SDIO2.
+  * @param  reg_index
+  *         this parameter can be one of the following values:
+  *         - SDIO_RSP1_INDEX
+  *         - SDIO_RSP2_INDEX
+  *         - SDIO_RSP3_INDEX
+  *         - SDIO_RSP4_INDEX
+  * @retval uint32_t: response register value
+  */
+uint32_t sdio_response_get(sdio_type *sdio_x, sdio_rsp_index_type reg_index)
+{
+  uint32_t response_value = 0;
+
+  switch(reg_index)
+  {
+    case SDIO_RSP1_INDEX:
+      response_value = sdio_x->rsp1;
+      break;
+    case SDIO_RSP2_INDEX:
+      response_value = sdio_x->rsp2;
+      break;
+    case SDIO_RSP3_INDEX:
+      response_value = sdio_x->rsp3;
+      break;
+    case SDIO_RSP4_INDEX:
+      response_value = sdio_x->rsp4;
+      break;
+    default: break;
+  }
+
+  return response_value;
+}
+
+/**
+  * @brief  config sdio data.
+  * @param  sdio_x: to select the sdio peripheral.
+  *         this parameter can be one of the following values:
+  *         SDIO1, SDIO2.
+  * @param  data_struct : pointer to a sdio_data_struct_type structure
+  *         that contains the configuration information for the sdio data.
+  * @retval none
+  */
+void sdio_data_config(sdio_type *sdio_x, sdio_data_struct_type *data_struct)
+{
+  /* disable data path state machine */
+  sdio_x->dtctrl_bit.tfren = FALSE;
+
+  /* config data block, transfer mode and transfer direction */
+  sdio_x->dtctrl_bit.blksize = data_struct->block_size;
+  sdio_x->dtctrl_bit.tfrdir = data_struct->transfer_direction;
+  sdio_x->dtctrl_bit.tfrmode = data_struct->transfer_mode;
+
+  /* config data length */
+  sdio_x->dtlen_bit.dtlen = data_struct->data_length;
+
+  /* config data transfer timeout */
+  sdio_x->dttmr_bit.timeout = data_struct->timeout;
+}
+
+/**
+  * @brief  enable or disable data path state machine(DPSM).
+  * @param  sdio_x: to select the sdio peripheral.
+  *         this parameter can be one of the following values:
+  *         SDIO1, SDIO2.
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void sdio_data_state_machine_enable(sdio_type *sdio_x, confirm_state new_state)
+{
+  sdio_x->dtctrl_bit.tfren = new_state;
+}
+
+/**
+  * @brief  get the number of remaining data bytes to be transferred.
+  * @param  sdio_x: to select the sdio peripheral.
+  *         this parameter can be one of the following values:
+  *         SDIO1, SDIO2.
+  * @retval uint32_t: number of bytes
+  */
+uint32_t sdio_data_counter_get(sdio_type *sdio_x)
+{
+  return sdio_x->dtcnt;
+}
+
+/**
+  * @brief  read a word data from sdio fifo.
+  * @param  sdio_x: to select the sdio peripheral.
+  *         this parameter can be one of the following values:
+  *         SDIO1, SDIO2.
+  * @retval uint32_t: data received
+  */
+uint32_t sdio_data_read(sdio_type *sdio_x)
+{
+  return sdio_x->buf;
+}
+
+/**
+  * @brief  get the number of words left to be written to or read from fifo..
+  * @param  sdio_x: to select the sdio peripheral.
+  *         this parameter can be one of the following values:
+  *         SDIO1, SDIO2.
+  * @retval uint32_t: number of words
+  */
+uint32_t sdio_buffer_counter_get(sdio_type *sdio_x)
+{
+  return sdio_x->bufcnt;
+}
+
+/**
+  * @brief  write one word data to fifo.
+  * @param  sdio_x: to select the sdio peripheral.
+  *         this parameter can be one of the following values:
+  *         SDIO1, SDIO2.
+  * @param  data: data to be transferred.
+  * @retval none
+  */
+void sdio_data_write(sdio_type *sdio_x, uint32_t data)
+{
+  sdio_x->buf = data;
+}
+
+/**
+  * @brief  set the read wait mode.
+  * @param  sdio_x: to select the sdio peripheral.
+  *         this parameter can be one of the following values:
+  *         SDIO1, SDIO2.
+  * @param  mode
+  *         this parameter can be one of the following values:
+  *         - SDIO_READ_WAIT_CONTROLLED_BY_D2
+  *         - SDIO_READ_WAIT_CONTROLLED_BY_CK
+  * @retval none
+  */
+void sdio_read_wait_mode_set(sdio_type *sdio_x, sdio_read_wait_mode_type mode)
+{
+  sdio_x->dtctrl_bit.rdwtmode = mode;
+}
+
+/**
+  * @brief  enable or disable to start sd i/o read wait operation.
+  * @param  sdio_x: to select the sdio peripheral.
+  *         this parameter can be one of the following values:
+  *         SDIO1, SDIO2.
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void sdio_read_wait_start(sdio_type *sdio_x, confirm_state new_state)
+{
+  sdio_x->dtctrl_bit.rdwtstart = new_state;
+}
+
+/**
+  * @brief  enable or disable to stop sd i/o read wait operation.
+  * @param  sdio_x: to select the sdio peripheral.
+  *         this parameter can be one of the following values:
+  *         SDIO1, SDIO2.
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void sdio_read_wait_stop(sdio_type *sdio_x, confirm_state new_state)
+{
+  sdio_x->dtctrl_bit.rdwtstop = new_state;
+}
+
+/**
+  * @brief  enable or disable the sd i/o function.
+  * @param  sdio_x: to select the sdio peripheral.
+  *         this parameter can be one of the following values:
+  *         SDIO1, SDIO2.
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void sdio_io_function_enable(sdio_type *sdio_x, confirm_state new_state)
+{
+  sdio_x->dtctrl_bit.ioen = new_state;
+}
+
+/**
+  * @brief  enable or disable sd i/o suspend command sending.
+  * @param  sdio_x: to select the sdio peripheral.
+  *         this parameter can be one of the following values:
+  *         SDIO1, SDIO2.
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void sdio_io_suspend_command_set(sdio_type *sdio_x, confirm_state new_state)
+{
+  sdio_x->cmdctrl_bit.iosusp = new_state;
+}
+
+/**
+  * @}
+  */
+
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */

lib/main/AT32F43x/Drivers/AT32F43x_StdPeriph_Driver/src/at32f435_437_spi.c

@@ -0,0 +1,650 @@
+/**
+  **************************************************************************
+  * @file     at32f435_437_spi.c
+  * @version  v2.1.0
+  * @date     2022-08-16
+  * @brief    contains all the functions for the spi firmware library
+  **************************************************************************
+  *                       Copyright notice & Disclaimer
+  *
+  * The software Board Support Package (BSP) that is made available to
+  * download from Artery official website is the copyrighted work of Artery.
+  * Artery authorizes customers to use, copy, and distribute the BSP
+  * software and its related documentation for the purpose of design and
+  * development in conjunction with Artery microcontrollers. Use of the
+  * software is governed by this copyright notice and the following disclaimer.
+  *
+  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+  *
+  **************************************************************************
+  */
+
+#include "at32f435_437_conf.h"
+
+/** @addtogroup AT32F435_437_periph_driver
+  * @{
+  */
+
+/** @defgroup SPI
+  * @brief SPI driver modules
+  * @{
+  */
+
+#ifdef SPI_MODULE_ENABLED
+
+/** @defgroup SPI_private_functions
+  * @{
+  */
+
+/**
+  * @brief  spi reset by crm reset register
+  * @param  spi_x: select the spi peripheral.
+  *         this parameter can be one of the following values:
+  *         SPI1, SPI2, SPI3 ,SPI4
+  * @retval none
+  */
+void spi_i2s_reset(spi_type *spi_x)
+{
+  if(spi_x == SPI1)
+  {
+    crm_periph_reset(CRM_SPI1_PERIPH_RESET, TRUE);
+    crm_periph_reset(CRM_SPI1_PERIPH_RESET, FALSE);
+  }
+  else if(spi_x == SPI2)
+  {
+    crm_periph_reset(CRM_SPI2_PERIPH_RESET, TRUE);
+    crm_periph_reset(CRM_SPI2_PERIPH_RESET, FALSE);
+  }
+  else if(spi_x == SPI3)
+  {
+    crm_periph_reset(CRM_SPI3_PERIPH_RESET, TRUE);
+    crm_periph_reset(CRM_SPI3_PERIPH_RESET, FALSE);
+  }
+  else if(spi_x == SPI4)
+  {
+    crm_periph_reset(CRM_SPI4_PERIPH_RESET, TRUE);
+    crm_periph_reset(CRM_SPI4_PERIPH_RESET, FALSE);
+  }
+}
+
+/**
+  * @brief  spi init config with its default value.
+  * @param  spi_init_struct : pointer to a spi_init_type structure which will
+  *         be initialized.
+  * @retval none
+  */
+void spi_default_para_init(spi_init_type* spi_init_struct)
+{
+  spi_init_struct->transmission_mode = SPI_TRANSMIT_FULL_DUPLEX;
+  spi_init_struct->master_slave_mode = SPI_MODE_SLAVE;
+  spi_init_struct->mclk_freq_division = SPI_MCLK_DIV_2;
+  spi_init_struct->first_bit_transmission = SPI_FIRST_BIT_MSB;
+  spi_init_struct->frame_bit_num = SPI_FRAME_8BIT;
+  spi_init_struct->clock_polarity = SPI_CLOCK_POLARITY_LOW;
+  spi_init_struct->clock_phase = SPI_CLOCK_PHASE_1EDGE;
+  spi_init_struct->cs_mode_selection = SPI_CS_SOFTWARE_MODE;
+}
+
+/**
+  * @brief  spi init config with its setting value.
+  * @param  spi_x: select the spi peripheral.
+  *         this parameter can be one of the following values:
+  *         SPI1, SPI2, SPI3 ,SPI4
+  * @param  spi_init_struct : pointer to a spi_init_type structure which will be initialized.
+  * @retval none
+  */
+void spi_init(spi_type* spi_x, spi_init_type* spi_init_struct)
+{
+  spi_x->i2sctrl_bit.i2smsel = FALSE;
+  if(spi_init_struct->transmission_mode == SPI_TRANSMIT_FULL_DUPLEX)
+  {
+    spi_x->ctrl1_bit.slben = FALSE;
+    spi_x->ctrl1_bit.slbtd = FALSE;
+    spi_x->ctrl1_bit.ora = FALSE;
+  }
+  else if(spi_init_struct->transmission_mode == SPI_TRANSMIT_SIMPLEX_RX)
+  {
+    spi_x->ctrl1_bit.slben = FALSE;
+    spi_x->ctrl1_bit.slbtd = FALSE;
+    spi_x->ctrl1_bit.ora = TRUE;
+  }
+  else if(spi_init_struct->transmission_mode == SPI_TRANSMIT_HALF_DUPLEX_RX)
+  {
+    spi_x->ctrl1_bit.slben = TRUE;
+    spi_x->ctrl1_bit.slbtd = FALSE;
+    spi_x->ctrl1_bit.ora = FALSE;
+  }
+  else if(spi_init_struct->transmission_mode == SPI_TRANSMIT_HALF_DUPLEX_TX)
+  {
+    spi_x->ctrl1_bit.slben = TRUE;
+    spi_x->ctrl1_bit.slbtd = TRUE;
+    spi_x->ctrl1_bit.ora = FALSE;
+  }
+
+  spi_x->ctrl1_bit.swcsen = spi_init_struct->cs_mode_selection;
+  if((spi_init_struct->master_slave_mode == SPI_MODE_MASTER) && (spi_init_struct->cs_mode_selection == SPI_CS_SOFTWARE_MODE))
+  {
+    spi_x->ctrl1_bit.swcsil = TRUE;
+  }
+  else
+  {
+    spi_x->ctrl1_bit.swcsil = FALSE;
+  }
+  spi_x->ctrl1_bit.msten = spi_init_struct->master_slave_mode;
+
+  if(spi_init_struct->mclk_freq_division <= SPI_MCLK_DIV_256)
+  {
+    spi_x->ctrl2_bit.mdiv3en = FALSE;
+    spi_x->ctrl2_bit.mdiv_h = FALSE;
+    spi_x->ctrl1_bit.mdiv_l = spi_init_struct->mclk_freq_division;
+  }
+  else if(spi_init_struct->mclk_freq_division == SPI_MCLK_DIV_3)
+  {
+    spi_x->ctrl2_bit.mdiv3en = TRUE;
+    spi_x->ctrl2_bit.mdiv_h = FALSE;
+    spi_x->ctrl1_bit.mdiv_l = 0;
+  }
+  else
+  {
+    spi_x->ctrl2_bit.mdiv3en = FALSE;
+    spi_x->ctrl2_bit.mdiv_h = TRUE;
+    spi_x->ctrl1_bit.mdiv_l = spi_init_struct->mclk_freq_division & 0x7;
+  }
+
+  spi_x->ctrl1_bit.ltf = spi_init_struct->first_bit_transmission;
+  spi_x->ctrl1_bit.fbn = spi_init_struct->frame_bit_num;
+  spi_x->ctrl1_bit.clkpol = spi_init_struct->clock_polarity;
+  spi_x->ctrl1_bit.clkpha = spi_init_struct->clock_phase;
+}
+
+/**
+  * @brief  enable or disable the ti mode for the spi peripheral.
+  * @param  spi_x: select the spi peripheral.
+  *         this parameter can be one of the following values:
+  *         SPI1, SPI2, SPI3 ,SPI4
+  * @param  new_state: new state of ti mode.
+  *         this parameter can be: TRUE or FALSE.
+  * @retval none
+  */
+void spi_ti_mode_enable(spi_type* spi_x, confirm_state new_state)
+{
+  spi_x->ctrl2_bit.tien = new_state;
+}
+
+/**
+  * @brief  spi next transmit crc for the spi peripheral.
+  * @param  spi_x: select the spi peripheral.
+  *         this parameter can be one of the following values:
+  *         SPI1, SPI2, SPI3 ,SPI4
+  * @retval none
+  */
+void spi_crc_next_transmit(spi_type* spi_x)
+{
+  spi_x->ctrl1_bit.ntc = TRUE;
+}
+
+/**
+  * @brief  set the crc polynomial value for the spi peripheral.
+  * @param  spi_x: select the spi peripheral.
+  *         this parameter can be one of the following values:
+  *         SPI1, SPI2, SPI3 ,SPI4
+  * @param  crc_poly: crc polynomial value.
+  * @retval none
+  */
+void spi_crc_polynomial_set(spi_type* spi_x, uint16_t crc_poly)
+{
+  spi_x->cpoly_bit.cpoly = crc_poly;
+}
+
+/**
+  * @brief  return the crc polynomial register value for the spi peripheral.
+  * @param  spi_x: select the spi peripheral.
+  *         this parameter can be one of the following values:
+  *         SPI1, SPI2, SPI3 ,SPI4
+  * @retval the select crc polynomial register value
+  */
+uint16_t spi_crc_polynomial_get(spi_type* spi_x)
+{
+  return spi_x->cpoly_bit.cpoly;
+}
+
+/**
+  * @brief  enable or disable the hardware crc calculation for the spi peripheral.
+  * @param  spi_x: select the spi peripheral.
+  *         this parameter can be one of the following values:
+  *         SPI1, SPI2, SPI3 ,SPI4
+  * @param  new_state: new state of crc calculation.
+  *         this parameter can be: TRUE or FALSE.
+  * @retval none
+  */
+void spi_crc_enable(spi_type* spi_x, confirm_state new_state)
+{
+  spi_x->ctrl1_bit.ccen = new_state;
+}
+
+/**
+  * @brief  return the transmit or the receive crc value for the spi peripheral.
+  * @param  spi_x: select the spi peripheral.
+  *         this parameter can be one of the following values:
+  *         SPI1, SPI2, SPI3 ,SPI4
+  * @param  crc_direction: select transmit or receive crc value to be read
+  *         - SPI_CRC_RX
+  *         - SPI_CRC_TX
+  * @retval the select crc register value
+  */
+uint16_t spi_crc_value_get(spi_type* spi_x, spi_crc_direction_type crc_direction)
+{
+  if(crc_direction == SPI_CRC_RX)
+    return  spi_x->rcrc_bit.rcrc;
+  else
+    return  spi_x->tcrc_bit.tcrc;
+}
+
+/**
+  * @brief  enable or disable the hardware cs output for the spi peripheral.
+  * @param  spi_x: select the spi peripheral.
+  *         this parameter can be one of the following values:
+  *         SPI1, SPI2, SPI3 ,SPI4
+  * @param  new_state: new state of spi master cs output.
+  *         this parameter can be: TRUE or FALSE.
+  *         note:the bit only use in spi master mode
+  * @retval none
+  */
+void spi_hardware_cs_output_enable(spi_type* spi_x, confirm_state new_state)
+{
+  spi_x->ctrl2_bit.hwcsoe = new_state;
+}
+
+/**
+  * @brief  set the software cs internal level for the spi peripheral.
+  * @param  spi_x: select the spi peripheral.
+  *         this parameter can be one of the following values:
+  *         SPI1, SPI2, SPI3 ,SPI4
+  * @param  level: set the state of spi cs level.
+  *         this parameter can be one of the following values:
+  *         - SPI_SWCS_INTERNAL_LEVEL_LOW
+  *         - SPI_SWCS_INTERNAL_LEVEL_HIGHT
+  *         note:the bit only use when swcsen bit is set.
+  *         note:when use this bit,io operation on the cs pin are invalid.
+  * @retval none
+  */
+void spi_software_cs_internal_level_set(spi_type* spi_x, spi_software_cs_level_type level)
+{
+  spi_x->ctrl1_bit.swcsil = level;
+}
+
+/**
+  * @brief  set the data frame bit num for the spi peripheral.
+  * @param  spi_x: select the spi peripheral.
+  *         this parameter can be one of the following values:
+  *         SPI1, SPI2, SPI3 ,SPI4
+  * @param  bit_num: set the data frame size
+  *         - SPI_FRAME_8BIT
+  *         - SPI_FRAME_16BIT
+  * @retval none
+  */
+void spi_frame_bit_num_set(spi_type* spi_x, spi_frame_bit_num_type bit_num)
+{
+  spi_x->ctrl1_bit.fbn = bit_num;
+}
+
+/**
+  * @brief  set the data transmission direction in single line bidirectiona half duplex mode of the spi peripheral.
+  * @param  spi_x: select the spi peripheral.
+  *         this parameter can be one of the following values:
+  *         SPI1, SPI2, SPI3 ,SPI4
+  * @param  direction: data transfer direction
+  *         this parameter can be one of the following values:
+  *         - SPI_HALF_DUPLEX_DIRECTION_RX
+  *         - SPI_HALF_DUPLEX_DIRECTION_TX
+  * @retval none
+  */
+void spi_half_duplex_direction_set(spi_type* spi_x, spi_half_duplex_direction_type direction)
+{
+    spi_x->ctrl1_bit.slbtd = direction;
+}
+
+/**
+  * @brief  enable or disable spi.
+  * @param  spi_x: select the spi peripheral.
+  *         this parameter can be one of the following values:
+  *         SPI1, SPI2, SPI3 ,SPI4
+  * @param  new_state: new state of spi.
+  *         this parameter can be: TRUE or FALSE.
+  * @retval none
+  */
+void spi_enable(spi_type* spi_x, confirm_state new_state)
+{
+  spi_x->ctrl1_bit.spien = new_state;
+}
+
+/**
+  * @brief  i2s init config with its default value.
+  * @param  i2s_init_struct : pointer to a i2s_init_type structure which will
+  *         be initialized.
+  * @retval none
+  */
+void i2s_default_para_init(i2s_init_type* i2s_init_struct)
+{
+  i2s_init_struct->operation_mode = I2S_MODE_SLAVE_TX;
+  i2s_init_struct->audio_protocol = I2S_AUDIO_PROTOCOL_PHILLIPS;
+  i2s_init_struct->audio_sampling_freq = I2S_AUDIO_FREQUENCY_DEFAULT;
+  i2s_init_struct->data_channel_format = I2S_DATA_16BIT_CHANNEL_16BIT;
+  i2s_init_struct->clock_polarity = I2S_CLOCK_POLARITY_LOW;
+  i2s_init_struct->mclk_output_enable = FALSE;
+}
+
+/**
+  * @brief  i2s init config with its setting value.
+  * @param  spi_x: select the spi peripheral.
+  *         this parameter can be one of the following values:
+  *         SPI1, SPI2, SPI3 ,SPI4 , I2S2EXT, I2S3EXT
+  * @param  i2s_init_struct : pointer to a i2s_init_type structure which will be initialized.
+  * @retval none
+  */
+void i2s_init(spi_type* spi_x, i2s_init_type* i2s_init_struct)
+{
+  crm_clocks_freq_type clocks_freq;
+  uint32_t i2s_sclk_index = 0;
+  uint32_t i2sdiv_index = 2, i2sodd_index = 0, frequency_index = 0;
+
+  /* i2s audio frequency config */
+  if(i2s_init_struct->audio_sampling_freq == I2S_AUDIO_FREQUENCY_DEFAULT)
+  {
+    i2sodd_index = 0;
+    i2sdiv_index = 2;
+  }
+  else
+  {
+    crm_clocks_freq_get(&clocks_freq);
+    i2s_sclk_index = clocks_freq.sclk_freq;
+    if((i2s_init_struct->audio_protocol == I2S_AUDIO_PROTOCOL_PCM_SHORT) || (i2s_init_struct->audio_protocol == I2S_AUDIO_PROTOCOL_PCM_LONG))
+    {
+      if(i2s_init_struct->mclk_output_enable == TRUE)
+      {
+        frequency_index = (((i2s_sclk_index / 128) * 10) / i2s_init_struct->audio_sampling_freq) + 5;
+      }
+      else
+      {
+        if(i2s_init_struct->data_channel_format == I2S_DATA_16BIT_CHANNEL_16BIT)
+          frequency_index = (((i2s_sclk_index / 16) * 10) / i2s_init_struct->audio_sampling_freq) + 5;
+        else
+          frequency_index = (((i2s_sclk_index / 32) * 10) / i2s_init_struct->audio_sampling_freq) + 5;
+      }
+    }
+    else
+    {
+      if(i2s_init_struct->mclk_output_enable == TRUE)
+      {
+        frequency_index = (((i2s_sclk_index / 256) * 10) / i2s_init_struct->audio_sampling_freq) + 5;
+      }
+      else
+      {
+        if(i2s_init_struct->data_channel_format == I2S_DATA_16BIT_CHANNEL_16BIT)
+          frequency_index = (((i2s_sclk_index / 32) * 10) / i2s_init_struct->audio_sampling_freq) + 5;
+        else
+          frequency_index = (((i2s_sclk_index / 64) * 10) / i2s_init_struct->audio_sampling_freq) + 5;
+      }
+    }
+  }
+  frequency_index = frequency_index / 10;
+  i2sodd_index = frequency_index & (uint16_t)0x0001;
+  i2sdiv_index = (frequency_index - i2sodd_index) / 2;
+  if((i2sdiv_index < 2) || (i2sdiv_index > 0x03FF))
+  {
+    i2sodd_index = 0;
+    i2sdiv_index = 2;
+  }
+  spi_x->i2sclk_bit.i2sodd = i2sodd_index;
+  if(i2sdiv_index > 0x00FF)
+  {
+    spi_x->i2sclk_bit.i2sdiv_h = (i2sdiv_index >> 8) & 0x0003;
+    spi_x->i2sclk_bit.i2sdiv_l = i2sdiv_index & 0x00FF;
+  }
+  else
+  {
+    spi_x->i2sclk_bit.i2sdiv_h = 0;
+    spi_x->i2sclk_bit.i2sdiv_l = i2sdiv_index;
+  }
+
+  /* i2s audio_protocol set*/
+  if(i2s_init_struct->audio_protocol == I2S_AUDIO_PROTOCOL_PCM_LONG)
+  {
+    spi_x->i2sctrl_bit.pcmfssel = 1;
+    spi_x->i2sctrl_bit.stdsel = 3;
+  }
+  else if(i2s_init_struct->audio_protocol == I2S_AUDIO_PROTOCOL_PCM_SHORT)
+  {
+    spi_x->i2sctrl_bit.pcmfssel = 0;
+    spi_x->i2sctrl_bit.stdsel = 3;
+  }
+  else if(i2s_init_struct->audio_protocol == I2S_AUDIO_PROTOCOL_LSB)
+  {
+    spi_x->i2sctrl_bit.pcmfssel = 0;
+    spi_x->i2sctrl_bit.stdsel = 2;
+  }
+  else if(i2s_init_struct->audio_protocol == I2S_AUDIO_PROTOCOL_MSB)
+  {
+    spi_x->i2sctrl_bit.pcmfssel = 0;
+    spi_x->i2sctrl_bit.stdsel = 1;
+  }
+  else if(i2s_init_struct->audio_protocol == I2S_AUDIO_PROTOCOL_PHILLIPS)
+  {
+    spi_x->i2sctrl_bit.pcmfssel = 0;
+    spi_x->i2sctrl_bit.stdsel = 0;
+  }
+
+  /* i2s data_channel_format set*/
+  if(i2s_init_struct->data_channel_format == I2S_DATA_16BIT_CHANNEL_16BIT)
+  {
+    spi_x->i2sctrl_bit.i2scbn = 0;
+    spi_x->i2sctrl_bit.i2sdbn = 0;
+  }
+  else if(i2s_init_struct->data_channel_format == I2S_DATA_16BIT_CHANNEL_32BIT)
+  {
+    spi_x->i2sctrl_bit.i2scbn = 1;
+    spi_x->i2sctrl_bit.i2sdbn = 0;
+  }
+  else if(i2s_init_struct->data_channel_format == I2S_DATA_24BIT_CHANNEL_32BIT)
+  {
+    spi_x->i2sctrl_bit.i2scbn = 1;
+    spi_x->i2sctrl_bit.i2sdbn = 1;
+  }
+  else if(i2s_init_struct->data_channel_format == I2S_DATA_32BIT_CHANNEL_32BIT)
+  {
+    spi_x->i2sctrl_bit.i2scbn = 1;
+    spi_x->i2sctrl_bit.i2sdbn = 2;
+  }
+
+  spi_x->i2sctrl_bit.i2sclkpol = i2s_init_struct->clock_polarity;
+  spi_x->i2sclk_bit.i2smclkoe = i2s_init_struct->mclk_output_enable;
+  spi_x->i2sctrl_bit.opersel = i2s_init_struct->operation_mode;
+  spi_x->i2sctrl_bit.i2smsel = TRUE;
+}
+
+/**
+  * @brief  enable or disable i2s.
+  * @param  spi_x: select the i2s peripheral.
+  *         this parameter can be one of the following values:
+  *         SPI1, SPI2, SPI3 ,SPI4 , I2S2EXT, I2S3EXT
+  * @param  new_state: new state of i2s.
+  *         this parameter can be: TRUE or FALSE.
+  * @retval none
+  */
+void i2s_enable(spi_type* spi_x, confirm_state new_state)
+{
+  spi_x->i2sctrl_bit.i2sen = new_state;
+}
+
+/**
+  * @brief  enable or disable the specified spi/i2s interrupts.
+  * @param  spi_x: select the spi/i2s peripheral.
+  *         this parameter can be one of the following values:
+  *         SPI1, SPI2, SPI3 ,SPI4 , I2S2EXT, I2S3EXT
+  * @param  spi_i2s_int: specifies the spi/i2s interrupt sources to be enabled or disabled.
+  *         this parameter can be one of the following values:
+  *         - SPI_I2S_ERROR_INT
+  *         - SPI_I2S_RDBF_INT
+  *         - SPI_I2S_TDBE_INT
+  * @param  new_state: new state of the specified spi/i2s interrupts.
+  *         this parameter can be: TRUE or FALSE.
+  * @retval none
+  */
+void spi_i2s_interrupt_enable(spi_type* spi_x, uint32_t spi_i2s_int, confirm_state new_state)
+{
+  if(new_state != FALSE)
+  {
+    spi_x->ctrl2 |= spi_i2s_int;
+  }
+  else
+  {
+    spi_x->ctrl2 &= ~spi_i2s_int;
+  }
+}
+
+/**
+  * @brief  enable or disable the spi/i2s dma transmitter mode.
+  * @param  spi_x: select the spi/i2s peripheral.
+  *         this parameter can be one of the following values:
+  *         SPI1, SPI2, SPI3 ,SPI4 , I2S2EXT, I2S3EXT
+  * @param  new_state: new state of the dma request.
+  *         this parameter can be: TRUE or FALSE.
+  * @retval none
+  */
+void spi_i2s_dma_transmitter_enable(spi_type* spi_x, confirm_state new_state)
+{
+  spi_x->ctrl2_bit.dmaten = new_state;
+}
+
+/**
+  * @brief  enable or disable the spi/i2s dma receiver mode.
+  * @param  spi_x: select the spi/i2s peripheral.
+  *         this parameter can be one of the following values:
+  *         SPI1, SPI2, SPI3 ,SPI4 , I2S2EXT, I2S3EXT
+  * @param  new_state: new state of the dma request.
+  *         this parameter can be: TRUE or FALSE.
+  * @retval none
+  */
+void spi_i2s_dma_receiver_enable(spi_type* spi_x, confirm_state new_state)
+{
+  spi_x->ctrl2_bit.dmaren = new_state;
+}
+
+/**
+  * @brief  spi/i2s data transmit
+  * @param  spi_x: select the spi/i2s peripheral.
+  *         this parameter can be one of the following values:
+  *         SPI1, SPI2, SPI3 ,SPI4 , I2S2EXT, I2S3EXT
+  * @param  tx_data: the data to be transmit.
+  *         this parameter can be:
+  *         - (0x0000~0xFFFF)
+  * @retval none
+  */
+void spi_i2s_data_transmit(spi_type* spi_x, uint16_t tx_data)
+{
+  spi_x->dt = tx_data;
+}
+
+/**
+  * @brief  spi/i2s data receive
+  * @param  spi_x: select the spi/i2s peripheral.
+  *         this parameter can be one of the following values:
+  *         SPI1, SPI2, SPI3 ,SPI4 , I2S2EXT, I2S3EXT
+  * @retval the received data value
+  */
+uint16_t spi_i2s_data_receive(spi_type* spi_x)
+{
+  return (uint16_t)spi_x->dt;
+}
+
+/**
+  * @brief  get flag of the specified spi/i2s peripheral.
+  * @param  spi_x: select the spi/i2s peripheral.
+  *         this parameter can be one of the following values:
+  *         SPI1, SPI2, SPI3 ,SPI4 , I2S2EXT, I2S3EXT
+  * @param  spi_i2s_flag: select the spi/i2s flag
+  *         this parameter can be one of the following values:
+  *         - SPI_I2S_RDBF_FLAG
+  *         - SPI_I2S_TDBE_FLAG
+  *         - I2S_ACS_FLAG    (this flag only use in i2s mode)
+  *         - I2S_TUERR_FLAG  (this flag only use in i2s mode)
+  *         - SPI_CCERR_FLAG  (this flag only use in spi mode)
+  *         - SPI_MMERR_FLAG  (this flag only use in spi mode)
+  *         - SPI_I2S_ROERR_FLAG
+  *         - SPI_I2S_BF_FLAG
+  *         - SPI_CSPAS_FLAG
+  * @retval the new state of spi/i2s flag
+  */
+flag_status spi_i2s_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag)
+{
+  flag_status status = RESET;
+  if ((spi_x->sts & spi_i2s_flag) == RESET)
+  {
+    status = RESET;
+  }
+  else
+  {
+    status = SET;
+  }
+  return status;
+}
+
+/**
+  * @brief  clear flag of the specified spi/i2s peripheral.
+  * @param  spi_x: select the spi/i2s peripheral.
+  *         this parameter can be one of the following values:
+  *         SPI1, SPI2, SPI3 ,SPI4 , I2S2EXT, I2S3EXT
+  * @param  spi_i2s_flag: select the spi/i2s flag
+  *         this parameter can be one of the following values:
+  *         - SPI_CCERR_FLAG
+  *         - SPI_I2S_RDBF_FLAG
+  *         - I2S_TUERR_FLAG
+  *         - SPI_MMERR_FLAG
+  *         - SPI_I2S_ROERR_FLAG
+  *         - SPI_CSPAS_FLAG
+  * @note
+  *         SPI_I2S_TDBE_FLAG  this flag is cleared when the tx buffer already contain data to be transmit.
+  *         I2S_ACS_FLAG       this flag cann't cleared by software,the flag indicate the channel side(not use in pcm standard mode).
+  *         SPI_I2S_BF_FLAG    this flag cann't cleared by software, it's set and cleared by hardware.
+  * @retval none
+  */
+void spi_i2s_flag_clear(spi_type* spi_x, uint32_t spi_i2s_flag)
+{
+  if(spi_i2s_flag == SPI_CCERR_FLAG)
+    spi_x->sts = ~SPI_CCERR_FLAG;
+  else if(spi_i2s_flag == SPI_I2S_RDBF_FLAG)
+    UNUSED(spi_x->dt);
+  else if(spi_i2s_flag == I2S_TUERR_FLAG)
+    UNUSED(spi_x->sts);
+  else if(spi_i2s_flag == SPI_CSPAS_FLAG)
+    UNUSED(spi_x->sts);
+  else if(spi_i2s_flag == SPI_MMERR_FLAG)
+  {
+    UNUSED(spi_x->sts);
+    spi_x->ctrl1 = spi_x->ctrl1;
+  }
+  else if(spi_i2s_flag == SPI_I2S_ROERR_FLAG)
+  {
+    UNUSED(spi_x->dt);
+    UNUSED(spi_x->sts);
+  }
+}
+
+/**
+  * @}
+  */
+
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */

lib/main/AT32F43x/Drivers/AT32F43x_StdPeriph_Driver/src/at32f435_437_usart.c

@@ -0,0 +1,732 @@
+/**
+  **************************************************************************
+  * @file     at32f435_437_usart.c
+  * @version  v2.1.0
+  * @date     2022-08-16
+  * @brief    contains all the functions for the usart firmware library
+  **************************************************************************
+  *                       Copyright notice & Disclaimer
+  *
+  * The software Board Support Package (BSP) that is made available to
+  * download from Artery official website is the copyrighted work of Artery.
+  * Artery authorizes customers to use, copy, and distribute the BSP
+  * software and its related documentation for the purpose of design and
+  * development in conjunction with Artery microcontrollers. Use of the
+  * software is governed by this copyright notice and the following disclaimer.
+  *
+  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+  *
+  **************************************************************************
+  */
+
+/* includes ------------------------------------------------------------------*/
+#include "at32f435_437_conf.h"
+
+/** @addtogroup AT32F435_437_periph_driver
+  * @{
+  */
+
+/** @defgroup USART
+  * @brief USART driver modules
+  * @{
+  */
+
+#ifdef USART_MODULE_ENABLED
+
+/** @defgroup USART_private_functions
+  * @{
+  */
+
+/**
+  * @brief  deinitialize the usart peripheral registers to their default reset values.
+  * @param  usart_x: select the usart or the uart peripheral.
+  *         this parameter can be one of the following values:
+  *         USART1, USART2, USART3, UART4, UART5, USART6, UART7,or UART8.
+  * @retval none
+  */
+void usart_reset(usart_type* usart_x)
+{
+  if(usart_x == USART1)
+  {
+    crm_periph_reset(CRM_USART1_PERIPH_RESET, TRUE);
+    crm_periph_reset(CRM_USART1_PERIPH_RESET, FALSE);
+  }
+  else if(usart_x == USART2)
+  {
+    crm_periph_reset(CRM_USART2_PERIPH_RESET, TRUE);
+    crm_periph_reset(CRM_USART2_PERIPH_RESET, FALSE);
+  }
+  else if(usart_x == USART3)
+  {
+    crm_periph_reset(CRM_USART3_PERIPH_RESET, TRUE);
+    crm_periph_reset(CRM_USART3_PERIPH_RESET, FALSE);
+  }
+  else if(usart_x == UART4)
+  {
+    crm_periph_reset(CRM_UART4_PERIPH_RESET, TRUE);
+    crm_periph_reset(CRM_UART4_PERIPH_RESET, FALSE);
+  }
+  else if(usart_x == UART5)
+  {
+    crm_periph_reset(CRM_UART5_PERIPH_RESET, TRUE);
+    crm_periph_reset(CRM_UART5_PERIPH_RESET, FALSE);
+  }
+  else if(usart_x == USART6)
+  {
+    crm_periph_reset(CRM_USART6_PERIPH_RESET, TRUE);
+    crm_periph_reset(CRM_USART6_PERIPH_RESET, FALSE);
+  }
+  else if(usart_x == UART7)
+  {
+    crm_periph_reset(CRM_UART7_PERIPH_RESET, TRUE);
+    crm_periph_reset(CRM_UART7_PERIPH_RESET, FALSE);
+  }
+  else if(usart_x == UART8)
+  {
+    crm_periph_reset(CRM_UART8_PERIPH_RESET, TRUE);
+    crm_periph_reset(CRM_UART8_PERIPH_RESET, FALSE);
+  }
+}
+
+/**
+  * @brief  initialize the usart peripheral according to the specified parameters.
+  * @param  usart_x: select the usart or the uart peripheral.
+  *         this parameter can be one of the following values:
+  *         USART1, USART2, USART3, UART4 ,UART5, USART6, UART7 or UART8.
+  * @param  baud_rate: configure the usart communication baud rate.
+  * @param  data_bit: data bits transmitted or received in a frame
+  *         this parameter can be one of the following values:
+  *         - USART_DATA_7BITS
+  *         - USART_DATA_8BITS
+  *         - USART_DATA_9BITS.
+  * @param  stop_bit: stop bits transmitted
+  *         this parameter can be one of the following values:
+  *         - USART_STOP_1_BIT
+  *         - USART_STOP_0_5_BIT.
+  *         - USART_STOP_2_BIT
+  *         - USART_STOP_1_5_BIT.
+  * @retval none
+  */
+void usart_init(usart_type* usart_x, uint32_t baud_rate, usart_data_bit_num_type data_bit, usart_stop_bit_num_type stop_bit)
+{
+  crm_clocks_freq_type clocks_freq;
+  uint32_t apb_clock, temp_val;
+  crm_clocks_freq_get(&clocks_freq);
+  if((usart_x == USART1) || (usart_x == USART6))
+  {
+    apb_clock = clocks_freq.apb2_freq;
+  }
+  else
+  {
+    apb_clock = clocks_freq.apb1_freq;
+  }
+  temp_val = (apb_clock * 10 / baud_rate);
+  if((temp_val % 10) < 5)
+  {
+    temp_val = (temp_val / 10);
+  }
+  else
+  {
+    temp_val = (temp_val / 10) + 1;
+  }
+  usart_x->baudr_bit.div = temp_val;
+  if(data_bit == USART_DATA_7BITS)
+  {
+    usart_x->ctrl1_bit.dbn_h = 1;
+    usart_x->ctrl1_bit.dbn_l = 0;
+  }
+  else if(data_bit == USART_DATA_8BITS)
+  {
+    usart_x->ctrl1_bit.dbn_h = 0;
+    usart_x->ctrl1_bit.dbn_l = 0;
+  }
+  else
+  {
+    usart_x->ctrl1_bit.dbn_h = 0;
+    usart_x->ctrl1_bit.dbn_l = 1;
+  }
+  usart_x->ctrl2_bit.stopbn = stop_bit;
+}
+
+/**
+  * @brief  usart parity selection config.
+  * @param  usart_x: select the usart or the uart peripheral.
+  *         this parameter can be one of the following values:
+  *         USART1, USART2, USART3, UART4 ,UART5, USART6, UART7 or UART8.
+  * @param  parity: select the none, odd or even parity.
+  *         this parameter can be one of the following values:
+  *         - USART_PARITY_NONE
+  *         - USART_PARITY_EVEN.
+  *         - USART_PARITY_ODD
+  * @retval none
+  */
+void usart_parity_selection_config(usart_type* usart_x, usart_parity_selection_type parity)
+{
+  if(parity == USART_PARITY_NONE)
+  {
+    usart_x->ctrl1_bit.psel = FALSE;
+    usart_x->ctrl1_bit.pen = FALSE;
+  }
+  else if(parity == USART_PARITY_EVEN)
+  {
+    usart_x->ctrl1_bit.psel = FALSE;
+    usart_x->ctrl1_bit.pen = TRUE;
+  }
+  else if(parity == USART_PARITY_ODD)
+  {
+    usart_x->ctrl1_bit.psel = TRUE;
+    usart_x->ctrl1_bit.pen = TRUE;
+  }
+}
+
+/**
+  * @brief  enable or disable the specified usart peripheral.
+  * @param  usart_x: select the usart or the uart peripheral.
+  *         this parameter can be one of the following values:
+  *         USART1, USART2, USART3, UART4, UART5, USART6, UART7 or UART8.
+  * @param  new_state: new state of the usart peripheral.
+  *         this parameter can be: TRUE or FALSE.
+  * @retval none
+  */
+void usart_enable(usart_type* usart_x, confirm_state new_state)
+{
+  usart_x->ctrl1_bit.uen = new_state;
+}
+
+/**
+  * @brief  usart transmitter enable.
+  * @param  usart_x: select the usart or the uart peripheral.
+  *         this parameter can be one of the following values:
+  *         USART1, USART2, USART3, UART4 ,UART5, USART6, UART7 or UART8.
+  * @param  new_state: TRUE or FALSE.
+  * @retval none
+  */
+void usart_transmitter_enable(usart_type* usart_x, confirm_state new_state)
+{
+  usart_x->ctrl1_bit.ten = new_state;
+}
+
+/**
+  * @brief  usart receiver enable.
+  * @param  usart_x: select the usart or the uart peripheral.
+  *         this parameter can be one of the following values:
+  *         USART1, USART2, USART3, UART4 ,UART5, USART6, UART7 or UART8.
+  * @param  new_state: TRUE or FALSE.
+  * @retval none
+  */
+void usart_receiver_enable(usart_type* usart_x, confirm_state new_state)
+{
+  usart_x->ctrl1_bit.ren = new_state;
+}
+
+/**
+  * @brief  usart clock config.
+  * @note   clock config are not available for UART4, UART5, UART7 and UART8.
+  * @param  usart_x: select the usart or the uart peripheral.
+  *         this parameter can be one of the following values:
+  *         USART1, USART2, USART3 or USART6.
+  * @param  clk_pol: polarity of the clock output on the ck pin.
+  *         this parameter can be one of the following values:
+  *         - USART_CLOCK_POLARITY_LOW
+  *         - USART_CLOCK_POLARITY_HIGH
+  * @param  clk_pha: phase of the clock output on the ck pin.
+  *         this parameter can be one of the following values:
+  *         - USART_CLOCK_PHASE_1EDGE
+  *         - USART_CLOCK_PHASE_2EDGE
+  * @param  clk_lb: whether the clock pulse of the last data bit transmitted (MSB) is outputted on the ck pin.
+  *         this parameter can be one of the following values:
+  *         - USART_CLOCK_LAST_BIT_NONE
+  *         - USART_CLOCK_LAST_BIT_OUTPUT
+  * @retval none
+  */
+void usart_clock_config(usart_type* usart_x, usart_clock_polarity_type clk_pol, usart_clock_phase_type clk_pha, usart_lbcp_type clk_lb)
+{
+  usart_x->ctrl2_bit.clkpol = clk_pol;
+  usart_x->ctrl2_bit.clkpha = clk_pha;
+  usart_x->ctrl2_bit.lbcp = clk_lb;
+}
+
+/**
+  * @brief  usart enable the ck pin.
+  * @note   clock enable are not available for UART4, UART5, UART7 and UART8.
+  * @param  usart_x: select the usart or the uart peripheral.
+  *         this parameter can be one of the following values:
+  *         USART1, USART2, USART3 or USART6.
+  * @param  new_state: TRUE or FALSE
+  * @retval none
+  */
+void usart_clock_enable(usart_type* usart_x, confirm_state new_state)
+{
+  usart_x->ctrl2_bit.clken = new_state;
+}
+
+/**
+  * @brief  enable or disable the specified usart interrupts.
+  * @param  usart_x: select the usart or the uart peripheral.
+  *         this parameter can be one of the following values:
+  *         USART1, USART2, USART3, UART4, UART5, USART6, UART7 or UART8.
+  * @param  usart_int: specifies the USART interrupt sources to be enabled or disabled.
+  *         this parameter can be one of the following values:
+  *         - USART_IDLE_INT:  idle interrupt
+  *         - USART_RDBF_INT:  rdbf interrupt
+  *         - USART_TDC_INT:   tdc interrupt
+  *         - USART_TDBE_INT:  tdbe interrupt
+  *         - USART_PERR_INT:  perr interrupt
+  *         - USART_BF_INT:    break frame interrupt
+  *         - USART_ERR_INT:   err interrupt
+  *         - USART_CTSCF_INT: ctscf interrupt
+  * @param  new_state: new state of the specified usart interrupts.
+  *         this parameter can be: TRUE or FALSE.
+  * @retval none
+  */
+void usart_interrupt_enable(usart_type* usart_x, uint32_t usart_int, confirm_state new_state)
+{
+  if(new_state == TRUE)
+    PERIPH_REG((uint32_t)usart_x, usart_int) |= PERIPH_REG_BIT(usart_int);
+  else
+    PERIPH_REG((uint32_t)usart_x, usart_int) &= ~PERIPH_REG_BIT(usart_int);
+}
+
+/**
+  * @brief  enable or disable the usart's dma transmitter interface.
+  * @param  usart_x: select the usart or the uart peripheral.
+  *         this parameter can be one of the following values:
+  *         USART1, USART2, USART3, UART4, UART5, USART6, UART7 or UART8.
+  * @param  new_state: new state of the dma request sources.
+  *         this parameter can be: TRUE or FALSE.
+  * @retval none
+  */
+void usart_dma_transmitter_enable(usart_type* usart_x, confirm_state new_state)
+{
+  usart_x->ctrl3_bit.dmaten = new_state;
+}
+
+/**
+  * @brief  enable or disable the usart's dma receiver interface.
+  * @param  usart_x: select the usart or the uart peripheral.
+  *         this parameter can be one of the following values:
+  *         USART1, USART2, USART3, UART4, UART5, USART6, UART7 or UART8.
+  * @param  new_state: new state of the dma request sources.
+  *         this parameter can be: TRUE or FALSE.
+  * @retval none
+  */
+void usart_dma_receiver_enable(usart_type* usart_x, confirm_state new_state)
+{
+  usart_x->ctrl3_bit.dmaren = new_state;
+}
+
+/**
+  * @brief  set the wakeup id of the usart.
+  * @param  usart_x: select the usart or the uart peripheral.
+  *         this parameter can be one of the following values:
+  *         USART1, USART2, USART3, UART4, UART5, USART6, UART7 or UART8.
+  * @param  usart_id: the matching id(0x0~0xFF).
+  * @retval none
+  */
+void usart_wakeup_id_set(usart_type* usart_x, uint8_t usart_id)
+{
+  if(usart_x->ctrl2_bit.idbn == USART_ID_FIXED_4_BIT)
+  {
+    usart_x->ctrl2_bit.id_l = (usart_id & 0x0F);
+    usart_x->ctrl2_bit.id_h = 0;
+  }
+  else
+  {
+    usart_x->ctrl2_bit.id_l = (usart_id & 0x0F);
+    usart_x->ctrl2_bit.id_h = ((usart_id & 0xF0) >> 4);
+  }
+}
+
+/**
+  * @brief  select the usart wakeup method in multi-processor communication.
+  * @param  usart_x: select the usart or the uart peripheral.
+  *         this parameter can be one of the following values:
+  *         USART1, USART2, USART3, UART4, UART5, USART6, UART7 or UART8.
+  * @param  wakeup_mode: determines the way to wake up usart method.
+  *         this parameter can be one of the following values:
+  *         - USART_WAKEUP_BY_IDLE_FRAME
+  *         - USART_WAKEUP_BY_MATCHING_ID
+  * @retval none
+  */
+void usart_wakeup_mode_set(usart_type* usart_x, usart_wakeup_mode_type wakeup_mode)
+{
+  usart_x->ctrl1_bit.wum = wakeup_mode;
+}
+
+/**
+  * @brief  config the usart in mute mode in multi-processor communication.
+  * @param  usart_x: select the usart or the uart peripheral.
+  *         this parameter can be one of the following values:
+  *         USART1, USART2, USART3, UART4, UART5, USART6, UART7 or UART8.
+  * @param  new_state: new state of the usart mute mode.
+  *         this parameter can be: TRUE or FALSE.
+  * @retval none
+  */
+void usart_receiver_mute_enable(usart_type* usart_x, confirm_state new_state)
+{
+  usart_x->ctrl1_bit.rm = new_state;
+}
+
+/**
+  * @brief  set the usart break frame bit num.
+  * @param  usart_x: select the usart or the uart peripheral.
+  *         this parameter can be one of the following values:
+  *         USART1, USART2, USART3, UART4, UART5, USART6, UART7 or UART8.
+  * @param  break_bit: specifies the break bit num.
+  *         this parameter can be one of the following values:
+  *         - USART_BREAK_10BITS
+  *         - USART_BREAK_11BITS
+  * @retval none
+  */
+void usart_break_bit_num_set(usart_type* usart_x, usart_break_bit_num_type break_bit)
+{
+  usart_x->ctrl2_bit.bfbn = break_bit;
+}
+
+/**
+  * @brief  enable or disable the usart lin mode.
+  * @param  usart_x: select the usart or the uart peripheral.
+  *         this parameter can be one of the following values:
+  *         USART1, USART2, USART3, UART4, UART5, USART6, UART7 or UART8.
+  * @param  new_state: new state of the usart lin mode.
+  *         this parameter can be: TRUE or FALSE.
+  * @retval none
+  */
+void usart_lin_mode_enable(usart_type* usart_x, confirm_state new_state)
+{
+  usart_x->ctrl2_bit.linen = new_state;
+}
+
+/**
+  * @brief  transmit single data through the usart peripheral.
+  * @param  usart_x: select the usart or the uart peripheral.
+  *         this parameter can be one of the following values:
+  *         USART1, USART2, USART3, UART4, UART5, USART6, UART7 or UART8.
+  * @param  data: the data to transmit.
+  * @retval none
+  */
+void usart_data_transmit(usart_type* usart_x, uint16_t data)
+{
+  usart_x->dt = (data & 0x01FF);
+}
+
+/**
+  * @brief  return the most recent received data by the usart peripheral.
+  * @param  usart_x: select the usart or the uart peripheral.
+  *         this parameter can be one of the following values:
+  *         USART1, USART2, USART3, UART4, UART5, USART6, UART7 or UART8.
+  * @retval the received data.
+  */
+uint16_t usart_data_receive(usart_type* usart_x)
+{
+  return (uint16_t)(usart_x->dt);
+}
+
+/**
+  * @brief  transmit break characters.
+  * @param  usart_x: select the usart or the uart peripheral.
+  *         this parameter can be one of the following values:
+  *         USART1, USART2, USART3, UART4, UART5, USART6, UART7 or UART8.
+  * @retval none
+  */
+void usart_break_send(usart_type* usart_x)
+{
+  usart_x->ctrl1_bit.sbf = TRUE;
+}
+
+/**
+  * @brief  config the specified usart smartcard guard time.
+  * @note   The guard time bits are not available for UART4, UART5, UART7 or UART8.
+  * @param  usart_x: select the usart or the uart peripheral.
+  *         this parameter can be one of the following values:
+  *         USART1, USART2, USART3 or USART6.
+  * @param  guard_time_val: specifies the guard time (0x00~0xFF).
+  * @retval none
+  */
+void usart_smartcard_guard_time_set(usart_type* usart_x, uint8_t guard_time_val)
+{
+  usart_x->gdiv_bit.scgt = guard_time_val;
+}
+
+/**
+  * @brief  config the irda/smartcard division.
+  * @note   the division are not available for UART4, UART5, UART7 or UART8.
+  * @param  usart_x: select the usart or the uart peripheral.
+  *         this parameter can be one of the following values:
+  *         USART1, USART2, USART3 or USART6.
+  * @param  div_val: specifies the division.
+  * @retval none
+  */
+void usart_irda_smartcard_division_set(usart_type* usart_x, uint8_t div_val)
+{
+  usart_x->gdiv_bit.isdiv = div_val;
+}
+
+/**
+  * @brief  enable or disable the usart smart card mode.
+  * @note   the smart card mode are not available for UART4, UART5, UART7 or UART8.
+  * @param  usart_x: select the usart or the uart peripheral.
+  *         this parameter can be one of the following values:
+  *         USART1, USART2, USART3 or USART6.
+  * @param  new_state: new state of the smart card mode.
+  *         this parameter can be: TRUE or FALSE.
+  * @retval none
+  */
+void usart_smartcard_mode_enable(usart_type* usart_x, confirm_state new_state)
+{
+  usart_x->ctrl3_bit.scmen = new_state;
+}
+
+/**
+  * @brief  enable or disable nack transmission in smartcard mode.
+  * @note   the smart card nack are not available for UART4, UART5, UART7 or UART8.
+  * @param  usart_x: select the usart or the uart peripheral.
+  *         this parameter can be one of the following values:
+  *         USART1, USART2, USART3 or USART6.
+  * @param  new_state: new state of the nack transmission.
+  *         this parameter can be: TRUE or FALSE.
+  * @retval none
+  */
+void usart_smartcard_nack_set(usart_type* usart_x, confirm_state new_state)
+{
+  usart_x->ctrl3_bit.scnacken = new_state;
+}
+
+/**
+  * @brief  enable or disable the usart single line bidirectional half-duplex communication.
+  * @param  usart_x: select the usart or the uart peripheral.
+  *         this parameter can be one of the following values:
+  *         USART1, USART2, USART3, UART4, UART5, USART6, UART7 or UART8.
+  * @param  new_state: new state of the single line half-duplex select.
+  *         this parameter can be: TRUE or FALSE.
+  * @retval none
+  */
+void usart_single_line_halfduplex_select(usart_type* usart_x, confirm_state new_state)
+{
+  usart_x->ctrl3_bit.slben = new_state;
+}
+
+/**
+  * @brief  enable or disable the usart's irda interface.
+  * @param  usart_x: select the usart or the uart peripheral.
+  *         this parameter can be one of the following values:
+  *         USART1, USART2, USART3, UART4, UART5, USART6, UART7 or UART8.
+  * @param  new_state: new state of the irda mode.
+  *         this parameter can be: TRUE or FALSE.
+  * @retval none
+  */
+void usart_irda_mode_enable(usart_type* usart_x, confirm_state new_state)
+{
+  usart_x->ctrl3_bit.irdaen = new_state;
+}
+
+/**
+  * @brief  configure the usart's irda low power.
+  * @param  usart_x: select the usart or the uart peripheral.
+  *         this parameter can be one of the following values:
+  *         USART1, USART2, USART3, UART4, UART5, USART6, UART7 or UART8.
+  * @param  new_state: new state of the irda mode.
+  *         this parameter can be: TRUE or FALSE.
+  * @retval none
+  */
+void usart_irda_low_power_enable(usart_type* usart_x, confirm_state new_state)
+{
+  usart_x->ctrl3_bit.irdalp = new_state;
+}
+
+/**
+  * @brief  configure the usart's hardware flow control.
+  * @param  usart_x: select the usart or the uart peripheral.
+  *         this parameter can be one of the following values:
+  *         USART1, USART2, USART3
+  * @param  flow_state: specifies the hardware flow control.
+  *         this parameter can be one of the following values:
+  *         - USART_HARDWARE_FLOW_NONE
+  *         - USART_HARDWARE_FLOW_RTS,
+  *         - USART_HARDWARE_FLOW_CTS,
+  *         - USART_HARDWARE_FLOW_RTS_CTS
+  * @retval none
+  */
+void usart_hardware_flow_control_set(usart_type* usart_x,usart_hardware_flow_control_type flow_state)
+{
+  if(flow_state == USART_HARDWARE_FLOW_NONE)
+  {
+    usart_x->ctrl3_bit.rtsen = FALSE;
+    usart_x->ctrl3_bit.ctsen = FALSE;
+  }
+  else if(flow_state == USART_HARDWARE_FLOW_RTS)
+  {
+    usart_x->ctrl3_bit.rtsen = TRUE;
+    usart_x->ctrl3_bit.ctsen = FALSE;
+  }
+  else if(flow_state == USART_HARDWARE_FLOW_CTS)
+  {
+    usart_x->ctrl3_bit.rtsen = FALSE;
+    usart_x->ctrl3_bit.ctsen = TRUE;
+  }
+  else if(flow_state == USART_HARDWARE_FLOW_RTS_CTS)
+  {
+    usart_x->ctrl3_bit.rtsen = TRUE;
+    usart_x->ctrl3_bit.ctsen = TRUE;
+  }
+}
+
+/**
+  * @brief  check whether the specified usart flag is set or not.
+  * @param  usart_x: select the usart or the uart peripheral.
+  *         this parameter can be one of the following values:
+  *         USART1, USART2, USART3, UART4, UART5, USART6, UART7 or UART8.
+  * @param  flag: specifies the flag to check.
+  *         this parameter can be one of the following values:
+  *         - USART_CTSCF_FLAG: cts change flag (not available for UART4,UART5,USART6,UART7 and UART8)
+  *         - USART_BFF_FLAG:   break frame flag
+  *         - USART_TDBE_FLAG:  transmit data buffer empty flag
+  *         - USART_TDC_FLAG:   transmit data complete flag
+  *         - USART_RDBF_FLAG:  receive data buffer full flag
+  *         - USART_IDLEF_FLAG: idle flag
+  *         - USART_ROERR_FLAG: receiver overflow error flag
+  *         - USART_NERR_FLAG:  noise error flag
+  *         - USART_FERR_FLAG:  framing error flag
+  *         - USART_PERR_FLAG:  parity error flag
+  * @retval the new state of usart_flag (SET or RESET).
+  */
+flag_status usart_flag_get(usart_type* usart_x, uint32_t flag)
+{
+  if(usart_x->sts & flag)
+  {
+    return SET;
+  }
+  else
+  {
+    return RESET;
+  }
+}
+
+/**
+  * @brief  clear the usart's pending flags.
+  * @param  usart_x: select the usart or the uart peripheral.
+  *         this parameter can be one of the following values:
+  *         USART1, USART2, USART3, UART4, UART5, USART6, UART7 or UART8.
+  * @param  flag: specifies the flag to clear.
+  *         this parameter can be any combination of the following values:
+  *         - USART_CTSCF_FLAG: (not available for UART4,UART5,USART6,UART7 and UART8).
+  *         - USART_BFF_FLAG:
+  *         - USART_TDC_FLAG:
+  *         - USART_RDBF_FLAG:
+  *         - USART_PERR_FLAG:
+  *         - USART_FERR_FLAG:
+  *         - USART_NERR_FLAG:
+  *         - USART_ROERR_FLAG:
+  *         - USART_IDLEF_FLAG:
+  * @note
+  *         - USART_PERR_FLAG, USART_FERR_FLAG, USART_NERR_FLAG, USART_ROERR_FLAG and USART_IDLEF_FLAG are cleared by software
+  *           sequence: a read operation to usart sts register (usart_flag_get())
+  *           followed by a read operation to usart dt register (usart_data_receive()).
+  *         - USART_RDBF_FLAG can be also cleared by a read to the usart dt register(usart_data_receive()).
+  *         - USART_TDC_FLAG can be also cleared by software sequence: a read operation to usart sts register (usart_flag_get())
+  *           followed by a write operation to usart dt register (usart_data_transmit()).
+  *         - USART_TDBE_FLAG is cleared only by a write to the usart dt register(usart_data_transmit()).
+  * @retval none
+  */
+void usart_flag_clear(usart_type* usart_x, uint32_t flag)
+{
+  if(flag & (USART_PERR_FLAG | USART_FERR_FLAG | USART_NERR_FLAG | USART_ROERR_FLAG | USART_IDLEF_FLAG))
+  {
+    UNUSED(usart_x->sts);
+    UNUSED(usart_x->dt);
+  }
+  else
+  {
+    usart_x->sts = ~flag;
+  }
+}
+
+/**
+  * @brief  configure the usart's rs485 transmit delay time.
+  * @param  usart_x: select the usart or the uart peripheral.
+  *         this parameter can be one of the following values:
+  *         USART1, USART2, USART3
+  * @param  start_delay_time: transmit start delay time.
+  * @param  complete_delay_time: transmit complete delay time.
+  * @retval none
+  */
+void usart_rs485_delay_time_config(usart_type* usart_x, uint8_t start_delay_time, uint8_t complete_delay_time)
+{
+  usart_x->ctrl1_bit.tsdt = start_delay_time;
+  usart_x->ctrl1_bit.tcdt = complete_delay_time;
+}
+
+/**
+  * @brief  swap the usart's transmit receive pin.
+  * @param  usart_x: select the usart or the uart peripheral.
+  *         this parameter can be one of the following values:
+  *         USART1, USART2, USART3, UART4, UART5, USART6, UART7,or UART8.
+  * @param  new_state: new state of the usart peripheral.
+  *         this parameter can be: TRUE or FALSE.
+  * @retval none
+  */
+void usart_transmit_receive_pin_swap(usart_type* usart_x, confirm_state new_state)
+{
+  usart_x->ctrl2_bit.trpswap = new_state;
+}
+
+/**
+  * @brief  set the usart's identification bit num.
+  * @param  usart_x: select the usart or the uart peripheral.
+  *         this parameter can be one of the following values:
+  *         USART1, USART2, USART3, UART4, UART5, USART6, UART7,or UART8.
+  * @param  id_bit_num: the usart wakeup identification bit num.
+  *         this parameter can be: USART_ID_FIXED_4_BIT or USART_ID_RELATED_DATA_BIT.
+  * @retval none
+  */
+void usart_id_bit_num_set(usart_type* usart_x, usart_identification_bit_num_type id_bit_num)
+{
+  usart_x->ctrl2_bit.idbn = (uint8_t)id_bit_num;
+}
+
+/**
+  * @brief  set the usart's de polarity.
+  * @param  usart_x: select the usart or the uart peripheral.
+  *         this parameter can be one of the following values:
+  *         USART1, USART2, USART3
+  * @param  de_polarity: the usart de polarity selection.
+  *         this parameter can be: USART_DE_POLARITY_HIGH or USART_DE_POLARITY_LOW.
+  * @retval none
+  */
+void usart_de_polarity_set(usart_type* usart_x, usart_de_polarity_type de_polarity)
+{
+  usart_x->ctrl3_bit.dep = (uint8_t)de_polarity;
+}
+
+/**
+  * @brief  enable or disable the usart's rs485 mode.
+  * @param  usart_x: select the usart or the uart peripheral.
+  *         this parameter can be one of the following values:
+  *         USART1, USART2, USART3
+  * @param  new_state: new state of the irda mode.
+  *         this parameter can be: TRUE or FALSE.
+  * @retval none
+  */
+void usart_rs485_mode_enable(usart_type* usart_x, confirm_state new_state)
+{
+  usart_x->ctrl3_bit.rs485en = new_state;
+}
+
+/**
+  * @}
+  */
+
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */

lib/main/AT32F43x/Drivers/AT32F43x_StdPeriph_Driver/src/at32f435_437_wdt.c

@@ -0,0 +1,156 @@
+/**
+  **************************************************************************
+  * @file     at32f435_437_wdt.c
+  * @version  v2.1.0
+  * @date     2022-08-16
+  * @brief    contains all the functions for the wdt firmware library
+  **************************************************************************
+  *                       Copyright notice & Disclaimer
+  *
+  * The software Board Support Package (BSP) that is made available to
+  * download from Artery official website is the copyrighted work of Artery.
+  * Artery authorizes customers to use, copy, and distribute the BSP
+  * software and its related documentation for the purpose of design and
+  * development in conjunction with Artery microcontrollers. Use of the
+  * software is governed by this copyright notice and the following disclaimer.
+  *
+  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+  *
+  **************************************************************************
+  */
+
+#include "at32f435_437_conf.h"
+
+/** @addtogroup AT32F435_437_periph_driver
+  * @{
+  */
+
+/** @defgroup WDT
+  * @brief WDT driver modules
+  * @{
+  */
+
+#ifdef WDT_MODULE_ENABLED
+
+/** @defgroup WDT_private_functions
+  * @{
+  */
+
+/**
+  * @brief  wdt enable ,the reload value will be sent to the counter
+  * @param  none
+  * @retval none
+  */
+void wdt_enable(void)
+{
+  WDT->cmd = WDT_CMD_ENABLE;
+}
+
+/**
+  * @brief  reload wdt counter
+  * @param  none
+  * @retval none
+  */
+void wdt_counter_reload(void)
+{
+  WDT->cmd = WDT_CMD_RELOAD;
+}
+
+/**
+  * @brief  set wdt counter reload value
+  * @param  reload_value (0x0000~0x0FFF)
+  * @retval none
+  */
+void wdt_reload_value_set(uint16_t reload_value)
+{
+  WDT->rld = reload_value;
+}
+
+/**
+  * @brief  set wdt division divider
+  * @param  division
+  *         this parameter can be one of the following values:
+  *         - WDT_CLK_DIV_4
+  *         - WDT_CLK_DIV_8
+  *         - WDT_CLK_DIV_16
+  *         - WDT_CLK_DIV_32
+  *         - WDT_CLK_DIV_64
+  *         - WDT_CLK_DIV_128
+  *         - WDT_CLK_DIV_256
+  * @retval none
+  */
+void wdt_divider_set(wdt_division_type division)
+{
+  WDT->div_bit.div = division;
+}
+
+/**
+  * @brief  enable or disable wdt cmd register write
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void wdt_register_write_enable( confirm_state new_state)
+{
+  if(new_state == FALSE)
+  {
+    WDT->cmd = WDT_CMD_LOCK;
+  }
+  else
+  {
+    WDT->cmd = WDT_CMD_UNLOCK;
+  }
+}
+
+/**
+  * @brief  get wdt flag
+  * @param  wdt_flag
+  *         this parameter can be one of the following values:
+  *         - WDT_DIVF_UPDATE_FLAG: division value update complete flag.
+  *         - WDT_RLDF_UPDATE_FLAG: reload value update complete flag.
+  *         - WDT_WINF_UPDATE_FLAG: window value update complete flag.
+  * @retval state of wdt flag
+  */
+flag_status wdt_flag_get(uint16_t wdt_flag)
+{
+  flag_status status = RESET;
+
+  if ((WDT->sts & wdt_flag) != (uint16_t)RESET)
+  {
+    status = SET;
+  }
+  else
+  {
+    status = RESET;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  wdt window counter value set
+  * @param  window_cnt (0x0000~0x0FFF)
+  * @retval none
+  */
+void wdt_window_counter_set(uint16_t window_cnt)
+{
+  WDT->win_bit.win = window_cnt;
+}
+
+/**
+  * @}
+  */
+
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */

lib/main/AT32F43x/Drivers/AT32F43x_StdPeriph_Driver/src/at32f435_437_wwdt.c

@@ -0,0 +1,141 @@
+/**
+  **************************************************************************
+  * @file     at32f435_437_wwdt.c
+  * @version  v2.1.0
+  * @date     2022-08-16
+  * @brief    contains all the functions for the wwdt firmware library
+  **************************************************************************
+  *                       Copyright notice & Disclaimer
+  *
+  * The software Board Support Package (BSP) that is made available to
+  * download from Artery official website is the copyrighted work of Artery.
+  * Artery authorizes customers to use, copy, and distribute the BSP
+  * software and its related documentation for the purpose of design and
+  * development in conjunction with Artery microcontrollers. Use of the
+  * software is governed by this copyright notice and the following disclaimer.
+  *
+  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+  *
+  **************************************************************************
+  */
+
+#include "at32f435_437_conf.h"
+
+/** @addtogroup AT32F435_437_periph_driver
+  * @{
+  */
+
+/** @defgroup WWDT
+  * @brief WWDT driver modules
+  * @{
+  */
+
+#ifdef WWDT_MODULE_ENABLED
+
+/** @defgroup WWDT_private_functions
+  * @{
+  */
+
+/**
+  * @brief  wwdt reset by crm reset register
+  * @retval none
+  */
+void wwdt_reset(void)
+{
+  crm_periph_reset(CRM_WWDT_PERIPH_RESET, TRUE);
+  crm_periph_reset(CRM_WWDT_PERIPH_RESET, FALSE);
+}
+
+/**
+  * @brief  wwdt division set
+  * @param  division
+  *         this parameter can be one of the following values:
+  *         - WWDT_PCLK1_DIV_4096        (wwdt counter clock = (pclk1/4096)/1)
+  *         - WWDT_PCLK1_DIV_8192        (wwdt counter clock = (pclk1/4096)/2)
+  *         - WWDT_PCLK1_DIV_16384       (wwdt counter clock = (pclk1/4096)/4)
+  *         - WWDT_PCLK1_DIV_32768       (wwdt counter clock = (pclk1/4096)/8)
+  * @retval none
+  */
+void wwdt_divider_set(wwdt_division_type division)
+{
+  WWDT->cfg_bit.div = division;
+}
+
+/**
+  * @brief  wwdt reload counter interrupt flag clear
+  * @param  none
+  * @retval none
+  */
+void wwdt_flag_clear(void)
+{
+  WWDT->sts = 0;
+}
+
+/**
+  * @brief  wwdt enable and the counter value load
+  * @param  wwdt_cnt (0x40~0x7f)
+  * @retval none
+  */
+void wwdt_enable(uint8_t wwdt_cnt)
+{
+  WWDT->ctrl = wwdt_cnt | WWDT_EN_BIT;
+}
+
+/**
+  * @brief  wwdt reload counter interrupt enable
+  * @param  none
+  * @retval none
+  */
+void wwdt_interrupt_enable(void)
+{
+  WWDT->cfg_bit.rldien = TRUE;
+}
+
+/**
+  * @brief  wwdt reload counter interrupt flag get
+  * @param  none
+  * @retval state of reload counter interrupt flag
+  */
+flag_status wwdt_flag_get(void)
+{
+  return (flag_status)WWDT->sts_bit.rldf;
+}
+
+/**
+  * @brief  wwdt counter value set
+  * @param  wwdt_cnt (0x40~0x7f)
+  * @retval none
+  */
+void wwdt_counter_set(uint8_t wwdt_cnt)
+{
+  WWDT->ctrl_bit.cnt = wwdt_cnt;
+}
+
+/**
+  * @brief  wwdt window counter value set
+  * @param  window_cnt (0x40~0x7f)
+  * @retval none
+  */
+void wwdt_window_counter_set(uint8_t window_cnt)
+{
+  WWDT->cfg_bit.win = window_cnt;
+}
+
+/**
+  * @}
+  */
+
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */

lib/main/AT32F43x/Drivers/AT32F43x_StdPeriph_Driver/src/at32f435_437_xmc.c

@@ -0,0 +1,909 @@
+/**
+  **************************************************************************
+  * @file     at32f435_437_xmc.c
+  * @version  v2.1.0
+  * @date     2022-08-16
+  * @brief    contains all the functions for the xmc firmware library
+  **************************************************************************
+  *                       Copyright notice & Disclaimer
+  *
+  * The software Board Support Package (BSP) that is made available to
+  * download from Artery official website is the copyrighted work of Artery.
+  * Artery authorizes customers to use, copy, and distribute the BSP
+  * software and its related documentation for the purpose of design and
+  * development in conjunction with Artery microcontrollers. Use of the
+  * software is governed by this copyright notice and the following disclaimer.
+  *
+  * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+  * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+  * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+  * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+  * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+  *
+  **************************************************************************
+  */
+
+#include "at32f435_437_conf.h"
+
+/** @addtogroup AT32F435_437_periph_driver
+  * @{
+  */
+
+/** @defgroup XMC
+  * @brief XMC driver modules
+  * @{
+  */
+
+#ifdef XMC_MODULE_ENABLED
+
+/** @defgroup XMC_private_functions
+  * @{
+  */
+
+/**
+  * @brief  xmc nor or sram registers reset
+  * @param  xmc_subbank
+  *         this parameter can be one of the following values:
+  *         - XMC_BANK1_NOR_SRAM1
+  *         - XMC_BANK1_NOR_SRAM2
+  *         - XMC_BANK1_NOR_SRAM3
+  *         - XMC_BANK1_NOR_SRAM4
+  * @retval none
+  */
+void xmc_nor_sram_reset(xmc_nor_sram_subbank_type xmc_subbank)
+{
+  /* XMC_BANK1_NORSRAM1 */
+  if(xmc_subbank == XMC_BANK1_NOR_SRAM1)
+  {
+    XMC_BANK1->ctrl_tmg_group[xmc_subbank].bk1ctrl = 0x000030DB;
+  }
+  /* XMC_BANK1_NORSRAM2,  XMC_BANK1_NORSRAM3 or XMC_BANK1_NORSRAM4 */
+  else
+  {
+    XMC_BANK1->ctrl_tmg_group[xmc_subbank].bk1ctrl = 0x000030D2;
+  }
+  XMC_BANK1->ctrl_tmg_group[xmc_subbank].bk1tmg = 0x0FFFFFFF;
+  XMC_BANK1->tmgwr_group[xmc_subbank].bk1tmgwr = 0x0FFFFFFF;
+}
+
+/**
+  * @brief  initialize the xmc nor/sram banks according to the specified
+  *         parameters in the xmc_norsraminitstruct.
+  * @param  xmc_norsram_init_struct : pointer to a xmc_norsram_init_type
+  *         structure that contains the configuration information for
+  *         the xmc nor/sram specified banks.
+  * @retval none
+  */
+void xmc_nor_sram_init(xmc_norsram_init_type* xmc_norsram_init_struct)
+{
+  /* bank1 nor/sram control register configuration */
+  XMC_BANK1->ctrl_tmg_group[xmc_norsram_init_struct->subbank].bk1ctrl =
+  (uint32_t)xmc_norsram_init_struct->data_addr_multiplex |
+  xmc_norsram_init_struct->device |
+  xmc_norsram_init_struct->bus_type |
+  xmc_norsram_init_struct->burst_mode_enable |
+  xmc_norsram_init_struct->asynwait_enable |
+  xmc_norsram_init_struct->wait_signal_lv |
+  xmc_norsram_init_struct->wrapped_mode_enable |
+  xmc_norsram_init_struct->wait_signal_config |
+  xmc_norsram_init_struct->write_enable |
+  xmc_norsram_init_struct->wait_signal_enable |
+  xmc_norsram_init_struct->write_timing_enable |
+  xmc_norsram_init_struct->write_burst_syn;
+
+  /* if nor flash device */
+  if(xmc_norsram_init_struct->device == XMC_DEVICE_NOR)
+  {
+    XMC_BANK1->ctrl_tmg_group[xmc_norsram_init_struct->subbank].bk1ctrl_bit.noren = 0x1;
+  }
+}
+
+/**
+  * @brief  initialize the xmc nor/sram banks according to the specified
+  *         parameters in the xmc_rw_timing_struct and xmc_w_timing_struct.
+  * @param  xmc_rw_timing_struct : pointer to a xmc_norsram_timing_init_type
+  *         structure that contains the configuration information for
+  *         the xmc nor/sram specified banks.
+  * @param  xmc_w_timing_struct : pointer to a xmc_norsram_timing_init_type
+  *         structure that contains the configuration information for
+  *         the xmc nor/sram specified banks.
+  * @retval none
+  */
+void xmc_nor_sram_timing_config(xmc_norsram_timing_init_type* xmc_rw_timing_struct,
+                                xmc_norsram_timing_init_type* xmc_w_timing_struct)
+{
+  /* bank1 nor/sram timing register configuration */
+  XMC_BANK1->ctrl_tmg_group[xmc_rw_timing_struct->subbank].bk1tmg =
+  (uint32_t)xmc_rw_timing_struct->addr_setup_time |
+  (xmc_rw_timing_struct->addr_hold_time << 4) |
+  (xmc_rw_timing_struct->data_setup_time << 8) |
+  (xmc_rw_timing_struct->bus_latency_time <<16) |
+  (xmc_rw_timing_struct->clk_psc << 20) |
+  (xmc_rw_timing_struct->data_latency_time << 24) |
+  xmc_rw_timing_struct->mode;
+
+  /* bank1 nor/sram timing register for write configuration, if extended mode is used */
+  if(xmc_rw_timing_struct->write_timing_enable == XMC_WRITE_TIMING_ENABLE)
+  {
+    XMC_BANK1->tmgwr_group[xmc_w_timing_struct->subbank].bk1tmgwr =
+    (uint32_t)xmc_w_timing_struct->addr_setup_time |
+    (xmc_w_timing_struct->addr_hold_time << 4) |
+    (xmc_w_timing_struct->data_setup_time << 8) |
+    (xmc_w_timing_struct->bus_latency_time << 16) |
+    (xmc_w_timing_struct->clk_psc << 20) |
+    (xmc_w_timing_struct->data_latency_time << 24) |
+    xmc_w_timing_struct->mode;
+  }
+  else
+  {
+    XMC_BANK1->tmgwr_group[xmc_w_timing_struct->subbank].bk1tmgwr = 0x0FFFFFFF;
+  }
+}
+
+/**
+  * @brief  fill each xmc_nor_sram_init_struct member with its default value.
+  * @param  xmc_nor_sram_init_struct: pointer to a xmc_norsram_init_type
+  *         structure which will be initialized.
+  * @retval none
+  */
+void xmc_norsram_default_para_init(xmc_norsram_init_type* xmc_nor_sram_init_struct)
+{
+  /* reset nor/sram init structure parameters values */
+  xmc_nor_sram_init_struct->subbank = XMC_BANK1_NOR_SRAM1;
+  xmc_nor_sram_init_struct->data_addr_multiplex = XMC_DATA_ADDR_MUX_ENABLE;
+  xmc_nor_sram_init_struct->device = XMC_DEVICE_SRAM;
+  xmc_nor_sram_init_struct->bus_type = XMC_BUSTYPE_8_BITS;
+  xmc_nor_sram_init_struct->burst_mode_enable = XMC_BURST_MODE_DISABLE;
+  xmc_nor_sram_init_struct->asynwait_enable = XMC_ASYN_WAIT_DISABLE;
+  xmc_nor_sram_init_struct->wait_signal_lv = XMC_WAIT_SIGNAL_LEVEL_LOW;
+  xmc_nor_sram_init_struct->wrapped_mode_enable = XMC_WRAPPED_MODE_DISABLE;
+  xmc_nor_sram_init_struct->wait_signal_config = XMC_WAIT_SIGNAL_SYN_BEFORE;
+  xmc_nor_sram_init_struct->write_enable = XMC_WRITE_OPERATION_ENABLE;
+  xmc_nor_sram_init_struct->wait_signal_enable = XMC_WAIT_SIGNAL_ENABLE;
+  xmc_nor_sram_init_struct->write_timing_enable = XMC_WRITE_TIMING_DISABLE;
+  xmc_nor_sram_init_struct->write_burst_syn = XMC_WRITE_BURST_SYN_DISABLE;
+}
+
+/**
+  * @brief  fill each xmc_rw_timing_struct and xmc_w_timing_struct member with its default value.
+  * @param  xmc_rw_timing_struct: pointer to a xmc_norsram_timing_init_type
+  *         structure which will be initialized.
+  * @param  xmc_w_timing_struct: pointer to a xmc_norsram_timing_init_type
+  *         structure which will be initialized.
+  * @retval none
+  */
+void xmc_norsram_timing_default_para_init(xmc_norsram_timing_init_type* xmc_rw_timing_struct,
+                                          xmc_norsram_timing_init_type* xmc_w_timing_struct)
+{
+  xmc_rw_timing_struct->subbank = XMC_BANK1_NOR_SRAM1;
+  xmc_rw_timing_struct->write_timing_enable = XMC_WRITE_TIMING_DISABLE;
+  xmc_rw_timing_struct->addr_setup_time = 0xF;
+  xmc_rw_timing_struct->addr_hold_time = 0xF;
+  xmc_rw_timing_struct->data_setup_time = 0xFF;
+  xmc_rw_timing_struct->bus_latency_time = 0xF;
+  xmc_rw_timing_struct->clk_psc = 0xF;
+  xmc_rw_timing_struct->data_latency_time = 0xF;
+  xmc_rw_timing_struct->mode = XMC_ACCESS_MODE_A;
+  xmc_w_timing_struct->subbank = XMC_BANK1_NOR_SRAM1;
+  xmc_w_timing_struct->write_timing_enable = XMC_WRITE_TIMING_DISABLE;
+  xmc_w_timing_struct->addr_setup_time = 0xF;
+  xmc_w_timing_struct->addr_hold_time = 0xF;
+  xmc_w_timing_struct->data_setup_time = 0xFF;
+  xmc_w_timing_struct->bus_latency_time = 0xF;
+  xmc_w_timing_struct->clk_psc = 0xF;
+  xmc_w_timing_struct->data_latency_time = 0xF;
+  xmc_w_timing_struct->mode = XMC_ACCESS_MODE_A;
+}
+
+/**
+  * @brief  enable or disable the specified nor/sram memory bank.
+  * @param  xmc_subbank
+  *         this parameter can be one of the following values:
+  *         - XMC_BANK1_NOR_SRAM1
+  *         - XMC_BANK1_NOR_SRAM2
+  *         - XMC_BANK1_NOR_SRAM3
+  *         - XMC_BANK1_NOR_SRAM4
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void xmc_nor_sram_enable(xmc_nor_sram_subbank_type xmc_subbank, confirm_state new_state)
+{
+  XMC_BANK1->ctrl_tmg_group[xmc_subbank].bk1ctrl_bit.en = new_state;
+}
+
+/**
+  * @brief  config the bus turnaround phase.
+  * @param  xmc_sub_bank
+  *         this parameter can be one of the following values:
+  *         - XMC_BANK1_NOR_SRAM1
+  *         - XMC_BANK1_NOR_SRAM2
+  *         - XMC_BANK1_NOR_SRAM3
+  *         - XMC_BANK1_NOR_SRAM4
+  * @param  w2w_timing :write timing
+  * @param  r2r_timing :read timing
+  * @retval none
+  */
+void xmc_ext_timing_config(xmc_nor_sram_subbank_type xmc_sub_bank, uint16_t w2w_timing, uint16_t r2r_timing)
+{
+  XMC_BANK1->ext_bit[xmc_sub_bank].buslatr2r = r2r_timing<<8;
+  XMC_BANK1->ext_bit[xmc_sub_bank].buslatw2w = w2w_timing;
+}
+
+/**
+  * @brief  xmc nand flash registers reset
+  * @param  xmc_bank
+  *         this parameter can be one of the following values:
+  *         - XMC_BANK2_NAND
+  *         - XMC_BANK3_NAND
+  * @retval none
+  */
+void xmc_nand_reset(xmc_class_bank_type xmc_bank)
+{
+  /* set the xmc_bank2_nand registers to their reset values */
+  if(xmc_bank == XMC_BANK2_NAND)
+  {
+    XMC_BANK2->bk2ctrl = 0x00000018;
+    XMC_BANK2->bk2is = 0x00000040;
+    XMC_BANK2->bk2tmgatt = 0xFCFCFCFC;
+    XMC_BANK2->bk2tmgmem = 0xFCFCFCFC;
+  }
+  /* set the xmc_bank3_nand registers to their reset values */
+  else
+  {
+    XMC_BANK3->bk3ctrl = 0x00000018;
+    XMC_BANK3->bk3is = 0x00000040;
+    XMC_BANK3->bk3tmgatt = 0xFCFCFCFC;
+    XMC_BANK3->bk3tmgmem = 0xFCFCFCFC;
+  }
+}
+
+/**
+  * @brief  initialize the xmc nand banks according to the specified
+  *         parameters in the xmc_nandinitstruct.
+  * @param  xmc_nand_init_struct : pointer to a xmc_nand_init_type
+  *         structure that contains the configuration information for the xmc
+  *         nand specified banks.
+  * @retval none
+  */
+void xmc_nand_init(xmc_nand_init_type* xmc_nand_init_struct)
+{
+  uint32_t tempctrl = 0x0;
+
+  /* Set the tempctrl value according to xmc_nand_init_struct parameters */
+  tempctrl = (uint32_t)xmc_nand_init_struct->wait_enable |
+              xmc_nand_init_struct->bus_type |
+              xmc_nand_init_struct->ecc_enable |
+              xmc_nand_init_struct->ecc_pagesize |
+              (xmc_nand_init_struct->delay_time_cycle << 9) |
+              (xmc_nand_init_struct->delay_time_ar << 13) |
+              0x00000008;
+
+  /* xmc_bank2_nand registers configuration */
+  if(xmc_nand_init_struct->nand_bank == XMC_BANK2_NAND)
+  {
+    XMC_BANK2->bk2ctrl = tempctrl;
+  }
+  /* xmc_bank3_nand registers configuration */
+  else
+  {
+    XMC_BANK3->bk3ctrl = tempctrl;
+  }
+}
+
+/**
+  * @brief  initialize the xmc nand banks according to the specified
+  *         parameters in the xmc_nandinitstruct.
+  * @param  xmc_regular_spacetiming_struct : pointer to a xmc_nand_pccard_timinginit_type
+  *         structure that contains the configuration information for the xmc
+  *         nand specified banks.
+  * @param  xmc_special_spacetiming_struct : pointer to a xmc_nand_pccard_timinginit_type
+  *         structure that contains the configuration information for the xmc
+  *         nand specified banks.
+  * @retval none
+  */
+void xmc_nand_timing_config(xmc_nand_pccard_timinginit_type* xmc_regular_spacetiming_struct,
+                            xmc_nand_pccard_timinginit_type* xmc_special_spacetiming_struct)
+{
+  uint32_t tempmem = 0x0, tempatt = 0x0;
+
+  /* set the tempmem value according to xmc_nand_init_struct parameters */
+  tempmem = (uint32_t)xmc_regular_spacetiming_struct->mem_setup_time |
+            (xmc_regular_spacetiming_struct->mem_waite_time << 8) |
+            (xmc_regular_spacetiming_struct->mem_hold_time << 16) |
+            (xmc_regular_spacetiming_struct->mem_hiz_time << 24);
+
+  /* set the tempatt value according to xmc_nand_init_struct parameters */
+  tempatt = (uint32_t)xmc_special_spacetiming_struct->mem_setup_time |
+            (xmc_special_spacetiming_struct->mem_waite_time << 8) |
+            (xmc_special_spacetiming_struct->mem_hold_time << 16) |
+            (xmc_special_spacetiming_struct->mem_hiz_time << 24);
+  /* xmc_bank2_nand registers configuration */
+  if(xmc_regular_spacetiming_struct->class_bank == XMC_BANK2_NAND)
+  {
+    XMC_BANK2->bk2tmgatt = tempatt;
+    XMC_BANK2->bk2tmgmem = tempmem;
+  }
+  else
+  {
+    XMC_BANK3->bk3tmgatt = tempatt;
+    XMC_BANK3->bk3tmgmem = tempmem;
+  }
+}
+
+/**
+  * @brief  fill each xmc_nand_init_struct member with its default value.
+  * @param  xmc_nand_init_struct: pointer to a xmc_nand_init_type
+  *         structure which will be initialized.
+  * @retval none
+  */
+void xmc_nand_default_para_init(xmc_nand_init_type* xmc_nand_init_struct)
+{
+  /* reset nand init structure parameters values */
+  xmc_nand_init_struct->nand_bank = XMC_BANK2_NAND;
+  xmc_nand_init_struct->wait_enable = XMC_WAIT_OPERATION_DISABLE;
+  xmc_nand_init_struct->bus_type = XMC_BUSTYPE_8_BITS;
+  xmc_nand_init_struct->ecc_enable = XMC_ECC_OPERATION_DISABLE;
+  xmc_nand_init_struct->ecc_pagesize = XMC_ECC_PAGESIZE_256_BYTES;
+  xmc_nand_init_struct->delay_time_cycle = 0x0;
+  xmc_nand_init_struct->delay_time_ar = 0x0;
+}
+
+/**
+  * @brief  fill each xmc_common_spacetiming_struct and xmc_attribute_spacetiming_struct member with its default value.
+  * @param  xmc_common_spacetiming_struct: pointer to a xmc_nand_pccard_timinginit_type
+  *         structure which will be initialized.
+  * @param  xmc_special_spacetiming_struct: pointer to a xmc_nand_pccard_timinginit_type
+  *         structure which will be initialized.
+  * @retval none
+  */
+void xmc_nand_timing_default_para_init(xmc_nand_pccard_timinginit_type* xmc_regular_spacetiming_struct,
+                                       xmc_nand_pccard_timinginit_type* xmc_special_spacetiming_struct)
+{
+  xmc_regular_spacetiming_struct->class_bank = XMC_BANK2_NAND;
+  xmc_regular_spacetiming_struct->mem_hold_time  = 0xFC;
+  xmc_regular_spacetiming_struct->mem_waite_time = 0xFC;
+  xmc_regular_spacetiming_struct->mem_setup_time = 0xFC;
+  xmc_regular_spacetiming_struct->mem_hiz_time = 0xFC;
+  xmc_special_spacetiming_struct->class_bank = XMC_BANK2_NAND;
+  xmc_special_spacetiming_struct->mem_hold_time = 0xFC;
+  xmc_special_spacetiming_struct->mem_waite_time = 0xFC;
+  xmc_special_spacetiming_struct->mem_setup_time = 0xFC;
+  xmc_special_spacetiming_struct->mem_hiz_time = 0xFC;
+}
+
+/**
+  * @brief  enable or disable the specified nand memory bank.
+  * @param  xmc_bank: specifies the xmc bank to be used
+  *   this parameter can be one of the following values:
+  *   - XMC_BANK2_NAND
+  *   - XMC_BANK3_NAND
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void xmc_nand_enable(xmc_class_bank_type xmc_bank, confirm_state new_state)
+{
+  /* enable or disable the nand bank2 by setting the en bit in the bk2ctrl register */
+  if(xmc_bank == XMC_BANK2_NAND)
+  {
+    XMC_BANK2->bk2ctrl_bit.en = new_state;
+  }
+  /* enable or disable the nand bank3 by setting the en bit in the bk3ctrl register */
+  else
+  {
+    XMC_BANK3->bk3ctrl_bit.en = new_state;
+  }
+}
+
+/**
+  * @brief  enable or disable the xmc nand ecc feature.
+  * @param  xmc_bank: specifies the xmc bank to be used
+  *   this parameter can be one of the following values:
+  *   - XMC_BANK2_NAND
+  *   - XMC_BANK3_NAND
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void xmc_nand_ecc_enable(xmc_class_bank_type xmc_bank, confirm_state new_state)
+{
+  /* enable the selected nand bank2 ecc function by setting the eccen bit in the bk2ctrl register */
+  if(xmc_bank == XMC_BANK2_NAND)
+  {
+    XMC_BANK2->bk2ctrl_bit.eccen = new_state;
+  }
+  /* enable the selected nand bank3 ecc function by setting the eccen bit in the bk3ctrl register */
+  else
+  {
+    XMC_BANK3->bk3ctrl_bit.eccen = new_state;
+  }
+}
+
+/**
+  * @brief  return the error correction code register value.
+  * @param  xmc_bank: specifies the xmc bank to be used
+  *   this parameter can be one of the following values:
+  *   - XMC_BANK2_NAND
+  *   - XMC_BANK3_NAND
+  * @retval the error correction code (ecc) value.
+  */
+uint32_t xmc_ecc_get(xmc_class_bank_type xmc_bank)
+{
+  uint32_t eccvaule = 0x0;
+
+  /* get the bk2ecc register value */
+  if(xmc_bank == XMC_BANK2_NAND)
+  {
+    eccvaule = XMC_BANK2->bk2ecc;
+  }
+  /* get the bk3ecc register value */
+  else
+  {
+    eccvaule = XMC_BANK3->bk3ecc;
+  }
+   /* return the error correction code value */
+  return eccvaule;
+}
+
+/**
+  * @brief  xmc sdram registers reset
+  * @param  xmc_bank
+  *         this parameter can be one of the following values:
+  *         - XMC_SDRAM_BANK1
+  *         - XMC_SDRAM_BANK2
+  * @retval none
+  */
+void xmc_sdram_reset(xmc_sdram_bank_type xmc_bank)
+{
+  XMC_SDRAM->ctrl[xmc_bank] = 0x000002D0;
+  XMC_SDRAM->tm[xmc_bank]   = 0x0FFFFFFF;
+  XMC_SDRAM->cmd            = 0x00000000;
+  XMC_SDRAM->rcnt           = 0x00000000;
+  XMC_SDRAM->sts            = 0x00000000;
+}
+
+/**
+  * @brief  initialize the xmc sdram banks according to the specified
+  *         parameters in the xmc_sdram_init_struct and xmc_sdram_timing_struct.
+  * @param  xmc_sdram_init_struct : pointer to a xmc_sdram_init_type
+  *         structure that contains the configuration information for the xmc
+  *         sdram specified banks.
+  * @param  xmc_sdram_timing_struct : pointer to a xmc_sdram_timing_type
+  *         structure that contains the configuration information for the xmc
+  *         sdram specified banks.
+  * @retval none
+  */
+void xmc_sdram_init(xmc_sdram_init_type *xmc_sdram_init_struct, xmc_sdram_timing_type *xmc_sdram_timing_struct)
+{
+  if(xmc_sdram_init_struct->sdram_bank == XMC_SDRAM_BANK1)
+  {
+    XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK1].ca = xmc_sdram_init_struct->column_address;
+    XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK1].ra = xmc_sdram_init_struct->row_address;
+    XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK1].db = xmc_sdram_init_struct->width;
+    XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK1].inbk = xmc_sdram_init_struct->internel_banks;
+    XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK1].cas = xmc_sdram_init_struct->cas;
+    XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK1].wrp = xmc_sdram_init_struct->write_protection;
+    XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK1].bstr = xmc_sdram_init_struct->burst_read;
+    XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK1].rd = xmc_sdram_init_struct->read_delay;
+    XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK1].clkdiv = xmc_sdram_init_struct->clkdiv;
+
+    XMC_SDRAM->tm_bit[XMC_SDRAM_BANK1].tmrd = xmc_sdram_timing_struct->tmrd;
+    XMC_SDRAM->tm_bit[XMC_SDRAM_BANK1].txsr = xmc_sdram_timing_struct->txsr;
+    XMC_SDRAM->tm_bit[XMC_SDRAM_BANK1].tras = xmc_sdram_timing_struct->tras;
+    XMC_SDRAM->tm_bit[XMC_SDRAM_BANK1].trc = xmc_sdram_timing_struct->trc;
+    XMC_SDRAM->tm_bit[XMC_SDRAM_BANK1].twr = xmc_sdram_timing_struct->twr;
+    XMC_SDRAM->tm_bit[XMC_SDRAM_BANK1].trp = xmc_sdram_timing_struct->trp;
+    XMC_SDRAM->tm_bit[XMC_SDRAM_BANK1].trcd = xmc_sdram_timing_struct->trcd;
+  }
+
+  if(xmc_sdram_init_struct->sdram_bank == XMC_SDRAM_BANK2)
+  {
+    XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK2].ca = xmc_sdram_init_struct->column_address;
+    XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK2].ra = xmc_sdram_init_struct->row_address;
+    XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK2].db = xmc_sdram_init_struct->width;
+    XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK2].inbk = xmc_sdram_init_struct->internel_banks;
+    XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK2].cas = xmc_sdram_init_struct->cas;
+    XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK2].wrp = xmc_sdram_init_struct->write_protection;
+    /* sdctrl2 bstr is not care */
+    XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK1].bstr = xmc_sdram_init_struct->burst_read;
+    XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK1].rd = xmc_sdram_init_struct->read_delay;
+    /* sdctrl2 clkdiv is not care */
+    XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK1].clkdiv = xmc_sdram_init_struct->clkdiv;
+
+    XMC_SDRAM->tm_bit[XMC_SDRAM_BANK2].tmrd = xmc_sdram_timing_struct->tmrd;
+    XMC_SDRAM->tm_bit[XMC_SDRAM_BANK2].txsr = xmc_sdram_timing_struct->txsr;
+    XMC_SDRAM->tm_bit[XMC_SDRAM_BANK2].tras = xmc_sdram_timing_struct->tras;
+    /* sdtm2 trc is not care */
+    XMC_SDRAM->tm_bit[XMC_SDRAM_BANK1].trc = xmc_sdram_timing_struct->trc;
+    XMC_SDRAM->tm_bit[XMC_SDRAM_BANK2].twr = xmc_sdram_timing_struct->twr;
+    /* sdtm2 trp is not care */
+    XMC_SDRAM->tm_bit[XMC_SDRAM_BANK1].trp = xmc_sdram_timing_struct->trp;
+    XMC_SDRAM->tm_bit[XMC_SDRAM_BANK2].trcd = xmc_sdram_timing_struct->trcd;
+  }
+}
+
+/**
+  * @brief  fill each xmc_sdram_init_struct member with its default value.
+  * @param  xmc_sdram_init_struct: pointer to a xmc_sdram_init_type
+  *         structure which will be initialized.
+  * @param  xmc_sdram_timing_struct: pointer to a xmc_sdram_timing_type
+  *         structure which will be initialized.
+  * @retval none
+  */
+void xmc_sdram_default_para_init(xmc_sdram_init_type *xmc_sdram_init_struct, xmc_sdram_timing_type *xmc_sdram_timing_struct)
+{
+  /* reset sdram init structure parameters values */
+  xmc_sdram_init_struct->sdram_bank       = XMC_SDRAM_BANK1;
+  xmc_sdram_init_struct->internel_banks   = XMC_INBK_4;
+  xmc_sdram_init_struct->clkdiv           = XMC_NO_CLK;
+  xmc_sdram_init_struct->write_protection = FALSE;
+  xmc_sdram_init_struct->burst_read       = FALSE;
+  xmc_sdram_init_struct->column_address   = XMC_COLUMN_8;
+  xmc_sdram_init_struct->row_address      = XMC_ROW_11;
+  xmc_sdram_init_struct->cas              = XMC_CAS_1;
+  xmc_sdram_init_struct->width            = XMC_MEM_WIDTH_8;
+  xmc_sdram_init_struct->read_delay       = XMC_READ_DELAY_1;
+
+  xmc_sdram_timing_struct->tmrd           = XMC_DELAY_CYCLE_16;
+  xmc_sdram_timing_struct->txsr           = XMC_DELAY_CYCLE_16;
+  xmc_sdram_timing_struct->tras           = XMC_DELAY_CYCLE_16;
+  xmc_sdram_timing_struct->trc            = XMC_DELAY_CYCLE_16;
+  xmc_sdram_timing_struct->twr            = XMC_DELAY_CYCLE_16;
+  xmc_sdram_timing_struct->trp            = XMC_DELAY_CYCLE_16;
+  xmc_sdram_timing_struct->trcd           = XMC_DELAY_CYCLE_16;
+}
+
+/**
+  * @brief  sdram command confg
+  * @param  xmc_sdram_cmd_struct: pointer to a xmc_sdram_cmd_type
+  *         structure which will be initialized.
+  * @retval none
+  */
+void xmc_sdram_cmd(xmc_sdram_cmd_type *xmc_sdram_cmd_struct)
+{
+  XMC_SDRAM->cmd = (xmc_sdram_cmd_struct->auto_refresh << 5) |
+                       (xmc_sdram_cmd_struct->data << 9) |
+                       xmc_sdram_cmd_struct->cmd |
+                       xmc_sdram_cmd_struct->cmd_banks;
+}
+
+
+/**
+  * @brief  get sdram bank status
+  * @param  xmc_bank: specifies the xmc bank to be used
+  *   this parameter can be one of the following values:
+  *   - XMC_SDRAM_BANK1
+  *   - XMC_SDRAM_BANK1
+  * @retval the bank status
+  */
+uint32_t xmc_sdram_status_get(xmc_sdram_bank_type xmc_bank)
+{
+  if(xmc_bank == XMC_SDRAM_BANK1)
+  {
+    return ((XMC_SDRAM->sts >> 1) & XMC_STATUS_MASK);
+  }
+  else
+  {
+    return ((XMC_SDRAM->sts >> 3) & XMC_STATUS_MASK);
+  }
+}
+
+/**
+  * @brief  set sdram refresh counter
+  * @param  counter: xmc sdram refresh counter
+  * @retval none
+  */
+void xmc_sdram_refresh_counter_set(uint32_t counter)
+{
+  XMC_SDRAM->rcnt_bit.rc = counter;
+}
+
+/**
+  * @brief  set sdram auto refresh number
+  * @param  number: xmc sdram auto refresh number
+  * @retval none
+  */
+void xmc_sdram_auto_refresh_set(uint32_t number)
+{
+  XMC_SDRAM->cmd_bit.art = number;
+}
+
+/**
+  * @brief  enable or disable the specified xmc interrupts.
+  * @param  xmc_bank: specifies the xmc bank to be used
+  *         this parameter can be one of the following values:
+  *         - XMC_BANK2_NAND
+  *         - XMC_BANK3_NAND
+  *         - XMC_BANK4_PCCARD
+  *         - XMC_BANK5_6_SDRAM
+  * @param  xmc_int: specifies the xmc interrupt sources to be enabled or disabled.
+  *         this parameter can be any combination of the following values:
+  *         - XMC_INT_RISING_EDGE
+  *         - XMC_INT_LEVEL
+  *         - XMC_INT_FALLING_EDGE
+  *         - XMC_INT_ERR
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void xmc_interrupt_enable(xmc_class_bank_type xmc_bank, xmc_interrupt_sources_type xmc_int, confirm_state new_state)
+{
+  if(new_state != FALSE)
+  {
+    /* enable the selected xmc_bank2 interrupts */
+    if(xmc_bank == XMC_BANK2_NAND)
+    {
+      XMC_BANK2->bk2is |= xmc_int;
+    }
+    /* enable the selected xmc_bank3 interrupts */
+    else if(xmc_bank == XMC_BANK3_NAND)
+    {
+      XMC_BANK3->bk3is |= xmc_int;
+    }
+    /* enable the selected xmc_bank4 interrupts */
+    else if(xmc_bank == XMC_BANK4_PCCARD)
+    {
+      XMC_BANK4->bk4is |= xmc_int;
+    }
+    /* enable the selected xmc_sdram interrupts */
+    else
+    {
+      XMC_SDRAM->rcnt |= xmc_int;
+    }
+  }
+  else
+  {
+    /* disable the selected xmc_bank2 interrupts */
+    if(xmc_bank == XMC_BANK2_NAND)
+    {
+      XMC_BANK2->bk2is &= ~xmc_int;
+    }
+    /* disable the selected xmc_bank3 interrupts */
+    else if(xmc_bank == XMC_BANK3_NAND)
+    {
+      XMC_BANK3->bk3is &= ~xmc_int;
+    }
+    /* disable the selected xmc_bank4 interrupts */
+    else if(xmc_bank == XMC_BANK4_PCCARD)
+    {
+      XMC_BANK4->bk4is &= ~xmc_int;
+    }
+    /* disable the selected xmc_sdram interrupts */
+    else
+    {
+      XMC_SDRAM->rcnt &= ~xmc_int;
+    }
+  }
+}
+
+/**
+  * @brief  check whether the specified xmc flag is set or not.
+  * @param  xmc_bank: specifies the xmc bank to be used
+  *         this parameter can be one of the following values:
+  *         - XMC_BANK2_NAND
+  *         - XMC_BANK3_NAND
+  *         - XMC_BANK4_PCCARD
+  *         - XMC_BANK5_6_SDRAM
+  * @param  xmc_flag: specifies the flag to check.
+  *         this parameter can be any combination of the following values:
+  *         - XMC_RISINGEDGE_FLAG
+  *         - XMC_LEVEL_FLAG
+  *         - XMC_FALLINGEDGE_FLAG
+  *         - XMC_FEMPT_FLAG
+  *         - XMC_BUSY_FLAG
+  *         - XMC_ERR_FLAG
+  * @retval none
+  */
+flag_status xmc_flag_status_get(xmc_class_bank_type xmc_bank, xmc_interrupt_flag_type xmc_flag)
+{
+  flag_status status = RESET;
+  uint32_t temp = 0;
+
+  if(xmc_bank == XMC_BANK2_NAND)
+  {
+    temp = XMC_BANK2->bk2is;
+  }
+  else if(xmc_bank == XMC_BANK3_NAND)
+  {
+    temp = XMC_BANK3->bk3is;
+  }
+  else if(xmc_bank == XMC_BANK4_PCCARD)
+  {
+    temp = XMC_BANK4->bk4is;
+  }
+  else
+  {
+    temp = XMC_SDRAM->sts;
+  }
+  /* get the flag status */
+  if((temp & xmc_flag) == RESET)
+  {
+    status = RESET;
+  }
+  else
+  {
+    status = SET;
+  }
+  /* return the flag status */
+  return status;
+}
+
+/**
+  * @brief  clear the xmc's pending flags.
+  * @param  xmc_bank: specifies the xmc bank to be used
+  *         this parameter can be one of the following values:
+  *         - XMC_BANK2_NAND
+  *         - XMC_BANK3_NAND
+  *         - XMC_BANK4_PCCARD
+  *         - XMC_BANK5_6_SDRAM
+  * @param  xmc_flag: specifies the flag to check.
+  *         this parameter can be any combination of the following values:
+  *         - XMC_RISINGEDGE_FLAG
+  *         - XMC_LEVEL_FLAG
+  *         - XMC_FALLINGEDGE_FLAG
+  *         - XMC_ERR_FLAG
+  * @retval none
+  */
+void xmc_flag_clear(xmc_class_bank_type xmc_bank, xmc_interrupt_flag_type xmc_flag)
+{
+  __IO uint32_t int_state;
+  if(xmc_bank == XMC_BANK2_NAND)
+  {
+    int_state = XMC_BANK2->bk2is & 0x38; /* keep interrupt state */
+    XMC_BANK2->bk2is = (~(xmc_flag | 0x38) | int_state);
+  }
+  else if(xmc_bank == XMC_BANK3_NAND)
+  {
+    int_state = XMC_BANK3->bk3is & 0x38; /* keep interrupt state */
+    XMC_BANK3->bk3is = (~(xmc_flag | 0x38) | int_state);
+  }
+  else if(xmc_bank == XMC_BANK4_PCCARD)
+  {
+    int_state = XMC_BANK4->bk4is & 0x38; /* keep interrupt state */
+    XMC_BANK4->bk4is = (~(xmc_flag | 0x38) | int_state);
+  }
+  else
+  {
+    XMC_SDRAM->rcnt |= xmc_flag;
+  }
+}
+
+/**
+  * @brief  xmc pc card registers reset
+  * @param  none
+  * @retval none
+  */
+void xmc_pccard_reset(void)
+{
+  /* Set the XMC_Bank4 registers to their reset values */
+  XMC_BANK4->bk4ctrl = 0x00000018;
+  XMC_BANK4->bk4is = 0x00000000;
+  XMC_BANK4->bk4tmgatt = 0xFCFCFCFC;
+  XMC_BANK4->bk4tmgio = 0xFCFCFCFC;
+  XMC_BANK4->bk4tmgmem = 0xFCFCFCFC;
+}
+
+/**
+  * @brief  initialize the xmc pccard bank according to the specified
+  *         parameters in the xmc_pccard_init_struct.
+  * @param  xmc_pccard_init_struct : pointer to a xmc_pccard_init_type
+  *         structure that contains the configuration information for the xmc
+  *         pccard bank.
+  * @retval none
+  */
+void xmc_pccard_init(xmc_pccard_init_type* xmc_pccard_init_struct)
+{
+  /* set the bk4ctrl register value according to xmc_pccard_init_struct parameters */
+  XMC_BANK4->bk4ctrl = (uint32_t)xmc_pccard_init_struct->enable_wait |
+                       XMC_BUSTYPE_16_BITS |
+                       (xmc_pccard_init_struct->delay_time_cr << 9) |
+                       (xmc_pccard_init_struct->delay_time_ar << 13);
+}
+
+/**
+  * @brief  initialize the xmc pccard bank according to the specified
+  *         parameters in the xmc_common_spacetiming_struct/xmc_attribute_spacetiming_struct
+  *         and xmc_iospace_timing_struct.
+  * @param  xmc_regular_spacetiming_struct : pointer to a xmc_pccard_init_type
+  *         structure that contains the configuration information for the xmc
+  *         pccard bank.
+  * @param  xmc_special_spacetiming_struct : pointer to a xmc_pccard_init_type
+  *         structure that contains the configuration information for the xmc
+  *         pccard bank.
+  * @param  xmc_iospace_timing_struct : pointer to a xmc_pccard_init_type
+  *         structure that contains the configuration information for the xmc
+  *         pccard bank.
+  * @retval none
+  */
+void xmc_pccard_timing_config(xmc_nand_pccard_timinginit_type* xmc_regular_spacetiming_struct,
+                              xmc_nand_pccard_timinginit_type* xmc_special_spacetiming_struct,
+                              xmc_nand_pccard_timinginit_type* xmc_iospace_timing_struct)
+{
+  /* set bk4tmgmem register value according to xmc_regular_spacetiming_struct parameters */
+  XMC_BANK4->bk4tmgmem = (uint32_t)xmc_regular_spacetiming_struct->mem_setup_time |
+                         (xmc_regular_spacetiming_struct->mem_waite_time << 8) |
+                         (xmc_regular_spacetiming_struct->mem_hold_time << 16) |
+                         (xmc_regular_spacetiming_struct->mem_hiz_time << 24);
+
+  /* Set bk4tmgatt register value according to xmc_special_spacetiming_struct parameters */
+  XMC_BANK4->bk4tmgatt = (uint32_t)xmc_special_spacetiming_struct->mem_setup_time |
+                         (xmc_special_spacetiming_struct->mem_waite_time << 8) |
+                         (xmc_special_spacetiming_struct->mem_hold_time << 16) |
+                         (xmc_special_spacetiming_struct->mem_hiz_time << 24);
+
+  /* Set bk4tmgio register value according to xmc_iospace_timing_struct parameters */
+  XMC_BANK4->bk4tmgio = (uint32_t)xmc_iospace_timing_struct->mem_setup_time |
+                        (xmc_iospace_timing_struct->mem_waite_time << 8) |
+                        (xmc_iospace_timing_struct->mem_hold_time << 16) |
+                        (xmc_iospace_timing_struct->mem_hiz_time << 24);
+}
+/**
+  * @brief  fill each xmc_pccard_init_struct member with its default value.
+  * @param  xmc_pccard_init_struct: pointer to a xmc_pccardinittype
+  *         structure which will be initialized.
+  * @retval none
+  */
+void xmc_pccard_default_para_init(xmc_pccard_init_type* xmc_pccard_init_struct)
+{
+  /* reset pccard init structure parameters values */
+  xmc_pccard_init_struct->enable_wait = XMC_WAIT_OPERATION_DISABLE;
+  xmc_pccard_init_struct->delay_time_ar = 0x0;
+  xmc_pccard_init_struct->delay_time_cr = 0x0;
+
+}
+/**
+  * @brief  fill each xmc_common_spacetiming_struct/xmc_attribute_spacetiming_struct
+  *         and xmc_iospace_timing_struct member with its default value.
+  * @param  xmc_regular_spacetiming_struct : pointer to a xmc_pccard_init_type
+  *         structure that contains the configuration information for the xmc
+  *         pccard bank.
+  * @param  xmc_special_spacetiming_struct : pointer to a xmc_pccard_init_type
+  *         structure that contains the configuration information for the xmc
+  *         pccard bank.
+  * @param  xmc_iospace_timing_struct : pointer to a xmc_pccard_init_type
+  *         structure that contains the configuration information for the xmc
+  *         pccard bank.
+  * @retval none
+  */
+void xmc_pccard_timing_default_para_init(xmc_nand_pccard_timinginit_type* xmc_regular_spacetiming_struct,
+                                         xmc_nand_pccard_timinginit_type* xmc_special_spacetiming_struct,
+                                         xmc_nand_pccard_timinginit_type* xmc_iospace_timing_struct)
+{
+  xmc_regular_spacetiming_struct->class_bank = XMC_BANK4_PCCARD;
+  xmc_regular_spacetiming_struct->mem_hold_time  = 0xFC;
+  xmc_regular_spacetiming_struct->mem_waite_time = 0xFC;
+  xmc_regular_spacetiming_struct->mem_setup_time = 0xFC;
+  xmc_regular_spacetiming_struct->mem_hiz_time = 0xFC;
+  xmc_special_spacetiming_struct->class_bank = XMC_BANK4_PCCARD;
+  xmc_special_spacetiming_struct->mem_hold_time  = 0xFC;
+  xmc_special_spacetiming_struct->mem_waite_time = 0xFC;
+  xmc_special_spacetiming_struct->mem_setup_time = 0xFC;
+  xmc_special_spacetiming_struct->mem_hiz_time = 0xFC;
+  xmc_iospace_timing_struct->class_bank = XMC_BANK4_PCCARD;
+  xmc_iospace_timing_struct->mem_hold_time = 0xFC;
+  xmc_iospace_timing_struct->mem_waite_time = 0xFC;
+  xmc_iospace_timing_struct->mem_setup_time = 0xFC;
+  xmc_iospace_timing_struct->mem_hiz_time = 0xFC;
+}
+/**
+  * @brief  enable or disable the pccard memory bank.
+  * @param  new_state (TRUE or FALSE)
+  * @retval none
+  */
+void xmc_pccard_enable(confirm_state new_state)
+{
+  /* enable the pccard bank4 by setting the en bit in the bk4ctrl register */
+  XMC_BANK4->bk4ctrl_bit.en = new_state;
+}
+
+/**
+  * @}
+  */
+
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */