290 lines
8.1 KiB
C
290 lines
8.1 KiB
C
/*
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* Override of CubeN6's usbd_conf.c.
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*
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* The submodule version uses __HAL_RCC_PWR_CLK_ENABLE / GPIOA_CLK_ENABLE
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* macros that live behind CPU_IN_SECURE_STATE in stm32n6xx_hal_rcc.h
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* (which pull in -mcmse-only HAL_MPU_*_NS variants). Our build doesn't
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* define CPU_IN_SECURE_STATE — see feedback_n6_peripheral_alias_cmse.md.
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* This file replaces those macro calls with direct RCC->AHB4ENSR writes
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* (matching the convention in main.c::tamp_clk_enable and the FSBL
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* stub's system_stm32n6xx_fsbl.c).
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*
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* Everything else is a verbatim copy of the upstream version — the
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* PCD↔USBD callback bridges, USBD_LL_* shims around HAL_PCD_*, USB
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* device init with embedded HS-PHY in FS speed.
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*/
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#include "main.h"
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#include "usbd_dfu.h"
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PCD_HandleTypeDef hpcd_USB_HS;
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/* ---------------- IRQ ---------------- */
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void USB1_OTG_HS_IRQHandler(void)
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{
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HAL_PCD_IRQHandler(&hpcd_USB_HS);
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}
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/* ---------------- PCD MSP ---------------- */
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void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd)
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{
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if (hpcd->Instance != USB1_OTG_HS) {
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return;
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}
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/* PWR clock — direct register write avoids the CMSE-gated HAL macro. */
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SET_BIT(RCC->AHB4ENSR, RCC_AHB4ENSR_PWRENS);
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(void)RCC->AHB4ENR;
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/* VDD33USB independent USB voltage monitor. The PWREx_ helpers are
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* NS-safe (no CMSE-gated macros internally). */
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HAL_PWREx_EnableVddUSBVMEN();
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while (__HAL_PWR_GET_FLAG(PWR_FLAG_USB33RDY) == 0U) {
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;
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}
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HAL_PWREx_EnableVddUSB();
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/* USB1 OTG HS kernel clock from HSE_DIRECT (48 MHz on N6570-DK). */
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RCC_PeriphCLKInitTypeDef pclk = {0};
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pclk.PeriphClockSelection = RCC_PERIPHCLK_USBOTGHS1;
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pclk.UsbOtgHs1ClockSelection = RCC_USBOTGHS1CLKSOURCE_HSE_DIRECT;
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if (HAL_RCCEx_PeriphCLKConfig(&pclk) != HAL_OK) {
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Error_Handler();
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}
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/* USB OTG HS PHY1 reference clock from HSE_DIRECT. */
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pclk.PeriphClockSelection = RCC_PERIPHCLK_USBPHY1;
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pclk.UsbPhy1ClockSelection = RCC_USBPHY1CLKSOURCE_HSE_DIRECT;
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if (HAL_RCCEx_PeriphCLKConfig(&pclk) != HAL_OK) {
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Error_Handler();
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}
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/* GPIOA clock — direct register write (DP/DM are PA11/PA12). */
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SET_BIT(RCC->AHB4ENSR, RCC_AHB4ENSR_GPIOAENS);
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(void)RCC->AHB4ENR;
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LL_AHB5_GRP1_ForceReset(RCC_AHB5RSTR_OTG1PHYCTLRST);
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__HAL_RCC_USB1_OTG_HS_FORCE_RESET();
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__HAL_RCC_USB1_OTG_HS_PHY_FORCE_RESET();
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LL_RCC_HSE_SelectHSEDiv2AsDiv2Clock();
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LL_AHB5_GRP1_ReleaseReset(RCC_AHB5RSTR_OTG1PHYCTLRST);
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__HAL_RCC_USB1_OTG_HS_CLK_ENABLE();
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/* USBPHYC FSEL = 0b010 (24 MHz reference). HAL never writes this and
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* the default 0b001 silently drops every SETUP packet — see
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* feedback_n6_usbphyc_fsel.md. */
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USB1_HS_PHYC->USBPHYC_CR &= ~(0x7U << 0x4U);
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USB1_HS_PHYC->USBPHYC_CR |= (0x2U << 0x4U);
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__HAL_RCC_USB1_OTG_HS_PHY_RELEASE_RESET();
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HAL_Delay(1);
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__HAL_RCC_USB1_OTG_HS_RELEASE_RESET();
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__HAL_RCC_USB1_OTG_HS_PHY_CLK_ENABLE();
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HAL_NVIC_SetPriority(USB1_OTG_HS_IRQn, 6, 0);
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HAL_NVIC_EnableIRQ(USB1_OTG_HS_IRQn);
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}
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void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd)
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{
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if (hpcd->Instance != USB1_OTG_HS) {
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return;
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}
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HAL_PWREx_DisableVddUSBVMEN();
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HAL_PWREx_DisableVddUSB();
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__HAL_RCC_USB1_OTG_HS_CLK_DISABLE();
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__HAL_RCC_USB1_OTG_HS_PHY_CLK_DISABLE();
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HAL_NVIC_DisableIRQ(USB1_OTG_HS_IRQn);
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}
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/* ---------------- PCD → USBD callbacks ---------------- */
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void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
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{
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USBD_LL_SetupStage(hpcd->pData, (uint8_t *)hpcd->Setup);
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}
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void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
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{
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USBD_LL_DataOutStage(hpcd->pData, epnum, hpcd->OUT_ep[epnum].xfer_buff);
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}
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void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
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{
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USBD_LL_DataInStage(hpcd->pData, epnum, hpcd->IN_ep[epnum].xfer_buff);
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}
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void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
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{
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USBD_LL_SOF(hpcd->pData);
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}
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void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
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{
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USBD_SpeedTypeDef speed = USBD_SPEED_FULL;
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switch (hpcd->Init.speed) {
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case PCD_SPEED_HIGH: speed = USBD_SPEED_HIGH; break;
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case PCD_SPEED_FULL: speed = USBD_SPEED_FULL; break;
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default: speed = USBD_SPEED_FULL; break;
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}
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USBD_LL_Reset(hpcd->pData);
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USBD_LL_SetSpeed(hpcd->pData, speed);
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}
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void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
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{
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USBD_LL_Suspend(hpcd->pData);
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}
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void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
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{
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USBD_LL_IsoOUTIncomplete(hpcd->pData, epnum);
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}
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void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
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{
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USBD_LL_IsoINIncomplete(hpcd->pData, epnum);
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}
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void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)
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{
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USBD_LL_DevConnected(hpcd->pData);
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}
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void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
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{
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USBD_LL_DevDisconnected(hpcd->pData);
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}
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/* ---------------- USBD → PCD shims ---------------- */
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USBD_StatusTypeDef USBD_LL_Init(USBD_HandleTypeDef *pdev)
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{
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hpcd_USB_HS.Instance = USB1_OTG_HS;
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hpcd_USB_HS.Init.dev_endpoints = 3U;
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hpcd_USB_HS.Init.speed = PCD_SPEED_HIGH;
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hpcd_USB_HS.Init.dma_enable = DISABLE;
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hpcd_USB_HS.Init.phy_itface = USB_OTG_HS_EMBEDDED_PHY;
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hpcd_USB_HS.Init.Sof_enable = DISABLE;
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hpcd_USB_HS.Init.low_power_enable = DISABLE;
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hpcd_USB_HS.Init.lpm_enable = DISABLE;
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hpcd_USB_HS.Init.vbus_sensing_enable = DISABLE;
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hpcd_USB_HS.Init.use_dedicated_ep1 = DISABLE;
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hpcd_USB_HS.Init.use_external_vbus = DISABLE;
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hpcd_USB_HS.pData = pdev;
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pdev->pData = &hpcd_USB_HS;
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HAL_PCD_Init(&hpcd_USB_HS);
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HAL_PCDEx_SetRxFiFo(&hpcd_USB_HS, 0xA0U);
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HAL_PCDEx_SetTxFiFo(&hpcd_USB_HS, 0, 0xA0U);
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return USBD_OK;
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}
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USBD_StatusTypeDef USBD_LL_DeInit(USBD_HandleTypeDef *pdev)
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{
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HAL_PCD_DeInit(pdev->pData);
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return USBD_OK;
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}
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USBD_StatusTypeDef USBD_LL_Start(USBD_HandleTypeDef *pdev)
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{
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HAL_PCD_Start(pdev->pData);
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return USBD_OK;
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}
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USBD_StatusTypeDef USBD_LL_Stop(USBD_HandleTypeDef *pdev)
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{
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HAL_PCD_Stop(pdev->pData);
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return USBD_OK;
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}
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USBD_StatusTypeDef USBD_LL_OpenEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr,
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uint8_t ep_type, uint16_t ep_mps)
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{
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HAL_PCD_EP_Open(pdev->pData, ep_addr, ep_mps, ep_type);
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return USBD_OK;
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}
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USBD_StatusTypeDef USBD_LL_CloseEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
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{
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HAL_PCD_EP_Close(pdev->pData, ep_addr);
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return USBD_OK;
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}
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USBD_StatusTypeDef USBD_LL_FlushEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
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{
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HAL_PCD_EP_Flush(pdev->pData, ep_addr);
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return USBD_OK;
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}
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USBD_StatusTypeDef USBD_LL_StallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
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{
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HAL_PCD_EP_SetStall(pdev->pData, ep_addr);
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return USBD_OK;
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}
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USBD_StatusTypeDef USBD_LL_ClearStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
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{
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HAL_PCD_EP_ClrStall(pdev->pData, ep_addr);
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return USBD_OK;
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}
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uint8_t USBD_LL_IsStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
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{
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PCD_HandleTypeDef *hpcd = pdev->pData;
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if ((ep_addr & 0x80U) == 0x80U) {
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return hpcd->IN_ep[ep_addr & 0x7FU].is_stall;
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}
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return hpcd->OUT_ep[ep_addr & 0x7FU].is_stall;
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}
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USBD_StatusTypeDef USBD_LL_SetUSBAddress(USBD_HandleTypeDef *pdev, uint8_t dev_addr)
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{
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HAL_PCD_SetAddress(pdev->pData, dev_addr);
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return USBD_OK;
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}
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USBD_StatusTypeDef USBD_LL_Transmit(USBD_HandleTypeDef *pdev, uint8_t ep_addr,
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uint8_t *pbuf, uint32_t size)
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{
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HAL_PCD_EP_Transmit(pdev->pData, ep_addr, pbuf, size);
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return USBD_OK;
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}
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USBD_StatusTypeDef USBD_LL_PrepareReceive(USBD_HandleTypeDef *pdev, uint8_t ep_addr,
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uint8_t *pbuf, uint32_t size)
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{
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HAL_PCD_EP_Receive(pdev->pData, ep_addr, pbuf, size);
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return USBD_OK;
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}
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uint32_t USBD_LL_GetRxDataSize(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
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{
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return HAL_PCD_EP_GetRxCount(pdev->pData, ep_addr);
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}
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void *USBD_static_malloc(uint32_t size)
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{
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(void)size;
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static uint32_t mem[(sizeof(USBD_DFU_HandleTypeDef) / 4U) + 1U];
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return mem;
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}
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void USBD_static_free(void *p)
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{
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(void)p;
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}
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void USBD_LL_Delay(uint32_t Delay)
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{
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HAL_Delay(Delay);
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}
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