431 lines
17 KiB
C
431 lines
17 KiB
C
/*
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* CMSIS system file for the Betaflight N6 OpenBootloader.
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*
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* Built with -mcmse so __ARM_FEATURE_CMSE=3 and the CMSIS headers resolve
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* every peripheral pointer (RCC, RIFSC, GPIOx, DBGMCU, TAMP, PWR, RTC,
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* EXTI, GPDMA1, HPDMA1, RNG, SYSCFG, ...) to its secure-alias base. OBL
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* is the only S-state code on the device, so all of its peripheral
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* accesses must go through the secure aliases.
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*
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* SystemInit opens every relevant slave + master so the NS application
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* can reach RAM, XSPI memory-mapped flash and AHB/APB peripherals after
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* the BXNS hand-off in jump_to_bf().
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*
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* SystemClock_Config_Impl is called from main() to lift the CPU from
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* the boot-ROM hand-off clock (HSI/4 ≈ 16 MHz) to 400 MHz so USB OTG_HS
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* gets a clean SOF stream when the OBL DFU branch runs.
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*/
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#include "stm32n6xx.h"
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#include <math.h>
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#if !defined(HSE_VALUE)
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#define HSE_VALUE 48000000UL
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#endif
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#if !defined(HSI_VALUE)
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#define HSI_VALUE 64000000UL
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#endif
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#if !defined(MSI_VALUE)
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#define MSI_VALUE 4000000UL
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#endif
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#if !defined(EXTERNAL_I2S_CLOCK_VALUE)
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#define EXTERNAL_I2S_CLOCK_VALUE 12288000UL
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#endif
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uint32_t SystemCoreClock = HSI_VALUE;
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extern void *g_pfnVectors;
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#define INTVECT_START ((uint32_t)&g_pfnVectors)
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void SystemInit(void)
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{
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SCB->VTOR = INTVECT_START;
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/* Caches stay off throughout OBL: the boot decision reads XSPI flash
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* and we want fresh fetches; BF re-enables caches in its own startup. */
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SCB_DisableICache();
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SCB_InvalidateICache();
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SCB_DisableDCache();
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SCB_InvalidateDCache();
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/* Debug subsystem clock. */
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RCC->MISCENSR = RCC_MISCENSR_DBGENS;
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(void)RCC->MISCENR;
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/* APB3 bus clock — DBGMCU lives on APB3 and accesses there read 0 /
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* silently drop until the bus is ungated. */
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RCC->BUSENSR = RCC_BUSENSR_APB3ENS;
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(void)RCC->BUSENR;
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/* RIFSC: every peripheral slave NS+Unpriv, debug-AP master CID 0. */
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for (uint32_t i = 0; i < 6U; i++) {
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RIFSC->RISC_SECCFGRx[i] = 0;
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RIFSC->RISC_PRIVCFGRx[i] = 0;
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}
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RIFSC->RIMC_CR &= ~0x7UL;
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(void)RIFSC->RIMC_CR;
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/* DBGMCU.CR: hold the M55 debuggable across run / sleep / stop /
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* standby so SWD attach to running user code works on OPEN-lifecycle
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* silicon. */
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DBGMCU->CR = DBGMCU_CR_DBGCLKEN
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| DBGMCU_CR_DBG_SLEEP
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| DBGMCU_CR_DBG_STOP
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| DBGMCU_CR_DBG_STANDBY;
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(void)DBGMCU->CR;
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/* TAMP is RIF-aware: its security/priv gating lives in its own
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* SECCFGR/PRIVCFGR (not RIFSC). Opening to NS+Unpriv exposes all
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* 32 BKPxR for read/write from NS world. */
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TAMP->SECCFGR = 0;
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TAMP->PRIVCFGR = 0;
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(void)TAMP->SECCFGR;
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/* GPIO SECCFGR + PRIVCFGR per port — every pin NS + Unpriv. Without
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* these the NS application's pinmux for SPI / I2C / UART / etc. is
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* silently rejected even with RIFSC opened. The bank-enable on
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* AHB4ENSR has to happen first: writes to a GPIO bank with its
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* clock gated off silently drop on the N6, so the SECCFGR loop
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* below would no-op for any port the boot ROM hadn't already
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* ungated. */
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RCC->AHB4ENSR = RCC_AHB4ENR_GPIOAEN_Msk | RCC_AHB4ENR_GPIOBEN_Msk
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| RCC_AHB4ENR_GPIOCEN_Msk | RCC_AHB4ENR_GPIODEN_Msk
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| RCC_AHB4ENR_GPIOEEN_Msk | RCC_AHB4ENR_GPIOFEN_Msk
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| RCC_AHB4ENR_GPIOGEN_Msk | RCC_AHB4ENR_GPIOHEN_Msk
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| RCC_AHB4ENR_GPIONEN_Msk | RCC_AHB4ENR_GPIOOEN_Msk
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| RCC_AHB4ENR_GPIOPEN_Msk | RCC_AHB4ENR_GPIOQEN_Msk;
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(void)RCC->AHB4ENR;
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static GPIO_TypeDef * const gpio_banks[] = {
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GPIOA, GPIOB, GPIOC, GPIOD,
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GPIOE, GPIOF, GPIOG, GPIOH,
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GPION, GPIOO, GPIOP, GPIOQ,
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};
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for (unsigned i = 0; i < sizeof(gpio_banks) / sizeof(gpio_banks[0]); i++) {
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gpio_banks[i]->SECCFGR = 0;
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gpio_banks[i]->PRIVCFGR = 0;
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}
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/* GPDMA1 + HPDMA1: clock-enable first (boot ROM hands them off
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* ungated) then open per-controller SECCFGR + PRIVCFGR. SECCFGR is
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* a bit-per-channel register at controller +0x00; writing 0 routes
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* every channel under NS attribution. */
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RCC->AHB1ENSR = RCC_AHB1ENSR_GPDMA1ENS;
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RCC->AHB5ENSR = RCC_AHB5ENSR_HPDMA1ENS;
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GPDMA1->SECCFGR = 0;
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GPDMA1->PRIVCFGR = 0;
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HPDMA1->SECCFGR = 0;
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HPDMA1->PRIVCFGR = 0;
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/* Per-peripheral SECCFGR + PRIVCFGR — peripherals carrying their
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* own security config above RIFSC. Clearing each = NS + Unpriv. */
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RCC->SECCFGR0 = 0;
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RCC->SECCFGR1 = 0;
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RCC->SECCFGR2 = 0;
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RCC->SECCFGR3 = 0;
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RCC->SECCFGR4 = 0;
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PWR->SECCFGR = 0;
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PWR->PRIVCFGR = 0;
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EXTI->SECCFGR1 = 0;
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EXTI->PRIVCFGR1 = 0;
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EXTI->SECCFGR2 = 0;
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EXTI->PRIVCFGR2 = 0;
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EXTI->SECCFGR3 = 0;
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EXTI->PRIVCFGR3 = 0;
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RTC->SECCFGR = 0;
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/* RIMC master attributes — every bus master (CPU, DMAs, USB, ETH, …)
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* presents as NS + Unpriv + CID 0 by default. */
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for (unsigned i = 0; i < 13U; i++) {
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RIFSC->RIMC_ATTRx[i] = 0;
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}
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/* RNG reset + clock-disable. The boot ROM may have left it ticking. */
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RCC->AHB3RSTSR = RCC_AHB3RSTSR_RNGRSTS;
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RCC->AHB3RSTCR = RCC_AHB3RSTCR_RNGRSTC;
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RCC->AHB3ENCR = RCC_AHB3ENCR_RNGENC;
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/* SYSCFG clock + VDDIOx supply rails (errata ES0620). */
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RCC->APB4ENSR2 = RCC_APB4ENSR2_SYSCFGENS;
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(void)RCC->APB4ENR2;
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SYSCFG->INITSVTORCR = SCB->VTOR;
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PWR->SVMCR1 |= PWR_SVMCR1_VDDIO4SV;
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PWR->SVMCR2 |= PWR_SVMCR2_VDDIO5SV;
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PWR->SVMCR3 |= PWR_SVMCR3_VDDIO2SV | PWR_SVMCR3_VDDIO3SV;
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SYSCFG->VDDIO2CCCR = 0x00000287UL;
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SYSCFG->VDDIO3CCCR = 0x00000287UL;
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SYSCFG->VDDIO4CCCR = 0x00000287UL;
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SYSCFG->VDDIO5CCCR = 0x00000287UL;
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SYSCFG->VDDCCCR = 0x00000287UL;
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/* VDDADC clamp + VREF buffer. */
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PWR->SVMCR3 |= PWR_SVMCR3_ASV;
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PWR->SVMCR3 |= PWR_SVMCR3_AVMEN;
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(void)PWR->SVMCR3;
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RCC->APB4ENR1 |= RCC_APB4ENR1_VREFBUFEN;
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/* Pulse APB4ENR2 bit 4 — required by ST's reference bring-up to
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* lower power; no documented register name. */
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RCC->APB4ENR2 |= 0x00000010UL;
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(void)RCC->APB4ENR2;
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RCC->APB4ENR2 &= ~0x00000010UL;
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/* LSI on. IWDG is clocked from LSI exclusively; without this the
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* watchdog hardware never ticks and a wedged BF never resets back
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* into OBL recovery. Boot ROM doesn't reliably leave LSI on. */
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RCC->CSR = RCC_CSR_LSIONS;
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while ((RCC->SR & RCC_SR_LSIRDY) == 0U) {
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;
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}
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/* Reset XSPI2 + XSPIM so we start from a known state regardless of how
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* boot ROM left them after loading us. */
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RCC->AHB5RSTSR = RCC_AHB5RSTSR_XSPIMRSTS | RCC_AHB5RSTSR_XSPI2RSTS;
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RCC->AHB5RSTCR = RCC_AHB5RSTCR_XSPIMRSTC | RCC_AHB5RSTCR_XSPI2RSTC;
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/* TIM2 reset + clock-disable. */
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RCC->APB1RSTSR1 = RCC_APB1RSTSR1_TIM2RSTS;
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RCC->APB1RSTCR1 = RCC_APB1RSTCR1_TIM2RSTC;
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RCC->APB1ENCR1 = RCC_APB1ENCR1_TIM2ENC;
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/* Enable AXISRAM1..6 clocks. Boot ROM only clocks AXISRAM2; the rest
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* must be brought up here or the first store from a consumer of
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* those banks busfaults silently. */
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RCC->MEMENSR = RCC_MEMENSR_AXISRAM1ENS | RCC_MEMENSR_AXISRAM2ENS
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| RCC_MEMENSR_AXISRAM3ENS | RCC_MEMENSR_AXISRAM4ENS
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| RCC_MEMENSR_AXISRAM5ENS | RCC_MEMENSR_AXISRAM6ENS;
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(void)RCC->MEMENR;
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(void)SYSCFG->INITSVTORCR;
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RCC->APB4ENCR2 = RCC_APB4ENCR2_SYSCFGENC;
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#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
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SCB->CPACR |= ((3UL << 20U) | (3UL << 22U)); /* CP10/CP11 full S access */
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#endif
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/* NSACR — bits 10/11 grant NS access to CP10/CP11 (FPU + MVE).
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* 0x0FFF is the broadest "NS can touch every implemented CP" set;
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* the harmless bits 0..7 hand future-proof access. NSACR is
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* Secure-only-writable so it has to be set here, before the BXNS
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* hand-off. (AIRCR.BFHFNMINS is deferred to jump_to_bf — flipping it
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* here routes any S-side fault during OBL's own remaining execution
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* to an NS state that doesn't yet have a vector table or stack,
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* which deterministically wedges the chip into LOCKUP.) */
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SCB->NSACR = 0x00000FFFUL;
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}
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void SystemCoreClockUpdate(void)
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{
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uint32_t sysclk = 0;
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uint32_t pllm = 0;
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uint32_t plln = 0;
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uint32_t pllfracn = 0;
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uint32_t pllp1 = 0;
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uint32_t pllp2 = 0;
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uint32_t pllcfgr;
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uint32_t pllsource = 0;
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uint32_t pllbypass = 0;
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uint32_t ic_divider;
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float_t pllvco;
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switch (RCC->CFGR1 & RCC_CFGR1_CPUSWS) {
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case 0:
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sysclk = HSI_VALUE >> ((RCC->HSICFGR & RCC_HSICFGR_HSIDIV) >> RCC_HSICFGR_HSIDIV_Pos);
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break;
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case RCC_CFGR1_CPUSWS_0:
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sysclk = (READ_BIT(RCC->MSICFGR, RCC_MSICFGR_MSIFREQSEL) == 0UL) ? MSI_VALUE : 16000000UL;
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break;
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case RCC_CFGR1_CPUSWS_1:
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sysclk = HSE_VALUE;
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break;
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case (RCC_CFGR1_CPUSWS_1 | RCC_CFGR1_CPUSWS_0):
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switch (READ_BIT(RCC->IC1CFGR, RCC_IC1CFGR_IC1SEL)) {
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case 0:
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pllcfgr = READ_REG(RCC->PLL1CFGR1);
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pllsource = pllcfgr & RCC_PLL1CFGR1_PLL1SEL;
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pllbypass = pllcfgr & RCC_PLL1CFGR1_PLL1BYP;
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if (pllbypass == 0U) {
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pllm = (pllcfgr & RCC_PLL1CFGR1_PLL1DIVM) >> RCC_PLL1CFGR1_PLL1DIVM_Pos;
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plln = (pllcfgr & RCC_PLL1CFGR1_PLL1DIVN) >> RCC_PLL1CFGR1_PLL1DIVN_Pos;
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pllfracn = READ_BIT(RCC->PLL1CFGR2, RCC_PLL1CFGR2_PLL1DIVNFRAC) >> RCC_PLL1CFGR2_PLL1DIVNFRAC_Pos;
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pllcfgr = READ_REG(RCC->PLL1CFGR3);
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pllp1 = (pllcfgr & RCC_PLL1CFGR3_PLL1PDIV1) >> RCC_PLL1CFGR3_PLL1PDIV1_Pos;
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pllp2 = (pllcfgr & RCC_PLL1CFGR3_PLL1PDIV2) >> RCC_PLL1CFGR3_PLL1PDIV2_Pos;
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}
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break;
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case RCC_IC1CFGR_IC1SEL_0:
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pllcfgr = READ_REG(RCC->PLL2CFGR1);
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pllsource = pllcfgr & RCC_PLL2CFGR1_PLL2SEL;
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pllbypass = pllcfgr & RCC_PLL2CFGR1_PLL2BYP;
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if (pllbypass == 0U) {
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pllm = (pllcfgr & RCC_PLL2CFGR1_PLL2DIVM) >> RCC_PLL2CFGR1_PLL2DIVM_Pos;
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plln = (pllcfgr & RCC_PLL2CFGR1_PLL2DIVN) >> RCC_PLL2CFGR1_PLL2DIVN_Pos;
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pllfracn = READ_BIT(RCC->PLL2CFGR2, RCC_PLL2CFGR2_PLL2DIVNFRAC) >> RCC_PLL2CFGR2_PLL2DIVNFRAC_Pos;
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pllcfgr = READ_REG(RCC->PLL2CFGR3);
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pllp1 = (pllcfgr & RCC_PLL2CFGR3_PLL2PDIV1) >> RCC_PLL2CFGR3_PLL2PDIV1_Pos;
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pllp2 = (pllcfgr & RCC_PLL2CFGR3_PLL2PDIV2) >> RCC_PLL2CFGR3_PLL2PDIV2_Pos;
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}
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break;
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case RCC_IC1CFGR_IC1SEL_1:
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pllcfgr = READ_REG(RCC->PLL3CFGR1);
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pllsource = pllcfgr & RCC_PLL3CFGR1_PLL3SEL;
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pllbypass = pllcfgr & RCC_PLL3CFGR1_PLL3BYP;
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if (pllbypass == 0U) {
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pllm = (pllcfgr & RCC_PLL3CFGR1_PLL3DIVM) >> RCC_PLL3CFGR1_PLL3DIVM_Pos;
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plln = (pllcfgr & RCC_PLL3CFGR1_PLL3DIVN) >> RCC_PLL3CFGR1_PLL3DIVN_Pos;
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pllfracn = READ_BIT(RCC->PLL3CFGR2, RCC_PLL3CFGR2_PLL3DIVNFRAC) >> RCC_PLL3CFGR2_PLL3DIVNFRAC_Pos;
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pllcfgr = READ_REG(RCC->PLL3CFGR3);
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pllp1 = (pllcfgr & RCC_PLL3CFGR3_PLL3PDIV1) >> RCC_PLL3CFGR3_PLL3PDIV1_Pos;
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pllp2 = (pllcfgr & RCC_PLL3CFGR3_PLL3PDIV2) >> RCC_PLL3CFGR3_PLL3PDIV2_Pos;
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}
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break;
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default:
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pllcfgr = READ_REG(RCC->PLL4CFGR1);
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pllsource = pllcfgr & RCC_PLL4CFGR1_PLL4SEL;
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pllbypass = pllcfgr & RCC_PLL4CFGR1_PLL4BYP;
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if (pllbypass == 0U) {
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pllm = (pllcfgr & RCC_PLL4CFGR1_PLL4DIVM) >> RCC_PLL4CFGR1_PLL4DIVM_Pos;
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plln = (pllcfgr & RCC_PLL4CFGR1_PLL4DIVN) >> RCC_PLL4CFGR1_PLL4DIVN_Pos;
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pllfracn = READ_BIT(RCC->PLL4CFGR2, RCC_PLL4CFGR2_PLL4DIVNFRAC) >> RCC_PLL4CFGR2_PLL4DIVNFRAC_Pos;
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pllcfgr = READ_REG(RCC->PLL4CFGR3);
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pllp1 = (pllcfgr & RCC_PLL4CFGR3_PLL4PDIV1) >> RCC_PLL4CFGR3_PLL4PDIV1_Pos;
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pllp2 = (pllcfgr & RCC_PLL4CFGR3_PLL4PDIV2) >> RCC_PLL4CFGR3_PLL4PDIV2_Pos;
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}
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break;
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}
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switch (pllsource) {
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case 0:
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sysclk = HSI_VALUE >> ((RCC->HSICFGR & RCC_HSICFGR_HSIDIV) >> RCC_HSICFGR_HSIDIV_Pos);
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break;
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case RCC_PLL1CFGR1_PLL1SEL_0:
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sysclk = (READ_BIT(RCC->MSICFGR, RCC_MSICFGR_MSIFREQSEL) == 0UL) ? MSI_VALUE : 16000000UL;
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break;
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case RCC_PLL1CFGR1_PLL1SEL_1:
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sysclk = HSE_VALUE;
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break;
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case (RCC_PLL1CFGR1_PLL1SEL_1 | RCC_PLL1CFGR1_PLL1SEL_0):
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sysclk = EXTERNAL_I2S_CLOCK_VALUE;
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break;
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default:
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break;
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}
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if (pllbypass == 0U) {
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pllvco = ((float_t)sysclk * ((float_t)plln + ((float_t)pllfracn / (float_t)0x1000000UL))) / (float_t)pllm;
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sysclk = (uint32_t)((float_t)(pllvco / (((float_t)pllp1) * ((float_t)pllp2))));
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}
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ic_divider = (READ_BIT(RCC->IC1CFGR, RCC_IC1CFGR_IC1INT) >> RCC_IC1CFGR_IC1INT_Pos) + 1UL;
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sysclk = sysclk / ic_divider;
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break;
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default:
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break;
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}
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SystemCoreClock = sysclk;
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}
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/*
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* SystemClock_Config_Impl — bring the CPU up to a USB-friendly speed.
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*
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* Lifted from CubeN6's OBL reference (Projects/STM32N6570-DK/.../OBL/
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* Core/Src/main.c::SystemClock_Config). Targets:
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* PLL1 VCO = HSE 48 MHz / PLLM 3 * PLLN 50 = 800 MHz
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* PLL1 output = VCO / (PLLP1 1 * PLLP2 1) = 800 MHz
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* CPU = IC1 /2 = 400 MHz
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* SYSCLK = IC2/IC6/IC11 /2 = 400 MHz (AXI / NPU / AXISRAM3..6)
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* HCLK = SYSCLK /2 = 200 MHz
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* PCLK1..5 = HCLK / 1 = 200 MHz
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* XSPI2 kclk = IC3 = PLL1 / 24 = 33 MHz (sufficient for indirect-mode
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* program / erase; XIP reads happen via the same kclk
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* once memory-mapped mode is on)
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* USB1_OTG_HS = HSE_DIRECT / 2 (handled in usbd_conf.c::HAL_PCD_MspInit)
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* USBPHYC_CR.FSEL = 0b010 (24 MHz) — set in HAL_PCD_MspInit
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*/
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void SystemClock_Config_Impl(void)
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{
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RCC_OscInitTypeDef osc = {0};
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RCC_ClkInitTypeDef clk = {0};
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RCC_PeriphCLKInitTypeDef pclk = {0};
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/* Boot ROM may hand off with PLL1 already running (it cranks PLL1
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* for fast XSPI staging on the FSBL-load path). HAL_RCC_OscConfig
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* refuses to reconfigure PLL1 while it's the active source, so
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* we tear the clock tree back to defaults first. Caches must be
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* disabled across the teardown — boot ROM leaves stale lines, and
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* an instruction-prefetch refill during the CPU-clock switch from
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* PLL1 to HSI bus-faults and escalates to LOCKUP. */
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SCB_DisableICache();
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SCB_DisableDCache();
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System_DeInit();
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osc.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
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osc.HSIState = RCC_HSI_ON;
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osc.HSIDiv = RCC_HSI_DIV1;
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osc.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
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osc.HSEState = RCC_HSE_ON;
|
|
|
|
osc.PLL1.PLLState = RCC_PLL_ON;
|
|
osc.PLL1.PLLSource = RCC_PLLSOURCE_HSE;
|
|
osc.PLL1.PLLM = 3;
|
|
osc.PLL1.PLLN = 50;
|
|
osc.PLL1.PLLP1 = 1;
|
|
osc.PLL1.PLLP2 = 1;
|
|
osc.PLL1.PLLFractional = 0;
|
|
|
|
osc.PLL2.PLLState = RCC_PLL_OFF;
|
|
osc.PLL3.PLLState = RCC_PLL_OFF;
|
|
osc.PLL4.PLLState = RCC_PLL_OFF;
|
|
|
|
if (HAL_RCC_OscConfig(&osc) != HAL_OK) {
|
|
while (1) {}
|
|
}
|
|
|
|
clk.ClockType = RCC_CLOCKTYPE_CPUCLK | RCC_CLOCKTYPE_SYSCLK
|
|
| RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1
|
|
| RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_PCLK4
|
|
| RCC_CLOCKTYPE_PCLK5;
|
|
clk.CPUCLKSource = RCC_CPUCLKSOURCE_IC1;
|
|
clk.SYSCLKSource = RCC_SYSCLKSOURCE_IC2_IC6_IC11;
|
|
|
|
clk.IC1Selection.ClockSelection = RCC_ICCLKSOURCE_PLL1;
|
|
clk.IC1Selection.ClockDivider = 2;
|
|
clk.IC11Selection.ClockSelection = RCC_ICCLKSOURCE_PLL1;
|
|
clk.IC11Selection.ClockDivider = 2;
|
|
clk.IC2Selection.ClockSelection = RCC_ICCLKSOURCE_PLL1;
|
|
clk.IC2Selection.ClockDivider = 2;
|
|
clk.IC6Selection.ClockSelection = RCC_ICCLKSOURCE_PLL1;
|
|
clk.IC6Selection.ClockDivider = 2;
|
|
|
|
clk.AHBCLKDivider = RCC_HCLK_DIV2;
|
|
clk.APB1CLKDivider = RCC_APB1_DIV1;
|
|
clk.APB2CLKDivider = RCC_APB2_DIV1;
|
|
clk.APB4CLKDivider = RCC_APB4_DIV1;
|
|
clk.APB5CLKDivider = RCC_APB5_DIV1;
|
|
|
|
if (HAL_RCC_ClockConfig(&clk) != HAL_OK) {
|
|
while (1) {}
|
|
}
|
|
|
|
/* XSPI2 kernel clock from IC3 = PLL1 / 24 = 33 MHz. Slow vs the
|
|
* 133 MHz the chip can handle, but reliable for command-mode
|
|
* programming and we don't need XIP throughput in OBL. */
|
|
pclk.PeriphClockSelection = RCC_PERIPHCLK_XSPI2;
|
|
pclk.Xspi2ClockSelection = RCC_XSPI2CLKSOURCE_IC3;
|
|
pclk.ICSelection[RCC_IC3].ClockSelection = RCC_ICCLKSOURCE_PLL1;
|
|
pclk.ICSelection[RCC_IC3].ClockDivider = 24;
|
|
if (HAL_RCCEx_PeriphCLKConfig(&pclk) != HAL_OK) {
|
|
while (1) {}
|
|
}
|
|
__HAL_RCC_XSPI2_CLK_ENABLE();
|
|
|
|
SystemCoreClockUpdate();
|
|
}
|