46 lines
1.6 KiB
C
46 lines
1.6 KiB
C
/*
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* Minimal HAL MSP for the FSBL stub. Only XSPI2's MSP is non-trivial: it
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* enables the peripheral + XSPIM + GPION clocks and configures the eleven
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* GPIO N pins for XSPIM_P2. The boot ROM already picked a working XSPI2
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* clock source; we don't reconfigure it. 1S-1S-1S READ at the boot-ROM rate
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* is sufficient for XIP and works regardless of HSLV fuse state, so no BSEC
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* read is needed.
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*/
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#include "main.h"
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void HAL_MspInit(void)
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{
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HAL_PWREx_EnableVddIO3();
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}
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void HAL_XSPI_MspInit(XSPI_HandleTypeDef *hxspi)
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{
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if (hxspi->Instance != XSPI2) {
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return;
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}
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GPIO_InitTypeDef GPIO_InitStruct = {0};
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/* PWR clock is left on by the boot ROM. __HAL_RCC_PWR_CLK_ENABLE
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* lives behind CPU_IN_SECURE_STATE in stm32n6xx_hal_rcc.h, which pulls
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* in HAL_MPU_*_NS variants that require -mcmse. */
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HAL_PWREx_EnableVddIO3();
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HAL_PWREx_ConfigVddIORange(PWR_VDDIO3, PWR_VDDIO_RANGE_1V8);
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__HAL_RCC_XSPIM_CLK_ENABLE();
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__HAL_RCC_XSPI2_CLK_ENABLE();
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__HAL_RCC_GPION_CLK_ENABLE();
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/* PN0 -> DQS0, PN1 -> NCS1, PN2..PN5 -> IO0..IO3, PN6 -> CLK,
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* PN8..PN11 -> IO4..IO7. AF9 = XSPIM_P2 on every pin in this bank. */
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GPIO_InitStruct.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3
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| GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_8
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| GPIO_PIN_9 | GPIO_PIN_10 | GPIO_PIN_11;
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GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
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GPIO_InitStruct.Pull = GPIO_NOPULL;
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GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
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GPIO_InitStruct.Alternate = GPIO_AF9_XSPIM_P2;
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HAL_GPIO_Init(GPION, &GPIO_InitStruct);
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}
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