Sync betaflight to Gitea
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/*
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* HAL configuration for the Betaflight N6 OpenBootloader. Mirrors the FSBL
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* stub's trimmed config and adds IWDG (boot watchdog armed before BF jump)
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* and PCD (USB device for the DFU loop).
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*/
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#ifndef STM32N6xx_HAL_CONF_H
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#define STM32N6xx_HAL_CONF_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define HAL_MODULE_ENABLED
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#define HAL_CORTEX_MODULE_ENABLED
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#define HAL_RCC_MODULE_ENABLED
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#define HAL_PWR_MODULE_ENABLED
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#define HAL_GPIO_MODULE_ENABLED
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#define HAL_DMA_MODULE_ENABLED
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#define HAL_XSPI_MODULE_ENABLED
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#define HAL_IWDG_MODULE_ENABLED
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#define HAL_PCD_MODULE_ENABLED
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#if !defined(HSE_VALUE)
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#define HSE_VALUE 48000000UL
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#endif
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#if !defined(HSE_STARTUP_TIMEOUT)
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#define HSE_STARTUP_TIMEOUT 100UL
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#endif
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#if !defined(LSE_VALUE)
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#define LSE_VALUE 32768UL
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#endif
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#if !defined(LSE_STARTUP_TIMEOUT)
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#define LSE_STARTUP_TIMEOUT 5000UL
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#endif
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#if !defined(MSI_VALUE)
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#define MSI_VALUE 4000000UL
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#endif
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#if !defined(HSI_VALUE)
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#define HSI_VALUE 64000000UL
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#endif
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#if !defined(LSI_VALUE)
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#define LSI_VALUE 32000UL
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#endif
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#define VDD_VALUE 3300UL
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#define TICK_INT_PRIORITY 15U
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#define USE_RTOS 0U
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#define USE_HAL_XSPI_REGISTER_CALLBACKS 0U
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#define USE_HAL_PWR_REGISTER_CALLBACKS 0U
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#define USE_SPI_CRC 0U
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#ifdef HAL_RCC_MODULE_ENABLED
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#include "stm32n6xx_hal_rcc.h"
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#endif
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#ifdef HAL_GPIO_MODULE_ENABLED
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#include "stm32n6xx_hal_gpio.h"
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#endif
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#ifdef HAL_CORTEX_MODULE_ENABLED
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#include "stm32n6xx_hal_cortex.h"
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#endif
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#ifdef HAL_PWR_MODULE_ENABLED
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#include "stm32n6xx_hal_pwr.h"
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#endif
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#ifdef HAL_DMA_MODULE_ENABLED
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#include "stm32n6xx_hal_dma.h"
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#endif
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#ifdef HAL_XSPI_MODULE_ENABLED
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#include "stm32n6xx_hal_xspi.h"
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#endif
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#ifdef HAL_IWDG_MODULE_ENABLED
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#include "stm32n6xx_hal_iwdg.h"
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#endif
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#ifdef HAL_PCD_MODULE_ENABLED
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#include "stm32n6xx_hal_pcd.h"
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#endif
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#define assert_param(expr) ((void)0U)
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#ifdef __cplusplus
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}
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#endif
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#endif /* STM32N6xx_HAL_CONF_H */
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