Sync betaflight to Gitea
This commit is contained in:
@@ -0,0 +1,203 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file at32f435_437_acc.h
|
||||
* @brief at32f435_437 acc header file
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __AT32F435_437_ACC_H
|
||||
#define __AT32F435_437_ACC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "at32f435_437.h"
|
||||
|
||||
/** @addtogroup AT32F435_437_periph_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup ACC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup ACC_exported_constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define ACC_CAL_HICKCAL ((uint16_t)0x0000) /*!< acc hick calibration */
|
||||
#define ACC_CAL_HICKTRIM ((uint16_t)0x0002) /*!< acc hick trim */
|
||||
|
||||
#define ACC_RSLOST_FLAG ((uint16_t)0x0002) /*!< acc reference signal lost error flag */
|
||||
#define ACC_CALRDY_FLAG ((uint16_t)0x0001) /*!< acc internal high-speed clock calibration ready error flag */
|
||||
|
||||
#define ACC_CALRDYIEN_INT ((uint16_t)0x0020) /*!< acc internal high-speed clock calibration ready interrupt enable */
|
||||
#define ACC_EIEN_INT ((uint16_t)0x0010) /*!< acc reference signal lost interrupt enable */
|
||||
|
||||
#define ACC_SOF_OTG1 ((uint16_t)0x0000) /*!< acc sof signal select: otg1 */
|
||||
#define ACC_SOF_OTG2 ((uint16_t)0x0004) /*!< acc sof signal select: otg2 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ACC_exported_types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief type define acc register all
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
|
||||
/**
|
||||
* @brief acc sts register, offset:0x00
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t sts;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t calrdy : 1; /* [0] */
|
||||
__IO uint32_t rslost : 1; /* [1] */
|
||||
__IO uint32_t reserved1 : 30;/* [31:2] */
|
||||
} sts_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief acc ctrl1 register, offset:0x04
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ctrl1;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t calon : 1; /* [0] */
|
||||
__IO uint32_t entrim : 1; /* [1] */
|
||||
__IO uint32_t reserved1 : 2; /* [3:2] */
|
||||
__IO uint32_t eien : 1; /* [4] */
|
||||
__IO uint32_t calrdyien : 1; /* [5] */
|
||||
__IO uint32_t reserved2 : 2; /* [7:6] */
|
||||
__IO uint32_t step : 4; /* [11:8] */
|
||||
__IO uint32_t reserved3 : 20;/* [31:12] */
|
||||
} ctrl1_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief acc ctrl2 register, offset:0x08
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ctrl2;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t hickcal : 8; /* [7:0] */
|
||||
__IO uint32_t hicktrim : 6; /* [13:8] */
|
||||
__IO uint32_t reserved1 : 18;/* [31:14] */
|
||||
} ctrl2_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief acc acc_c1 register, offset:0x0C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t c1;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t c1 : 16;/* [15:0] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:16] */
|
||||
} c1_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief acc acc_c2 register, offset:0x10
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t c2;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t c2 : 16;/* [15:0] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:16] */
|
||||
} c2_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief acc acc_c3 register, offset:0x14
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t c3;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t c3 : 16;/* [15:0] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:16] */
|
||||
} c3_bit;
|
||||
};
|
||||
} acc_type;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#define ACC_REGS ((acc_type *) ACC_BASE)
|
||||
|
||||
/** @defgroup ACC_exported_functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void acc_calibration_mode_enable(uint16_t acc_trim, confirm_state new_state);
|
||||
void acc_step_set(uint8_t step_value);
|
||||
void acc_sof_select(uint16_t sof_sel);
|
||||
void acc_interrupt_enable(uint16_t acc_int, confirm_state new_state);
|
||||
uint8_t acc_hicktrim_get(void);
|
||||
uint8_t acc_hickcal_get(void);
|
||||
void acc_write_c1(uint16_t acc_c1_value);
|
||||
void acc_write_c2(uint16_t acc_c2_value);
|
||||
void acc_write_c3(uint16_t acc_c3_value);
|
||||
uint16_t acc_read_c1(void);
|
||||
uint16_t acc_read_c2(void);
|
||||
uint16_t acc_read_c3(void);
|
||||
flag_status acc_flag_get(uint16_t acc_flag);
|
||||
void acc_flag_clear(uint16_t acc_flag);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,936 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file at32f435_437_adc.h
|
||||
* @brief at32f435_437 adc header file
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __AT32F435_437_ADC_H
|
||||
#define __AT32F435_437_ADC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "at32f435_437.h"
|
||||
|
||||
|
||||
/** @addtogroup AT32F435_437_periph_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup ADC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_interrupts_definition
|
||||
* @brief adc interrupt
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define ADC_OCCE_INT ((uint32_t)0x00000020) /*!< ordinary channels conversion end interrupt */
|
||||
#define ADC_VMOR_INT ((uint32_t)0x00000040) /*!< voltage monitoring out of range interrupt */
|
||||
#define ADC_PCCE_INT ((uint32_t)0x00000080) /*!< preempt channels conversion end interrupt */
|
||||
#define ADC_OCCO_INT ((uint32_t)0x04000000) /*!< ordinary channel conversion overflow interrupt */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_flags_definition
|
||||
* @brief adc flag
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define ADC_VMOR_FLAG ((uint8_t)0x01) /*!< voltage monitoring out of range flag */
|
||||
#define ADC_OCCE_FLAG ((uint8_t)0x02) /*!< ordinary channels conversion end flag */
|
||||
#define ADC_PCCE_FLAG ((uint8_t)0x04) /*!< preempt channels conversion end flag */
|
||||
#define ADC_PCCS_FLAG ((uint8_t)0x08) /*!< preempt channel conversion start flag */
|
||||
#define ADC_OCCS_FLAG ((uint8_t)0x10) /*!< ordinary channel conversion start flag */
|
||||
#define ADC_OCCO_FLAG ((uint8_t)0x20) /*!< ordinary channel conversion overflow flag */
|
||||
#define ADC_RDY_FLAG ((uint8_t)0x40) /*!< adc ready to conversion flag */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_exported_types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief adc division type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
ADC_HCLK_DIV_2 = 0x00, /*!< adcclk is hclk/2 */
|
||||
ADC_HCLK_DIV_3 = 0x01, /*!< adcclk is hclk/3 */
|
||||
ADC_HCLK_DIV_4 = 0x02, /*!< adcclk is hclk/4 */
|
||||
ADC_HCLK_DIV_5 = 0x03, /*!< adcclk is hclk/5 */
|
||||
ADC_HCLK_DIV_6 = 0x04, /*!< adcclk is hclk/6 */
|
||||
ADC_HCLK_DIV_7 = 0x05, /*!< adcclk is hclk/7 */
|
||||
ADC_HCLK_DIV_8 = 0x06, /*!< adcclk is hclk/8 */
|
||||
ADC_HCLK_DIV_9 = 0x07, /*!< adcclk is hclk/9 */
|
||||
ADC_HCLK_DIV_10 = 0x08, /*!< adcclk is hclk/10 */
|
||||
ADC_HCLK_DIV_11 = 0x09, /*!< adcclk is hclk/11 */
|
||||
ADC_HCLK_DIV_12 = 0x0A, /*!< adcclk is hclk/12 */
|
||||
ADC_HCLK_DIV_13 = 0x0B, /*!< adcclk is hclk/13 */
|
||||
ADC_HCLK_DIV_14 = 0x0C, /*!< adcclk is hclk/14 */
|
||||
ADC_HCLK_DIV_15 = 0x0D, /*!< adcclk is hclk/15 */
|
||||
ADC_HCLK_DIV_16 = 0x0E, /*!< adcclk is hclk/16 */
|
||||
ADC_HCLK_DIV_17 = 0x0F /*!< adcclk is hclk/17 */
|
||||
} adc_div_type;
|
||||
|
||||
/**
|
||||
* @brief adc combine mode type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
ADC_INDEPENDENT_MODE = 0x00, /*!< independent mode */
|
||||
ADC_ORDINARY_SMLT_PREEMPT_SMLT_ONESLAVE_MODE = 0x01, /*!< single slaver combined ordinary simultaneous + preempt simultaneous mode */
|
||||
ADC_ORDINARY_SMLT_PREEMPT_INTERLTRIG_ONESLAVE_MODE = 0x02, /*!< single slaver combined ordinary simultaneous + preempt interleaved trigger mode */
|
||||
ADC_PREEMPT_SMLT_ONLY_ONESLAVE_MODE = 0x05, /*!< single slaver preempt simultaneous mode only */
|
||||
ADC_ORDINARY_SMLT_ONLY_ONESLAVE_MODE = 0x06, /*!< single slaver ordinary simultaneous mode only */
|
||||
ADC_ORDINARY_SHIFT_ONLY_ONESLAVE_MODE = 0x07, /*!< single slaver ordinary shifting mode only */
|
||||
ADC_PREEMPT_INTERLTRIG_ONLY_ONESLAVE_MODE = 0x09, /*!< single slaver preempt interleaved trigger mode only */
|
||||
ADC_ORDINARY_SMLT_PREEMPT_SMLT_TWOSLAVE_MODE = 0x11, /*!< double slaver combined ordinary simultaneous + preempt simultaneous mode */
|
||||
ADC_ORDINARY_SMLT_PREEMPT_INTERLTRIG_TWOSLAVE_MODE = 0x12, /*!< double slaver combined ordinary simultaneous + preempt interleaved trigger mode */
|
||||
ADC_PREEMPT_SMLT_ONLY_TWOSLAVE_MODE = 0x15, /*!< double slaver preempt simultaneous mode only */
|
||||
ADC_ORDINARY_SMLT_ONLY_TWOSLAVE_MODE = 0x16, /*!< double slaver ordinary simultaneous mode only */
|
||||
ADC_ORDINARY_SHIFT_ONLY_TWOSLAVE_MODE = 0x17, /*!< double slaver ordinary shifting mode only */
|
||||
ADC_PREEMPT_INTERLTRIG_ONLY_TWOSLAVE_MODE = 0x19 /*!< double slaver preempt interleaved trigger mode only */
|
||||
} adc_combine_mode_type;
|
||||
|
||||
/**
|
||||
* @brief adc common dma mode type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
ADC_COMMON_DMAMODE_DISABLE = 0x00, /*!< dma mode disabled */
|
||||
ADC_COMMON_DMAMODE_1 = 0x01, /*!< dma mode1: each dma request trans a half-word data(reference manual account the rule of data package) */
|
||||
ADC_COMMON_DMAMODE_2 = 0x02, /*!< dma mode2: each dma request trans two half-word data(reference manual account the rule of data package) */
|
||||
ADC_COMMON_DMAMODE_3 = 0x03, /*!< dma mode3: each dma request trans two bytes data(reference manual account the rule of data package) */
|
||||
ADC_COMMON_DMAMODE_4 = 0x04, /*!< dma mode4: each dma request trans three bytes data(reference manual account the rule of data package) */
|
||||
ADC_COMMON_DMAMODE_5 = 0x05 /*!< dma mode5: odd dma request trans two half-word data,even dma request trans a half-word data(reference manual account the rule of data package) */
|
||||
} adc_common_dma_mode_type;
|
||||
|
||||
/**
|
||||
* @brief adc common sampling interval type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
ADC_SAMPLING_INTERVAL_5CYCLES = 0x00, /*!< ordinary shifting mode adjacent adc sampling interval 5 adcclk */
|
||||
ADC_SAMPLING_INTERVAL_6CYCLES = 0x01, /*!< ordinary shifting mode adjacent adc sampling interval 6 adcclk */
|
||||
ADC_SAMPLING_INTERVAL_7CYCLES = 0x02, /*!< ordinary shifting mode adjacent adc sampling interval 7 adcclk */
|
||||
ADC_SAMPLING_INTERVAL_8CYCLES = 0x03, /*!< ordinary shifting mode adjacent adc sampling interval 8 adcclk */
|
||||
ADC_SAMPLING_INTERVAL_9CYCLES = 0x04, /*!< ordinary shifting mode adjacent adc sampling interval 9 adcclk */
|
||||
ADC_SAMPLING_INTERVAL_10CYCLES = 0x05, /*!< ordinary shifting mode adjacent adc sampling interval 10 adcclk */
|
||||
ADC_SAMPLING_INTERVAL_11CYCLES = 0x06, /*!< ordinary shifting mode adjacent adc sampling interval 11 adcclk */
|
||||
ADC_SAMPLING_INTERVAL_12CYCLES = 0x07, /*!< ordinary shifting mode adjacent adc sampling interval 12 adcclk */
|
||||
ADC_SAMPLING_INTERVAL_13CYCLES = 0x08, /*!< ordinary shifting mode adjacent adc sampling interval 13 adcclk */
|
||||
ADC_SAMPLING_INTERVAL_14CYCLES = 0x09, /*!< ordinary shifting mode adjacent adc sampling interval 14 adcclk */
|
||||
ADC_SAMPLING_INTERVAL_15CYCLES = 0x0A, /*!< ordinary shifting mode adjacent adc sampling interval 15 adcclk */
|
||||
ADC_SAMPLING_INTERVAL_16CYCLES = 0x0B, /*!< ordinary shifting mode adjacent adc sampling interval 16 adcclk */
|
||||
ADC_SAMPLING_INTERVAL_17CYCLES = 0x0C, /*!< ordinary shifting mode adjacent adc sampling interval 17 adcclk */
|
||||
ADC_SAMPLING_INTERVAL_18CYCLES = 0x0D, /*!< ordinary shifting mode adjacent adc sampling interval 18 adcclk */
|
||||
ADC_SAMPLING_INTERVAL_19CYCLES = 0x0E, /*!< ordinary shifting mode adjacent adc sampling interval 19 adcclk */
|
||||
ADC_SAMPLING_INTERVAL_20CYCLES = 0x0F /*!< ordinary shifting mode adjacent adc sampling interval 20 adcclk */
|
||||
} adc_sampling_interval_type;
|
||||
|
||||
/**
|
||||
* @brief adc conversion resolution type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
ADC_RESOLUTION_12B = 0x00, /*!< conversion resolution 12 bit */
|
||||
ADC_RESOLUTION_10B = 0x01, /*!< conversion resolution 10 bit */
|
||||
ADC_RESOLUTION_8B = 0x02, /*!< conversion resolution 8 bit */
|
||||
ADC_RESOLUTION_6B = 0x03 /*!< conversion resolution 6 bit */
|
||||
} adc_resolution_type;
|
||||
|
||||
/**
|
||||
* @brief adc data align type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
ADC_RIGHT_ALIGNMENT = 0x00, /*!< data right alignment */
|
||||
ADC_LEFT_ALIGNMENT = 0x01 /*!< data left alignment */
|
||||
} adc_data_align_type;
|
||||
|
||||
/**
|
||||
* @brief adc channel select type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
ADC_CHANNEL_0 = 0x00, /*!< adc channel 0 */
|
||||
ADC_CHANNEL_1 = 0x01, /*!< adc channel 1 */
|
||||
ADC_CHANNEL_2 = 0x02, /*!< adc channel 2 */
|
||||
ADC_CHANNEL_3 = 0x03, /*!< adc channel 3 */
|
||||
ADC_CHANNEL_4 = 0x04, /*!< adc channel 4 */
|
||||
ADC_CHANNEL_5 = 0x05, /*!< adc channel 5 */
|
||||
ADC_CHANNEL_6 = 0x06, /*!< adc channel 6 */
|
||||
ADC_CHANNEL_7 = 0x07, /*!< adc channel 7 */
|
||||
ADC_CHANNEL_8 = 0x08, /*!< adc channel 8 */
|
||||
ADC_CHANNEL_9 = 0x09, /*!< adc channel 9 */
|
||||
ADC_CHANNEL_10 = 0x0A, /*!< adc channel 10 */
|
||||
ADC_CHANNEL_11 = 0x0B, /*!< adc channel 11 */
|
||||
ADC_CHANNEL_12 = 0x0C, /*!< adc channel 12 */
|
||||
ADC_CHANNEL_13 = 0x0D, /*!< adc channel 13 */
|
||||
ADC_CHANNEL_14 = 0x0E, /*!< adc channel 14 */
|
||||
ADC_CHANNEL_15 = 0x0F, /*!< adc channel 15 */
|
||||
ADC_CHANNEL_16 = 0x10, /*!< adc channel 16 */
|
||||
ADC_CHANNEL_17 = 0x11, /*!< adc channel 17 */
|
||||
ADC_CHANNEL_18 = 0x12 /*!< adc channel 18 */
|
||||
} adc_channel_select_type;
|
||||
|
||||
/**
|
||||
* @brief adc sampletime select type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
ADC_SAMPLETIME_2_5 = 0x00, /*!< adc sample time 2.5 cycle */
|
||||
ADC_SAMPLETIME_6_5 = 0x01, /*!< adc sample time 6.5 cycle */
|
||||
ADC_SAMPLETIME_12_5 = 0x02, /*!< adc sample time 12.5 cycle */
|
||||
ADC_SAMPLETIME_24_5 = 0x03, /*!< adc sample time 24.5 cycle */
|
||||
ADC_SAMPLETIME_47_5 = 0x04, /*!< adc sample time 47.5 cycle */
|
||||
ADC_SAMPLETIME_92_5 = 0x05, /*!< adc sample time 92.5 cycle */
|
||||
ADC_SAMPLETIME_247_5 = 0x06, /*!< adc sample time 247.5 cycle */
|
||||
ADC_SAMPLETIME_640_5 = 0x07 /*!< adc sample time 640.5 cycle */
|
||||
} adc_sampletime_select_type;
|
||||
|
||||
/**
|
||||
* @brief adc ordinary group trigger event select type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
ADC_ORDINARY_TRIG_TMR1CH1 = 0x00, /*!< timer1 ch1 event as trigger source of ordinary sequence */
|
||||
ADC_ORDINARY_TRIG_TMR1CH2 = 0x01, /*!< timer1 ch2 event as trigger source of ordinary sequence */
|
||||
ADC_ORDINARY_TRIG_TMR1CH3 = 0x02, /*!< timer1 ch3 event as trigger source of ordinary sequence */
|
||||
ADC_ORDINARY_TRIG_TMR2CH2 = 0x03, /*!< timer2 ch2 event as trigger source of ordinary sequence */
|
||||
ADC_ORDINARY_TRIG_TMR2CH3 = 0x04, /*!< timer2 ch3 event as trigger source of ordinary sequence */
|
||||
ADC_ORDINARY_TRIG_TMR2CH4 = 0x05, /*!< timer2 ch4 event as trigger source of ordinary sequence */
|
||||
ADC_ORDINARY_TRIG_TMR2TRGOUT = 0x06, /*!< timer2 trgout event as trigger source of ordinary sequence */
|
||||
ADC_ORDINARY_TRIG_TMR3CH1 = 0x07, /*!< timer3 ch1 event as trigger source of ordinary sequence */
|
||||
ADC_ORDINARY_TRIG_TMR3TRGOUT = 0x08, /*!< timer3 trgout event as trigger source of ordinary sequence */
|
||||
ADC_ORDINARY_TRIG_TMR4CH4 = 0x09, /*!< timer4 ch4 event as trigger source of ordinary sequence */
|
||||
ADC_ORDINARY_TRIG_TMR5CH1 = 0x0A, /*!< timer5 ch1 event as trigger source of ordinary sequence */
|
||||
ADC_ORDINARY_TRIG_TMR5CH2 = 0x0B, /*!< timer5 ch2 event as trigger source of ordinary sequence */
|
||||
ADC_ORDINARY_TRIG_TMR5CH3 = 0x0C, /*!< timer5 ch3 event as trigger source of ordinary sequence */
|
||||
ADC_ORDINARY_TRIG_TMR8CH1 = 0x0D, /*!< timer8 ch1 event as trigger source of ordinary sequence */
|
||||
ADC_ORDINARY_TRIG_TMR8TRGOUT = 0x0E, /*!< timer8 trgout event as trigger source of ordinary sequence */
|
||||
ADC_ORDINARY_TRIG_EXINT11 = 0x0F, /*!< exint line11 event as trigger source of ordinary sequence */
|
||||
ADC_ORDINARY_TRIG_TMR20TRGOUT = 0x10, /*!< timer20 trgout event as trigger source of ordinary sequence */
|
||||
ADC_ORDINARY_TRIG_TMR20TRGOUT2 = 0x11, /*!< timer20 trgout2 event as trigger source of ordinary sequence */
|
||||
ADC_ORDINARY_TRIG_TMR20CH1 = 0x12, /*!< timer20 ch1 event as trigger source of ordinary sequence */
|
||||
ADC_ORDINARY_TRIG_TMR20CH2 = 0x13, /*!< timer20 ch2 event as trigger source of ordinary sequence */
|
||||
ADC_ORDINARY_TRIG_TMR20CH3 = 0x14, /*!< timer20 ch3 event as trigger source of ordinary sequence */
|
||||
ADC_ORDINARY_TRIG_TMR8TRGOUT2 = 0x15, /*!< timer8 trgout2 event as trigger source of ordinary sequence */
|
||||
ADC_ORDINARY_TRIG_TMR1TRGOUT2 = 0x16, /*!< timer1 trgout2 event as trigger source of ordinary sequence */
|
||||
ADC_ORDINARY_TRIG_TMR4TRGOUT = 0x17, /*!< timer4 trgout event as trigger source of ordinary sequence */
|
||||
ADC_ORDINARY_TRIG_TMR6TRGOUT = 0x18, /*!< timer6 trgout event as trigger source of ordinary sequence */
|
||||
ADC_ORDINARY_TRIG_TMR3CH4 = 0x19, /*!< timer3 ch4 event as trigger source of ordinary sequence */
|
||||
ADC_ORDINARY_TRIG_TMR4CH1 = 0x1A, /*!< timer4 ch1 event as trigger source of ordinary sequence */
|
||||
ADC_ORDINARY_TRIG_TMR1TRGOUT = 0x1B, /*!< timer1 trgout event as trigger source of ordinary sequence */
|
||||
ADC_ORDINARY_TRIG_TMR2CH1 = 0x1C, /*!< timer2 ch1 event as trigger source of ordinary sequence */
|
||||
ADC_ORDINARY_TRIG_TMR7TRGOUT = 0x1E /*!< timer7 trgout event as trigger source of ordinary sequence */
|
||||
} adc_ordinary_trig_select_type;
|
||||
|
||||
/**
|
||||
* @brief adc ordinary channel conversion's external_trigger_edge type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
ADC_ORDINARY_TRIG_EDGE_NONE = 0x00, /*!< ordinary channels trigger detection disabled */
|
||||
ADC_ORDINARY_TRIG_EDGE_RISING = 0x01, /*!< ordinary channels trigger detection on the rising edge */
|
||||
ADC_ORDINARY_TRIG_EDGE_FALLING = 0x02, /*!< ordinary channels trigger detection on the falling edge */
|
||||
ADC_ORDINARY_TRIG_EDGE_RISING_FALLING = 0x03 /*!< ordinary channels trigger detection on both the rising and falling edges */
|
||||
} adc_ordinary_trig_edge_type;
|
||||
|
||||
/**
|
||||
* @brief adc preempt group external trigger event select type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
ADC_PREEMPT_TRIG_TMR1CH4 = 0x00, /*!< timer1 ch4 event as trigger source of preempt sequence */
|
||||
ADC_PREEMPT_TRIG_TMR1TRGOUT = 0x01, /*!< timer1 trgout event as trigger source of preempt sequence */
|
||||
ADC_PREEMPT_TRIG_TMR2CH1 = 0x02, /*!< timer2 ch1 event as trigger source of preempt sequence */
|
||||
ADC_PREEMPT_TRIG_TMR2TRGOUT = 0x03, /*!< timer2 trgout event as trigger source of preempt sequence */
|
||||
ADC_PREEMPT_TRIG_TMR3CH2 = 0x04, /*!< timer3 ch2 event as trigger source of preempt sequence */
|
||||
ADC_PREEMPT_TRIG_TMR3CH4 = 0x05, /*!< timer3 ch4 event as trigger source of preempt sequence */
|
||||
ADC_PREEMPT_TRIG_TMR4CH1 = 0x06, /*!< timer4 ch1 event as trigger source of preempt sequence */
|
||||
ADC_PREEMPT_TRIG_TMR4CH2 = 0x07, /*!< timer4 ch2 event as trigger source of preempt sequence */
|
||||
ADC_PREEMPT_TRIG_TMR4CH3 = 0x08, /*!< timer4 ch3 event as trigger source of preempt sequence */
|
||||
ADC_PREEMPT_TRIG_TMR4TRGOUT = 0x09, /*!< timer4 trgout event as trigger source of preempt sequence */
|
||||
ADC_PREEMPT_TRIG_TMR5CH4 = 0x0A, /*!< timer5 ch4 event as trigger source of preempt sequence */
|
||||
ADC_PREEMPT_TRIG_TMR5TRGOUT = 0x0B, /*!< timer5 trgout event as trigger source of preempt sequence */
|
||||
ADC_PREEMPT_TRIG_TMR8CH2 = 0x0C, /*!< timer8 ch2 event as trigger source of preempt sequence */
|
||||
ADC_PREEMPT_TRIG_TMR8CH3 = 0x0D, /*!< timer8 ch3 event as trigger source of preempt sequence */
|
||||
ADC_PREEMPT_TRIG_TMR8CH4 = 0x0E, /*!< timer8 ch4 event as trigger source of preempt sequence */
|
||||
ADC_PREEMPT_TRIG_EXINT15 = 0x0F, /*!< exint line15 event as trigger source of preempt sequence */
|
||||
ADC_PREEMPT_TRIG_TMR20TRGOUT = 0x10, /*!< timer20 trgout event as trigger source of preempt sequence */
|
||||
ADC_PREEMPT_TRIG_TMR20TRGOUT2 = 0x11, /*!< timer20 trgout2 event as trigger source of preempt sequence */
|
||||
ADC_PREEMPT_TRIG_TMR20CH4 = 0x12, /*!< timer20 ch4 event as trigger source of preempt sequence */
|
||||
ADC_PREEMPT_TRIG_TMR1TRGOUT2 = 0x13, /*!< timer1 trgout2 event as trigger source of preempt sequence */
|
||||
ADC_PREEMPT_TRIG_TMR8TRGOUT = 0x14, /*!< timer8 trgout event as trigger source of preempt sequence */
|
||||
ADC_PREEMPT_TRIG_TMR8TRGOUT2 = 0x15, /*!< timer8 trgout2 event as trigger source of preempt sequence */
|
||||
ADC_PREEMPT_TRIG_TMR3CH3 = 0x16, /*!< timer3 ch3 event as trigger source of preempt sequence */
|
||||
ADC_PREEMPT_TRIG_TMR3TRGOUT = 0x17, /*!< timer3 trgout event as trigger source of preempt sequence */
|
||||
ADC_PREEMPT_TRIG_TMR3CH1 = 0x18, /*!< timer3 ch1 event as trigger source of preempt sequence */
|
||||
ADC_PREEMPT_TRIG_TMR6TRGOUT = 0x19, /*!< timer6 trgout event as trigger source of preempt sequence */
|
||||
ADC_PREEMPT_TRIG_TMR4CH4 = 0x1A, /*!< timer4 ch4 event as trigger source of preempt sequence */
|
||||
ADC_PREEMPT_TRIG_TMR1CH3 = 0x1B, /*!< timer1 ch3 event as trigger source of preempt sequence */
|
||||
ADC_PREEMPT_TRIG_TMR20CH2 = 0x1C, /*!< timer20 ch2 event as trigger source of preempt sequence */
|
||||
ADC_PREEMPT_TRIG_TMR7TRGOUT = 0x1E /*!< timer7 trgout event as trigger source of preempt sequence */
|
||||
} adc_preempt_trig_select_type;
|
||||
|
||||
/**
|
||||
* @brief adc preempt channel conversion's external_trigger_edge type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
ADC_PREEMPT_TRIG_EDGE_NONE = 0x00, /*!< preempt channels trigger detection disabled */
|
||||
ADC_PREEMPT_TRIG_EDGE_RISING = 0x01, /*!< preempt channels trigger detection on the rising edge */
|
||||
ADC_PREEMPT_TRIG_EDGE_FALLING = 0x02, /*!< preempt channels trigger detection on the falling edge */
|
||||
ADC_PREEMPT_TRIG_EDGE_RISING_FALLING = 0x03 /*!< preempt channels trigger detection on both the rising and falling edges */
|
||||
} adc_preempt_trig_edge_type;
|
||||
|
||||
/**
|
||||
* @brief adc preempt channel type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
ADC_PREEMPT_CHANNEL_1 = 0x00, /*!< adc preempt channel 1 */
|
||||
ADC_PREEMPT_CHANNEL_2 = 0x01, /*!< adc preempt channel 2 */
|
||||
ADC_PREEMPT_CHANNEL_3 = 0x02, /*!< adc preempt channel 3 */
|
||||
ADC_PREEMPT_CHANNEL_4 = 0x03 /*!< adc preempt channel 4 */
|
||||
} adc_preempt_channel_type;
|
||||
|
||||
/**
|
||||
* @brief adc voltage_monitoring type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
ADC_VMONITOR_SINGLE_ORDINARY = 0x00800200, /*!< voltage_monitoring on a single ordinary channel */
|
||||
ADC_VMONITOR_SINGLE_PREEMPT = 0x00400200, /*!< voltage_monitoring on a single preempt channel */
|
||||
ADC_VMONITOR_SINGLE_ORDINARY_PREEMPT = 0x00C00200, /*!< voltage_monitoring on a single ordinary or preempt channel */
|
||||
ADC_VMONITOR_ALL_ORDINARY = 0x00800000, /*!< voltage_monitoring on all ordinary channel */
|
||||
ADC_VMONITOR_ALL_PREEMPT = 0x00400000, /*!< voltage_monitoring on all preempt channel */
|
||||
ADC_VMONITOR_ALL_ORDINARY_PREEMPT = 0x00C00000, /*!< voltage_monitoring on all ordinary and preempt channel */
|
||||
ADC_VMONITOR_NONE = 0x00000000 /*!< no channel guarded by the voltage_monitoring */
|
||||
} adc_voltage_monitoring_type;
|
||||
|
||||
/**
|
||||
* @brief adc oversample ratio type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
ADC_OVERSAMPLE_RATIO_2 = 0x00, /*!< adc oversample ratio 2 */
|
||||
ADC_OVERSAMPLE_RATIO_4 = 0x01, /*!< adc oversample ratio 4 */
|
||||
ADC_OVERSAMPLE_RATIO_8 = 0x02, /*!< adc oversample ratio 8 */
|
||||
ADC_OVERSAMPLE_RATIO_16 = 0x03, /*!< adc oversample ratio 16 */
|
||||
ADC_OVERSAMPLE_RATIO_32 = 0x04, /*!< adc oversample ratio 32 */
|
||||
ADC_OVERSAMPLE_RATIO_64 = 0x05, /*!< adc oversample ratio 64 */
|
||||
ADC_OVERSAMPLE_RATIO_128 = 0x06, /*!< adc oversample ratio 128 */
|
||||
ADC_OVERSAMPLE_RATIO_256 = 0x07 /*!< adc oversample ratio 256 */
|
||||
} adc_oversample_ratio_type;
|
||||
|
||||
/**
|
||||
* @brief adc oversample shift type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
ADC_OVERSAMPLE_SHIFT_0 = 0x00, /*!< adc oversample shift 0 */
|
||||
ADC_OVERSAMPLE_SHIFT_1 = 0x01, /*!< adc oversample shift 1 */
|
||||
ADC_OVERSAMPLE_SHIFT_2 = 0x02, /*!< adc oversample shift 2 */
|
||||
ADC_OVERSAMPLE_SHIFT_3 = 0x03, /*!< adc oversample shift 3 */
|
||||
ADC_OVERSAMPLE_SHIFT_4 = 0x04, /*!< adc oversample shift 4 */
|
||||
ADC_OVERSAMPLE_SHIFT_5 = 0x05, /*!< adc oversample shift 5 */
|
||||
ADC_OVERSAMPLE_SHIFT_6 = 0x06, /*!< adc oversample shift 6 */
|
||||
ADC_OVERSAMPLE_SHIFT_7 = 0x07, /*!< adc oversample shift 7 */
|
||||
ADC_OVERSAMPLE_SHIFT_8 = 0x08 /*!< adc oversample shift 8 */
|
||||
} adc_oversample_shift_type;
|
||||
|
||||
/**
|
||||
* @brief adc ordinary oversample recover type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
ADC_OVERSAMPLE_CONTINUE = 0x00, /*!< continue mode:when preempt triggered,oversampling is temporary stopped and continued after preempt sequence */
|
||||
ADC_OVERSAMPLE_RESTART = 0x01 /*!< restart mode:when preempt triggered,oversampling is aborted and resumed from start after preempt sequence */
|
||||
} adc_ordinary_oversample_restart_type;
|
||||
|
||||
/**
|
||||
* @brief adc common config type
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
adc_combine_mode_type combine_mode; /*!< adc combine mode select */
|
||||
adc_div_type div; /*!< adc division select */
|
||||
adc_common_dma_mode_type common_dma_mode; /*!< adc common dma mode select */
|
||||
confirm_state common_dma_request_repeat_state; /*!< adc common dma repeat state */
|
||||
adc_sampling_interval_type sampling_interval; /*!< ordinary shifting mode adjacent adc sampling interval select */
|
||||
confirm_state tempervintrv_state; /*!< adc temperature sensor and vintrv state */
|
||||
confirm_state vbat_state; /*!< adc voltage battery state */
|
||||
} adc_common_config_type;
|
||||
|
||||
/**
|
||||
* @brief adc base config type
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
confirm_state sequence_mode; /*!< adc sequence mode */
|
||||
confirm_state repeat_mode; /*!< adc repeat mode */
|
||||
adc_data_align_type data_align; /*!< adc data alignment */
|
||||
uint8_t ordinary_channel_length; /*!< adc ordinary channel sequence length*/
|
||||
} adc_base_config_type;
|
||||
|
||||
/**
|
||||
* @brief type define adc register all
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
|
||||
/**
|
||||
* @brief adc sts register, offset:0x00
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t sts;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t vmor : 1; /* [0] */
|
||||
__IO uint32_t occe : 1; /* [1] */
|
||||
__IO uint32_t pcce : 1; /* [2] */
|
||||
__IO uint32_t pccs : 1; /* [3] */
|
||||
__IO uint32_t occs : 1; /* [4] */
|
||||
__IO uint32_t occo : 1; /* [5] */
|
||||
__IO uint32_t rdy : 1; /* [6] */
|
||||
__IO uint32_t reserved1 : 25;/* [31:7] */
|
||||
} sts_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief adc ctrl1 register, offset:0x04
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ctrl1;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t vmcsel : 5; /* [4:0] */
|
||||
__IO uint32_t occeien : 1; /* [5] */
|
||||
__IO uint32_t vmorien : 1; /* [6] */
|
||||
__IO uint32_t pcceien : 1; /* [7] */
|
||||
__IO uint32_t sqen : 1; /* [8] */
|
||||
__IO uint32_t vmsgen : 1; /* [9] */
|
||||
__IO uint32_t pcautoen : 1; /* [10] */
|
||||
__IO uint32_t ocpen : 1; /* [11] */
|
||||
__IO uint32_t pcpen : 1; /* [12] */
|
||||
__IO uint32_t ocpcnt : 3; /* [15:13] */
|
||||
__IO uint32_t reserved1 : 6; /* [21:16] */
|
||||
__IO uint32_t pcvmen : 1; /* [22] */
|
||||
__IO uint32_t ocvmen : 1; /* [23] */
|
||||
__IO uint32_t crsel : 2; /* [25:24] */
|
||||
__IO uint32_t occoien : 1; /* [26] */
|
||||
__IO uint32_t reserved2 : 5; /* [31:27] */
|
||||
} ctrl1_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief adc ctrl2 register, offset:0x08
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ctrl2;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t adcen : 1; /* [0] */
|
||||
__IO uint32_t rpen : 1; /* [1] */
|
||||
__IO uint32_t adcal : 1; /* [2] */
|
||||
__IO uint32_t adcalinit : 1; /* [3] */
|
||||
__IO uint32_t adabrt : 1; /* [4] */
|
||||
__IO uint32_t reserved1 : 3; /* [7:5] */
|
||||
__IO uint32_t ocdmaen : 1; /* [8] */
|
||||
__IO uint32_t ocdrcen : 1; /* [9] */
|
||||
__IO uint32_t eocsfen : 1; /* [10] */
|
||||
__IO uint32_t dtalign : 1; /* [11] */
|
||||
__IO uint32_t reserved2 : 4; /* [15:12] */
|
||||
__IO uint32_t pctesel_l : 4; /* [19:16] */
|
||||
__IO uint32_t pcete : 2; /* [21:20] */
|
||||
__IO uint32_t pcswtrg : 1; /* [22] */
|
||||
__IO uint32_t pctesel_h : 1; /* [23] */
|
||||
__IO uint32_t octesel_l : 4; /* [27:24] */
|
||||
__IO uint32_t ocete : 2; /* [29:28] */
|
||||
__IO uint32_t ocswtrg : 1; /* [30] */
|
||||
__IO uint32_t octesel_h : 1; /* [31] */
|
||||
} ctrl2_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief adc spt1 register, offset:0x0C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t spt1;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t cspt10 : 3; /* [2:0] */
|
||||
__IO uint32_t cspt11 : 3; /* [5:3] */
|
||||
__IO uint32_t cspt12 : 3; /* [8:6] */
|
||||
__IO uint32_t cspt13 : 3; /* [11:9] */
|
||||
__IO uint32_t cspt14 : 3; /* [14:12] */
|
||||
__IO uint32_t cspt15 : 3; /* [17:15] */
|
||||
__IO uint32_t cspt16 : 3; /* [20:18] */
|
||||
__IO uint32_t cspt17 : 3; /* [23:21] */
|
||||
__IO uint32_t cspt18 : 3; /* [26:24] */
|
||||
__IO uint32_t reserved1 : 5;/* [31:27] */
|
||||
} spt1_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief adc spt2 register, offset:0x10
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t spt2;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t cspt0 : 3;/* [2:0] */
|
||||
__IO uint32_t cspt1 : 3;/* [5:3] */
|
||||
__IO uint32_t cspt2 : 3;/* [8:6] */
|
||||
__IO uint32_t cspt3 : 3;/* [11:9] */
|
||||
__IO uint32_t cspt4 : 3;/* [14:12] */
|
||||
__IO uint32_t cspt5 : 3;/* [17:15] */
|
||||
__IO uint32_t cspt6 : 3;/* [20:18] */
|
||||
__IO uint32_t cspt7 : 3;/* [23:21] */
|
||||
__IO uint32_t cspt8 : 3;/* [26:24] */
|
||||
__IO uint32_t cspt9 : 3;/* [29:27] */
|
||||
__IO uint32_t reserved1 : 2;/* [31:30] */
|
||||
} spt2_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief adc pcdto1 register, offset:0x14
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t pcdto1;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t pcdto1 : 12; /* [11:0] */
|
||||
__IO uint32_t reserved1 : 20; /* [31:12] */
|
||||
} pcdto1_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief adc pcdto2 register, offset:0x18
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t pcdto2;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t pcdto2 : 12; /* [11:0] */
|
||||
__IO uint32_t reserved1 : 20; /* [31:12] */
|
||||
} pcdto2_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief adc pcdto3 register, offset:0x1C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t pcdto3;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t pcdto3 : 12; /* [11:0] */
|
||||
__IO uint32_t reserved1 : 20; /* [31:12] */
|
||||
} pcdto3_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief adc pcdto4 register, offset:0x20
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t pcdto4;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t pcdto4 : 12; /* [11:0] */
|
||||
__IO uint32_t reserved1 : 20; /* [31:12] */
|
||||
} pcdto4_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief adc vmhb register, offset:0x24
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t vmhb;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t vmhb : 12; /* [11:0] */
|
||||
__IO uint32_t reserved1 : 20; /* [31:12] */
|
||||
} vmhb_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief adc vmlb register, offset:0x28
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t vmlb;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t vmlb : 12; /* [11:0] */
|
||||
__IO uint32_t reserved1 : 20; /* [31:12] */
|
||||
} vmlb_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief adc osq1 register, offset:0x2C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t osq1;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t osn13 : 5; /* [4:0] */
|
||||
__IO uint32_t osn14 : 5; /* [9:5] */
|
||||
__IO uint32_t osn15 : 5; /* [14:10] */
|
||||
__IO uint32_t osn16 : 5; /* [19:15] */
|
||||
__IO uint32_t oclen : 4; /* [23:20] */
|
||||
__IO uint32_t reserved1 : 8; /* [31:24] */
|
||||
} osq1_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief adc osq2 register, offset:0x30
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t osq2;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t osn7 : 5; /* [4:0] */
|
||||
__IO uint32_t osn8 : 5; /* [9:5] */
|
||||
__IO uint32_t osn9 : 5; /* [14:10] */
|
||||
__IO uint32_t osn10 : 5; /* [19:15] */
|
||||
__IO uint32_t osn11 : 5; /* [24:20] */
|
||||
__IO uint32_t osn12 : 5; /* [29:25] */
|
||||
__IO uint32_t reserved1 : 2; /* [31:30] */
|
||||
} osq2_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief adc osq3 register, offset:0x34
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t osq3;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t osn1 : 5; /* [4:0] */
|
||||
__IO uint32_t osn2 : 5; /* [9:5] */
|
||||
__IO uint32_t osn3 : 5; /* [14:10] */
|
||||
__IO uint32_t osn4 : 5; /* [19:15] */
|
||||
__IO uint32_t osn5 : 5; /* [24:20] */
|
||||
__IO uint32_t osn6 : 5; /* [29:25] */
|
||||
__IO uint32_t reserved1 : 2; /* [31:30] */
|
||||
} osq3_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief adc psq register, offset:0x38
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t psq;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t psn1 : 5; /* [4:0] */
|
||||
__IO uint32_t psn2 : 5; /* [9:5] */
|
||||
__IO uint32_t psn3 : 5; /* [14:10] */
|
||||
__IO uint32_t psn4 : 5; /* [19:15] */
|
||||
__IO uint32_t pclen : 2; /* [21:20] */
|
||||
__IO uint32_t reserved1 : 10;/* [31:22] */
|
||||
} psq_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief adc pdt1 register, offset:0x3C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t pdt1;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t pdt1 : 16; /* [15:0] */
|
||||
__IO uint32_t reserved1 : 16; /* [31:16] */
|
||||
} pdt1_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief adc pdt2 register, offset:0x40
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t pdt2;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t pdt2 : 16; /* [15:0] */
|
||||
__IO uint32_t reserved1 : 16; /* [31:16] */
|
||||
} pdt2_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief adc pdt3 register, offset:0x44
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t pdt3;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t pdt3 : 16; /* [15:0] */
|
||||
__IO uint32_t reserved1 : 16; /* [31:16] */
|
||||
} pdt3_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief adc pdt4 register, offset:0x48
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t pdt4;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t pdt4 : 16; /* [15:0] */
|
||||
__IO uint32_t reserved1 : 16; /* [31:16] */
|
||||
} pdt4_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief adc odt register, offset:0x4C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t odt;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t odt : 16; /* [15:0] */
|
||||
__IO uint32_t reserved1 : 16; /* [31:16] */
|
||||
} odt_bit;
|
||||
};
|
||||
|
||||
__IO uint32_t reserved1[12];
|
||||
|
||||
/**
|
||||
* @brief adc ovsp register, offset:0x80
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ovsp;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t oosen : 1; /* [0] */
|
||||
__IO uint32_t posen : 1; /* [1] */
|
||||
__IO uint32_t osrsel : 3; /* [4:2] */
|
||||
__IO uint32_t osssel : 4; /* [8:5] */
|
||||
__IO uint32_t oostren : 1; /* [9] */
|
||||
__IO uint32_t oosrsel : 1; /* [10] */
|
||||
__IO uint32_t reserved1 : 21; /* [31:11] */
|
||||
} ovsp_bit;
|
||||
};
|
||||
|
||||
__IO uint32_t reserved2[12];
|
||||
|
||||
/**
|
||||
* @brief adc calval register, offset:0xB4
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t calval;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t calval : 7; /* [6:0] */
|
||||
__IO uint32_t reserved1 : 25; /* [31:7] */
|
||||
} calval_bit;
|
||||
};
|
||||
} adc_type;
|
||||
|
||||
/**
|
||||
* @brief type define adc register all
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
|
||||
/**
|
||||
* @brief adc csts register, offset:0x00
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t csts;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t vmor1 : 1; /* [0] */
|
||||
__IO uint32_t occe1 : 1; /* [1] */
|
||||
__IO uint32_t pcce1 : 1; /* [2] */
|
||||
__IO uint32_t pccs1 : 1; /* [3] */
|
||||
__IO uint32_t occs1 : 1; /* [4] */
|
||||
__IO uint32_t occo1 : 1; /* [5] */
|
||||
__IO uint32_t rdy1 : 1; /* [6] */
|
||||
__IO uint32_t reserved1 : 1; /* [7] */
|
||||
__IO uint32_t vmor2 : 1; /* [8] */
|
||||
__IO uint32_t occe2 : 1; /* [9] */
|
||||
__IO uint32_t pcce2 : 1; /* [10] */
|
||||
__IO uint32_t pccs2 : 1; /* [11] */
|
||||
__IO uint32_t occs2 : 1; /* [12] */
|
||||
__IO uint32_t occo2 : 1; /* [13] */
|
||||
__IO uint32_t rdy2 : 1; /* [14] */
|
||||
__IO uint32_t reserved2 : 1; /* [15] */
|
||||
__IO uint32_t vmor3 : 1; /* [16] */
|
||||
__IO uint32_t occe3 : 1; /* [17] */
|
||||
__IO uint32_t pcce3 : 1; /* [18] */
|
||||
__IO uint32_t pccs3 : 1; /* [19] */
|
||||
__IO uint32_t occs3 : 1; /* [20] */
|
||||
__IO uint32_t occo3 : 1; /* [21] */
|
||||
__IO uint32_t rdy3 : 1; /* [22] */
|
||||
__IO uint32_t reserved3 : 9; /* [31:23] */
|
||||
} csts_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief adc cctrl register, offset:0x04
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t cctrl;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t mssel : 5; /* [4_0] */
|
||||
__IO uint32_t reserved1 : 3; /* [7:5] */
|
||||
__IO uint32_t asisel : 4; /* [11:8] */
|
||||
__IO uint32_t reserved2 : 1; /* [12] */
|
||||
__IO uint32_t msdrcen : 1; /* [13] */
|
||||
__IO uint32_t msdmasel_l : 2; /* [15:14] */
|
||||
__IO uint32_t adcdiv : 4; /* [19:16] */
|
||||
__IO uint32_t reserved3 : 2; /* [21:20] */
|
||||
__IO uint32_t vbaten : 1; /* [22] */
|
||||
__IO uint32_t itsrven : 1; /* [23] */
|
||||
__IO uint32_t reserved4 : 4; /* [27:24] */
|
||||
__IO uint32_t msdmasel_h : 1; /* [28] */
|
||||
__IO uint32_t reserved5 : 3; /* [31:29] */
|
||||
} cctrl_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief adc codt register, offset:0x08
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t codt;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t codtl : 16; /* [15:0] */
|
||||
__IO uint32_t codth : 16; /* [31:16] */
|
||||
} codt_bit;
|
||||
};
|
||||
} adccom_type;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#define ADC1 ((adc_type *) ADC1_BASE)
|
||||
#define ADC2 ((adc_type *) ADC2_BASE)
|
||||
#define ADC3 ((adc_type *) ADC3_BASE)
|
||||
#define ADCCOM ((adccom_type *) ADCCOM_BASE)
|
||||
|
||||
/** @defgroup ADC_exported_functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void adc_reset(void);
|
||||
void adc_enable(adc_type *adc_x, confirm_state new_state);
|
||||
void adc_base_default_para_init(adc_base_config_type *adc_base_struct);
|
||||
void adc_base_config(adc_type *adc_x, adc_base_config_type *adc_base_struct);
|
||||
void adc_common_default_para_init(adc_common_config_type *adc_common_struct);
|
||||
void adc_common_config(adc_common_config_type *adc_common_struct);
|
||||
void adc_resolution_set(adc_type *adc_x, adc_resolution_type resolution);
|
||||
void adc_voltage_battery_enable(confirm_state new_state);
|
||||
void adc_dma_mode_enable(adc_type *adc_x, confirm_state new_state);
|
||||
void adc_dma_request_repeat_enable(adc_type *adc_x, confirm_state new_state);
|
||||
void adc_interrupt_enable(adc_type *adc_x, uint32_t adc_int, confirm_state new_state);
|
||||
void adc_calibration_value_set(adc_type *adc_x, uint8_t adc_calibration_value);
|
||||
void adc_calibration_init(adc_type *adc_x);
|
||||
flag_status adc_calibration_init_status_get(adc_type *adc_x);
|
||||
void adc_calibration_start(adc_type *adc_x);
|
||||
flag_status adc_calibration_status_get(adc_type *adc_x);
|
||||
void adc_voltage_monitor_enable(adc_type *adc_x, adc_voltage_monitoring_type adc_voltage_monitoring);
|
||||
void adc_voltage_monitor_threshold_value_set(adc_type *adc_x, uint16_t adc_high_threshold, uint16_t adc_low_threshold);
|
||||
void adc_voltage_monitor_single_channel_select(adc_type *adc_x, adc_channel_select_type adc_channel);
|
||||
void adc_ordinary_channel_set(adc_type *adc_x, adc_channel_select_type adc_channel, uint8_t adc_sequence, adc_sampletime_select_type adc_sampletime);
|
||||
void adc_preempt_channel_length_set(adc_type *adc_x, uint8_t adc_channel_lenght);
|
||||
void adc_preempt_channel_set(adc_type *adc_x, adc_channel_select_type adc_channel, uint8_t adc_sequence, adc_sampletime_select_type adc_sampletime);
|
||||
void adc_ordinary_conversion_trigger_set(adc_type *adc_x, adc_ordinary_trig_select_type adc_ordinary_trig, adc_ordinary_trig_edge_type adc_ordinary_trig_edge);
|
||||
void adc_preempt_conversion_trigger_set(adc_type *adc_x, adc_preempt_trig_select_type adc_preempt_trig, adc_preempt_trig_edge_type adc_preempt_trig_edge);
|
||||
void adc_preempt_offset_value_set(adc_type *adc_x, adc_preempt_channel_type adc_preempt_channel, uint16_t adc_offset_value);
|
||||
void adc_ordinary_part_count_set(adc_type *adc_x, uint8_t adc_channel_count);
|
||||
void adc_ordinary_part_mode_enable(adc_type *adc_x, confirm_state new_state);
|
||||
void adc_preempt_part_mode_enable(adc_type *adc_x, confirm_state new_state);
|
||||
void adc_preempt_auto_mode_enable(adc_type *adc_x, confirm_state new_state);
|
||||
void adc_conversion_stop(adc_type *adc_x);
|
||||
flag_status adc_conversion_stop_status_get(adc_type *adc_x);
|
||||
void adc_occe_each_conversion_enable(adc_type *adc_x, confirm_state new_state);
|
||||
void adc_ordinary_software_trigger_enable(adc_type *adc_x, confirm_state new_state);
|
||||
flag_status adc_ordinary_software_trigger_status_get(adc_type *adc_x);
|
||||
void adc_preempt_software_trigger_enable(adc_type *adc_x, confirm_state new_state);
|
||||
flag_status adc_preempt_software_trigger_status_get(adc_type *adc_x);
|
||||
uint16_t adc_ordinary_conversion_data_get(adc_type *adc_x);
|
||||
uint32_t adc_combine_ordinary_conversion_data_get(void);
|
||||
uint16_t adc_preempt_conversion_data_get(adc_type *adc_x, adc_preempt_channel_type adc_preempt_channel);
|
||||
flag_status adc_flag_get(adc_type *adc_x, uint8_t adc_flag);
|
||||
void adc_flag_clear(adc_type *adc_x, uint32_t adc_flag);
|
||||
void adc_ordinary_oversample_enable(adc_type *adc_x, confirm_state new_state);
|
||||
void adc_preempt_oversample_enable(adc_type *adc_x, confirm_state new_state);
|
||||
void adc_oversample_ratio_shift_set(adc_type *adc_x, adc_oversample_ratio_type adc_oversample_ratio, adc_oversample_shift_type adc_oversample_shift);
|
||||
void adc_ordinary_oversample_trig_enable(adc_type *adc_x, confirm_state new_state);
|
||||
void adc_ordinary_oversample_restart_set(adc_type *adc_x, adc_ordinary_oversample_restart_type adc_ordinary_oversample_restart);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,170 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file at32f435_437_crc.h
|
||||
* @brief at32f435_437 crc header file
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
/* define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __AT32F435_437_CRC_H
|
||||
#define __AT32F435_437_CRC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* includes ------------------------------------------------------------------*/
|
||||
#include "at32f435_437.h"
|
||||
|
||||
/** @addtogroup AT32F435_437_periph_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CRC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_exported_types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief crc reverse input data
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
CRC_REVERSE_INPUT_NO_AFFECTE = 0x00, /*!< input data no reverse */
|
||||
CRC_REVERSE_INPUT_BY_BYTE = 0x01, /*!< input data reverse by byte */
|
||||
CRC_REVERSE_INPUT_BY_HALFWORD = 0x02, /*!< input data reverse by half word */
|
||||
CRC_REVERSE_INPUT_BY_WORD = 0x03 /*!< input data reverse by word */
|
||||
} crc_reverse_input_type;
|
||||
|
||||
/**
|
||||
* @brief crc reverse output data
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
CRC_REVERSE_OUTPUT_NO_AFFECTE = 0x00, /*!< output data no reverse */
|
||||
CRC_REVERSE_OUTPUT_DATA = 0x01 /*!< output data reverse by word */
|
||||
} crc_reverse_output_type;
|
||||
|
||||
/**
|
||||
* @brief type define crc register all
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
/**
|
||||
* @brief crc dt register, offset:0x00
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t dt;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t dt : 32; /* [31:0] */
|
||||
} dt_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief crc cdt register, offset:0x04
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t cdt;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t cdt : 8 ; /* [7:0] */
|
||||
__IO uint32_t reserved1 : 24 ;/* [31:8] */
|
||||
} cdt_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief crc ctrl register, offset:0x08
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ctrl;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t rst : 1 ; /* [0] */
|
||||
__IO uint32_t reserved1 : 4 ; /* [4:1] */
|
||||
__IO uint32_t revid : 2 ; /* [6:5] */
|
||||
__IO uint32_t revod : 1 ; /* [7] */
|
||||
__IO uint32_t reserved2 : 24 ;/* [31:8] */
|
||||
} ctrl_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief crm reserved1 register, offset:0x0C
|
||||
*/
|
||||
__IO uint32_t reserved1;
|
||||
|
||||
/**
|
||||
* @brief crc idt register, offset:0x10
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t idt;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t idt : 32; /* [31:0] */
|
||||
} idt_bit;
|
||||
};
|
||||
|
||||
} crc_type;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#define CRC ((crc_type *) CRC_BASE)
|
||||
|
||||
/** @defgroup CRC_exported_functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void crc_data_reset(void);
|
||||
uint32_t crc_one_word_calculate(uint32_t data);
|
||||
uint32_t crc_block_calculate(uint32_t *pbuffer, uint32_t length);
|
||||
uint32_t crc_data_get(void);
|
||||
void crc_common_data_set(uint8_t cdt_value);
|
||||
uint8_t crc_common_data_get(void);
|
||||
void crc_init_data_set(uint32_t value);
|
||||
void crc_reverse_input_data_set(crc_reverse_input_type value);
|
||||
void crc_reverse_output_data_set(crc_reverse_output_type value);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,392 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file at32f435_437_dac.h
|
||||
* @brief at32f435_437 dac header file
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __AT32F435_437_DAC_H
|
||||
#define __AT32F435_437_DAC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "at32f435_437.h"
|
||||
|
||||
/** @addtogroup AT32F435_437_periph_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DAC
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DAC1_D1DMAUDRF ((uint32_t)(0x00002000))
|
||||
#define DAC2_D2DMAUDRF ((uint32_t)(0x20000000))
|
||||
|
||||
/** @defgroup DAC_exported_types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief dac select type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
DAC1_SELECT = 0x01, /*!< dac1 select */
|
||||
DAC2_SELECT = 0x02 /*!< dac2 select */
|
||||
} dac_select_type;
|
||||
|
||||
/**
|
||||
* @brief dac trigger type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
DAC_TMR6_TRGOUT_EVENT = 0x00, /*!< dac trigger selection:timer6 trgout event */
|
||||
DAC_TMR8_TRGOUT_EVENT = 0x01, /*!< dac trigger selection:timer8 trgout event */
|
||||
DAC_TMR7_TRGOUT_EVENT = 0x02, /*!< dac trigger selection:timer7 trgout event */
|
||||
DAC_TMR5_TRGOUT_EVENT = 0x03, /*!< dac trigger selection:timer5 trgout event */
|
||||
DAC_TMR2_TRGOUT_EVENT = 0x04, /*!< dac trigger selection:timer2 trgout event */
|
||||
DAC_TMR4_TRGOUT_EVENT = 0x05, /*!< dac trigger selection:timer4 trgout event */
|
||||
DAC_EXTERNAL_INTERRUPT_LINE_9 = 0x06, /*!< dac trigger selection:external line9 */
|
||||
DAC_SOFTWARE_TRIGGER = 0x07 /*!< dac trigger selection:software trigger */
|
||||
} dac_trigger_type;
|
||||
|
||||
/**
|
||||
* @brief dac wave type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
DAC_WAVE_GENERATE_NONE = 0x00, /*!< dac wave generation disabled */
|
||||
DAC_WAVE_GENERATE_NOISE = 0x01, /*!< dac noise wave generation enabled */
|
||||
DAC_WAVE_GENERATE_TRIANGLE = 0x02 /*!< dac triangle wave generation enabled */
|
||||
} dac_wave_type;
|
||||
|
||||
/**
|
||||
* @brief dac mask amplitude type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
DAC_LSFR_BIT0_AMPLITUDE_1 = 0x00, /*!< unmask bit0/ triangle amplitude equal to 1 */
|
||||
DAC_LSFR_BIT10_AMPLITUDE_3 = 0x01, /*!< unmask bit[1:0]/ triangle amplitude equal to 3 */
|
||||
DAC_LSFR_BIT20_AMPLITUDE_7 = 0x02, /*!< unmask bit[2:0]/ triangle amplitude equal to 7 */
|
||||
DAC_LSFR_BIT30_AMPLITUDE_15 = 0x03, /*!< unmask bit[3:0]/ triangle amplitude equal to 15 */
|
||||
DAC_LSFR_BIT40_AMPLITUDE_31 = 0x04, /*!< unmask bit[4:0]/ triangle amplitude equal to 31 */
|
||||
DAC_LSFR_BIT50_AMPLITUDE_63 = 0x05, /*!< unmask bit[5:0]/ triangle amplitude equal to 63 */
|
||||
DAC_LSFR_BIT60_AMPLITUDE_127 = 0x06, /*!< unmask bit[6:0]/ triangle amplitude equal to 127 */
|
||||
DAC_LSFR_BIT70_AMPLITUDE_255 = 0x07, /*!< unmask bit[7:0]/ triangle amplitude equal to 255 */
|
||||
DAC_LSFR_BIT80_AMPLITUDE_511 = 0x08, /*!< unmask bit[8:0]/ triangle amplitude equal to 511 */
|
||||
DAC_LSFR_BIT90_AMPLITUDE_1023 = 0x09, /*!< unmask bit[9:0]/ triangle amplitude equal to 1023 */
|
||||
DAC_LSFR_BITA0_AMPLITUDE_2047 = 0x0A, /*!< unmask bit[10:0]/ triangle amplitude equal to 2047 */
|
||||
DAC_LSFR_BITB0_AMPLITUDE_4095 = 0x0B /*!< unmask bit[11:0]/ triangle amplitude equal to 4095 */
|
||||
} dac_mask_amplitude_type;
|
||||
|
||||
/**
|
||||
* @brief dac1 aligned data type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
DAC1_12BIT_RIGHT = 0x40007408, /*!< dac1 12-bit data right-aligned */
|
||||
DAC1_12BIT_LEFT = 0x4000740C, /*!< dac1 12-bit data left-aligned */
|
||||
DAC1_8BIT_RIGHT = 0x40007410 /*!< dac1 8-bit data right-aligned */
|
||||
} dac1_aligned_data_type;
|
||||
|
||||
/**
|
||||
* @brief dac2 aligned data type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
DAC2_12BIT_RIGHT = 0x40007414, /*!< dac2 12-bit data right-aligned */
|
||||
DAC2_12BIT_LEFT = 0x40007418, /*!< dac2 12-bit data left-aligned */
|
||||
DAC2_8BIT_RIGHT = 0x4000741C /*!< dac2 8-bit data right-aligned */
|
||||
} dac2_aligned_data_type;
|
||||
|
||||
/**
|
||||
* @brief dac dual data type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
DAC_DUAL_12BIT_RIGHT = 0x40007420, /*!<double dac 12-bit data right-aligned */
|
||||
DAC_DUAL_12BIT_LEFT = 0x40007424, /*!<double dac 12-bit data left-aligned */
|
||||
DAC_DUAL_8BIT_RIGHT = 0x40007428 /*!<double dac 8-bit data right-aligned */
|
||||
} dac_dual_data_type;
|
||||
|
||||
/**
|
||||
* @brief type define dac register all
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
/**
|
||||
* @brief dac ctrl register, offset:0x00
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ctrl;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t d1en : 1; /* [0] */
|
||||
__IO uint32_t d1obdis : 1; /* [1] */
|
||||
__IO uint32_t d1trgen : 1; /* [2] */
|
||||
__IO uint32_t d1trgsel : 3; /* [5:3] */
|
||||
__IO uint32_t d1nm : 2; /* [7:6] */
|
||||
__IO uint32_t d1nbsel : 4; /* [11:8] */
|
||||
__IO uint32_t d1dmaen : 1; /* [12] */
|
||||
__IO uint32_t d1dmaudrien : 1; /* [13] */
|
||||
__IO uint32_t reserved1 : 2; /* [15:14] */
|
||||
__IO uint32_t d2en : 1; /* [16] */
|
||||
__IO uint32_t d2obdis : 1; /* [17] */
|
||||
__IO uint32_t d2trgen : 1; /* [18] */
|
||||
__IO uint32_t d2trgsel : 3; /* [21:19] */
|
||||
__IO uint32_t d2nm : 2; /* [23:22] */
|
||||
__IO uint32_t d2nbsel : 4; /* [27:24] */
|
||||
__IO uint32_t d2dmaen : 1; /* [28] */
|
||||
__IO uint32_t d2dmaudrien : 1; /* [29] */
|
||||
__IO uint32_t reserved2 : 2; /* [31:30] */
|
||||
} ctrl_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief dac swtrg register, offset:0x04
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t swtrg;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t d1swtrg : 1; /* [0] */
|
||||
__IO uint32_t d2swtrg : 1; /* [1] */
|
||||
__IO uint32_t reserved1 : 30;/* [31:2] */
|
||||
} swtrg_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief dac d1dth12r register, offset:0x08
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t d1dth12r;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t d1dt12r : 12;/* [11:0] */
|
||||
__IO uint32_t reserved1 : 20;/* [31:2] */
|
||||
} d1dth12r_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief dac d1dth12l register, offset:0x0C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t d1dth12l;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t d1dt12l : 12;/* [11:0] */
|
||||
__IO uint32_t reserved1 : 20;/* [31:2] */
|
||||
} d1dth12l_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief dac d1dth8r register, offset:0x10
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t d1dth8r;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t d1dt8r : 8; /* [7:0] */
|
||||
__IO uint32_t reserved1 : 24;/* [31:8] */
|
||||
} d1dth8r_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief dac d2dth12r register, offset:0x14
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t d2dth12r;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t d2dt12r : 12;/* [11:0] */
|
||||
__IO uint32_t reserved1 : 20;/* [31:2] */
|
||||
} d2dth12r_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief dac d2dth12l register, offset:0x18
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t d2dth12l;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t d2dt12l : 12;/* [11:0] */
|
||||
__IO uint32_t reserved1 : 20;/* [31:2] */
|
||||
} d2dth12l_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief dac d2dth8r register, offset:0x1C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t d2dth8r;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t d2dt8r : 8; /* [7:0] */
|
||||
__IO uint32_t reserved1 : 24;/* [31:8] */
|
||||
} d2dth8r_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief dac ddth12r register, offset:0x20
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ddth12r;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t dd1dt12r : 12;/* [11:0] */
|
||||
__IO uint32_t reserved1 : 4; /* [15:12] */
|
||||
__IO uint32_t dd2dt12r : 12;/* [27:16] */
|
||||
__IO uint32_t reserved2 : 4; /* [31:28] */
|
||||
} ddth12r_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief dac ddth12l register, offset:0x24
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ddth12l;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t reserved1 : 4; /* [3:0] */
|
||||
__IO uint32_t dd1dt12l : 12;/* [15:4] */
|
||||
__IO uint32_t reserved2 : 4; /* [19:16] */
|
||||
__IO uint32_t dd2dt12l : 12;/* [31:20] */
|
||||
} ddth12l_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief dac ddth8r register, offset:0x28
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ddth8r;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t dd1dt8r : 8; /* [7:0] */
|
||||
__IO uint32_t dd2dt8r : 8; /* [15:8] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:16] */
|
||||
} ddth8r_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief dac d1odt register, offset:0x2c
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t d1odt;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t d1odt : 12;/* [11:0] */
|
||||
__IO uint32_t reserved1 : 20;/* [31:12] */
|
||||
} d1odt_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief dac d2odt register, offset:0x30
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t d2odt;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t d2odt : 12;/* [11:0] */
|
||||
__IO uint32_t reserved1 : 20;/* [31:12] */
|
||||
} d2odt_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief dac sr register, offset:0x34
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t sts;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t reserved1 : 13;/* [12:0] */
|
||||
__IO uint32_t d1dmaudrf : 1; /* [13] */
|
||||
__IO uint32_t reserved2 : 15;/* [28:14] */
|
||||
__IO uint32_t d2dmaudrf : 1; /* [29] */
|
||||
__IO uint32_t reserved3 : 2;/* [31:30] */
|
||||
} sts_bit;
|
||||
};
|
||||
} dac_type;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#define DAC ((dac_type *) DAC_BASE)
|
||||
|
||||
/** @defgroup DAC_exported_functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void dac_reset(void);
|
||||
void dac_enable(dac_select_type dac_select, confirm_state new_state);
|
||||
void dac_output_buffer_enable(dac_select_type dac_select, confirm_state new_state);
|
||||
void dac_trigger_enable(dac_select_type dac_select, confirm_state new_state);
|
||||
void dac_trigger_select(dac_select_type dac_select, dac_trigger_type dac_trigger_source);
|
||||
void dac_software_trigger_generate(dac_select_type dac_select);
|
||||
void dac_dual_software_trigger_generate(void);
|
||||
void dac_wave_generate(dac_select_type dac_select, dac_wave_type dac_wave);
|
||||
void dac_mask_amplitude_select(dac_select_type dac_select, dac_mask_amplitude_type dac_mask_amplitude);
|
||||
void dac_dma_enable(dac_select_type dac_select, confirm_state new_state);
|
||||
uint16_t dac_data_output_get(dac_select_type dac_select);
|
||||
void dac_1_data_set(dac1_aligned_data_type dac1_aligned, uint16_t dac1_data);
|
||||
void dac_2_data_set(dac2_aligned_data_type dac2_aligned, uint16_t dac2_data);
|
||||
void dac_dual_data_set(dac_dual_data_type dac_dual, uint16_t data1, uint16_t data2);
|
||||
void dac_udr_enable(dac_select_type dac_select, confirm_state new_state);
|
||||
flag_status dac_udr_flag_get(dac_select_type dac_select);
|
||||
void dac_udr_flag_clear(dac_select_type dac_select);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,206 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file at32f435_437_mcudbg.h
|
||||
* @brief at32f435_437 mcudbg header file
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __AT32F435_437_MCUDBG_H
|
||||
#define __AT32F435_437_MCUDBG_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "at32f435_437.h"
|
||||
|
||||
/** @addtogroup AT32F435_437_periph_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DEBUG
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DEBUG_mode_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* debug ctrl register bit */
|
||||
#define DEBUG_SLEEP 0x00000001 /*!< debug sleep mode */
|
||||
#define DEBUG_DEEPSLEEP 0x00000002 /*!< debug deepsleep mode */
|
||||
#define DEBUG_STANDBY 0x00000004 /*!< debug standby mode */
|
||||
|
||||
/* debug apb1 frz register bit */
|
||||
#define DEBUG_TMR2_PAUSE 0x00000001 /*!< debug timer2 pause */
|
||||
#define DEBUG_TMR3_PAUSE 0x00000002 /*!< debug timer3 pause */
|
||||
#define DEBUG_TMR4_PAUSE 0x00000004 /*!< debug timer4 pause */
|
||||
#define DEBUG_TMR5_PAUSE 0x00000008 /*!< debug timer5 pause */
|
||||
#define DEBUG_TMR6_PAUSE 0x00000010 /*!< debug timer6 pause */
|
||||
#define DEBUG_TMR7_PAUSE 0x00000020 /*!< debug timer7 pause */
|
||||
#define DEBUG_TMR12_PAUSE 0x00000040 /*!< debug timer12 pause */
|
||||
#define DEBUG_TMR13_PAUSE 0x00000080 /*!< debug timer13 pause */
|
||||
#define DEBUG_TMR14_PAUSE 0x00000100 /*!< debug timer14 pause */
|
||||
#define DEBUG_ERTC_PAUSE 0x00000400 /*!< debug ertc pause */
|
||||
#define DEBUG_WWDT_PAUSE 0x00000800 /*!< debug window watchdog timer pause */
|
||||
#define DEBUG_WDT_PAUSE 0x00001000 /*!< debug watchdog timer pause */
|
||||
#define DEBUG_ERTC_512_PAUSE 0x00008000 /*!< debug ertc_512 pause */
|
||||
#define DEBUG_I2C1_SMBUS_TIMEOUT 0x01000000 /*!< debug i2c1 smbus timeout */
|
||||
#define DEBUG_I2C2_SMBUS_TIMEOUT 0x08000000 /*!< debug i2c2 smbus timeout */
|
||||
#define DEBUG_I2C3_SMBUS_TIMEOUT 0x10000000 /*!< debug i2c3 smbus timeout */
|
||||
#define DEBUG_CAN1_PAUSE 0x02000000 /*!< debug can1 pause */
|
||||
#define DEBUG_CAN2_PAUSE 0x04000000 /*!< debug can2 pause */
|
||||
|
||||
/* debug apb2 frz register bit */
|
||||
#define DEBUG_TMR1_PAUSE 0x00000001 /*!< debug timer1 pause */
|
||||
#define DEBUG_TMR8_PAUSE 0x00000002 /*!< debug timer8 pause */
|
||||
#define DEBUG_TMR20_PAUSE 0x00000040 /*!< debug timer20 pause */
|
||||
#define DEBUG_TMR9_PAUSE 0x00010000 /*!< debug timer9 pause */
|
||||
#define DEBUG_TMR10_PAUSE 0x00020000 /*!< debug timer10 pause */
|
||||
#define DEBUG_TMR11_PAUSE 0x00040000 /*!< debug timer11 pause */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DEBUG_exported_types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief type define debug register all
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
/**
|
||||
* @brief debug idcode register, offset:0x00
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t pid;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t pid : 32;/* [31:0] */
|
||||
} idcode_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief debug ctrl register, offset:0x04
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ctrl;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t sleep_debug : 1;/* [0] */
|
||||
__IO uint32_t deepsleep_debug : 1;/* [1] */
|
||||
__IO uint32_t standby_debug : 1;/* [2] */
|
||||
__IO uint32_t reserved1 : 29;/* [31:3] */
|
||||
} ctrl_bit;
|
||||
};
|
||||
/**
|
||||
* @brief debug apb1 frz register, offset:0x08
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t apb1_frz;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t tmr2_pause : 1;/* [0] */
|
||||
__IO uint32_t tmr3_pause : 1;/* [1] */
|
||||
__IO uint32_t tmr4_pause : 1;/* [2] */
|
||||
__IO uint32_t tmr5_pause : 1;/* [3] */
|
||||
__IO uint32_t tmr6_pause : 1;/* [4] */
|
||||
__IO uint32_t tmr7_pause : 1;/* [5] */
|
||||
__IO uint32_t tmr12_pause : 1;/* [6] */
|
||||
__IO uint32_t tmr13_pause : 1;/* [7] */
|
||||
__IO uint32_t tmr14_pause : 1;/* [8] */
|
||||
__IO uint32_t reserved1 : 1;/* [9] */
|
||||
__IO uint32_t ertc_pause : 1;/* [10] */
|
||||
__IO uint32_t wwdt_pause : 1;/* [11] */
|
||||
__IO uint32_t wdt_pause : 1;/* [12] */
|
||||
__IO uint32_t reserved2 : 2;/* [14:13] */
|
||||
__IO uint32_t ertc_512_pause : 1;/* [15] */
|
||||
__IO uint32_t reserved3 : 8;/* [23:16] */
|
||||
__IO uint32_t i2c1_smbus_timeout : 1;/* [24] */
|
||||
__IO uint32_t can1_pause : 1;/* [25] */
|
||||
__IO uint32_t can2_pause : 1;/* [26] */
|
||||
__IO uint32_t i2c2_smbus_timeout : 1;/* [27] */
|
||||
__IO uint32_t i2c3_smbus_timeout : 1;/* [28] */
|
||||
__IO uint32_t reserved4 : 3;/* [31:29] */
|
||||
} apb1_frz_bit;
|
||||
};
|
||||
/**
|
||||
* @brief debug apb2 frz register, offset:0x0c
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t apb2_frz;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t tmr1_pause : 1;/* [0] */
|
||||
__IO uint32_t tmr8_pause : 1;/* [1] */
|
||||
__IO uint32_t reserved1 : 4;/* [5:2] */
|
||||
__IO uint32_t tmr20_pause : 1;/* [6] */
|
||||
__IO uint32_t reserved2 : 9;/* [15:7] */
|
||||
__IO uint32_t tmr9_pause : 1;/* [16] */
|
||||
__IO uint32_t tmr10_pause : 1;/* [17] */
|
||||
__IO uint32_t tmr11_pause : 1;/* [18] */
|
||||
__IO uint32_t reserved3 : 13;/* [31:19] */
|
||||
} apb2_frz_bit;
|
||||
};
|
||||
|
||||
} debug_type;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#define DEBUGMCU ((debug_type *) DEBUG_BASE)
|
||||
|
||||
/** @defgroup DEBUG_exported_functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
uint32_t debug_device_id_get(void);
|
||||
void debug_low_power_mode_set(uint32_t low_power_mode, confirm_state new_state);
|
||||
void debug_apb1_periph_mode_set(uint32_t apb1_periph, confirm_state new_state);
|
||||
void debug_apb2_periph_mode_set(uint32_t apb2_periph, confirm_state new_state);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,69 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file at32f435_437_def.h
|
||||
* @brief at32f435_437 macros header file
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __AT32F435_437_DEF_H
|
||||
#define __AT32F435_437_DEF_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* gnu compiler */
|
||||
#if defined (__GNUC__)
|
||||
#ifndef ALIGNED_HEAD
|
||||
#define ALIGNED_HEAD
|
||||
#endif
|
||||
#ifndef ALIGNED_TAIL
|
||||
#define ALIGNED_TAIL __attribute__ ((aligned (4)))
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* arm compiler */
|
||||
#if defined (__CC_ARM)
|
||||
#ifndef ALIGNED_HEAD
|
||||
#define ALIGNED_HEAD __align(4)
|
||||
#endif
|
||||
#ifndef ALIGNED_TAIL
|
||||
#define ALIGNED_TAIL
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* iar compiler */
|
||||
#if defined (__ICCARM__)
|
||||
#ifndef ALIGNED_HEAD
|
||||
#define ALIGNED_HEAD
|
||||
#endif
|
||||
#ifndef ALIGNED_TAIL
|
||||
#define ALIGNED_TAIL
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#define UNUSED(x) (void)x /* to avoid gcc/g++ warnings */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,783 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file at32f435_437_dma.h
|
||||
* @brief at32f435_437 dma header file
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __AT32F435_437_DMA_H
|
||||
#define __AT32F435_437_DMA_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "at32f435_437.h"
|
||||
|
||||
/** @addtogroup AT32F435_437_periph_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DMA
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_interrupts_definition
|
||||
* @brief dma interrupt
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DMA_FDT_INT ((uint32_t)0x00000002) /*!< dma full data transfer interrupt */
|
||||
#define DMA_HDT_INT ((uint32_t)0x00000004) /*!< dma half data transfer interrupt */
|
||||
#define DMA_DTERR_INT ((uint32_t)0x00000008) /*!< dma errorr interrupt */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_flags_definition
|
||||
* @brief edma flag
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DMA1_GL1_FLAG ((uint32_t)0x00000001) /*!< dma1 channel1 global flag */
|
||||
#define DMA1_FDT1_FLAG ((uint32_t)0x00000002) /*!< dma1 channel1 full data transfer flag */
|
||||
#define DMA1_HDT1_FLAG ((uint32_t)0x00000004) /*!< dma1 channel1 half data transfer flag */
|
||||
#define DMA1_DTERR1_FLAG ((uint32_t)0x00000008) /*!< dma1 channel1 error flag */
|
||||
#define DMA1_GL2_FLAG ((uint32_t)0x00000010) /*!< dma1 channel2 global flag */
|
||||
#define DMA1_FDT2_FLAG ((uint32_t)0x00000020) /*!< dma1 channel2 full data transfer flag */
|
||||
#define DMA1_HDT2_FLAG ((uint32_t)0x00000040) /*!< dma1 channel2 half data transfer flag */
|
||||
#define DMA1_DTERR2_FLAG ((uint32_t)0x00000080) /*!< dma1 channel2 error flag */
|
||||
#define DMA1_GL3_FLAG ((uint32_t)0x00000100) /*!< dma1 channel3 global flag */
|
||||
#define DMA1_FDT3_FLAG ((uint32_t)0x00000200) /*!< dma1 channel3 full data transfer flag */
|
||||
#define DMA1_HDT3_FLAG ((uint32_t)0x00000400) /*!< dma1 channel3 half data transfer flag */
|
||||
#define DMA1_DTERR3_FLAG ((uint32_t)0x00000800) /*!< dma1 channel3 error flag */
|
||||
#define DMA1_GL4_FLAG ((uint32_t)0x00001000) /*!< dma1 channel4 global flag */
|
||||
#define DMA1_FDT4_FLAG ((uint32_t)0x00002000) /*!< dma1 channel4 full data transfer flag */
|
||||
#define DMA1_HDT4_FLAG ((uint32_t)0x00004000) /*!< dma1 channel4 half data transfer flag */
|
||||
#define DMA1_DTERR4_FLAG ((uint32_t)0x00008000) /*!< dma1 channel4 error flag */
|
||||
#define DMA1_GL5_FLAG ((uint32_t)0x00010000) /*!< dma1 channel5 global flag */
|
||||
#define DMA1_FDT5_FLAG ((uint32_t)0x00020000) /*!< dma1 channel5 full data transfer flag */
|
||||
#define DMA1_HDT5_FLAG ((uint32_t)0x00040000) /*!< dma1 channel5 half data transfer flag */
|
||||
#define DMA1_DTERR5_FLAG ((uint32_t)0x00080000) /*!< dma1 channel5 error flag */
|
||||
#define DMA1_GL6_FLAG ((uint32_t)0x00100000) /*!< dma1 channel6 global flag */
|
||||
#define DMA1_FDT6_FLAG ((uint32_t)0x00200000) /*!< dma1 channel6 full data transfer flag */
|
||||
#define DMA1_HDT6_FLAG ((uint32_t)0x00400000) /*!< dma1 channel6 half data transfer flag */
|
||||
#define DMA1_DTERR6_FLAG ((uint32_t)0x00800000) /*!< dma1 channel6 error flag */
|
||||
#define DMA1_GL7_FLAG ((uint32_t)0x01000000) /*!< dma1 channel7 global flag */
|
||||
#define DMA1_FDT7_FLAG ((uint32_t)0x02000000) /*!< dma1 channel7 full data transfer flag */
|
||||
#define DMA1_HDT7_FLAG ((uint32_t)0x04000000) /*!< dma1 channel7 half data transfer flag */
|
||||
#define DMA1_DTERR7_FLAG ((uint32_t)0x08000000) /*!< dma1 channel7 error flag */
|
||||
|
||||
#define DMA2_GL1_FLAG ((uint32_t)0x10000001) /*!< dma2 channel1 global flag */
|
||||
#define DMA2_FDT1_FLAG ((uint32_t)0x10000002) /*!< dma2 channel1 full data transfer flag */
|
||||
#define DMA2_HDT1_FLAG ((uint32_t)0x10000004) /*!< dma2 channel1 half data transfer flag */
|
||||
#define DMA2_DTERR1_FLAG ((uint32_t)0x10000008) /*!< dma2 channel1 error flag */
|
||||
#define DMA2_GL2_FLAG ((uint32_t)0x10000010) /*!< dma2 channel2 global flag */
|
||||
#define DMA2_FDT2_FLAG ((uint32_t)0x10000020) /*!< dma2 channel2 full data transfer flag */
|
||||
#define DMA2_HDT2_FLAG ((uint32_t)0x10000040) /*!< dma2 channel2 half data transfer flag */
|
||||
#define DMA2_DTERR2_FLAG ((uint32_t)0x10000080) /*!< dma2 channel2 error flag */
|
||||
#define DMA2_GL3_FLAG ((uint32_t)0x10000100) /*!< dma2 channel3 global flag */
|
||||
#define DMA2_FDT3_FLAG ((uint32_t)0x10000200) /*!< dma2 channel3 full data transfer flag */
|
||||
#define DMA2_HDT3_FLAG ((uint32_t)0x10000400) /*!< dma2 channel3 half data transfer flag */
|
||||
#define DMA2_DTERR3_FLAG ((uint32_t)0x10000800) /*!< dma2 channel3 error flag */
|
||||
#define DMA2_GL4_FLAG ((uint32_t)0x10001000) /*!< dma2 channel4 global flag */
|
||||
#define DMA2_FDT4_FLAG ((uint32_t)0x10002000) /*!< dma2 channel4 full data transfer flag */
|
||||
#define DMA2_HDT4_FLAG ((uint32_t)0x10004000) /*!< dma2 channel4 half data transfer flag */
|
||||
#define DMA2_DTERR4_FLAG ((uint32_t)0x10008000) /*!< dma2 channel4 error flag */
|
||||
#define DMA2_GL5_FLAG ((uint32_t)0x10010000) /*!< dma2 channel5 global flag */
|
||||
#define DMA2_FDT5_FLAG ((uint32_t)0x10020000) /*!< dma2 channel5 full data transfer flag */
|
||||
#define DMA2_HDT5_FLAG ((uint32_t)0x10040000) /*!< dma2 channel5 half data transfer flag */
|
||||
#define DMA2_DTERR5_FLAG ((uint32_t)0x10080000) /*!< dma2 channel5 error flag */
|
||||
#define DMA2_GL6_FLAG ((uint32_t)0x10100000) /*!< dma2 channel6 global flag */
|
||||
#define DMA2_FDT6_FLAG ((uint32_t)0x10200000) /*!< dma2 channel6 full data transfer flag */
|
||||
#define DMA2_HDT6_FLAG ((uint32_t)0x10400000) /*!< dma2 channel6 half data transfer flag */
|
||||
#define DMA2_DTERR6_FLAG ((uint32_t)0x10800000) /*!< dma2 channel6 error flag */
|
||||
#define DMA2_GL7_FLAG ((uint32_t)0x11000000) /*!< dma2 channel7 global flag */
|
||||
#define DMA2_FDT7_FLAG ((uint32_t)0x12000000) /*!< dma2 channel7 full data transfer flag */
|
||||
#define DMA2_HDT7_FLAG ((uint32_t)0x14000000) /*!< dma2 channel7 half data transfer flag */
|
||||
#define DMA2_DTERR7_FLAG ((uint32_t)0x18000000) /*!< dma2 channel7 error flag */
|
||||
|
||||
/**
|
||||
* @brief dmamux flag
|
||||
*/
|
||||
#define DMAMUX_SYNC_OV1_FLAG ((uint32_t)0x00000001) /*!< dmamux channel1 synchronization overrun event flag */
|
||||
#define DMAMUX_SYNC_OV2_FLAG ((uint32_t)0x00000002) /*!< dmamux channel2 synchronization overrun event flag */
|
||||
#define DMAMUX_SYNC_OV3_FLAG ((uint32_t)0x00000004) /*!< dmamux channel3 synchronization overrun event flag */
|
||||
#define DMAMUX_SYNC_OV4_FLAG ((uint32_t)0x00000008) /*!< dmamux channel4 synchronization overrun event flag */
|
||||
#define DMAMUX_SYNC_OV5_FLAG ((uint32_t)0x00000010) /*!< dmamux channel5 synchronization overrun event flag */
|
||||
#define DMAMUX_SYNC_OV6_FLAG ((uint32_t)0x00000020) /*!< dmamux channel6 synchronization overrun event flag */
|
||||
#define DMAMUX_SYNC_OV7_FLAG ((uint32_t)0x00000040) /*!< dmamux channel7 synchronization overrun event flag */
|
||||
|
||||
#define DMAMUX_GEN_TRIG_OV1_FLAG ((uint32_t)0x00000001) /*!< dmamux generator channel1 overrun event flag */
|
||||
#define DMAMUX_GEN_TRIG_OV2_FLAG ((uint32_t)0x00000002) /*!< dmamux generator channel2 overrun event flag */
|
||||
#define DMAMUX_GEN_TRIG_OV3_FLAG ((uint32_t)0x00000004) /*!< dmamux generator channel3 overrun event flag */
|
||||
#define DMAMUX_GEN_TRIG_OV4_FLAG ((uint32_t)0x00000008) /*!< dmamux generator channel4 overrun event flag */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_exported_types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief dma direction type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
DMA_DIR_PERIPHERAL_TO_MEMORY = 0x0000, /*!< dma data transfer direction: peripheral to memory */
|
||||
DMA_DIR_MEMORY_TO_PERIPHERAL = 0x0010, /*!< dma data transfer direction: memory to peripheral */
|
||||
DMA_DIR_MEMORY_TO_MEMORY = 0x4000 /*!< dma data transfer direction: memory to memory */
|
||||
} dma_dir_type;
|
||||
|
||||
/**
|
||||
* @brief dma peripheral data size type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
DMA_PERIPHERAL_DATA_WIDTH_BYTE = 0x00, /*!< dma peripheral databus width 8bit */
|
||||
DMA_PERIPHERAL_DATA_WIDTH_HALFWORD = 0x01, /*!< dma peripheral databus width 16bit */
|
||||
DMA_PERIPHERAL_DATA_WIDTH_WORD = 0x02 /*!< dma peripheral databus width 32bit */
|
||||
} dma_peripheral_data_size_type;
|
||||
|
||||
/**
|
||||
* @brief dma memory data size type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
DMA_MEMORY_DATA_WIDTH_BYTE = 0x00, /*!< dma memory databus width 8bit */
|
||||
DMA_MEMORY_DATA_WIDTH_HALFWORD = 0x01, /*!< dma memory databus width 16bit */
|
||||
DMA_MEMORY_DATA_WIDTH_WORD = 0x02 /*!< dma memory databus width 32bit */
|
||||
} dma_memory_data_size_type;
|
||||
|
||||
/**
|
||||
* @brief dma priority level type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
DMA_PRIORITY_LOW = 0x00, /*!< dma channel priority: low */
|
||||
DMA_PRIORITY_MEDIUM = 0x01, /*!< dma channel priority: medium */
|
||||
DMA_PRIORITY_HIGH = 0x02, /*!< dma channel priority: high */
|
||||
DMA_PRIORITY_VERY_HIGH = 0x03 /*!< dma channel priority: very high */
|
||||
} dma_priority_level_type;
|
||||
|
||||
/**
|
||||
* @brief dmamux request type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
DMAMUX_DMAREQ_ID_REQ_G1 = 0x01, /*!< dmamux channel dma request inputs resources: generator channel1 */
|
||||
DMAMUX_DMAREQ_ID_REQ_G2 = 0x02, /*!< dmamux channel dma request inputs resources: generator channel2 */
|
||||
DMAMUX_DMAREQ_ID_REQ_G3 = 0x03, /*!< dmamux channel dma request inputs resources: generator channel3 */
|
||||
DMAMUX_DMAREQ_ID_REQ_G4 = 0x04, /*!< dmamux channel dma request inputs resources: generator channel4 */
|
||||
DMAMUX_DMAREQ_ID_ADC1 = 0x05, /*!< dmamux channel dma request inputs resources: adc1 */
|
||||
DMAMUX_DMAREQ_ID_ADC2 = 0x24, /*!< dmamux channel dma request inputs resources: adc2 */
|
||||
DMAMUX_DMAREQ_ID_ADC3 = 0x25, /*!< dmamux channel dma request inputs resources: adc3 */
|
||||
DMAMUX_DMAREQ_ID_DAC1 = 0x06, /*!< dmamux channel dma request inputs resources: dac1 */
|
||||
DMAMUX_DMAREQ_ID_DAC2 = 0x29, /*!< dmamux channel dma request inputs resources: dac2 */
|
||||
DMAMUX_DMAREQ_ID_TMR6_OVERFLOW = 0x08, /*!< dmamux channel dma request inputs resources: timer6 overflow */
|
||||
DMAMUX_DMAREQ_ID_TMR7_OVERFLOW = 0x09, /*!< dmamux channel dma request inputs resources: timer7 overflow */
|
||||
DMAMUX_DMAREQ_ID_SPI1_RX = 0x0A, /*!< dmamux channel dma request inputs resources: spi1 rx */
|
||||
DMAMUX_DMAREQ_ID_SPI1_TX = 0x0B, /*!< dmamux channel dma request inputs resources: spi1 tx */
|
||||
DMAMUX_DMAREQ_ID_SPI2_RX = 0x0C, /*!< dmamux channel dma request inputs resources: spi2 rx */
|
||||
DMAMUX_DMAREQ_ID_SPI2_TX = 0x0D, /*!< dmamux channel dma request inputs resources: spi2 tx */
|
||||
DMAMUX_DMAREQ_ID_SPI3_RX = 0x0E, /*!< dmamux channel dma request inputs resources: spi3 rx */
|
||||
DMAMUX_DMAREQ_ID_SPI3_TX = 0x0F, /*!< dmamux channel dma request inputs resources: spi3 tx */
|
||||
DMAMUX_DMAREQ_ID_SPI4_RX = 0x6A, /*!< dmamux channel dma request inputs resources: spi4 rx */
|
||||
DMAMUX_DMAREQ_ID_SPI4_TX = 0x6B, /*!< dmamux channel dma request inputs resources: spi4 tx */
|
||||
DMAMUX_DMAREQ_ID_I2S2_EXT_RX = 0x6E, /*!< dmamux channel dma request inputs resources: i2s2_ext_rx */
|
||||
DMAMUX_DMAREQ_ID_I2S2_EXT_TX = 0x6F, /*!< dmamux channel dma request inputs resources: i2s2_ext_tx */
|
||||
DMAMUX_DMAREQ_ID_I2S3_EXT_RX = 0x70, /*!< dmamux channel dma request inputs resources: i2s3_ext_rx */
|
||||
DMAMUX_DMAREQ_ID_I2S3_EXT_TX = 0x71, /*!< dmamux channel dma request inputs resources: i2s3_ext_tx */
|
||||
DMAMUX_DMAREQ_ID_I2C1_RX = 0x10, /*!< dmamux channel dma request inputs resources: i2c1_rx */
|
||||
DMAMUX_DMAREQ_ID_I2C1_TX = 0x11, /*!< dmamux channel dma request inputs resources: i2c1_tx */
|
||||
DMAMUX_DMAREQ_ID_I2C2_RX = 0x12, /*!< dmamux channel dma request inputs resources: i2c2_rx */
|
||||
DMAMUX_DMAREQ_ID_I2C2_TX = 0x13, /*!< dmamux channel dma request inputs resources: i2c2_tx */
|
||||
DMAMUX_DMAREQ_ID_I2C3_RX = 0x14, /*!< dmamux channel dma request inputs resources: i2c3_rx */
|
||||
DMAMUX_DMAREQ_ID_I2C3_TX = 0x15, /*!< dmamux channel dma request inputs resources: i2c3_tx */
|
||||
DMAMUX_DMAREQ_ID_USART1_RX = 0x18, /*!< dmamux channel dma request inputs resources: usart1_rx */
|
||||
DMAMUX_DMAREQ_ID_USART1_TX = 0x19, /*!< dmamux channel dma request inputs resources: usart1_tx */
|
||||
DMAMUX_DMAREQ_ID_USART2_RX = 0x1A, /*!< dmamux channel dma request inputs resources: usart2_rx */
|
||||
DMAMUX_DMAREQ_ID_USART2_TX = 0x1B, /*!< dmamux channel dma request inputs resources: usart2_tx */
|
||||
DMAMUX_DMAREQ_ID_USART3_RX = 0x1C, /*!< dmamux channel dma request inputs resources: usart3_rx */
|
||||
DMAMUX_DMAREQ_ID_USART3_TX = 0x1D, /*!< dmamux channel dma request inputs resources: usart3_tx */
|
||||
DMAMUX_DMAREQ_ID_UART4_RX = 0x1E, /*!< dmamux channel dma request inputs resources: uart4_rx */
|
||||
DMAMUX_DMAREQ_ID_UART4_TX = 0x1F, /*!< dmamux channel dma request inputs resources: uart4_tx */
|
||||
DMAMUX_DMAREQ_ID_UART5_RX = 0x20, /*!< dmamux channel dma request inputs resources: uart5_rx */
|
||||
DMAMUX_DMAREQ_ID_UART5_TX = 0x21, /*!< dmamux channel dma request inputs resources: uart5_tx */
|
||||
DMAMUX_DMAREQ_ID_USART6_RX = 0x72, /*!< dmamux channel dma request inputs resources: usart6_rx */
|
||||
DMAMUX_DMAREQ_ID_USART6_TX = 0x73, /*!< dmamux channel dma request inputs resources: usart6_tx */
|
||||
DMAMUX_DMAREQ_ID_UART7_RX = 0x74, /*!< dmamux channel dma request inputs resources: uart7_rx */
|
||||
DMAMUX_DMAREQ_ID_UART7_TX = 0x75, /*!< dmamux channel dma request inputs resources: uart7_tx */
|
||||
DMAMUX_DMAREQ_ID_UART8_RX = 0x76, /*!< dmamux channel dma request inputs resources: uart8_rx */
|
||||
DMAMUX_DMAREQ_ID_UART8_TX = 0x77, /*!< dmamux channel dma request inputs resources: uart8_tx */
|
||||
DMAMUX_DMAREQ_ID_SDIO1 = 0x27, /*!< dmamux channel dma request inputs resources: sdio1 */
|
||||
DMAMUX_DMAREQ_ID_SDIO2 = 0x67, /*!< dmamux channel dma request inputs resources: sdio2 */
|
||||
DMAMUX_DMAREQ_ID_QSPI1 = 0x28, /*!< dmamux channel dma request inputs resources: qspi1 */
|
||||
DMAMUX_DMAREQ_ID_QSPI2 = 0x68, /*!< dmamux channel dma request inputs resources: qspi2 */
|
||||
DMAMUX_DMAREQ_ID_TMR1_CH1 = 0x2A, /*!< dmamux channel dma request inputs resources: timer1 ch1 */
|
||||
DMAMUX_DMAREQ_ID_TMR1_CH2 = 0x2B, /*!< dmamux channel dma request inputs resources: timer1 ch2 */
|
||||
DMAMUX_DMAREQ_ID_TMR1_CH3 = 0x2C, /*!< dmamux channel dma request inputs resources: timer1 ch3 */
|
||||
DMAMUX_DMAREQ_ID_TMR1_CH4 = 0x2D, /*!< dmamux channel dma request inputs resources: timer1 ch4 */
|
||||
DMAMUX_DMAREQ_ID_TMR1_OVERFLOW = 0x2E, /*!< dmamux channel dma request inputs resources: timer1 overflow */
|
||||
DMAMUX_DMAREQ_ID_TMR1_TRIG = 0x2F, /*!< dmamux channel dma request inputs resources: timer1 trigger */
|
||||
DMAMUX_DMAREQ_ID_TMR1_HALL = 0x30, /*!< dmamux channel dma request inputs resources: timer1 hall */
|
||||
DMAMUX_DMAREQ_ID_TMR8_CH1 = 0x31, /*!< dmamux channel dma request inputs resources: timer8 ch1 */
|
||||
DMAMUX_DMAREQ_ID_TMR8_CH2 = 0x32, /*!< dmamux channel dma request inputs resources: timer8 ch2 */
|
||||
DMAMUX_DMAREQ_ID_TMR8_CH3 = 0x33, /*!< dmamux channel dma request inputs resources: timer8 ch3 */
|
||||
DMAMUX_DMAREQ_ID_TMR8_CH4 = 0x34, /*!< dmamux channel dma request inputs resources: timer8 ch4 */
|
||||
DMAMUX_DMAREQ_ID_TMR8_OVERFLOW = 0x35, /*!< dmamux channel dma request inputs resources: timer8 overflow */
|
||||
DMAMUX_DMAREQ_ID_TMR8_TRIG = 0x36, /*!< dmamux channel dma request inputs resources: timer8 trigger */
|
||||
DMAMUX_DMAREQ_ID_TMR8_HALL = 0x37, /*!< dmamux channel dma request inputs resources: timer8 hall */
|
||||
DMAMUX_DMAREQ_ID_TMR2_CH1 = 0x38, /*!< dmamux channel dma request inputs resources: timer2 ch1 */
|
||||
DMAMUX_DMAREQ_ID_TMR2_CH2 = 0x39, /*!< dmamux channel dma request inputs resources: timer2 ch2 */
|
||||
DMAMUX_DMAREQ_ID_TMR2_CH3 = 0x3A, /*!< dmamux channel dma request inputs resources: timer2 ch3 */
|
||||
DMAMUX_DMAREQ_ID_TMR2_CH4 = 0x3B, /*!< dmamux channel dma request inputs resources: timer2 ch4 */
|
||||
DMAMUX_DMAREQ_ID_TMR2_OVERFLOW = 0x3C, /*!< dmamux channel dma request inputs resources: timer2 overflow */
|
||||
DMAMUX_DMAREQ_ID_TMR2_TRIG = 0x7E, /*!< dmamux channel dma request inputs resources: timer2 trigger */
|
||||
DMAMUX_DMAREQ_ID_TMR3_CH1 = 0x3D, /*!< dmamux channel dma request inputs resources: timer3 ch1 */
|
||||
DMAMUX_DMAREQ_ID_TMR3_CH2 = 0x3E, /*!< dmamux channel dma request inputs resources: timer3 ch2 */
|
||||
DMAMUX_DMAREQ_ID_TMR3_CH3 = 0x3F, /*!< dmamux channel dma request inputs resources: timer3 ch3 */
|
||||
DMAMUX_DMAREQ_ID_TMR3_CH4 = 0x40, /*!< dmamux channel dma request inputs resources: timer3 ch4 */
|
||||
DMAMUX_DMAREQ_ID_TMR3_OVERFLOW = 0x41, /*!< dmamux channel dma request inputs resources: timer3 overflow */
|
||||
DMAMUX_DMAREQ_ID_TMR3_TRIG = 0x42, /*!< dmamux channel dma request inputs resources: timer3 trigger */
|
||||
DMAMUX_DMAREQ_ID_TMR4_CH1 = 0x43, /*!< dmamux channel dma request inputs resources: timer4 ch1 */
|
||||
DMAMUX_DMAREQ_ID_TMR4_CH2 = 0x44, /*!< dmamux channel dma request inputs resources: timer4 ch2 */
|
||||
DMAMUX_DMAREQ_ID_TMR4_CH3 = 0x45, /*!< dmamux channel dma request inputs resources: timer4 ch3 */
|
||||
DMAMUX_DMAREQ_ID_TMR4_CH4 = 0x46, /*!< dmamux channel dma request inputs resources: timer4 ch4 */
|
||||
DMAMUX_DMAREQ_ID_TMR4_OVERFLOW = 0x47, /*!< dmamux channel dma request inputs resources: timer4 overflow */
|
||||
DMAMUX_DMAREQ_ID_TMR4_TRIG = 0x7F, /*!< dmamux channel dma request inputs resources: timer4 trigger */
|
||||
DMAMUX_DMAREQ_ID_TMR5_CH1 = 0x48, /*!< dmamux channel dma request inputs resources: timer5 ch1 */
|
||||
DMAMUX_DMAREQ_ID_TMR5_CH2 = 0x49, /*!< dmamux channel dma request inputs resources: timer5 ch2 */
|
||||
DMAMUX_DMAREQ_ID_TMR5_CH3 = 0x4A, /*!< dmamux channel dma request inputs resources: timer5 ch3 */
|
||||
DMAMUX_DMAREQ_ID_TMR5_CH4 = 0x4B, /*!< dmamux channel dma request inputs resources: timer5 ch4 */
|
||||
DMAMUX_DMAREQ_ID_TMR5_OVERFLOW = 0x4C, /*!< dmamux channel dma request inputs resources: timer5 overflow */
|
||||
DMAMUX_DMAREQ_ID_TMR5_TRIG = 0x4D, /*!< dmamux channel dma request inputs resources: timer5 trigger */
|
||||
DMAMUX_DMAREQ_ID_TMR20_CH1 = 0x56, /*!< dmamux channel dma request inputs resources: timer20 ch1 */
|
||||
DMAMUX_DMAREQ_ID_TMR20_CH2 = 0x57, /*!< dmamux channel dma request inputs resources: timer20 ch2 */
|
||||
DMAMUX_DMAREQ_ID_TMR20_CH3 = 0x58, /*!< dmamux channel dma request inputs resources: timer20 ch3 */
|
||||
DMAMUX_DMAREQ_ID_TMR20_CH4 = 0x59, /*!< dmamux channel dma request inputs resources: timer20 ch4 */
|
||||
DMAMUX_DMAREQ_ID_TMR20_OVERFLOW = 0x5A, /*!< dmamux channel dma request inputs resources: timer20 overflow */
|
||||
DMAMUX_DMAREQ_ID_TMR20_TRIG = 0x5D, /*!< dmamux channel dma request inputs resources: timer20 trigger */
|
||||
DMAMUX_DMAREQ_ID_TMR20_HALL = 0x5E, /*!< dmamux channel dma request inputs resources: timer20 hall */
|
||||
DMAMUX_DMAREQ_ID_DVP = 0x69 /*!< dmamux channel dma request inputs resources: dvp */
|
||||
} dmamux_requst_id_sel_type;
|
||||
|
||||
/**
|
||||
* @brief dmamux sync id type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
DMAMUX_SYNC_ID_EXINT0 = 0x00, /*!< dmamux channel synchronization inputs resources: exint line0 */
|
||||
DMAMUX_SYNC_ID_EXINT1 = 0x01, /*!< dmamux channel synchronization inputs resources: exint line1 */
|
||||
DMAMUX_SYNC_ID_EXINT2 = 0x02, /*!< dmamux channel synchronization inputs resources: exint line2 */
|
||||
DMAMUX_SYNC_ID_EXINT3 = 0x03, /*!< dmamux channel synchronization inputs resources: exint line3 */
|
||||
DMAMUX_SYNC_ID_EXINT4 = 0x04, /*!< dmamux channel synchronization inputs resources: exint line4 */
|
||||
DMAMUX_SYNC_ID_EXINT5 = 0x05, /*!< dmamux channel synchronization inputs resources: exint line5 */
|
||||
DMAMUX_SYNC_ID_EXINT6 = 0x06, /*!< dmamux channel synchronization inputs resources: exint line6 */
|
||||
DMAMUX_SYNC_ID_EXINT7 = 0x07, /*!< dmamux channel synchronization inputs resources: exint line7 */
|
||||
DMAMUX_SYNC_ID_EXINT8 = 0x08, /*!< dmamux channel synchronization inputs resources: exint line8 */
|
||||
DMAMUX_SYNC_ID_EXINT9 = 0x09, /*!< dmamux channel synchronization inputs resources: exint line9 */
|
||||
DMAMUX_SYNC_ID_EXINT10 = 0x0A, /*!< dmamux channel synchronization inputs resources: exint line10 */
|
||||
DMAMUX_SYNC_ID_EXINT11 = 0x0B, /*!< dmamux channel synchronization inputs resources: exint line11 */
|
||||
DMAMUX_SYNC_ID_EXINT12 = 0x0C, /*!< dmamux channel synchronization inputs resources: exint line12 */
|
||||
DMAMUX_SYNC_ID_EXINT13 = 0x0D, /*!< dmamux channel synchronization inputs resources: exint line13 */
|
||||
DMAMUX_SYNC_ID_EXINT14 = 0x0E, /*!< dmamux channel synchronization inputs resources: exint line14 */
|
||||
DMAMUX_SYNC_ID_EXINT15 = 0x0F, /*!< dmamux channel synchronization inputs resources: exint line15 */
|
||||
DMAMUX_SYNC_ID_DMAMUX_CH1_EVT = 0x10, /*!< dmamux channel synchronization inputs resources: dmamux channel1 event */
|
||||
DMAMUX_SYNC_ID_DMAMUX_CH2_EVT = 0x11, /*!< dmamux channel synchronization inputs resources: dmamux channel2 event */
|
||||
DMAMUX_SYNC_ID_DMAMUX_CH3_EVT = 0x12, /*!< dmamux channel synchronization inputs resources: dmamux channel3 event */
|
||||
DMAMUX_SYNC_ID_DMAMUX_CH4_EVT = 0x13, /*!< dmamux channel synchronization inputs resources: dmamux channel4 event */
|
||||
DMAMUX_SYNC_ID_DMAMUX_CH5_EVT = 0x14, /*!< dmamux channel synchronization inputs resources: dmamux channel5 event */
|
||||
DMAMUX_SYNC_ID_DMAMUX_CH6_EVT = 0x15, /*!< dmamux channel synchronization inputs resources: dmamux channel6 event */
|
||||
DMAMUX_SYNC_ID_DMAMUX_CH7_EVT = 0x16 /*!< dmamux channel synchronization inputs resources: dmamux channel7 event */
|
||||
} dmamux_sync_id_sel_type;
|
||||
|
||||
/**
|
||||
* @brief dmamux sync polarity type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
DMAMUX_SYNC_POLARITY_DISABLE = 0x00, /*!< dmamux channel synchronization inputs resources polarity default value */
|
||||
DMAMUX_SYNC_POLARITY_RISING = 0x01, /*!< dmamux channel synchronization inputs resources polarity: rising */
|
||||
DMAMUX_SYNC_POLARITY_FALLING = 0x02, /*!< dmamux channel synchronization inputs resources polarity: falling */
|
||||
DMAMUX_SYNC_POLARITY_RISING_FALLING = 0x03 /*!< dmamux channel synchronization inputs resources polarity: rising_falling */
|
||||
} dmamux_sync_pol_type;
|
||||
|
||||
/**
|
||||
* @brief dmamux generator id type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
DMAMUX_GEN_ID_EXINT0 = 0x00, /*!< dmamux generator channel inputs resources: exint line0 */
|
||||
DMAMUX_GEN_ID_EXINT1 = 0x01, /*!< dmamux generator channel inputs resources: exint line1 */
|
||||
DMAMUX_GEN_ID_EXINT2 = 0x02, /*!< dmamux generator channel inputs resources: exint line2 */
|
||||
DMAMUX_GEN_ID_EXINT3 = 0x03, /*!< dmamux generator channel inputs resources: exint line3 */
|
||||
DMAMUX_GEN_ID_EXINT4 = 0x04, /*!< dmamux generator channel inputs resources: exint line4 */
|
||||
DMAMUX_GEN_ID_EXINT5 = 0x05, /*!< dmamux generator channel inputs resources: exint line5 */
|
||||
DMAMUX_GEN_ID_EXINT6 = 0x06, /*!< dmamux generator channel inputs resources: exint line6 */
|
||||
DMAMUX_GEN_ID_EXINT7 = 0x07, /*!< dmamux generator channel inputs resources: exint line7 */
|
||||
DMAMUX_GEN_ID_EXINT8 = 0x08, /*!< dmamux generator channel inputs resources: exint line8 */
|
||||
DMAMUX_GEN_ID_EXINT9 = 0x09, /*!< dmamux generator channel inputs resources: exint line9 */
|
||||
DMAMUX_GEN_ID_EXINT10 = 0x0A, /*!< dmamux generator channel inputs resources: exint line10 */
|
||||
DMAMUX_GEN_ID_EXINT11 = 0x0B, /*!< dmamux generator channel inputs resources: exint line11 */
|
||||
DMAMUX_GEN_ID_EXINT12 = 0x0C, /*!< dmamux generator channel inputs resources: exint line12 */
|
||||
DMAMUX_GEN_ID_EXINT13 = 0x0D, /*!< dmamux generator channel inputs resources: exint line13 */
|
||||
DMAMUX_GEN_ID_EXINT14 = 0x0E, /*!< dmamux generator channel inputs resources: exint line14 */
|
||||
DMAMUX_GEN_ID_EXINT15 = 0x0F, /*!< dmamux generator channel inputs resources: exint line15 */
|
||||
DMAMUX_GEN_ID_DMAMUX_CH1_EVT = 0x10, /*!< dmamux generator channel inputs resources: dmamux channel1 event */
|
||||
DMAMUX_GEN_ID_DMAMUX_CH2_EVT = 0x11, /*!< dmamux generator channel inputs resources: dmamux channel2 event */
|
||||
DMAMUX_GEN_ID_DMAMUX_CH3_EVT = 0x12, /*!< dmamux generator channel inputs resources: dmamux channel3 event */
|
||||
DMAMUX_GEN_ID_DMAMUX_CH4_EVT = 0x13, /*!< dmamux generator channel inputs resources: dmamux channel4 event */
|
||||
DMAMUX_GEN_ID_DMAMUX_CH5_EVT = 0x14, /*!< dmamux generator channel inputs resources: dmamux channel5 event */
|
||||
DMAMUX_GEN_ID_DMAMUX_CH6_EVT = 0x15, /*!< dmamux generator channel inputs resources: dmamux channel6 event */
|
||||
DMAMUX_GEN_ID_DMAMUX_CH7_EVT = 0x16 /*!< dmamux generator channel inputs resources: dmamux channel7 event */
|
||||
} dmamux_gen_id_sel_type;
|
||||
|
||||
/**
|
||||
* @brief dmamux generator polarity type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
DMAMUX_GEN_POLARITY_DISABLE = 0x00, /*!< dmamux generator channel inputs resources polarity default value */
|
||||
DMAMUX_GEN_POLARITY_RISING = 0x01, /*!< dmamux generator channel inputs resources polarity: rising */
|
||||
DMAMUX_GEN_POLARITY_FALLING = 0x02, /*!< dmamux generator channel inputs resources polarity: falling */
|
||||
DMAMUX_GEN_POLARITY_RISING_FALLING = 0x03 /*!< dmamux generator channel inputs resources polarity: rising_falling */
|
||||
} dmamux_gen_pol_type;
|
||||
|
||||
/**
|
||||
* @brief dma init type
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t peripheral_base_addr; /*!< base addrress for peripheral */
|
||||
uint32_t memory_base_addr; /*!< base addrress for memory */
|
||||
dma_dir_type direction; /*!< dma transmit direction, peripheral as source or as destnation */
|
||||
uint16_t buffer_size; /*!< counter to transfer (0~0xFFFF) */
|
||||
confirm_state peripheral_inc_enable; /*!< periphera address increment after one transmit */
|
||||
confirm_state memory_inc_enable; /*!< memory address increment after one transmit */
|
||||
dma_peripheral_data_size_type peripheral_data_width; /*!< peripheral data width for transmit */
|
||||
dma_memory_data_size_type memory_data_width; /*!< memory data width for transmit */
|
||||
confirm_state loop_mode_enable; /*!< when loop mode enable, buffer size will reload if count to 0*/
|
||||
dma_priority_level_type priority; /*!< dma priority can choose from very high,high,dedium or low */
|
||||
} dma_init_type;
|
||||
|
||||
/**
|
||||
* @brief dmamux sync init type
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
dmamux_sync_id_sel_type sync_signal_sel; /*!< dma dmamux synchronization input select */
|
||||
uint32_t sync_polarity; /*!< dma dmamux synchronization polarity */
|
||||
uint32_t sync_request_number; /*!< dma dmamux number of dma requests before an output event is generated */
|
||||
confirm_state sync_event_enable; /*!< dma dmamux event generation disabled */
|
||||
confirm_state sync_enable; /*!< dma dmamux synchronization enable */
|
||||
} dmamux_sync_init_type;
|
||||
|
||||
/**
|
||||
* @brief dmamux generator init type
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
dmamux_gen_id_sel_type gen_signal_sel; /*!< dma dmamux generator dma request trigger input select */
|
||||
dmamux_gen_pol_type gen_polarity; /*!< dma dmamux generator trigger polarity */
|
||||
uint32_t gen_request_number; /*!< dma dmamux the number of dma requests to be generated after a trigger event */
|
||||
confirm_state gen_enable; /*!< dma dmamux generator enable */
|
||||
} dmamux_gen_init_type;
|
||||
|
||||
/**
|
||||
* @brief type define dma1 register
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
/**
|
||||
* @brief dma sts register, offset:0x00
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t sts;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t gf1 : 1; /* [0] */
|
||||
__IO uint32_t fdtf1 : 1; /* [1] */
|
||||
__IO uint32_t hdtf1 : 1; /* [2] */
|
||||
__IO uint32_t dterrf1 : 1; /* [3] */
|
||||
__IO uint32_t gf2 : 1; /* [4] */
|
||||
__IO uint32_t fdtf2 : 1; /* [5] */
|
||||
__IO uint32_t hdtf2 : 1; /* [6] */
|
||||
__IO uint32_t dterrf2 : 1; /* [7] */
|
||||
__IO uint32_t gf3 : 1; /* [8] */
|
||||
__IO uint32_t fdtf3 : 1; /* [9] */
|
||||
__IO uint32_t hdtf3 : 1; /* [10] */
|
||||
__IO uint32_t dterrf3 : 1; /* [11] */
|
||||
__IO uint32_t gf4 : 1; /* [12] */
|
||||
__IO uint32_t fdtf4 : 1; /* [13] */
|
||||
__IO uint32_t hdtf4 : 1; /* [14] */
|
||||
__IO uint32_t dterrf4 : 1; /* [15] */
|
||||
__IO uint32_t gf5 : 1; /* [16] */
|
||||
__IO uint32_t fdtf5 : 1; /* [17] */
|
||||
__IO uint32_t hdtf5 : 1; /* [18] */
|
||||
__IO uint32_t dterrf5 : 1; /* [19] */
|
||||
__IO uint32_t gf6 : 1; /* [20] */
|
||||
__IO uint32_t fdtf6 : 1; /* [21] */
|
||||
__IO uint32_t hdtf6 : 1; /* [22] */
|
||||
__IO uint32_t dterrf6 : 1; /* [23] */
|
||||
__IO uint32_t gf7 : 1; /* [24] */
|
||||
__IO uint32_t fdtf7 : 1; /* [25] */
|
||||
__IO uint32_t hdtf7 : 1; /* [26] */
|
||||
__IO uint32_t dterrf7 : 1; /* [27] */
|
||||
__IO uint32_t reserved1 : 4; /* [31:28] */
|
||||
} sts_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief dma clr register, offset:0x04
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t clr;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t gfc1 : 1; /* [0] */
|
||||
__IO uint32_t fdtfc1 : 1; /* [1] */
|
||||
__IO uint32_t hdtfc1 : 1; /* [2] */
|
||||
__IO uint32_t dterrfc1 : 1; /* [3] */
|
||||
__IO uint32_t gfc2 : 1; /* [4] */
|
||||
__IO uint32_t fdtfc2 : 1; /* [5] */
|
||||
__IO uint32_t hdtfc2 : 1; /* [6] */
|
||||
__IO uint32_t dterrfc2 : 1; /* [7] */
|
||||
__IO uint32_t gfc3 : 1; /* [8] */
|
||||
__IO uint32_t fdtfc3 : 1; /* [9] */
|
||||
__IO uint32_t hdtfc3 : 1; /* [10] */
|
||||
__IO uint32_t dterrfc3 : 1; /* [11] */
|
||||
__IO uint32_t gfc4 : 1; /* [12] */
|
||||
__IO uint32_t fdtfc4 : 1; /* [13] */
|
||||
__IO uint32_t hdtfc4 : 1; /* [14] */
|
||||
__IO uint32_t dterrfc4 : 1; /* [15] */
|
||||
__IO uint32_t gfc5 : 1; /* [16] */
|
||||
__IO uint32_t fdtfc5 : 1; /* [17] */
|
||||
__IO uint32_t hdtfc5 : 1; /* [18] */
|
||||
__IO uint32_t dterrfc5 : 1; /* [19] */
|
||||
__IO uint32_t gfc6 : 1; /* [20] */
|
||||
__IO uint32_t fdtfc6 : 1; /* [21] */
|
||||
__IO uint32_t hdtfc6 : 1; /* [22] */
|
||||
__IO uint32_t dterrfc6 : 1; /* [23] */
|
||||
__IO uint32_t gfc7 : 1; /* [24] */
|
||||
__IO uint32_t fdtfc7 : 1; /* [25] */
|
||||
__IO uint32_t hdtfc7 : 1; /* [26] */
|
||||
__IO uint32_t dterrfc7 : 1; /* [27] */
|
||||
__IO uint32_t reserved1 : 4; /* [31:28] */
|
||||
} clr_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief reserved, offset:0x08~0xFC
|
||||
*/
|
||||
__IO uint32_t reserved1[62];
|
||||
|
||||
/**
|
||||
* @brief dmamux sel register, offset:0x100
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t muxsel;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t tblsel : 1; /* [0] */
|
||||
__IO uint32_t reserved1 : 31;/* [31:1] */
|
||||
}muxsel_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief reserved, offset:0x104~0x12C
|
||||
*/
|
||||
__IO uint32_t reserved2[11];
|
||||
|
||||
/**
|
||||
* @brief dmamux syncsts register, offset:0x130
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t muxsyncsts;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t syncovf : 7; /* [6:0] */
|
||||
__IO uint32_t reserved1 : 25;/* [31:7] */
|
||||
}muxsyncsts_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief dmamux syncclr register, offset:0x134
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t muxsyncclr;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t syncovfc : 7; /* [6:0] */
|
||||
__IO uint32_t reserved1 : 25;/* [31:7] */
|
||||
}muxsyncclr_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief dmamux request generator status register, offset:0x138
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t muxgsts;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t trgovf : 4; /* [3:0] */
|
||||
__IO uint32_t reserved1 : 28;/* [31:4] */
|
||||
}muxgsts_bit;
|
||||
};
|
||||
/**
|
||||
* @brief dmamux request generator status clear register, offset:0x13C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t muxgclr;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t trgovfc : 4; /* [3:0] */
|
||||
__IO uint32_t reserved1 : 28;/* [31:4] */
|
||||
}muxgclr_bit;
|
||||
};
|
||||
} dma_type;
|
||||
|
||||
/**
|
||||
* @brief type define dma channel register all
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
/**
|
||||
* @brief dma ch ctrl0 register, offset:0x08+20*(x-1) x=1...7
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ctrl;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t chen : 1; /* [0] */
|
||||
__IO uint32_t fdtien : 1; /* [1] */
|
||||
__IO uint32_t hdtien : 1; /* [2] */
|
||||
__IO uint32_t dterrien : 1; /* [3] */
|
||||
__IO uint32_t dtd : 1; /* [4] */
|
||||
__IO uint32_t lm : 1; /* [5] */
|
||||
__IO uint32_t pincm : 1; /* [6] */
|
||||
__IO uint32_t mincm : 1; /* [7] */
|
||||
__IO uint32_t pwidth : 2; /* [9:8] */
|
||||
__IO uint32_t mwidth : 2; /* [11:10] */
|
||||
__IO uint32_t chpl : 2; /* [13:12] */
|
||||
__IO uint32_t m2m : 1; /* [14] */
|
||||
__IO uint32_t reserved1 : 17;/* [31:15] */
|
||||
} ctrl_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief dma tcnt register, offset:0x0C+20*(x-1) x=1...7
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t dtcnt;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t cnt : 16;/* [15:0] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:16] */
|
||||
} dtcnt_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief dma cpba register, offset:0x10+20*(x-1) x=1...7
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t paddr;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t paddr : 32;/* [31:0] */
|
||||
} paddr_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief dma cmba register, offset:0x14+20*(x-1) x=1...7
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t maddr;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t maddr : 32;/* [31:0] */
|
||||
} maddr_bit;
|
||||
};
|
||||
} dma_channel_type;
|
||||
|
||||
/**
|
||||
* @brief type define dmamux muxsctrl register
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
/**
|
||||
* @brief dma muxsctrl register
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t muxctrl;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t reqsel : 7; /* [6:0] */
|
||||
__IO uint32_t reserved1 : 1; /* [7] */
|
||||
__IO uint32_t syncovien : 1; /* [8] */
|
||||
__IO uint32_t evtgen : 1; /* [9] */
|
||||
__IO uint32_t reserved2 : 6; /* [15:10] */
|
||||
__IO uint32_t syncen : 1; /* [16] */
|
||||
__IO uint32_t syncpol : 2; /* [18:17] */
|
||||
__IO uint32_t reqcnt : 5; /* [23:19] */
|
||||
__IO uint32_t syncsel : 5; /* [28:24] */
|
||||
__IO uint32_t reserved3 : 3; /* [31:29] */
|
||||
}muxctrl_bit;
|
||||
};
|
||||
} dmamux_channel_type;
|
||||
|
||||
/**
|
||||
* @brief type define dmamux request generator register all
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
/**
|
||||
* @brief dmamux request generator register, offset:0x120+4*(x-1) x=1...4
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t gctrl;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t sigsel : 5; /* [4:0] */
|
||||
__IO uint32_t reserved1 : 3; /* [7:5] */
|
||||
__IO uint32_t trgovien : 1; /* [8] */
|
||||
__IO uint32_t reserved2 : 7; /* [15:9] */
|
||||
__IO uint32_t gen : 1; /* [16] */
|
||||
__IO uint32_t gpol : 2; /* [18:17] */
|
||||
__IO uint32_t greqcnt : 5; /* [23:19] */
|
||||
__IO uint32_t reserved3 : 8; /* [31:24] */
|
||||
}gctrl_bit;
|
||||
};
|
||||
} dmamux_generator_type;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#define DMA1 ((dma_type *) DMA1_BASE)
|
||||
#define DMA1_CHANNEL1 ((dma_channel_type *) DMA1_CHANNEL1_BASE)
|
||||
#define DMA1_CHANNEL2 ((dma_channel_type *) DMA1_CHANNEL2_BASE)
|
||||
#define DMA1_CHANNEL3 ((dma_channel_type *) DMA1_CHANNEL3_BASE)
|
||||
#define DMA1_CHANNEL4 ((dma_channel_type *) DMA1_CHANNEL4_BASE)
|
||||
#define DMA1_CHANNEL5 ((dma_channel_type *) DMA1_CHANNEL5_BASE)
|
||||
#define DMA1_CHANNEL6 ((dma_channel_type *) DMA1_CHANNEL6_BASE)
|
||||
#define DMA1_CHANNEL7 ((dma_channel_type *) DMA1_CHANNEL7_BASE)
|
||||
|
||||
#define DMA1MUX_CHANNEL1 ((dmamux_channel_type *) DMA1MUX_CHANNEL1_BASE)
|
||||
#define DMA1MUX_CHANNEL2 ((dmamux_channel_type *) DMA1MUX_CHANNEL2_BASE)
|
||||
#define DMA1MUX_CHANNEL3 ((dmamux_channel_type *) DMA1MUX_CHANNEL3_BASE)
|
||||
#define DMA1MUX_CHANNEL4 ((dmamux_channel_type *) DMA1MUX_CHANNEL4_BASE)
|
||||
#define DMA1MUX_CHANNEL5 ((dmamux_channel_type *) DMA1MUX_CHANNEL5_BASE)
|
||||
#define DMA1MUX_CHANNEL6 ((dmamux_channel_type *) DMA1MUX_CHANNEL6_BASE)
|
||||
#define DMA1MUX_CHANNEL7 ((dmamux_channel_type *) DMA1MUX_CHANNEL7_BASE)
|
||||
|
||||
#define DMA1MUX_GENERATOR1 ((dmamux_generator_type *) DMA1MUX_GENERATOR1_BASE)
|
||||
#define DMA1MUX_GENERATOR2 ((dmamux_generator_type *) DMA1MUX_GENERATOR2_BASE)
|
||||
#define DMA1MUX_GENERATOR3 ((dmamux_generator_type *) DMA1MUX_GENERATOR3_BASE)
|
||||
#define DMA1MUX_GENERATOR4 ((dmamux_generator_type *) DMA1MUX_GENERATOR4_BASE)
|
||||
|
||||
#define DMA2 ((dma_type *) DMA2_BASE)
|
||||
#define DMA2_CHANNEL1 ((dma_channel_type *) DMA2_CHANNEL1_BASE)
|
||||
#define DMA2_CHANNEL2 ((dma_channel_type *) DMA2_CHANNEL2_BASE)
|
||||
#define DMA2_CHANNEL3 ((dma_channel_type *) DMA2_CHANNEL3_BASE)
|
||||
#define DMA2_CHANNEL4 ((dma_channel_type *) DMA2_CHANNEL4_BASE)
|
||||
#define DMA2_CHANNEL5 ((dma_channel_type *) DMA2_CHANNEL5_BASE)
|
||||
#define DMA2_CHANNEL6 ((dma_channel_type *) DMA2_CHANNEL6_BASE)
|
||||
#define DMA2_CHANNEL7 ((dma_channel_type *) DMA2_CHANNEL7_BASE)
|
||||
|
||||
#define DMA2MUX_CHANNEL1 ((dmamux_channel_type *) DMA2MUX_CHANNEL1_BASE)
|
||||
#define DMA2MUX_CHANNEL2 ((dmamux_channel_type *) DMA2MUX_CHANNEL2_BASE)
|
||||
#define DMA2MUX_CHANNEL3 ((dmamux_channel_type *) DMA2MUX_CHANNEL3_BASE)
|
||||
#define DMA2MUX_CHANNEL4 ((dmamux_channel_type *) DMA2MUX_CHANNEL4_BASE)
|
||||
#define DMA2MUX_CHANNEL5 ((dmamux_channel_type *) DMA2MUX_CHANNEL5_BASE)
|
||||
#define DMA2MUX_CHANNEL6 ((dmamux_channel_type *) DMA2MUX_CHANNEL6_BASE)
|
||||
#define DMA2MUX_CHANNEL7 ((dmamux_channel_type *) DMA2MUX_CHANNEL7_BASE)
|
||||
|
||||
#define DMA2MUX_GENERATOR1 ((dmamux_generator_type *) DMA2MUX_GENERATOR1_BASE)
|
||||
#define DMA2MUX_GENERATOR2 ((dmamux_generator_type *) DMA2MUX_GENERATOR2_BASE)
|
||||
#define DMA2MUX_GENERATOR3 ((dmamux_generator_type *) DMA2MUX_GENERATOR3_BASE)
|
||||
#define DMA2MUX_GENERATOR4 ((dmamux_generator_type *) DMA2MUX_GENERATOR4_BASE)
|
||||
|
||||
/** @defgroup DMA_exported_functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* dma controller function */
|
||||
void dma_reset(dma_channel_type *dmax_channely);
|
||||
void dma_data_number_set(dma_channel_type *dmax_channely, uint16_t data_number);
|
||||
uint16_t dma_data_number_get(dma_channel_type *dmax_channely);
|
||||
void dma_interrupt_enable(dma_channel_type *dmax_channely, uint32_t dma_int, confirm_state new_state);
|
||||
void dma_channel_enable(dma_channel_type *dmax_channely, confirm_state new_state);
|
||||
flag_status dma_flag_get(uint32_t dmax_flag);
|
||||
void dma_flag_clear(uint32_t dmax_flag);
|
||||
void dma_default_para_init(dma_init_type *dma_init_struct);
|
||||
void dma_init(dma_channel_type *dmax_channely, dma_init_type *dma_init_struct);
|
||||
|
||||
/* dma requst multiplexer function */
|
||||
void dma_flexible_config(dma_type* dma_x, dmamux_channel_type *dmamux_channelx, dmamux_requst_id_sel_type dmamux_req_sel);
|
||||
void dmamux_enable(dma_type *dma_x, confirm_state new_state);
|
||||
void dmamux_init(dmamux_channel_type *dmamux_channelx, dmamux_requst_id_sel_type dmamux_req_sel);
|
||||
void dmamux_sync_default_para_init(dmamux_sync_init_type *dmamux_sync_init_struct);
|
||||
void dmamux_sync_config(dmamux_channel_type *dmamux_channelx, dmamux_sync_init_type *dmamux_sync_init_struct);
|
||||
void dmamux_generator_default_para_init(dmamux_gen_init_type *dmamux_gen_init_struct);
|
||||
void dmamux_generator_config(dmamux_generator_type *dmamux_gen_x, dmamux_gen_init_type *dmamux_gen_init_struct);
|
||||
void dmamux_sync_interrupt_enable(dmamux_channel_type *dmamux_channelx, confirm_state new_state);
|
||||
void dmamux_generator_interrupt_enable(dmamux_generator_type *dmamux_gen_x, confirm_state new_state);
|
||||
flag_status dmamux_sync_flag_get(dma_type *dma_x, uint32_t flag);
|
||||
void dmamux_sync_flag_clear(dma_type *dma_x, uint32_t flag);
|
||||
flag_status dmamux_generator_flag_get(dma_type *dma_x, uint32_t flag);
|
||||
void dmamux_generator_flag_clear(dma_type *dma_x, uint32_t flag);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,620 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file at32f435_437_dvp.h
|
||||
* @brief at32f435_437 dvp header file
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __AT32F435_437_DVP_H
|
||||
#define __AT32F435_437_DVP_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "at32f435_437.h"
|
||||
|
||||
/** @addtogroup AT32F435_437_periph_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DVP
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DVP_event_flags_definition
|
||||
* @brief dvp event flag
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DVP_CFD_EVT_FLAG ((uint32_t)0x00000001) /*!< capture frame done event status flag */
|
||||
#define DVP_OVR_EVT_FLAG ((uint32_t)0x00000002) /*!< data fifo overrun event status flag */
|
||||
#define DVP_ESE_EVT_FLAG ((uint32_t)0x00000004) /*!< embedded synchronization error event status flag */
|
||||
#define DVP_VS_EVT_FLAG ((uint32_t)0x00000008) /*!< vertical synchonization event status flag */
|
||||
#define DVP_HS_EVT_FLAG ((uint32_t)0x00000010) /*!< horizontal synchonization event status flag */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DVP_interrupt_flags_definition
|
||||
* @brief dvp interrupt flag
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DVP_CFD_INT_FLAG ((uint32_t)0x80000001) /*!< capture frame done interrupt status flag */
|
||||
#define DVP_OVR_INT_FLAG ((uint32_t)0x80000002) /*!< data fifo overrun interrupt status flag */
|
||||
#define DVP_ESE_INT_FLAG ((uint32_t)0x80000004) /*!< embedded synchronization error interrupt status flag */
|
||||
#define DVP_VS_INT_FLAG ((uint32_t)0x80000008) /*!< vertical synchonization interrupt status flag */
|
||||
#define DVP_HS_INT_FLAG ((uint32_t)0x80000010) /*!< horizontal synchonization interrupt status flag */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DVP_interrupts_definition
|
||||
* @brief dvp interrupt
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DVP_CFD_INT ((uint32_t)0x00000001) /*!< capture frame done interrupt */
|
||||
#define DVP_OVR_INT ((uint32_t)0x00000002) /*!< data fifo overrun interrupt */
|
||||
#define DVP_ESE_INT ((uint32_t)0x00000004) /*!< embedded synchronization error interrupt */
|
||||
#define DVP_VS_INT ((uint32_t)0x00000008) /*!< vertical synchonization interrupt */
|
||||
#define DVP_HS_INT ((uint32_t)0x00000010) /*!< horizontal synchonization interrupt */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DVP_exported_types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief dvp cfm type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
DVP_CAP_FUNC_MODE_CONTINUOUS = 0x00,
|
||||
DVP_CAP_FUNC_MODE_SINGLE = 0x01
|
||||
} dvp_cfm_type;
|
||||
|
||||
/**
|
||||
* @brief dvp sm type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
DVP_SYNC_MODE_HARDWARE = 0x00,
|
||||
DVP_SYNC_MODE_EMBEDDED = 0x01
|
||||
} dvp_sm_type;
|
||||
|
||||
/**
|
||||
* @brief dvp ckp type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
DVP_CLK_POLARITY_RISING = 0x00,
|
||||
DVP_CLK_POLARITY_FALLING = 0x01
|
||||
} dvp_ckp_type;
|
||||
|
||||
/**
|
||||
* @brief dvp hsp type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
DVP_HSYNC_POLARITY_HIGH = 0x00,
|
||||
DVP_HSYNC_POLARITY_LOW = 0x01
|
||||
} dvp_hsp_type;
|
||||
|
||||
/**
|
||||
* @brief dvp vsp type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
DVP_VSYNC_POLARITY_LOW = 0x00,
|
||||
DVP_VSYNC_POLARITY_HIGH = 0x01
|
||||
} dvp_vsp_type;
|
||||
|
||||
/**
|
||||
* @brief dvp bfrc type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
DVP_BFRC_ALL = 0x00,
|
||||
DVP_BFRC_HALF = 0x01,
|
||||
DVP_BFRC_QUARTER = 0x02
|
||||
} dvp_bfrc_type;
|
||||
|
||||
/**
|
||||
* @brief dvp pdl type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
DVP_PIXEL_DATA_LENGTH_8 = 0x00,
|
||||
DVP_PIXEL_DATA_LENGTH_10 = 0x01,
|
||||
DVP_PIXEL_DATA_LENGTH_12 = 0x02,
|
||||
DVP_PIXEL_DATA_LENGTH_14 = 0x03
|
||||
} dvp_pdl_type;
|
||||
|
||||
/**
|
||||
* @brief dvp pcdc type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
DVP_PCDC_ALL = 0x00,
|
||||
DVP_PCDC_ONE_IN_TWO = 0x01,
|
||||
DVP_PCDC_ONE_IN_FOUR = 0x02,
|
||||
DVP_PCDC_TWO_IN_FOUR = 0x03
|
||||
} dvp_pcdc_type;
|
||||
|
||||
/**
|
||||
* @brief dvp pcds type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
DVP_PCDS_CAP_FIRST = 0x00,
|
||||
DVP_PCDS_DROP_FIRST = 0x01
|
||||
} dvp_pcds_type;
|
||||
|
||||
/**
|
||||
* @brief dvp lcdc type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
DVP_LCDC_ALL = 0x00,
|
||||
DVP_LCDC_ONE_IN_TWO = 0x01
|
||||
} dvp_lcdc_type;
|
||||
|
||||
/**
|
||||
* @brief dvp lcds type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
DVP_LCDS_CAP_FIRST = 0x00,
|
||||
DVP_LCDS_DROP_FIRST = 0x01
|
||||
} dvp_lcds_type;
|
||||
|
||||
/**
|
||||
* @brief dvp status basic type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
DVP_STATUS_HSYN = 0x00,
|
||||
DVP_STATUS_VSYN = 0x01,
|
||||
DVP_STATUS_OFNE = 0x02
|
||||
} dvp_status_basic_type;
|
||||
|
||||
/**
|
||||
* @brief dvp pcdes type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
DVP_PCDES_CAP_FIRST = 0x00,
|
||||
DVP_PCDES_DROP_FIRST = 0x01
|
||||
} dvp_pcdes_type;
|
||||
|
||||
/**
|
||||
* @brief dvp efdf type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
DVP_EFDF_BYPASS = 0x00,
|
||||
DVP_EFDF_YUV422_UYVY = 0x04,
|
||||
DVP_EFDF_YUV422_YUYV = 0x05,
|
||||
DVP_EFDF_RGB565_555 = 0x06,
|
||||
DVP_EFDF_Y8 = 0x07
|
||||
} dvp_efdf_type;
|
||||
|
||||
/**
|
||||
* @brief dvp idus type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
DVP_IDUS_MSB = 0x00,
|
||||
DVP_IDUS_LSB = 0x01
|
||||
} dvp_idus_type;
|
||||
|
||||
/**
|
||||
* @brief dvp dmabt type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
DVP_DMABT_SINGLE = 0x00,
|
||||
DVP_DMABT_BURST = 0x01
|
||||
} dvp_dmabt_type;
|
||||
|
||||
/**
|
||||
* @brief dvp hseid type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
DVP_HSEID_LINE_END = 0x00,
|
||||
DVP_HSEID_LINE_START = 0x01
|
||||
} dvp_hseid_type;
|
||||
|
||||
/**
|
||||
* @brief dvp vseid type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
DVP_VSEID_FRAME_END = 0x00,
|
||||
DVP_VSEID_FRMAE_START = 0x01
|
||||
} dvp_vseid_type;
|
||||
/**
|
||||
* @brief dvp idun type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
DVP_IDUN_0 = 0x00,
|
||||
DVP_IDUN_2 = 0x01,
|
||||
DVP_IDUN_4 = 0x02,
|
||||
DVP_IDUN_6 = 0x03
|
||||
} dvp_idun_type;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
/**
|
||||
* @brief dvp ctrl register, offset:0x00
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ctrl;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t cap : 1; /* [0] */
|
||||
__IO uint32_t cfm : 1; /* [1] */
|
||||
__IO uint32_t crp : 1; /* [2] */
|
||||
__IO uint32_t jpeg : 1; /* [3] */
|
||||
__IO uint32_t sm : 1; /* [4] */
|
||||
__IO uint32_t ckp : 1; /* [5] */
|
||||
__IO uint32_t hsp : 1; /* [6] */
|
||||
__IO uint32_t vsp : 1; /* [7] */
|
||||
__IO uint32_t bfrc : 2; /* [9:8] */
|
||||
__IO uint32_t pdl : 2; /* [11:10] */
|
||||
__IO uint32_t reserved1 : 2; /* [13:12] */
|
||||
__IO uint32_t ena : 1; /* [14] */
|
||||
__IO uint32_t reserved2 : 1; /* [15] */
|
||||
__IO uint32_t pcdc : 2; /* [17:16] */
|
||||
__IO uint32_t pcds : 1; /* [18] */
|
||||
__IO uint32_t lcdc : 1; /* [19] */
|
||||
__IO uint32_t lcds : 1; /* [20] */
|
||||
__IO uint32_t reserved3 : 11;/* [31:21] */
|
||||
} ctrl_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief dvp sts register, offset:0x04
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t sts;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t hsyn : 1; /* [0] */
|
||||
__IO uint32_t vsyn : 1; /* [1] */
|
||||
__IO uint32_t ofne : 1; /* [2] */
|
||||
__IO uint32_t reserved1 : 29;/* [31:3] */
|
||||
} sts_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief dvp ests register, offset:0x08
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ests;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t cfdes : 1; /* [0] */
|
||||
__IO uint32_t ovres : 1; /* [1] */
|
||||
__IO uint32_t esees : 1; /* [2] */
|
||||
__IO uint32_t vses : 1; /* [3] */
|
||||
__IO uint32_t hses : 1; /* [4] */
|
||||
__IO uint32_t reserved1 : 27;/* [31:5] */
|
||||
} ests_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief dvp ier register, offset:0x0C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ier;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t cfdie : 1; /* [0] */
|
||||
__IO uint32_t ovrie : 1; /* [1] */
|
||||
__IO uint32_t eseie : 1; /* [2] */
|
||||
__IO uint32_t vsie : 1; /* [3] */
|
||||
__IO uint32_t hsie : 1; /* [4] */
|
||||
__IO uint32_t reserved1 : 27;/* [31:5] */
|
||||
} ier_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief dvp ists register, offset:0x10
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ists;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t cfdis : 1; /* [0] */
|
||||
__IO uint32_t ovris : 1; /* [1] */
|
||||
__IO uint32_t eseis : 1; /* [2] */
|
||||
__IO uint32_t vsis : 1; /* [3] */
|
||||
__IO uint32_t hsis : 1; /* [4] */
|
||||
__IO uint32_t reserved1 : 27;/* [31:5] */
|
||||
} ists_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief dvp iclr register, offset:0x14
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t iclr;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t cfdic : 1; /* [0] */
|
||||
__IO uint32_t ovric : 1; /* [1] */
|
||||
__IO uint32_t eseic : 1; /* [2] */
|
||||
__IO uint32_t vsic : 1; /* [3] */
|
||||
__IO uint32_t hsic : 1; /* [4] */
|
||||
__IO uint32_t reserved1 : 27;/* [31:5] */
|
||||
} iclr_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief dvp scr register, offset:0x18
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t scr;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t fmsc : 8; /* [7:0] */
|
||||
__IO uint32_t lnsc : 8; /* [15:8] */
|
||||
__IO uint32_t lnec : 8; /* [23:16] */
|
||||
__IO uint32_t fmec : 8; /* [31:24] */
|
||||
} scr_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief dvp sur register, offset:0x1C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t sur;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t fmsu : 8; /* [7:0] */
|
||||
__IO uint32_t lnsu : 8; /* [15:8] */
|
||||
__IO uint32_t lneu : 8; /* [23:16] */
|
||||
__IO uint32_t fmeu : 8; /* [31:24] */
|
||||
} sur_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief dvp cwst register, offset:0x20
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t cwst;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t chstr : 14;/* [13:0] */
|
||||
__IO uint32_t reserved1 : 2; /* [15:14] */
|
||||
__IO uint32_t cvstr : 13;/* [28:16] */
|
||||
__IO uint32_t reserved2 : 3; /* [31:29] */
|
||||
} cwst_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief dvp cwsz register, offset:0x24
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t cwsz;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t chnum : 14;/* [13:0] */
|
||||
__IO uint32_t reserved1 : 2; /* [15:14] */
|
||||
__IO uint32_t cvnum : 14;/* [29:16] */
|
||||
__IO uint32_t reserved2 : 2; /* [31:30] */
|
||||
} cwsz_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief dvp dt register, offset:0x28
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t dt;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t dr0 : 8; /* [7:0] */
|
||||
__IO uint32_t dr1 : 8; /* [15:8] */
|
||||
__IO uint32_t dr2 : 8; /* [23:16] */
|
||||
__IO uint32_t dr3 : 8; /* [31:24] */
|
||||
} dt_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief dvp reserved1 register, offset:0x2C-0x3C
|
||||
*/
|
||||
__IO uint32_t reserved1[5];
|
||||
|
||||
/**
|
||||
* @brief dvp actrl register, offset:0x40
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t actrl;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t eisre : 1; /* [0] */
|
||||
__IO uint32_t efrce : 1; /* [1] */
|
||||
__IO uint32_t mibe : 1; /* [2] */
|
||||
__IO uint32_t pcdes : 1; /* [3] */
|
||||
__IO uint32_t efdf : 3; /* [6:4] */
|
||||
__IO uint32_t reserved1 : 1; /* [7] */
|
||||
__IO uint32_t idun : 2; /* [9:8] */
|
||||
__IO uint32_t idus : 1; /* [10] */
|
||||
__IO uint32_t reserved2 : 1; /* [11] */
|
||||
__IO uint32_t dmabt : 1; /* [12] */
|
||||
__IO uint32_t reserved3 : 1; /* [13] */
|
||||
__IO uint32_t reserved4 : 1; /* [14] */
|
||||
__IO uint32_t reserved5 : 1; /* [15] */
|
||||
__IO uint32_t hseid : 1; /* [16] */
|
||||
__IO uint32_t vseid : 1; /* [17] */
|
||||
__IO uint32_t reserved6 : 1; /* [18] */
|
||||
__IO uint32_t reserved7 : 2; /* [20:19] */
|
||||
__IO uint32_t reserved8 : 11;/* [31:21] */
|
||||
} actrl_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief dvp reserved2 register, offset:0x44
|
||||
*/
|
||||
__IO uint32_t reserved2;
|
||||
|
||||
/**
|
||||
* @brief dvp hscf register, offset:0x48
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t hscf;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t hsrss : 13;/* [12:0] */
|
||||
__IO uint32_t reserved1 : 3; /* [15:13] */
|
||||
__IO uint32_t hsrts : 13;/* [28:16] */
|
||||
__IO uint32_t reserved2 : 3; /* [31:29] */
|
||||
} hscf_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief dvp vscf register, offset:0x4C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t vscf;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t vsrss : 13;/* [12:0] */
|
||||
__IO uint32_t reserved1 : 3; /* [15:13] */
|
||||
__IO uint32_t vsrts : 13;/* [28:16] */
|
||||
__IO uint32_t reserved2 : 3; /* [31:29] */
|
||||
} vscf_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief dvp frf register, offset:0x50
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t frf;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t efrcsf : 5; /* [4:0] */
|
||||
__IO uint32_t reserved1 : 3; /* [7:5] */
|
||||
__IO uint32_t efrctf : 5; /* [12:8] */
|
||||
__IO uint32_t reserved2 : 19;/* [31:13] */
|
||||
} frf_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief dvp bth register, offset:0x54
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t bth;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t mibthd : 8; /* [7:0] */
|
||||
__IO uint32_t reserved1 : 24;/* [31:8] */
|
||||
} bth_bit;
|
||||
};
|
||||
|
||||
} dvp_type;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#define DVP ((dvp_type *) DVP_BASE)
|
||||
|
||||
/** @defgroup DVP_exported_functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void dvp_reset(void);
|
||||
void dvp_capture_enable(confirm_state new_state);
|
||||
void dvp_capture_enable(confirm_state new_state);
|
||||
void dvp_capture_mode_set(dvp_cfm_type cap_mode);
|
||||
void dvp_window_crop_enable(confirm_state new_state);
|
||||
void dvp_window_crop_set(uint16_t crop_x, uint16_t crop_y, uint16_t crop_w, uint16_t crop_h, uint8_t bytes);
|
||||
void dvp_jpeg_enable(confirm_state new_state);
|
||||
void dvp_sync_mode_set(dvp_sm_type sync_mode);
|
||||
void dvp_sync_code_set(uint8_t fmsc, uint8_t fmec, uint8_t lnsc, uint8_t lnec);
|
||||
void dvp_sync_unmask_set(uint8_t fmsu, uint8_t fmeu, uint8_t lnsu, uint8_t lneu);
|
||||
void dvp_pclk_polarity_set(dvp_ckp_type eage);
|
||||
void dvp_hsync_polarity_set(dvp_hsp_type hsync_pol);
|
||||
void dvp_vsync_polarity_set(dvp_vsp_type vsync_pol);
|
||||
void dvp_basic_frame_rate_control_set(dvp_bfrc_type dvp_bfrc);
|
||||
void dvp_pixel_data_length_set(dvp_pdl_type dvp_pdl);
|
||||
void dvp_enable(confirm_state new_state);
|
||||
void dvp_zoomout_select(dvp_pcdes_type dvp_pcdes);
|
||||
void dvp_zoomout_set(dvp_pcdc_type dvp_pcdc, dvp_pcds_type dvp_pcds, dvp_lcdc_type dvp_lcdc, dvp_lcds_type dvp_lcds);
|
||||
flag_status dvp_basic_status_get(dvp_status_basic_type dvp_status_basic);
|
||||
void dvp_interrupt_enable(uint32_t dvp_int, confirm_state new_state);
|
||||
flag_status dvp_flag_get(uint32_t flag);
|
||||
void dvp_flag_clear(uint32_t flag);
|
||||
void dvp_enhanced_scaling_resize_enable(confirm_state new_state);
|
||||
void dvp_enhanced_scaling_resize_set(uint16_t src_w, uint16_t des_w, uint16_t src_h, uint16_t des_h);
|
||||
void dvp_enhanced_framerate_set(uint16_t efrcsf, uint16_t efrctf, confirm_state new_state);
|
||||
void dvp_monochrome_image_binarization_set(uint8_t mibthd, confirm_state new_state);
|
||||
void dvp_enhanced_data_format_set(dvp_efdf_type dvp_efdf);
|
||||
void dvp_input_data_unused_set(dvp_idus_type dvp_idus, dvp_idun_type dvp_idun);
|
||||
void dvp_dma_burst_set(dvp_dmabt_type dvp_dmabt);
|
||||
void dvp_sync_event_interrupt_set(dvp_hseid_type dvp_hseid, dvp_vseid_type dvp_vseid);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,232 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file at32f435_437_exint.h
|
||||
* @brief at32f435_437 exint header file
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __AT32F435_437_EXINT_H
|
||||
#define __AT32F435_437_EXINT_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "at32f435_437.h"
|
||||
|
||||
/** @addtogroup AT32F435_437_periph_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup EXINT
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup EXINT_lines
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define EXINT_LINE_NONE ((uint32_t)0x000000)
|
||||
#define EXINT_LINE_0 ((uint32_t)0x000001) /*!< external interrupt line 0 */
|
||||
#define EXINT_LINE_1 ((uint32_t)0x000002) /*!< external interrupt line 1 */
|
||||
#define EXINT_LINE_2 ((uint32_t)0x000004) /*!< external interrupt line 2 */
|
||||
#define EXINT_LINE_3 ((uint32_t)0x000008) /*!< external interrupt line 3 */
|
||||
#define EXINT_LINE_4 ((uint32_t)0x000010) /*!< external interrupt line 4 */
|
||||
#define EXINT_LINE_5 ((uint32_t)0x000020) /*!< external interrupt line 5 */
|
||||
#define EXINT_LINE_6 ((uint32_t)0x000040) /*!< external interrupt line 6 */
|
||||
#define EXINT_LINE_7 ((uint32_t)0x000080) /*!< external interrupt line 7 */
|
||||
#define EXINT_LINE_8 ((uint32_t)0x000100) /*!< external interrupt line 8 */
|
||||
#define EXINT_LINE_9 ((uint32_t)0x000200) /*!< external interrupt line 9 */
|
||||
#define EXINT_LINE_10 ((uint32_t)0x000400) /*!< external interrupt line 10 */
|
||||
#define EXINT_LINE_11 ((uint32_t)0x000800) /*!< external interrupt line 11 */
|
||||
#define EXINT_LINE_12 ((uint32_t)0x001000) /*!< external interrupt line 12 */
|
||||
#define EXINT_LINE_13 ((uint32_t)0x002000) /*!< external interrupt line 13 */
|
||||
#define EXINT_LINE_14 ((uint32_t)0x004000) /*!< external interrupt line 14 */
|
||||
#define EXINT_LINE_15 ((uint32_t)0x008000) /*!< external interrupt line 15 */
|
||||
#define EXINT_LINE_16 ((uint32_t)0x010000) /*!< external interrupt line 16 */
|
||||
#define EXINT_LINE_17 ((uint32_t)0x020000) /*!< external interrupt line 17 */
|
||||
#define EXINT_LINE_18 ((uint32_t)0x040000) /*!< external interrupt line 18 */
|
||||
#define EXINT_LINE_19 ((uint32_t)0x080000) /*!< external interrupt line 19 */
|
||||
#define EXINT_LINE_20 ((uint32_t)0x100000) /*!< external interrupt line 20 */
|
||||
#define EXINT_LINE_21 ((uint32_t)0x200000) /*!< external interrupt line 21 */
|
||||
#define EXINT_LINE_22 ((uint32_t)0x400000) /*!< external interrupt line 22 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup EXINT_exported_types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief exint line mode type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
EXINT_LINE_INTERRUPUT = 0x00, /*!< external interrupt line interrupt mode */
|
||||
EXINT_LINE_EVENT = 0x01 /*!< external interrupt line event mode */
|
||||
} exint_line_mode_type;
|
||||
|
||||
/**
|
||||
* @brief exint polarity configuration type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
EXINT_TRIGGER_RISING_EDGE = 0x00, /*!< external interrupt line rising trigger mode */
|
||||
EXINT_TRIGGER_FALLING_EDGE = 0x01, /*!< external interrupt line falling trigger mode */
|
||||
EXINT_TRIGGER_BOTH_EDGE = 0x02 /*!< external interrupt line both rising and falling trigger mode */
|
||||
} exint_polarity_config_type;
|
||||
|
||||
/**
|
||||
* @brief exint init type
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
exint_line_mode_type line_mode; /*!< choose mode event or interrupt mode */
|
||||
uint32_t line_select; /*!< select the exint line, availiable for single line or multiple lines */
|
||||
exint_polarity_config_type line_polarity; /*!< select the tregger polarity, with rising edge, falling edge or both edge */
|
||||
confirm_state line_enable; /*!< enable or disable exint */
|
||||
} exint_init_type;
|
||||
|
||||
/**
|
||||
* @brief type define exint register all
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
|
||||
/**
|
||||
* @brief exint inten register, offset:0x00
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t inten;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t intenx : 23;/* [22:0] */
|
||||
__IO uint32_t reserved1 : 9; /* [31:23] */
|
||||
} inten_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief exint evten register, offset:0x04
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t evten;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t evtenx : 23;/* [22:0] */
|
||||
__IO uint32_t reserved1 : 9; /* [31:23] */
|
||||
} evten_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief exint polcfg1 register, offset:0x08
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t polcfg1;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t rpx : 23;/* [22:0] */
|
||||
__IO uint32_t reserved1 : 9; /* [31:23] */
|
||||
} polcfg1_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief exint polcfg2 register, offset:0x0C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t polcfg2;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t fpx : 23;/* [22:0] */
|
||||
__IO uint32_t reserved1 : 9; /* [31:23] */
|
||||
} polcfg2_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief exint swtrg register, offset:0x10
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t swtrg;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t swtx : 23;/* [22:0] */
|
||||
__IO uint32_t reserved1 : 9; /* [31:23] */
|
||||
} swtrg_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief exint intsts register, offset:0x14
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t intsts;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t linex : 23;/* [22:0] */
|
||||
__IO uint32_t reserved1 : 9; /* [31:23] */
|
||||
} intsts_bit;
|
||||
};
|
||||
} exint_type;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#define EXINT ((exint_type *) EXINT_BASE)
|
||||
|
||||
/** @defgroup EXINT_exported_functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void exint_reset(void);
|
||||
void exint_default_para_init(exint_init_type *exint_struct);
|
||||
void exint_init(exint_init_type *exint_struct);
|
||||
void exint_flag_clear(uint32_t exint_line);
|
||||
flag_status exint_flag_get(uint32_t exint_line);
|
||||
void exint_software_interrupt_event_generate(uint32_t exint_line);
|
||||
void exint_interrupt_enable(uint32_t exint_line, confirm_state new_state);
|
||||
void exint_event_enable(uint32_t exint_line, confirm_state new_state);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,722 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file at32f435_437_flash.h
|
||||
* @brief at32f435_437 flash header file
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __AT32F435_437_FLASH_H
|
||||
#define __AT32F435_437_FLASH_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "at32f435_437.h"
|
||||
|
||||
/** @addtogroup AT32F435_437_periph_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASH
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_exported_constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief flash unlock keys
|
||||
*/
|
||||
#define FLASH_UNLOCK_KEY1 ((uint32_t)0x45670123) /*!< flash operation unlock order key1 */
|
||||
#define FLASH_UNLOCK_KEY2 ((uint32_t)0xCDEF89AB) /*!< flash operation unlock order key2 */
|
||||
#define FAP_RELIEVE_KEY ((uint16_t)0x00A5) /*!< flash fap relieve key val */
|
||||
#define SLIB_UNLOCK_KEY ((uint32_t)0xA35F6D24) /*!< flash slib operation unlock order key */
|
||||
|
||||
/**
|
||||
* @brief flash bank address
|
||||
*/
|
||||
#if defined (AT32F435CMU7) || defined (AT32F435CMT7) || defined (AT32F435RMT7) || \
|
||||
defined (AT32F435VMT7) || defined (AT32F435ZMT7) || defined (AT32F437RMT7) || \
|
||||
defined (AT32F437VMT7) || defined (AT32F437ZMT7)
|
||||
#define FLASH_BANK1_START_ADDR ((uint32_t)0x08000000) /*!< flash start address of bank1 */
|
||||
#define FLASH_BANK1_END_ADDR ((uint32_t)0x081FFFFF) /*!< flash end address of bank1 */
|
||||
#define FLASH_BANK2_START_ADDR ((uint32_t)0x08200000) /*!< flash start address of bank2 */
|
||||
#define FLASH_BANK2_END_ADDR ((uint32_t)0x083EFFFF) /*!< flash end address of bank2 */
|
||||
#else
|
||||
#define FLASH_BANK1_START_ADDR ((uint32_t)0x08000000) /*!< flash start address of bank1 */
|
||||
#define FLASH_BANK1_END_ADDR ((uint32_t)0x0807FFFF) /*!< flash end address of bank1 */
|
||||
#define FLASH_BANK2_START_ADDR ((uint32_t)0x08080000) /*!< flash start address of bank2 */
|
||||
#define FLASH_BANK2_END_ADDR ((uint32_t)0x080FFFFF) /*!< flash end address of bank2 */
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief flash flag
|
||||
*/
|
||||
#define FLASH_OBF_FLAG FLASH_BANK1_OBF_FLAG /*!< flash operate busy flag */
|
||||
#define FLASH_ODF_FLAG FLASH_BANK1_ODF_FLAG /*!< flash operate done flag */
|
||||
#define FLASH_PRGMERR_FLAG FLASH_BANK1_PRGMERR_FLAG /*!< flash program error flag */
|
||||
#define FLASH_EPPERR_FLAG FLASH_BANK1_EPPERR_FLAG /*!< flash erase/program protection error flag */
|
||||
#define FLASH_BANK1_OBF_FLAG ((uint32_t)0x00000001) /*!< flash bank1 operate busy flag */
|
||||
#define FLASH_BANK1_ODF_FLAG ((uint32_t)0x00000020) /*!< flash bank1 operate done flag */
|
||||
#define FLASH_BANK1_PRGMERR_FLAG ((uint32_t)0x00000004) /*!< flash bank1 program error flag */
|
||||
#define FLASH_BANK1_EPPERR_FLAG ((uint32_t)0x00000010) /*!< flash bank1 erase/program protection error flag */
|
||||
#define FLASH_BANK2_OBF_FLAG ((uint32_t)0x10000001) /*!< flash bank2 operate busy flag */
|
||||
#define FLASH_BANK2_ODF_FLAG ((uint32_t)0x10000020) /*!< flash bank2 operate done flag */
|
||||
#define FLASH_BANK2_PRGMERR_FLAG ((uint32_t)0x10000004) /*!< flash bank2 program error flag */
|
||||
#define FLASH_BANK2_EPPERR_FLAG ((uint32_t)0x10000010) /*!< flash bank2 erase/program protection error flag */
|
||||
#define FLASH_USDERR_FLAG ((uint32_t)0x40000001) /*!< flash user system data error flag */
|
||||
|
||||
/**
|
||||
* @brief flash interrupts
|
||||
*/
|
||||
#define FLASH_ERR_INT FLASH_BANK1_ERR_INT /*!< flash error interrupt */
|
||||
#define FLASH_ODF_INT FLASH_BANK1_ODF_INT /*!< flash operate done interrupt */
|
||||
#define FLASH_BANK1_ERR_INT ((uint32_t)0x00000001) /*!< flash bank1 error interrupt */
|
||||
#define FLASH_BANK1_ODF_INT ((uint32_t)0x00000002) /*!< flash bank1 operate done interrupt */
|
||||
#define FLASH_BANK2_ERR_INT ((uint32_t)0x00000004) /*!< flash bank2 error interrupt */
|
||||
#define FLASH_BANK2_ODF_INT ((uint32_t)0x00000008) /*!< flash bank2 operate done interrupt */
|
||||
|
||||
/**
|
||||
* @brief flash slib mask
|
||||
*/
|
||||
#define FLASH_SLIB_START_SECTOR ((uint32_t)0x0000FFFF) /*!< flash slib start sector */
|
||||
#define FLASH_SLIB_INST_START_SECTOR ((uint32_t)0x0000FFFF) /*!< flash slib i-bus area start sector */
|
||||
#define FLASH_SLIB_END_SECTOR ((uint32_t)0xFFFF0000) /*!< flash slib end sector */
|
||||
|
||||
/**
|
||||
* @brief user system data wdt_ato
|
||||
*/
|
||||
#define USD_WDT_ATO_DISABLE ((uint16_t)0x0001) /*!< wdt auto start disabled */
|
||||
#define USD_WDT_ATO_ENABLE ((uint16_t)0x0000) /*!< wdt auto start enabled */
|
||||
|
||||
/**
|
||||
* @brief user system data depslp_rst
|
||||
*/
|
||||
#define USD_DEPSLP_NO_RST ((uint16_t)0x0002) /*!< no reset generated when entering in deepsleep */
|
||||
#define USD_DEPSLP_RST ((uint16_t)0x0000) /*!< reset generated when entering in deepsleep */
|
||||
|
||||
/**
|
||||
* @brief user system data stdby_rst
|
||||
*/
|
||||
#define USD_STDBY_NO_RST ((uint16_t)0x0004) /*!< no reset generated when entering in standby */
|
||||
#define USD_STDBY_RST ((uint16_t)0x0000) /*!< reset generated when entering in standby */
|
||||
|
||||
/**
|
||||
* @brief user system data btopt
|
||||
*/
|
||||
#define FLASH_BOOT_FROM_BANK1 ((uint16_t)0x0008) /*!< boot from bank1 */
|
||||
#define FLASH_BOOT_FROM_BANK2 ((uint16_t)0x0000) /*!< boot from bank 2 or bank 1,depending on the activation of the bank */
|
||||
|
||||
/**
|
||||
* @brief user system data wdt_depslp
|
||||
*/
|
||||
#define USD_WDT_DEPSLP_CONTINUE ((uint16_t)0x0020) /*!< wdt continue count when entering in deepsleep */
|
||||
#define USD_WDT_DEPSLP_STOP ((uint16_t)0x0000) /*!< wdt stop count when entering in deepsleep */
|
||||
|
||||
/**
|
||||
* @brief user system data wdt_stdby
|
||||
*/
|
||||
#define USD_WDT_STDBY_CONTINUE ((uint16_t)0x0040) /*!< wdt continue count when entering in standby */
|
||||
#define USD_WDT_STDBY_STOP ((uint16_t)0x0000) /*!< wdt stop count when entering in standby */
|
||||
|
||||
/**
|
||||
* @brief flash timeout definition
|
||||
*/
|
||||
#define ERASE_TIMEOUT ((uint32_t)0x80000000) /*!< internal flash erase operation timeout */
|
||||
#define PROGRAMMING_TIMEOUT ((uint32_t)0x00100000) /*!< internal flash program operation timeout */
|
||||
#define OPERATION_TIMEOUT ((uint32_t)0x10000000) /*!< flash common operation timeout */
|
||||
|
||||
/**
|
||||
* @brief set the flash clock divider definition
|
||||
* @param div: the flash clock divider.
|
||||
* this parameter can be one of the following values:
|
||||
* - FLASH_CLOCK_DIV_2
|
||||
* - FLASH_CLOCK_DIV_3
|
||||
* - FLASH_CLOCK_DIV_4
|
||||
*/
|
||||
#define flash_clock_divider_set(div) (FLASH->divr_bit.fdiv = div)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_exported_types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief flash usd eopb0 type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
FLASH_EOPB0_SRAM_512K = 0x00, /*!< sram 512k, flash zw area 128k */
|
||||
FLASH_EOPB0_SRAM_448K = 0x01, /*!< sram 448k, flash zw area 192k */
|
||||
FLASH_EOPB0_SRAM_384K = 0x02, /*!< sram 384k, flash zw area 256k */
|
||||
FLASH_EOPB0_SRAM_320K = 0x03, /*!< sram 320k, flash zw area 320k */
|
||||
FLASH_EOPB0_SRAM_256K = 0x04, /*!< sram 256k, flash zw area 384k */
|
||||
FLASH_EOPB0_SRAM_192K = 0x05, /*!< sram 192k, flash zw area 448k */
|
||||
FLASH_EOPB0_SRAM_128K = 0x06 /*!< sram 128k, flash zw area 512k */
|
||||
} flash_usd_eopb0_type;
|
||||
|
||||
/**
|
||||
* @brief flash clock divider type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
FLASH_CLOCK_DIV_2 = 0x00, /*!< flash clock divide by 2 */
|
||||
FLASH_CLOCK_DIV_3 = 0x01, /*!< flash clock divide by 3 */
|
||||
FLASH_CLOCK_DIV_4 = 0x02 /*!< flash clock divide by 4 */
|
||||
} flash_clock_divider_type;
|
||||
|
||||
/**
|
||||
* @brief flash status type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
FLASH_OPERATE_BUSY = 0x00, /*!< flash status is operate busy */
|
||||
FLASH_PROGRAM_ERROR = 0x01, /*!< flash status is program error */
|
||||
FLASH_EPP_ERROR = 0x02, /*!< flash status is epp error */
|
||||
FLASH_OPERATE_DONE = 0x03, /*!< flash status is operate done */
|
||||
FLASH_OPERATE_TIMEOUT = 0x04 /*!< flash status is operate timeout */
|
||||
} flash_status_type;
|
||||
|
||||
/**
|
||||
* @brief type define flash register all
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
/**
|
||||
* @brief flash psr register, offset:0x00
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t psr;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t reserved1 : 12;/* [11:0] */
|
||||
__IO uint32_t nzw_bst : 1; /* [12] */
|
||||
__IO uint32_t nzw_bst_sts : 1; /* [13] */
|
||||
__IO uint32_t reserved2 : 18;/* [31:14] */
|
||||
} psr_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief flash unlock register, offset:0x04
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t unlock;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t ukval : 32;/* [31:0] */
|
||||
} unlock_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief flash usd unlock register, offset:0x08
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t usd_unlock;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t usd_ukval : 32;/* [31:0] */
|
||||
} usd_unlock_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief flash sts register, offset:0x0C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t sts;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t obf : 1; /* [0] */
|
||||
__IO uint32_t reserved1 : 1; /* [1] */
|
||||
__IO uint32_t prgmerr : 1; /* [2] */
|
||||
__IO uint32_t reserved2 : 1; /* [3] */
|
||||
__IO uint32_t epperr : 1; /* [4] */
|
||||
__IO uint32_t odf : 1; /* [5] */
|
||||
__IO uint32_t reserved3 : 26;/* [31:6] */
|
||||
} sts_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief flash ctrl register, offset:0x10
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ctrl;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t fprgm : 1; /* [0] */
|
||||
__IO uint32_t secers : 1; /* [1] */
|
||||
__IO uint32_t bankers : 1; /* [2] */
|
||||
__IO uint32_t blkers : 1; /* [3] */
|
||||
__IO uint32_t usdprgm : 1; /* [4] */
|
||||
__IO uint32_t usders : 1; /* [5] */
|
||||
__IO uint32_t erstr : 1; /* [6] */
|
||||
__IO uint32_t oplk : 1; /* [7] */
|
||||
__IO uint32_t reserved1 : 1; /* [8] */
|
||||
__IO uint32_t usdulks : 1; /* [9] */
|
||||
__IO uint32_t errie : 1; /* [10] */
|
||||
__IO uint32_t reserved2 : 1; /* [11] */
|
||||
__IO uint32_t odfie : 1; /* [12] */
|
||||
__IO uint32_t reserved3 : 19;/* [31:13] */
|
||||
} ctrl_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief flash addr register, offset:0x14
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t addr;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t fa : 32;/* [31:0] */
|
||||
} addr_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief flash reserved1 register, offset:0x18
|
||||
*/
|
||||
__IO uint32_t reserved1;
|
||||
|
||||
/**
|
||||
* @brief flash usd register, offset:0x1C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t usd;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t usderr : 1; /* [0] */
|
||||
__IO uint32_t fap : 1; /* [1] */
|
||||
__IO uint32_t wdt_ato_en : 1; /* [2] */
|
||||
__IO uint32_t depslp_rst : 1; /* [3] */
|
||||
__IO uint32_t stdby_rst : 1; /* [4] */
|
||||
__IO uint32_t btopt : 1; /* [5] */
|
||||
__IO uint32_t reserved1 : 1; /* [6] */
|
||||
__IO uint32_t wdt_depslp : 1; /* [7] */
|
||||
__IO uint32_t wdt_stdby : 1; /* [8] */
|
||||
__IO uint32_t reserved2 : 1; /* [9] */
|
||||
__IO uint32_t user_d0 : 8; /* [17:10] */
|
||||
__IO uint32_t user_d1 : 8; /* [25:18] */
|
||||
__IO uint32_t reserved3 : 6; /* [31:26] */
|
||||
} usd_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief flash epps0 register, offset:0x20
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t epps0;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t epps : 32;/* [31:0] */
|
||||
} epps0_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief flash reserved2 register, offset:0x28~0x24
|
||||
*/
|
||||
__IO uint32_t reserved2[2];
|
||||
|
||||
/**
|
||||
* @brief flash epps1 register, offset:0x2C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t epps1;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t epps : 32;/* [31:0] */
|
||||
} epps1_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief flash reserved3 register, offset:0x40~0x30
|
||||
*/
|
||||
__IO uint32_t reserved3[5];
|
||||
|
||||
/**
|
||||
* @brief flash unlock2 register, offset:0x44
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t unlock2;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t ukval : 32;/* [31:0] */
|
||||
} unlock2_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief flash reserved4 register, offset:0x48
|
||||
*/
|
||||
__IO uint32_t reserved4;
|
||||
|
||||
/**
|
||||
* @brief flash sts2 register, offset:0x4C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t sts2;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t obf : 1; /* [0] */
|
||||
__IO uint32_t reserved1 : 1; /* [1] */
|
||||
__IO uint32_t prgmerr : 1; /* [2] */
|
||||
__IO uint32_t reserved2 : 1; /* [3] */
|
||||
__IO uint32_t epperr : 1; /* [4] */
|
||||
__IO uint32_t odf : 1; /* [5] */
|
||||
__IO uint32_t reserved3 : 26;/* [31:6] */
|
||||
} sts2_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief flash ctrl2 register, offset:0x50
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ctrl2;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t fprgm : 1; /* [0] */
|
||||
__IO uint32_t secers : 1; /* [1] */
|
||||
__IO uint32_t bankers : 1; /* [2] */
|
||||
__IO uint32_t blkers : 1; /* [3] */
|
||||
__IO uint32_t reserved1 : 2; /* [5:4] */
|
||||
__IO uint32_t erstr : 1; /* [6] */
|
||||
__IO uint32_t oplk : 1; /* [7] */
|
||||
__IO uint32_t reserved2 : 2; /* [9:8] */
|
||||
__IO uint32_t errie : 1; /* [10] */
|
||||
__IO uint32_t reserved3 : 1; /* [11] */
|
||||
__IO uint32_t odfie : 1; /* [12] */
|
||||
__IO uint32_t reserved4 : 19;/* [31:13] */
|
||||
} ctrl2_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief flash addr2 register, offset:0x54
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t addr2;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t fa : 32;/* [31:0] */
|
||||
} addr2_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief flash contr register, offset:0x58
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t contr;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t reserved1 : 31;/* [30:0] */
|
||||
__IO uint32_t fcontr_en : 1; /* [31] */
|
||||
} contr_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief flash reserved5 register, offset:0x5C
|
||||
*/
|
||||
__IO uint32_t reserved5;
|
||||
|
||||
/**
|
||||
* @brief flash divr register, offset:0x60
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t divr;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t fdiv : 2; /* [1:0] */
|
||||
__IO uint32_t reserved1 : 2; /* [3:2] */
|
||||
__IO uint32_t fdiv_sts : 2; /* [5:4] */
|
||||
__IO uint32_t reserved2 : 26;/* [31:6] */
|
||||
} divr_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief flash reserved6 register, offset:0xC4~0x64
|
||||
*/
|
||||
__IO uint32_t reserved6[25];
|
||||
|
||||
/**
|
||||
* @brief flash slib_sts2 register, offset:0xC8
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t slib_sts2;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t slib_inst_ss : 16;/* [15:0] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:16] */
|
||||
} slib_sts2_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief flash slib_sts0 register, offset:0xCC
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t slib_sts0;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t reserved1 : 3; /* [2:0] */
|
||||
__IO uint32_t slib_enf : 1; /* [3] */
|
||||
__IO uint32_t reserved2 : 28;/* [31:4] */
|
||||
} slib_sts0_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief flash slib_sts1 register, offset:0xD0
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t slib_sts1;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t slib_ss : 16;/* [15:0] */
|
||||
__IO uint32_t slib_es : 16;/* [31:16] */
|
||||
} slib_sts1_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief flash slib_pwd_clr register, offset:0xD4
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t slib_pwd_clr;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t slib_pclr_val : 32;/* [31:0] */
|
||||
} slib_pwd_clr_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief flash slib_misc_sts register, offset:0xD8
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t slib_misc_sts;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t slib_pwd_err : 1; /* [0] */
|
||||
__IO uint32_t slib_pwd_ok : 1; /* [1] */
|
||||
__IO uint32_t slib_ulkf : 1; /* [2] */
|
||||
__IO uint32_t reserved1 : 13;/* [15:3] */
|
||||
__IO uint32_t slib_rcnt : 9; /* [24:16] */
|
||||
__IO uint32_t reserved2 : 7; /* [31:25] */
|
||||
} slib_misc_sts_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief flash slib_set_pwd register, offset:0xDC
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t slib_set_pwd;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t slib_pset_val : 32;/* [31:0] */
|
||||
} slib_set_pwd_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief flash slib_set_range0 register, offset:0xE0
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t slib_set_range0;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t slib_ss_set : 16;/* [15:0] */
|
||||
__IO uint32_t slib_es_set : 16;/* [31:16] */
|
||||
} slib_set_range0_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief flash slib_set_range1 register, offset:0xE4
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t slib_set_range1;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t slib_iss_set : 16;/* [15:0] */
|
||||
__IO uint32_t reserved1 : 15;/* [30:16] */
|
||||
__IO uint32_t set_slib_strt : 1; /* [31] */
|
||||
} slib_set_range1_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief flash reserved7 register, offset:0xEC~0xE8
|
||||
*/
|
||||
__IO uint32_t reserved7[2];
|
||||
|
||||
/**
|
||||
* @brief flash slib_unlock register, offset:0xF0
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t slib_unlock;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t slib_ukval : 32;/* [31:0] */
|
||||
} slib_unlock_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief flash crc_ctrl register, offset:0xF4
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t crc_ctrl;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t crc_ss : 12;/* [11:0] */
|
||||
__IO uint32_t crc_sn : 12;/* [23:12] */
|
||||
__IO uint32_t reserved1 : 7; /* [30:24] */
|
||||
__IO uint32_t crc_strt : 1; /* [31] */
|
||||
} crc_ctrl_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief flash crc_chkr register, offset:0xF8
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t crc_chkr;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t crc_chkr : 32;/* [31:0] */
|
||||
} crc_chkr_bit;
|
||||
};
|
||||
|
||||
} flash_type;
|
||||
|
||||
/**
|
||||
* @brief user system data
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint16_t fap;
|
||||
__IO uint16_t ssb;
|
||||
__IO uint16_t data0;
|
||||
__IO uint16_t data1;
|
||||
__IO uint16_t epp0;
|
||||
__IO uint16_t epp1;
|
||||
__IO uint16_t epp2;
|
||||
__IO uint16_t epp3;
|
||||
__IO uint16_t eopb0;
|
||||
__IO uint16_t reserved1;
|
||||
__IO uint16_t epp4;
|
||||
__IO uint16_t epp5;
|
||||
__IO uint16_t epp6;
|
||||
__IO uint16_t epp7;
|
||||
__IO uint16_t reserved2[12];
|
||||
__IO uint16_t qspikey[8];
|
||||
} usd_type;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#define FLASH ((flash_type *) FLASH_REG_BASE)
|
||||
#define USD ((usd_type *) USD_BASE)
|
||||
|
||||
/** @defgroup FLASH_exported_functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
flag_status flash_flag_get(uint32_t flash_flag);
|
||||
void flash_flag_clear(uint32_t flash_flag);
|
||||
flash_status_type flash_operation_status_get(void);
|
||||
flash_status_type flash_bank1_operation_status_get(void);
|
||||
flash_status_type flash_bank2_operation_status_get(void);
|
||||
flash_status_type flash_operation_wait_for(uint32_t time_out);
|
||||
flash_status_type flash_bank1_operation_wait_for(uint32_t time_out);
|
||||
flash_status_type flash_bank2_operation_wait_for(uint32_t time_out);
|
||||
void flash_unlock(void);
|
||||
void flash_bank1_unlock(void);
|
||||
void flash_bank2_unlock(void);
|
||||
void flash_lock(void);
|
||||
void flash_bank1_lock(void);
|
||||
void flash_bank2_lock(void);
|
||||
flash_status_type flash_sector_erase(uint32_t sector_address);
|
||||
flash_status_type flash_block_erase(uint32_t block_address);
|
||||
flash_status_type flash_internal_all_erase(void);
|
||||
flash_status_type flash_bank1_erase(void);
|
||||
flash_status_type flash_bank2_erase(void);
|
||||
flash_status_type flash_user_system_data_erase(void);
|
||||
flash_status_type flash_eopb0_config(flash_usd_eopb0_type data);
|
||||
flash_status_type flash_word_program(uint32_t address, uint32_t data);
|
||||
flash_status_type flash_halfword_program(uint32_t address, uint16_t data);
|
||||
flash_status_type flash_byte_program(uint32_t address, uint8_t data);
|
||||
flash_status_type flash_user_system_data_program(uint32_t address, uint8_t data);
|
||||
flash_status_type flash_epp_set(uint32_t *sector_bits);
|
||||
void flash_epp_status_get(uint32_t *sector_bits);
|
||||
flash_status_type flash_fap_enable(confirm_state new_state);
|
||||
flag_status flash_fap_status_get(void);
|
||||
flash_status_type flash_ssb_set(uint8_t usd_ssb);
|
||||
uint8_t flash_ssb_status_get(void);
|
||||
void flash_interrupt_enable(uint32_t flash_int, confirm_state new_state);
|
||||
flash_status_type flash_slib_enable(uint32_t pwd, uint16_t start_sector, uint16_t inst_start_sector, uint16_t end_sector);
|
||||
error_status flash_slib_disable(uint32_t pwd);
|
||||
uint32_t flash_slib_remaining_count_get(void);
|
||||
flag_status flash_slib_state_get(void);
|
||||
uint16_t flash_slib_start_sector_get(void);
|
||||
uint16_t flash_slib_inststart_sector_get(void);
|
||||
uint16_t flash_slib_end_sector_get(void);
|
||||
uint32_t flash_crc_calibrate(uint32_t start_sector, uint32_t sector_cnt);
|
||||
void flash_nzw_boost_enable(confirm_state new_state);
|
||||
void flash_continue_read_enable(confirm_state new_state);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,563 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file at32f435_437_gpio.h
|
||||
* @brief at32f435_437 gpio header file
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
/* define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __AT32F435_437_GPIO_H
|
||||
#define __AT32F435_437_GPIO_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* includes ------------------------------------------------------------------*/
|
||||
#include "at32f435_437.h"
|
||||
|
||||
/** @addtogroup AT32F435_437_periph_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup GPIO
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_pins_number_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define GPIO_PINS_0 0x0001 /*!< gpio pins number 0 */
|
||||
#define GPIO_PINS_1 0x0002 /*!< gpio pins number 1 */
|
||||
#define GPIO_PINS_2 0x0004 /*!< gpio pins number 2 */
|
||||
#define GPIO_PINS_3 0x0008 /*!< gpio pins number 3 */
|
||||
#define GPIO_PINS_4 0x0010 /*!< gpio pins number 4 */
|
||||
#define GPIO_PINS_5 0x0020 /*!< gpio pins number 5 */
|
||||
#define GPIO_PINS_6 0x0040 /*!< gpio pins number 6 */
|
||||
#define GPIO_PINS_7 0x0080 /*!< gpio pins number 7 */
|
||||
#define GPIO_PINS_8 0x0100 /*!< gpio pins number 8 */
|
||||
#define GPIO_PINS_9 0x0200 /*!< gpio pins number 9 */
|
||||
#define GPIO_PINS_10 0x0400 /*!< gpio pins number 10 */
|
||||
#define GPIO_PINS_11 0x0800 /*!< gpio pins number 11 */
|
||||
#define GPIO_PINS_12 0x1000 /*!< gpio pins number 12 */
|
||||
#define GPIO_PINS_13 0x2000 /*!< gpio pins number 13 */
|
||||
#define GPIO_PINS_14 0x4000 /*!< gpio pins number 14 */
|
||||
#define GPIO_PINS_15 0x8000 /*!< gpio pins number 15 */
|
||||
#define GPIO_PINS_ALL 0xFFFF /*!< gpio all pins */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_exported_types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief gpio mode select
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
GPIO_MODE_INPUT = 0x00, /*!< gpio input mode */
|
||||
GPIO_MODE_OUTPUT = 0x01, /*!< gpio output mode */
|
||||
GPIO_MODE_MUX = 0x02, /*!< gpio mux function mode */
|
||||
GPIO_MODE_ANALOG = 0x03 /*!< gpio analog in/out mode */
|
||||
} gpio_mode_type;
|
||||
|
||||
/**
|
||||
* @brief gpio output drive strength select
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
GPIO_DRIVE_STRENGTH_STRONGER = 0x01, /*!< stronger sourcing/sinking strength */
|
||||
GPIO_DRIVE_STRENGTH_MODERATE = 0x02 /*!< moderate sourcing/sinking strength */
|
||||
} gpio_drive_type;
|
||||
|
||||
/**
|
||||
* @brief gpio output type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
GPIO_OUTPUT_PUSH_PULL = 0x00, /*!< output push-pull */
|
||||
GPIO_OUTPUT_OPEN_DRAIN = 0x01 /*!< output open-drain */
|
||||
} gpio_output_type;
|
||||
|
||||
/**
|
||||
* @brief gpio pull type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
GPIO_PULL_NONE = 0x00, /*!< floating for input, no pull for output */
|
||||
GPIO_PULL_UP = 0x01, /*!< pull-up */
|
||||
GPIO_PULL_DOWN = 0x02 /*!< pull-down */
|
||||
} gpio_pull_type;
|
||||
|
||||
/**
|
||||
* @brief gpio init type
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t gpio_pins; /*!< pins number selection */
|
||||
gpio_output_type gpio_out_type; /*!< output type selection */
|
||||
gpio_pull_type gpio_pull; /*!< pull type selection */
|
||||
gpio_mode_type gpio_mode; /*!< mode selection */
|
||||
gpio_drive_type gpio_drive_strength; /*!< drive strength selection */
|
||||
} gpio_init_type;
|
||||
|
||||
/**
|
||||
* @brief gpio pins source type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
GPIO_PINS_SOURCE0 = 0x00, /*!< gpio pins source number 0 */
|
||||
GPIO_PINS_SOURCE1 = 0x01, /*!< gpio pins source number 1 */
|
||||
GPIO_PINS_SOURCE2 = 0x02, /*!< gpio pins source number 2 */
|
||||
GPIO_PINS_SOURCE3 = 0x03, /*!< gpio pins source number 3 */
|
||||
GPIO_PINS_SOURCE4 = 0x04, /*!< gpio pins source number 4 */
|
||||
GPIO_PINS_SOURCE5 = 0x05, /*!< gpio pins source number 5 */
|
||||
GPIO_PINS_SOURCE6 = 0x06, /*!< gpio pins source number 6 */
|
||||
GPIO_PINS_SOURCE7 = 0x07, /*!< gpio pins source number 7 */
|
||||
GPIO_PINS_SOURCE8 = 0x08, /*!< gpio pins source number 8 */
|
||||
GPIO_PINS_SOURCE9 = 0x09, /*!< gpio pins source number 9 */
|
||||
GPIO_PINS_SOURCE10 = 0x0A, /*!< gpio pins source number 10 */
|
||||
GPIO_PINS_SOURCE11 = 0x0B, /*!< gpio pins source number 11 */
|
||||
GPIO_PINS_SOURCE12 = 0x0C, /*!< gpio pins source number 12 */
|
||||
GPIO_PINS_SOURCE13 = 0x0D, /*!< gpio pins source number 13 */
|
||||
GPIO_PINS_SOURCE14 = 0x0E, /*!< gpio pins source number 14 */
|
||||
GPIO_PINS_SOURCE15 = 0x0F /*!< gpio pins source number 15 */
|
||||
} gpio_pins_source_type;
|
||||
|
||||
/**
|
||||
* @brief gpio muxing function selection type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
GPIO_MUX_0 = 0x00, /*!< gpio muxing function selection 0 */
|
||||
GPIO_MUX_1 = 0x01, /*!< gpio muxing function selection 1 */
|
||||
GPIO_MUX_2 = 0x02, /*!< gpio muxing function selection 2 */
|
||||
GPIO_MUX_3 = 0x03, /*!< gpio muxing function selection 3 */
|
||||
GPIO_MUX_4 = 0x04, /*!< gpio muxing function selection 4 */
|
||||
GPIO_MUX_5 = 0x05, /*!< gpio muxing function selection 5 */
|
||||
GPIO_MUX_6 = 0x06, /*!< gpio muxing function selection 6 */
|
||||
GPIO_MUX_7 = 0x07, /*!< gpio muxing function selection 7 */
|
||||
GPIO_MUX_8 = 0x08, /*!< gpio muxing function selection 8 */
|
||||
GPIO_MUX_9 = 0x09, /*!< gpio muxing function selection 9 */
|
||||
GPIO_MUX_10 = 0x0A, /*!< gpio muxing function selection 10 */
|
||||
GPIO_MUX_11 = 0x0B, /*!< gpio muxing function selection 11 */
|
||||
GPIO_MUX_12 = 0x0C, /*!< gpio muxing function selection 12 */
|
||||
GPIO_MUX_13 = 0x0D, /*!< gpio muxing function selection 13 */
|
||||
GPIO_MUX_14 = 0x0E, /*!< gpio muxing function selection 14 */
|
||||
GPIO_MUX_15 = 0x0F /*!< gpio muxing function selection 15 */
|
||||
} gpio_mux_sel_type;
|
||||
|
||||
/**
|
||||
* @brief type define gpio register all
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
/**
|
||||
* @brief gpio mode register, offset:0x00
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t cfgr;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t iomc0 : 2; /* [1:0] */
|
||||
__IO uint32_t iomc1 : 2; /* [3:2] */
|
||||
__IO uint32_t iomc2 : 2; /* [5:4] */
|
||||
__IO uint32_t iomc3 : 2; /* [7:6] */
|
||||
__IO uint32_t iomc4 : 2; /* [9:8] */
|
||||
__IO uint32_t iomc5 : 2; /* [11:10] */
|
||||
__IO uint32_t iomc6 : 2; /* [13:12] */
|
||||
__IO uint32_t iomc7 : 2; /* [15:14] */
|
||||
__IO uint32_t iomc8 : 2; /* [17:16] */
|
||||
__IO uint32_t iomc9 : 2; /* [19:18] */
|
||||
__IO uint32_t iomc10 : 2; /* [21:20] */
|
||||
__IO uint32_t iomc11 : 2; /* [23:22] */
|
||||
__IO uint32_t iomc12 : 2; /* [25:24] */
|
||||
__IO uint32_t iomc13 : 2; /* [27:26] */
|
||||
__IO uint32_t iomc14 : 2; /* [29:28] */
|
||||
__IO uint32_t iomc15 : 2; /* [31:30] */
|
||||
} cfgr_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief gpio output type register, offset:0x04
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t omode;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t om0 : 1; /* [0] */
|
||||
__IO uint32_t om1 : 1; /* [1] */
|
||||
__IO uint32_t om2 : 1; /* [2] */
|
||||
__IO uint32_t om3 : 1; /* [3] */
|
||||
__IO uint32_t om4 : 1; /* [4] */
|
||||
__IO uint32_t om5 : 1; /* [5] */
|
||||
__IO uint32_t om6 : 1; /* [6] */
|
||||
__IO uint32_t om7 : 1; /* [7] */
|
||||
__IO uint32_t om8 : 1; /* [8] */
|
||||
__IO uint32_t om9 : 1; /* [9] */
|
||||
__IO uint32_t om10 : 1; /* [10] */
|
||||
__IO uint32_t om11 : 1; /* [11] */
|
||||
__IO uint32_t om12 : 1; /* [12] */
|
||||
__IO uint32_t om13 : 1; /* [13] */
|
||||
__IO uint32_t om14 : 1; /* [14] */
|
||||
__IO uint32_t om15 : 1; /* [15] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:16] */
|
||||
} omode_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief gpio output driver register, offset:0x08
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t odrvr;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t odrv0 : 2; /* [1:0] */
|
||||
__IO uint32_t odrv1 : 2; /* [3:2] */
|
||||
__IO uint32_t odrv2 : 2; /* [5:4] */
|
||||
__IO uint32_t odrv3 : 2; /* [7:6] */
|
||||
__IO uint32_t odrv4 : 2; /* [9:8] */
|
||||
__IO uint32_t odrv5 : 2; /* [11:10] */
|
||||
__IO uint32_t odrv6 : 2; /* [13:12] */
|
||||
__IO uint32_t odrv7 : 2; /* [15:14] */
|
||||
__IO uint32_t odrv8 : 2; /* [17:16] */
|
||||
__IO uint32_t odrv9 : 2; /* [19:18] */
|
||||
__IO uint32_t odrv10 : 2; /* [21:20] */
|
||||
__IO uint32_t odrv11 : 2; /* [23:22] */
|
||||
__IO uint32_t odrv12 : 2; /* [25:24] */
|
||||
__IO uint32_t odrv13 : 2; /* [27:26] */
|
||||
__IO uint32_t odrv14 : 2; /* [29:28] */
|
||||
__IO uint32_t odrv15 : 2; /* [31:30] */
|
||||
} odrvr_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief gpio pull up/down register, offset:0x0C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t pull;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t pull0 : 2; /* [1:0] */
|
||||
__IO uint32_t pull1 : 2; /* [3:2] */
|
||||
__IO uint32_t pull2 : 2; /* [5:4] */
|
||||
__IO uint32_t pull3 : 2; /* [7:6] */
|
||||
__IO uint32_t pull4 : 2; /* [9:8] */
|
||||
__IO uint32_t pull5 : 2; /* [11:10] */
|
||||
__IO uint32_t pull6 : 2; /* [13:12] */
|
||||
__IO uint32_t pull7 : 2; /* [15:14] */
|
||||
__IO uint32_t pull8 : 2; /* [17:16] */
|
||||
__IO uint32_t pull9 : 2; /* [19:18] */
|
||||
__IO uint32_t pull10 : 2; /* [21:20] */
|
||||
__IO uint32_t pull11 : 2; /* [23:22] */
|
||||
__IO uint32_t pull12 : 2; /* [25:24] */
|
||||
__IO uint32_t pull13 : 2; /* [27:26] */
|
||||
__IO uint32_t pull14 : 2; /* [29:28] */
|
||||
__IO uint32_t pull15 : 2; /* [31:30] */
|
||||
} pull_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief gpio input data register, offset:0x10
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t idt;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t idt0 : 1; /* [0] */
|
||||
__IO uint32_t idt1 : 1; /* [1] */
|
||||
__IO uint32_t idt2 : 1; /* [2] */
|
||||
__IO uint32_t idt3 : 1; /* [3] */
|
||||
__IO uint32_t idt4 : 1; /* [4] */
|
||||
__IO uint32_t idt5 : 1; /* [5] */
|
||||
__IO uint32_t idt6 : 1; /* [6] */
|
||||
__IO uint32_t idt7 : 1; /* [7] */
|
||||
__IO uint32_t idt8 : 1; /* [8] */
|
||||
__IO uint32_t idt9 : 1; /* [9] */
|
||||
__IO uint32_t idt10 : 1; /* [10] */
|
||||
__IO uint32_t idt11 : 1; /* [11] */
|
||||
__IO uint32_t idt12 : 1; /* [12] */
|
||||
__IO uint32_t idt13 : 1; /* [13] */
|
||||
__IO uint32_t idt14 : 1; /* [14] */
|
||||
__IO uint32_t idt15 : 1; /* [15] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:16] */
|
||||
} idt_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief gpio output data register, offset:0x14
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t odt;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t odt0 : 1; /* [0] */
|
||||
__IO uint32_t odt1 : 1; /* [1] */
|
||||
__IO uint32_t odt2 : 1; /* [2] */
|
||||
__IO uint32_t odt3 : 1; /* [3] */
|
||||
__IO uint32_t odt4 : 1; /* [4] */
|
||||
__IO uint32_t odt5 : 1; /* [5] */
|
||||
__IO uint32_t odt6 : 1; /* [6] */
|
||||
__IO uint32_t odt7 : 1; /* [7] */
|
||||
__IO uint32_t odt8 : 1; /* [8] */
|
||||
__IO uint32_t odt9 : 1; /* [9] */
|
||||
__IO uint32_t odt10 : 1; /* [10] */
|
||||
__IO uint32_t odt11 : 1; /* [11] */
|
||||
__IO uint32_t odt12 : 1; /* [12] */
|
||||
__IO uint32_t odt13 : 1; /* [13] */
|
||||
__IO uint32_t odt14 : 1; /* [14] */
|
||||
__IO uint32_t odt15 : 1; /* [15] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:16] */
|
||||
} odt_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief gpio scr register, offset:0x18
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t scr;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t iosb0 : 1; /* [0] */
|
||||
__IO uint32_t iosb1 : 1; /* [1] */
|
||||
__IO uint32_t iosb2 : 1; /* [2] */
|
||||
__IO uint32_t iosb3 : 1; /* [3] */
|
||||
__IO uint32_t iosb4 : 1; /* [4] */
|
||||
__IO uint32_t iosb5 : 1; /* [5] */
|
||||
__IO uint32_t iosb6 : 1; /* [6] */
|
||||
__IO uint32_t iosb7 : 1; /* [7] */
|
||||
__IO uint32_t iosb8 : 1; /* [8] */
|
||||
__IO uint32_t iosb9 : 1; /* [9] */
|
||||
__IO uint32_t iosb10 : 1; /* [10] */
|
||||
__IO uint32_t iosb11 : 1; /* [11] */
|
||||
__IO uint32_t iosb12 : 1; /* [12] */
|
||||
__IO uint32_t iosb13 : 1; /* [13] */
|
||||
__IO uint32_t iosb14 : 1; /* [14] */
|
||||
__IO uint32_t iosb15 : 1; /* [15] */
|
||||
__IO uint32_t iocb0 : 1; /* [16] */
|
||||
__IO uint32_t iocb1 : 1; /* [17] */
|
||||
__IO uint32_t iocb2 : 1; /* [18] */
|
||||
__IO uint32_t iocb3 : 1; /* [19] */
|
||||
__IO uint32_t iocb4 : 1; /* [20] */
|
||||
__IO uint32_t iocb5 : 1; /* [21] */
|
||||
__IO uint32_t iocb6 : 1; /* [22] */
|
||||
__IO uint32_t iocb7 : 1; /* [23] */
|
||||
__IO uint32_t iocb8 : 1; /* [24] */
|
||||
__IO uint32_t iocb9 : 1; /* [25] */
|
||||
__IO uint32_t iocb10 : 1; /* [26] */
|
||||
__IO uint32_t iocb11 : 1; /* [27] */
|
||||
__IO uint32_t iocb12 : 1; /* [28] */
|
||||
__IO uint32_t iocb13 : 1; /* [29] */
|
||||
__IO uint32_t iocb14 : 1; /* [30] */
|
||||
__IO uint32_t iocb15 : 1; /* [31] */
|
||||
} scr_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief gpio wpen register, offset:0x1C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t wpr;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t wpen0 : 1; /* [0] */
|
||||
__IO uint32_t wpen1 : 1; /* [1] */
|
||||
__IO uint32_t wpen2 : 1; /* [2] */
|
||||
__IO uint32_t wpen3 : 1; /* [3] */
|
||||
__IO uint32_t wpen4 : 1; /* [4] */
|
||||
__IO uint32_t wpen5 : 1; /* [5] */
|
||||
__IO uint32_t wpen6 : 1; /* [6] */
|
||||
__IO uint32_t wpen7 : 1; /* [7] */
|
||||
__IO uint32_t wpen8 : 1; /* [8] */
|
||||
__IO uint32_t wpen9 : 1; /* [9] */
|
||||
__IO uint32_t wpen10 : 1; /* [10] */
|
||||
__IO uint32_t wpen11 : 1; /* [11] */
|
||||
__IO uint32_t wpen12 : 1; /* [12] */
|
||||
__IO uint32_t wpen13 : 1; /* [13] */
|
||||
__IO uint32_t wpen14 : 1; /* [14] */
|
||||
__IO uint32_t wpen15 : 1; /* [15] */
|
||||
__IO uint32_t wpseq : 1; /* [16] */
|
||||
__IO uint32_t reserved1 : 15;/* [31:17] */
|
||||
} wpr_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief gpio muxl register, offset:0x20
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t muxl;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t muxl0 : 4; /* [3:0] */
|
||||
__IO uint32_t muxl1 : 4; /* [7:4] */
|
||||
__IO uint32_t muxl2 : 4; /* [11:8] */
|
||||
__IO uint32_t muxl3 : 4; /* [15:12] */
|
||||
__IO uint32_t muxl4 : 4; /* [19:16] */
|
||||
__IO uint32_t muxl5 : 4; /* [23:20] */
|
||||
__IO uint32_t muxl6 : 4; /* [27:24] */
|
||||
__IO uint32_t muxl7 : 4; /* [31:28] */
|
||||
} muxl_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief gpio muxh register, offset:0x24
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t muxh;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t muxh8 : 4; /* [3:0] */
|
||||
__IO uint32_t muxh9 : 4; /* [7:4] */
|
||||
__IO uint32_t muxh10 : 4; /* [11:8] */
|
||||
__IO uint32_t muxh11 : 4; /* [15:12] */
|
||||
__IO uint32_t muxh12 : 4; /* [19:16] */
|
||||
__IO uint32_t muxh13 : 4; /* [23:20] */
|
||||
__IO uint32_t muxh14 : 4; /* [27:24] */
|
||||
__IO uint32_t muxh15 : 4; /* [31:28] */
|
||||
} muxh_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief gpio clr register, offset:0x28
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t clr;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t iocb0 : 1; /* [0] */
|
||||
__IO uint32_t iocb1 : 1; /* [1] */
|
||||
__IO uint32_t iocb2 : 1; /* [2] */
|
||||
__IO uint32_t iocb3 : 1; /* [3] */
|
||||
__IO uint32_t iocb4 : 1; /* [4] */
|
||||
__IO uint32_t iocb5 : 1; /* [5] */
|
||||
__IO uint32_t iocb6 : 1; /* [6] */
|
||||
__IO uint32_t iocb7 : 1; /* [7] */
|
||||
__IO uint32_t iocb8 : 1; /* [8] */
|
||||
__IO uint32_t iocb9 : 1; /* [9] */
|
||||
__IO uint32_t iocb10 : 1; /* [10] */
|
||||
__IO uint32_t iocb11 : 1; /* [11] */
|
||||
__IO uint32_t iocb12 : 1; /* [12] */
|
||||
__IO uint32_t iocb13 : 1; /* [13] */
|
||||
__IO uint32_t iocb14 : 1; /* [14] */
|
||||
__IO uint32_t iocb15 : 1; /* [15] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:16] */
|
||||
} clr_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief gpio reserved1 register, offset:0x2C~0x38
|
||||
*/
|
||||
__IO uint32_t reserved1[4];
|
||||
|
||||
/**
|
||||
* @brief gpio hdrv register, offset:0x3C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t hdrv;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t hdrv0 : 1; /* [0] */
|
||||
__IO uint32_t hdrv1 : 1; /* [1] */
|
||||
__IO uint32_t hdrv2 : 1; /* [2] */
|
||||
__IO uint32_t hdrv3 : 1; /* [3] */
|
||||
__IO uint32_t hdrv4 : 1; /* [4] */
|
||||
__IO uint32_t hdrv5 : 1; /* [5] */
|
||||
__IO uint32_t hdrv6 : 1; /* [6] */
|
||||
__IO uint32_t hdrv7 : 1; /* [7] */
|
||||
__IO uint32_t hdrv8 : 1; /* [8] */
|
||||
__IO uint32_t hdrv9 : 1; /* [9] */
|
||||
__IO uint32_t hdrv10 : 1; /* [10] */
|
||||
__IO uint32_t hdrv11 : 1; /* [11] */
|
||||
__IO uint32_t hdrv12 : 1; /* [12] */
|
||||
__IO uint32_t hdrv13 : 1; /* [13] */
|
||||
__IO uint32_t hdrv14 : 1; /* [14] */
|
||||
__IO uint32_t hdrv15 : 1; /* [15] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:16] */
|
||||
} hdrv_bit;
|
||||
};
|
||||
|
||||
} gpio_type;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#define GPIOA ((gpio_type *) GPIOA_BASE)
|
||||
#define GPIOB ((gpio_type *) GPIOB_BASE)
|
||||
#define GPIOC ((gpio_type *) GPIOC_BASE)
|
||||
#define GPIOD ((gpio_type *) GPIOD_BASE)
|
||||
#define GPIOE ((gpio_type *) GPIOE_BASE)
|
||||
#define GPIOF ((gpio_type *) GPIOF_BASE)
|
||||
#define GPIOG ((gpio_type *) GPIOG_BASE)
|
||||
#define GPIOH ((gpio_type *) GPIOH_BASE)
|
||||
|
||||
/** @defgroup GPIO_exported_functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void gpio_reset(gpio_type *gpio_x);
|
||||
void gpio_init(gpio_type *gpio_x, gpio_init_type *gpio_init_struct);
|
||||
void gpio_default_para_init(gpio_init_type *gpio_init_struct);
|
||||
flag_status gpio_input_data_bit_read(gpio_type *gpio_x, uint16_t pins);
|
||||
uint16_t gpio_input_data_read(gpio_type *gpio_x);
|
||||
flag_status gpio_output_data_bit_read(gpio_type *gpio_x, uint16_t pins);
|
||||
uint16_t gpio_output_data_read(gpio_type *gpio_x);
|
||||
void gpio_bits_set(gpio_type *gpio_x, uint16_t pins);
|
||||
void gpio_bits_reset(gpio_type *gpio_x, uint16_t pins);
|
||||
void gpio_bits_write(gpio_type *gpio_x, uint16_t pins, confirm_state bit_state);
|
||||
void gpio_port_write(gpio_type *gpio_x, uint16_t port_value);
|
||||
void gpio_pin_wp_config(gpio_type *gpio_x, uint16_t pins);
|
||||
void gpio_pins_huge_driven_config(gpio_type *gpio_x, uint16_t pins, confirm_state new_state);
|
||||
void gpio_pin_mux_config(gpio_type *gpio_x, gpio_pins_source_type gpio_pin_source, gpio_mux_sel_type gpio_mux);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,477 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file at32f435_437_i2c.h
|
||||
* @brief at32f435_437 i2c header file
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
/* define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __AT32F435_437_I2C_H
|
||||
#define __AT32F435_437_I2C_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* includes ------------------------------------------------------------------*/
|
||||
#include "at32f435_437.h"
|
||||
|
||||
/** @addtogroup AT32F435_437_periph_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief maximum number of single transfers
|
||||
*/
|
||||
#define MAX_TRANSFER_CNT 255 /*!< maximum number of single transfers */
|
||||
|
||||
/** @defgroup I2C_interrupts_definition
|
||||
* @brief i2c interrupt
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_TD_INT ((uint32_t)0x00000002) /*!< i2c transmit data interrupt */
|
||||
#define I2C_RD_INT ((uint32_t)0x00000004) /*!< i2c receive data interrupt */
|
||||
#define I2C_ADDR_INT ((uint32_t)0x00000008) /*!< i2c address match interrupt */
|
||||
#define I2C_ACKFIAL_INT ((uint32_t)0x00000010) /*!< i2c ack fail interrupt */
|
||||
#define I2C_STOP_INT ((uint32_t)0x00000020) /*!< i2c stop detect interrupt */
|
||||
#define I2C_TDC_INT ((uint32_t)0x00000040) /*!< i2c transmit data complete interrupt */
|
||||
#define I2C_ERR_INT ((uint32_t)0x00000080) /*!< i2c bus error interrupt */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_flags_definition
|
||||
* @brief i2c flag
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_TDBE_FLAG ((uint32_t)0x00000001) /*!< i2c transmit data buffer empty flag */
|
||||
#define I2C_TDIS_FLAG ((uint32_t)0x00000002) /*!< i2c send interrupt status */
|
||||
#define I2C_RDBF_FLAG ((uint32_t)0x00000004) /*!< i2c receive data buffer full flag */
|
||||
#define I2C_ADDRF_FLAG ((uint32_t)0x00000008) /*!< i2c 0~7 bit address match flag */
|
||||
#define I2C_ACKFAIL_FLAG ((uint32_t)0x00000010) /*!< i2c acknowledge failure flag */
|
||||
#define I2C_STOPF_FLAG ((uint32_t)0x00000020) /*!< i2c stop condition generation complete flag */
|
||||
#define I2C_TDC_FLAG ((uint32_t)0x00000040) /*!< i2c transmit data complete flag */
|
||||
#define I2C_TCRLD_FLAG ((uint32_t)0x00000080) /*!< i2c transmission is complete, waiting to load data */
|
||||
#define I2C_BUSERR_FLAG ((uint32_t)0x00000100) /*!< i2c bus error flag */
|
||||
#define I2C_ARLOST_FLAG ((uint32_t)0x00000200) /*!< i2c arbitration lost flag */
|
||||
#define I2C_OUF_FLAG ((uint32_t)0x00000400) /*!< i2c overflow or underflow flag */
|
||||
#define I2C_PECERR_FLAG ((uint32_t)0x00000800) /*!< i2c pec receive error flag */
|
||||
#define I2C_TMOUT_FLAG ((uint32_t)0x00001000) /*!< i2c smbus timeout flag */
|
||||
#define I2C_ALERTF_FLAG ((uint32_t)0x00002000) /*!< i2c smbus alert flag */
|
||||
#define I2C_BUSYF_FLAG ((uint32_t)0x00008000) /*!< i2c bus busy flag transmission mode */
|
||||
#define I2C_SDIR_FLAG ((uint32_t)0x00010000) /*!< i2c slave data transmit direction */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_exported_types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief i2c smbus mode set
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
I2C_SMBUS_MODE_DEVICE = 0x00, /*!< smbus device mode */
|
||||
I2C_SMBUS_MODE_HOST = 0x01 /*!< smbus host mode */
|
||||
} i2c_smbus_mode_type;
|
||||
|
||||
/**
|
||||
* @brief i2c address mode
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
I2C_ADDRESS_MODE_7BIT = 0x00, /*!< 7bit address mode */
|
||||
I2C_ADDRESS_MODE_10BIT = 0x01 /*!< 10bit address mode */
|
||||
} i2c_address_mode_type;
|
||||
|
||||
/**
|
||||
* @brief i2c transfer direction
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
I2C_DIR_TRANSMIT = 0x00, /*!< master request a write transfer */
|
||||
I2C_DIR_RECEIVE = 0x01 /*!< master request a read transfer */
|
||||
} i2c_transfer_dir_type;
|
||||
|
||||
/**
|
||||
* @brief i2c dma requests direction
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
I2C_DMA_REQUEST_TX = 0x00, /*!< dma transmit request */
|
||||
I2C_DMA_REQUEST_RX = 0x01 /*!< dma receive request */
|
||||
} i2c_dma_request_type;
|
||||
|
||||
/**
|
||||
* @brief i2c smbus alert pin set
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
I2C_SMBUS_ALERT_HIGH = 0x00, /*!< smbus alert pin set high */
|
||||
I2C_SMBUS_ALERT_LOW = 0x01 /*!< smbus alert pin set low */
|
||||
} i2c_smbus_alert_set_type;
|
||||
|
||||
/**
|
||||
* @brief i2c clock timeout detection mode
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
I2C_TIMEOUT_DETCET_LOW = 0x00, /*!< detect low level timeout */
|
||||
I2C_TIMEOUT_DETCET_HIGH = 0x01 /*!< detect high level timeout */
|
||||
} i2c_timeout_detcet_type;
|
||||
|
||||
/**
|
||||
* @brief i2c own address2 mask
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
I2C_ADDR2_NOMASK = 0x00, /*!< compare bit [7:1] */
|
||||
I2C_ADDR2_MASK01 = 0x01, /*!< only compare bit [7:2] */
|
||||
I2C_ADDR2_MASK02 = 0x02, /*!< only compare bit [7:2] */
|
||||
I2C_ADDR2_MASK03 = 0x03, /*!< only compare bit [7:3] */
|
||||
I2C_ADDR2_MASK04 = 0x04, /*!< only compare bit [7:4] */
|
||||
I2C_ADDR2_MASK05 = 0x05, /*!< only compare bit [7:5] */
|
||||
I2C_ADDR2_MASK06 = 0x06, /*!< only compare bit [7:6] */
|
||||
I2C_ADDR2_MASK07 = 0x07 /*!< only compare bit [7] */
|
||||
} i2c_addr2_mask_type;
|
||||
|
||||
/**
|
||||
* @brief i2c reload end mode
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
I2C_AUTO_STOP_MODE = 0x02000000, /*!< auto generate stop mode */
|
||||
I2C_SOFT_STOP_MODE = 0x00000000, /*!< soft generate stop mode */
|
||||
I2C_RELOAD_MODE = 0x01000000 /*!< reload mode */
|
||||
} i2c_reload_stop_mode_type;
|
||||
|
||||
/**
|
||||
* @brief i2c start mode
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
I2C_WITHOUT_START = 0x00000000, /*!< transfer data without start condition */
|
||||
I2C_GEN_START_READ = 0x00002400, /*!< read data and generate start */
|
||||
I2C_GEN_START_WRITE = 0x00002000 /*!< send data and generate start */
|
||||
} i2c_start_mode_type;
|
||||
|
||||
/**
|
||||
* @brief type define i2c register all
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
/**
|
||||
* @brief i2c ctrl1 register, offset:0x00
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ctrl1;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t i2cen : 1; /* [0] */
|
||||
__IO uint32_t tdien : 1; /* [1] */
|
||||
__IO uint32_t rdien : 1; /* [2] */
|
||||
__IO uint32_t addrien : 1; /* [3] */
|
||||
__IO uint32_t ackfailien : 1; /* [4] */
|
||||
__IO uint32_t stopien : 1; /* [5] */
|
||||
__IO uint32_t tdcien : 1; /* [6] */
|
||||
__IO uint32_t errien : 1; /* [7] */
|
||||
__IO uint32_t dflt : 4; /* [11:8] */
|
||||
__IO uint32_t reserved1 : 2; /* [13:12] */
|
||||
__IO uint32_t dmaten : 1; /* [14] */
|
||||
__IO uint32_t dmaren : 1; /* [15] */
|
||||
__IO uint32_t sctrl : 1; /* [16] */
|
||||
__IO uint32_t stretch : 1; /* [17] */
|
||||
__IO uint32_t reserved2 : 1; /* [18] */
|
||||
__IO uint32_t gcaen : 1; /* [19] */
|
||||
__IO uint32_t haddren : 1; /* [20] */
|
||||
__IO uint32_t devaddren : 1; /* [21] */
|
||||
__IO uint32_t smbalert : 1; /* [22] */
|
||||
__IO uint32_t pecen : 1; /* [23] */
|
||||
__IO uint32_t reserved3 : 8; /* [31:24] */
|
||||
} ctrl1_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief i2c ctrl2 register, offset:0x04
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ctrl2;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t saddr : 10;/* [9:0] */
|
||||
__IO uint32_t dir : 1; /* [10] */
|
||||
__IO uint32_t addr10 : 1; /* [11] */
|
||||
__IO uint32_t readh10 : 1; /* [12] */
|
||||
__IO uint32_t genstart : 1; /* [13] */
|
||||
__IO uint32_t genstop : 1; /* [14] */
|
||||
__IO uint32_t nacken : 1; /* [15] */
|
||||
__IO uint32_t cnt : 8; /* [23:16] */
|
||||
__IO uint32_t rlden : 1; /* [24] */
|
||||
__IO uint32_t astopen : 1; /* [25] */
|
||||
__IO uint32_t pecten : 1; /* [26] */
|
||||
__IO uint32_t reserved1 : 5; /* [31:27] */
|
||||
} ctrl2_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief i2c oaddr1 register, offset:0x08
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t oaddr1;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t addr1 : 10;/* [9:0] */
|
||||
__IO uint32_t addr1mode : 1; /* [10] */
|
||||
__IO uint32_t reserved1 : 4; /* [14:11] */
|
||||
__IO uint32_t addr1en : 1; /* [15] */
|
||||
__IO uint32_t reserved2 : 16;/* [31:16] */
|
||||
} oaddr1_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief i2c oaddr2 register, offset:0x0c
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t oaddr2;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t reserved1 : 1; /* [0] */
|
||||
__IO uint32_t addr2 : 7; /* [7:1] */
|
||||
__IO uint32_t addr2mask : 3; /* [10:8] */
|
||||
__IO uint32_t reserved2 : 4; /* [14:11] */
|
||||
__IO uint32_t addr2en : 1; /* [15] */
|
||||
__IO uint32_t reserved3 : 16;/* [31:16] */
|
||||
} oaddr2_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief i2c clkctrl register, offset:0x10
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t clkctrl;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t scll : 8; /* [7:0] */
|
||||
__IO uint32_t sclh : 8; /* [15:8] */
|
||||
__IO uint32_t sdad : 4; /* [19:16] */
|
||||
__IO uint32_t scld : 4; /* [23:20] */
|
||||
__IO uint32_t divh : 4; /* [27:24] */
|
||||
__IO uint32_t divl : 4; /* [31:28] */
|
||||
} clkctrl_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief i2c timeout register, offset:0x14
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t timeout;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t totime : 12;/* [11:0] */
|
||||
__IO uint32_t tomode : 1; /* [12] */
|
||||
__IO uint32_t reserved1 : 2; /* [14:13] */
|
||||
__IO uint32_t toen : 1; /* [15] */
|
||||
__IO uint32_t exttime : 12;/* [27:16] */
|
||||
__IO uint32_t reserved2 : 3; /* [30:28] */
|
||||
__IO uint32_t exten : 1; /* [31] */
|
||||
} timeout_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief i2c sts register, offset:0x18
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t sts;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t tdbe : 1; /* [0] */
|
||||
__IO uint32_t tdis : 1; /* [1] */
|
||||
__IO uint32_t rdbf : 1; /* [2] */
|
||||
__IO uint32_t addrf : 1; /* [3] */
|
||||
__IO uint32_t ackfail : 1; /* [4] */
|
||||
__IO uint32_t stopf : 1; /* [5] */
|
||||
__IO uint32_t tdc : 1; /* [6] */
|
||||
__IO uint32_t tcrld : 1; /* [7] */
|
||||
__IO uint32_t buserr : 1; /* [8] */
|
||||
__IO uint32_t arlost : 1; /* [9] */
|
||||
__IO uint32_t ouf : 1; /* [10] */
|
||||
__IO uint32_t pecerr : 1; /* [11] */
|
||||
__IO uint32_t tmout : 1; /* [12] */
|
||||
__IO uint32_t alertf : 1; /* [13] */
|
||||
__IO uint32_t reserved1 : 1; /* [14] */
|
||||
__IO uint32_t busyf : 1; /* [15] */
|
||||
__IO uint32_t sdir : 1; /* [16] */
|
||||
__IO uint32_t addr : 7; /* [23:17] */
|
||||
__IO uint32_t reserved2 : 8; /* [31:24] */
|
||||
} sts_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief i2c clr register, offset:0x1c
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t clr;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t reserved1 : 3; /* [2:0] */
|
||||
__IO uint32_t addrc : 1; /* [3] */
|
||||
__IO uint32_t ackfailc : 1; /* [4] */
|
||||
__IO uint32_t stopc : 1; /* [5] */
|
||||
__IO uint32_t reserved2 : 2; /* [6:7] */
|
||||
__IO uint32_t buserrc : 1; /* [8] */
|
||||
__IO uint32_t arlostc : 1; /* [9] */
|
||||
__IO uint32_t oufc : 1; /* [10] */
|
||||
__IO uint32_t pecerrc : 1; /* [11] */
|
||||
__IO uint32_t tmoutc : 1; /* [12] */
|
||||
__IO uint32_t alertc : 1; /* [13] */
|
||||
__IO uint32_t reserved3 : 18;/* [31:14] */
|
||||
} clr_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief i2c pec register, offset:0x20
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t pec;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t pecval : 8; /* [7:0] */
|
||||
__IO uint32_t reserved1 : 24;/* [31:8] */
|
||||
} pec_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief i2c rxdt register, offset:0x20
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t rxdt;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t dt : 8; /* [7:0] */
|
||||
__IO uint32_t reserved1 : 24;/* [31:8] */
|
||||
} rxdt_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief i2c txdt register, offset:0x20
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t txdt;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t dt : 8; /* [7:0] */
|
||||
__IO uint32_t reserved1 : 24;/* [31:8] */
|
||||
} txdt_bit;
|
||||
};
|
||||
|
||||
} i2c_type;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#define I2C1 ((i2c_type *) I2C1_BASE)
|
||||
#define I2C2 ((i2c_type *) I2C2_BASE)
|
||||
#define I2C3 ((i2c_type *) I2C3_BASE)
|
||||
|
||||
/** @defgroup I2C_exported_functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void i2c_reset(i2c_type *i2c_x);
|
||||
void i2c_init(i2c_type *i2c_x, uint8_t dfilters, uint32_t clk);
|
||||
void i2c_own_address1_set(i2c_type *i2c_x, i2c_address_mode_type mode, uint16_t address);
|
||||
void i2c_own_address2_set(i2c_type *i2c_x, uint8_t address, i2c_addr2_mask_type mask);
|
||||
void i2c_own_address2_enable(i2c_type *i2c_x, confirm_state new_state);
|
||||
void i2c_smbus_enable(i2c_type *i2c_x, i2c_smbus_mode_type mode, confirm_state new_state);
|
||||
void i2c_enable(i2c_type *i2c_x, confirm_state new_state);
|
||||
void i2c_clock_stretch_enable(i2c_type *i2c_x, confirm_state new_state);
|
||||
void i2c_ack_enable(i2c_type *i2c_x, confirm_state new_state);
|
||||
void i2c_addr10_mode_enable(i2c_type *i2c_x, confirm_state new_state);
|
||||
void i2c_transfer_addr_set(i2c_type *i2c_x, uint16_t address);
|
||||
uint16_t i2c_transfer_addr_get(i2c_type *i2c_x);
|
||||
void i2c_transfer_dir_set(i2c_type *i2c_x, i2c_transfer_dir_type i2c_direction);
|
||||
i2c_transfer_dir_type i2c_transfer_dir_get(i2c_type *i2c_x);
|
||||
uint8_t i2c_matched_addr_get(i2c_type *i2c_x);
|
||||
void i2c_auto_stop_enable(i2c_type *i2c_x, confirm_state new_state);
|
||||
void i2c_reload_enable(i2c_type *i2c_x, confirm_state new_state);
|
||||
void i2c_cnt_set(i2c_type *i2c_x, uint8_t cnt);
|
||||
void i2c_addr10_header_enable(i2c_type *i2c_x, confirm_state new_state);
|
||||
void i2c_general_call_enable(i2c_type *i2c_x, confirm_state new_state);
|
||||
void i2c_smbus_alert_set(i2c_type *i2c_x, i2c_smbus_alert_set_type level);
|
||||
void i2c_slave_data_ctrl_enable(i2c_type *i2c_x, confirm_state new_state);
|
||||
void i2c_pec_calculate_enable(i2c_type *i2c_x, confirm_state new_state);
|
||||
void i2c_pec_transmit_enable(i2c_type *i2c_x, confirm_state new_state);
|
||||
uint8_t i2c_pec_value_get(i2c_type *i2c_x);
|
||||
void i2c_timeout_set(i2c_type *i2c_x, uint16_t timeout);
|
||||
void i2c_timeout_detcet_set(i2c_type *i2c_x, i2c_timeout_detcet_type mode);
|
||||
void i2c_timeout_enable(i2c_type *i2c_x, confirm_state new_state);
|
||||
void i2c_ext_timeout_set(i2c_type *i2c_x, uint16_t timeout);
|
||||
void i2c_ext_timeout_enable(i2c_type *i2c_x, confirm_state new_state);
|
||||
void i2c_interrupt_enable(i2c_type *i2c_x, uint32_t source, confirm_state new_state);
|
||||
flag_status i2c_interrupt_get(i2c_type *i2c_x, uint16_t source);
|
||||
void i2c_dma_enable(i2c_type *i2c_x, i2c_dma_request_type dma_req, confirm_state new_state);
|
||||
void i2c_transmit_set(i2c_type *i2c_x, uint16_t address, uint8_t cnt, i2c_reload_stop_mode_type rld_stop, i2c_start_mode_type start);
|
||||
void i2c_start_generate(i2c_type *i2c_x);
|
||||
void i2c_stop_generate(i2c_type *i2c_x);
|
||||
void i2c_data_send(i2c_type *i2c_x, uint8_t data);
|
||||
uint8_t i2c_data_receive(i2c_type *i2c_x);
|
||||
flag_status i2c_flag_get(i2c_type *i2c_x, uint32_t flag);
|
||||
void i2c_flag_clear(i2c_type *i2c_x, uint32_t flag);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,123 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file at32f435_437_misc.h
|
||||
* @brief at32f435_437 misc header file
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
/* define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __AT32F435_437_MISC_H
|
||||
#define __AT32F435_437_MISC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* includes ------------------------------------------------------------------*/
|
||||
#include "at32f435_437.h"
|
||||
|
||||
/** @addtogroup AT32F435_437_periph_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup MISC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup MISC_vector_table_base_address
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define NVIC_VECTTAB_RAM ((uint32_t)0x20000000) /*!< nvic vector table based ram address */
|
||||
#define NVIC_VECTTAB_FLASH ((uint32_t)0x08000000) /*!< nvic vector table based flash address */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup MISC_exported_types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief nvic interrupt priority group
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NVIC_PRIORITY_GROUP_0 = ((uint32_t)0x7), /*!< 0 bits for preemption priority, 4 bits for subpriority */
|
||||
NVIC_PRIORITY_GROUP_1 = ((uint32_t)0x6), /*!< 1 bits for preemption priority, 3 bits for subpriority */
|
||||
NVIC_PRIORITY_GROUP_2 = ((uint32_t)0x5), /*!< 2 bits for preemption priority, 2 bits for subpriority */
|
||||
NVIC_PRIORITY_GROUP_3 = ((uint32_t)0x4), /*!< 3 bits for preemption priority, 1 bits for subpriority */
|
||||
NVIC_PRIORITY_GROUP_4 = ((uint32_t)0x3) /*!< 4 bits for preemption priority, 0 bits for subpriority */
|
||||
} nvic_priority_group_type;
|
||||
|
||||
/**
|
||||
* @brief nvic low power mode
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NVIC_LP_SLEEPONEXIT = 0x02, /*!< enable sleep-on-exit feature */
|
||||
NVIC_LP_SLEEPDEEP = 0x04, /*!< enable sleep-deep output signal when entering sleep mode */
|
||||
NVIC_LP_SEVONPEND = 0x10 /*!< send event on pending */
|
||||
} nvic_lowpower_mode_type;
|
||||
|
||||
/**
|
||||
* @brief systick clock source
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
SYSTICK_CLOCK_SOURCE_AHBCLK_DIV8 = ((uint32_t)0x00000000), /*!< systick clock source from core clock div8 */
|
||||
SYSTICK_CLOCK_SOURCE_AHBCLK_NODIV = ((uint32_t)0x00000004) /*!< systick clock source from core clock */
|
||||
} systick_clock_source_type;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup MISC_exported_functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void nvic_system_reset(void);
|
||||
void nvic_irq_enable(IRQn_Type irqn, uint32_t preempt_priority, uint32_t sub_priority);
|
||||
void nvic_irq_disable(IRQn_Type irqn);
|
||||
void nvic_priority_group_config(nvic_priority_group_type priority_group);
|
||||
void nvic_vector_table_set(uint32_t base, uint32_t offset);
|
||||
void nvic_lowpower_mode_config(nvic_lowpower_mode_type lp_mode, confirm_state new_state);
|
||||
void systick_clock_source_config(systick_clock_source_type source);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,230 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file at32f435_437_pwc.h
|
||||
* @brief at32f435_437 pwr header file
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __AT32F435_437_PWC_H
|
||||
#define __AT32F435_437_PWC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "at32f435_437.h"
|
||||
|
||||
/** @addtogroup AT32F435_437_periph_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup PWC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PWC_flags_definition
|
||||
* @brief pwc flag
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define PWC_WAKEUP_FLAG ((uint32_t)0x00000001) /*!< wakeup flag */
|
||||
#define PWC_STANDBY_FLAG ((uint32_t)0x00000002) /*!< standby flag */
|
||||
#define PWC_PVM_OUTPUT_FLAG ((uint32_t)0x00000004) /*!< pvm output flag */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief pwc wakeup pin num definition
|
||||
*/
|
||||
#define PWC_WAKEUP_PIN_1 ((uint32_t)0x00000100) /*!< standby wake-up pin1 */
|
||||
#define PWC_WAKEUP_PIN_2 ((uint32_t)0x00000200) /*!< standby wake-up pin2 */
|
||||
|
||||
/**
|
||||
* @brief select ldo output voltage.
|
||||
* @param val: set the ldo output voltage.
|
||||
* this parameter can be one of the following values:
|
||||
* - PWC_LDO_OUTPUT_1V3: system clock up to 288MHz.
|
||||
* - PWC_LDO_OUTPUT_1V2: system clock up to 240MHz.
|
||||
* - PWC_LDO_OUTPUT_1V1: system clock up to 192MHz.
|
||||
* - PWC_LDO_OUTPUT_1V0: system clock up to 144MHz.
|
||||
* @note useage limited.
|
||||
* PWC_LDO_OUTPUT_1V3: operation temperature range -40~85 degree, VDD must over 3.0V.
|
||||
*/
|
||||
#define pwc_ldo_output_voltage_set(val) (PWC->ldoov_bit.ldoovsel = val)
|
||||
|
||||
/** @defgroup PWC_exported_types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief pwc pvm voltage type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
PWC_PVM_VOLTAGE_2V3 = 0x01, /*!< power voltage monitoring boundary 2.3v */
|
||||
PWC_PVM_VOLTAGE_2V4 = 0x02, /*!< power voltage monitoring boundary 2.4v */
|
||||
PWC_PVM_VOLTAGE_2V5 = 0x03, /*!< power voltage monitoring boundary 2.5v */
|
||||
PWC_PVM_VOLTAGE_2V6 = 0x04, /*!< power voltage monitoring boundary 2.6v */
|
||||
PWC_PVM_VOLTAGE_2V7 = 0x05, /*!< power voltage monitoring boundary 2.7v */
|
||||
PWC_PVM_VOLTAGE_2V8 = 0x06, /*!< power voltage monitoring boundary 2.8v */
|
||||
PWC_PVM_VOLTAGE_2V9 = 0x07 /*!< power voltage monitoring boundary 2.9v */
|
||||
} pwc_pvm_voltage_type;
|
||||
|
||||
/**
|
||||
* @brief pwc ldo output voltage type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
PWC_LDO_OUTPUT_1V3 = 0x01, /*!< ldo output voltage is 1.3v */
|
||||
PWC_LDO_OUTPUT_1V2 = 0x00, /*!< ldo output voltage is 1.2v */
|
||||
PWC_LDO_OUTPUT_1V1 = 0x04, /*!< ldo output voltage is 1.1v */
|
||||
PWC_LDO_OUTPUT_1V0 = 0x05, /*!< ldo output voltage is 1.0v */
|
||||
} pwc_ldo_output_voltage_type;
|
||||
|
||||
/**
|
||||
* @brief pwc sleep enter type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
PWC_SLEEP_ENTER_WFI = 0x00, /*!< use wfi enter sleep mode */
|
||||
PWC_SLEEP_ENTER_WFE = 0x01 /*!< use wfe enter sleep mode */
|
||||
} pwc_sleep_enter_type ;
|
||||
|
||||
/**
|
||||
* @brief pwc deep sleep enter type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
PWC_DEEP_SLEEP_ENTER_WFI = 0x00, /*!< use wfi enter deepsleep mode */
|
||||
PWC_DEEP_SLEEP_ENTER_WFE = 0x01 /*!< use wfe enter deepsleep mode */
|
||||
} pwc_deep_sleep_enter_type ;
|
||||
|
||||
/**
|
||||
* @brief pwc regulator type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
PWC_REGULATOR_ON = 0x00, /*!< voltage regulator state on when deepsleep mode */
|
||||
PWC_REGULATOR_LOW_POWER = 0x01 /*!< voltage regulator state low power when deepsleep mode */
|
||||
} pwc_regulator_type ;
|
||||
|
||||
/**
|
||||
* @brief type define pwc register all
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
/**
|
||||
* @brief pwc ctrl register, offset:0x00
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ctrl;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t vrsel : 1; /* [0] */
|
||||
__IO uint32_t lpsel : 1; /* [1] */
|
||||
__IO uint32_t clswef : 1; /* [2] */
|
||||
__IO uint32_t clsef : 1; /* [3] */
|
||||
__IO uint32_t pvmen : 1; /* [4] */
|
||||
__IO uint32_t pvmsel : 3; /* [7:5] */
|
||||
__IO uint32_t bpwen : 1; /* [8] */
|
||||
__IO uint32_t reserved1 : 23;/* [31:9] */
|
||||
} ctrl_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief pwc ctrlsts register, offset:0x04
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ctrlsts;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t swef : 1; /* [0] */
|
||||
__IO uint32_t sef : 1; /* [1] */
|
||||
__IO uint32_t pvmof : 1; /* [2] */
|
||||
__IO uint32_t reserved1 : 5; /* [7:3] */
|
||||
__IO uint32_t swpen1 : 1; /* [8] */
|
||||
__IO uint32_t swpen2 : 1; /* [9] */
|
||||
__IO uint32_t reserved2 : 22;/* [31:10] */
|
||||
} ctrlsts_bit;
|
||||
};
|
||||
|
||||
__IO uint32_t reserved1[2];
|
||||
|
||||
/**
|
||||
* @brief pwc ldoov register, offset:0x10
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ldoov;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t ldoovsel : 3; /* [2:0] */
|
||||
__IO uint32_t reserved1 : 29;/* [31:3] */
|
||||
} ldoov_bit;
|
||||
};
|
||||
|
||||
} pwc_type;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#define PWC ((pwc_type *) PWC_BASE)
|
||||
|
||||
/** @defgroup PWC_exported_functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void pwc_reset(void);
|
||||
void pwc_battery_powered_domain_access(confirm_state new_state);
|
||||
void pwc_pvm_level_select(pwc_pvm_voltage_type pvm_voltage);
|
||||
void pwc_power_voltage_monitor_enable(confirm_state new_state);
|
||||
void pwc_wakeup_pin_enable(uint32_t pin_num, confirm_state new_state);
|
||||
void pwc_flag_clear(uint32_t pwc_flag);
|
||||
flag_status pwc_flag_get(uint32_t pwc_flag);
|
||||
void pwc_sleep_mode_enter(pwc_sleep_enter_type pwc_sleep_enter);
|
||||
void pwc_deep_sleep_mode_enter(pwc_deep_sleep_enter_type pwc_deep_sleep_enter);
|
||||
void pwc_voltage_regulate_set(pwc_regulator_type pwc_regulator);
|
||||
void pwc_standby_mode_enter(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,553 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file at32f435_437_qspi.h
|
||||
* @brief at32f435_437 qspi header file
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __AT32F435_437_QSPI_H
|
||||
#define __AT32F435_437_QSPI_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "at32f435_437.h"
|
||||
|
||||
/** @addtogroup AT32F435_437_periph_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup QSPI
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup QSPI_flags_definition
|
||||
* @brief qspi flag
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define QSPI_CMDSTS_FLAG ((uint32_t)0x00000001) /*!< qspi command complete status flag */
|
||||
#define QSPI_RXFIFORDY_FLAG ((uint32_t)0x00000002) /*!< qspi rxfifo ready status flag */
|
||||
#define QSPI_TXFIFORDY_FLAG ((uint32_t)0x00000004) /*!< qspi txfifo ready status flag */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup QSPI_exported_types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief qspi xip read access mode type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
QSPI_XIPR_SEL_MODED = 0x00, /*!< qspi xip read select mode d */
|
||||
QSPI_XIPR_SEL_MODET = 0x01 /*!< qspi xip read select mode t */
|
||||
} qspi_xip_read_sel_type;
|
||||
|
||||
/**
|
||||
* @brief qspi xip write access mode type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
QSPI_XIPW_SEL_MODED = 0x00, /*!< qspi xip write select mode d */
|
||||
QSPI_XIPW_SEL_MODET = 0x01 /*!< qspi xip write select mode t */
|
||||
} qspi_xip_write_sel_type;
|
||||
|
||||
/**
|
||||
* @brief qspi busy bit offset position in status register type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
QSPI_BUSY_OFFSET_0 = 0x00, /*!< qspi busy bit offset position 0 */
|
||||
QSPI_BUSY_OFFSET_1 = 0x01, /*!< qspi busy bit offset position 1 */
|
||||
QSPI_BUSY_OFFSET_2 = 0x02, /*!< qspi busy bit offset position 2 */
|
||||
QSPI_BUSY_OFFSET_3 = 0x03, /*!< qspi busy bit offset position 3 */
|
||||
QSPI_BUSY_OFFSET_4 = 0x04, /*!< qspi busy bit offset position 4 */
|
||||
QSPI_BUSY_OFFSET_5 = 0x05, /*!< qspi busy bit offset position 5 */
|
||||
QSPI_BUSY_OFFSET_6 = 0x06, /*!< qspi busy bit offset position 6 */
|
||||
QSPI_BUSY_OFFSET_7 = 0x07 /*!< qspi busy bit offset position 7 */
|
||||
} qspi_busy_pos_type;
|
||||
|
||||
/**
|
||||
* @brief qspi read status configure type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
QSPI_RSTSC_HW_AUTO = 0x00, /*!< qspi read status by hardware */
|
||||
QSPI_RSTSC_SW_ONCE = 0x01 /*!< qspi read status by software */
|
||||
} qspi_read_status_conf_type;
|
||||
|
||||
/**
|
||||
* @brief qspi operate mode type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
QSPI_OPERATE_MODE_111 = 0x00, /*!< qspi serial mode */
|
||||
QSPI_OPERATE_MODE_112 = 0x01, /*!< qspi dual mode */
|
||||
QSPI_OPERATE_MODE_114 = 0x02, /*!< qspi quad mode */
|
||||
QSPI_OPERATE_MODE_122 = 0x03, /*!< qspi dual i/o mode */
|
||||
QSPI_OPERATE_MODE_144 = 0x04, /*!< qspi quad i/o mode */
|
||||
QSPI_OPERATE_MODE_222 = 0x05, /*!< qspi instruction 2-bit mode */
|
||||
QSPI_OPERATE_MODE_444 = 0x06 /*!< qspi instruction 4-bit mode(qpi) */
|
||||
} qspi_operate_mode_type;
|
||||
|
||||
/**
|
||||
* @brief qspi clock division type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
QSPI_CLK_DIV_2 = 0x00, /*!< qspi clk divide by 2 */
|
||||
QSPI_CLK_DIV_4 = 0x01, /*!< qspi clk divide by 4 */
|
||||
QSPI_CLK_DIV_6 = 0x02, /*!< qspi clk divide by 6 */
|
||||
QSPI_CLK_DIV_8 = 0x03, /*!< qspi clk divide by 8 */
|
||||
QSPI_CLK_DIV_3 = 0x04, /*!< qspi clk divide by 3 */
|
||||
QSPI_CLK_DIV_5 = 0x05, /*!< qspi clk divide by 5 */
|
||||
QSPI_CLK_DIV_10 = 0x06, /*!< qspi clk divide by 10 */
|
||||
QSPI_CLK_DIV_12 = 0x07 /*!< qspi clk divide by 12 */
|
||||
} qspi_clk_div_type;
|
||||
|
||||
/**
|
||||
* @brief qspi command port address length type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
QSPI_CMD_ADRLEN_0_BYTE = 0x00, /*!< qspi no address */
|
||||
QSPI_CMD_ADRLEN_1_BYTE = 0x01, /*!< qspi address length 1 byte */
|
||||
QSPI_CMD_ADRLEN_2_BYTE = 0x02, /*!< qspi address length 2 byte */
|
||||
QSPI_CMD_ADRLEN_3_BYTE = 0x03, /*!< qspi address length 3 byte */
|
||||
QSPI_CMD_ADRLEN_4_BYTE = 0x04 /*!< qspi address length 4 byte */
|
||||
} qspi_cmd_adrlen_type;
|
||||
|
||||
/**
|
||||
* @brief qspi command port instruction length type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
QSPI_CMD_INSLEN_0_BYTE = 0x00, /*!< qspi no instruction code */
|
||||
QSPI_CMD_INSLEN_1_BYTE = 0x01, /*!< qspi instruction code 1 byte */
|
||||
QSPI_CMD_INSLEN_2_BYTE = 0x02 /*!< qspi instruction code 2 byte(repeat) */
|
||||
} qspi_cmd_inslen_type;
|
||||
|
||||
/**
|
||||
* @brief qspi xip r/w address length type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
QSPI_XIP_ADDRLEN_3_BYTE = 0x00, /*!< qspi xip address length 3 byte */
|
||||
QSPI_XIP_ADDRLEN_4_BYTE = 0x01 /*!< qspi xip address length 4 byte */
|
||||
} qspi_xip_addrlen_type;
|
||||
|
||||
/**
|
||||
* @brief qspi sckout mode type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
QSPI_SCK_MODE_0 = 0x00, /*!< qspi sck mode 0 */
|
||||
QSPI_SCK_MODE_3 = 0x01 /*!< qspi sck mode 3 */
|
||||
} qspi_clk_mode_type;
|
||||
|
||||
/**
|
||||
* @brief qspi dma tx/rx fifo threshold type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
QSPI_DMA_FIFO_THOD_WORD08 = 0x00, /*!< qspi dma fifo threshold 8 words */
|
||||
QSPI_DMA_FIFO_THOD_WORD16 = 0x01, /*!< qspi dma fifo threshold 16 words */
|
||||
QSPI_DMA_FIFO_THOD_WORD32 = 0x02 /*!< qspi dma fifo threshold 32 words */
|
||||
} qspi_dma_fifo_thod_type;
|
||||
|
||||
/**
|
||||
* @brief qspi cmd type
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
confirm_state pe_mode_enable; /*!< perfornance enhance mode enable */
|
||||
uint8_t pe_mode_operate_code; /*!< performance enhance mode operate code */
|
||||
uint8_t instruction_code; /*!< instruction code */
|
||||
qspi_cmd_inslen_type instruction_length; /*!< instruction code length */
|
||||
uint32_t address_code; /*!< address code */
|
||||
qspi_cmd_adrlen_type address_length; /*!< address legnth */
|
||||
uint32_t data_counter; /*!< read/write data counter */
|
||||
uint8_t second_dummy_cycle_num; /*!< number of second dummy state cycle 0~32 */
|
||||
qspi_operate_mode_type operation_mode; /*!< operation mode */
|
||||
qspi_read_status_conf_type read_status_config; /*!< config to read status */
|
||||
confirm_state read_status_enable; /*!< config to read status */
|
||||
confirm_state write_data_enable; /*!< enable to write data */
|
||||
} qspi_cmd_type;
|
||||
|
||||
/**
|
||||
* @brief qspi xip type
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t read_instruction_code; /*!< read instruction code */
|
||||
qspi_xip_addrlen_type read_address_length; /*!< read address legnth */
|
||||
qspi_operate_mode_type read_operation_mode; /*!< read operation mode */
|
||||
uint8_t read_second_dummy_cycle_num; /*!< read number of second dummy state cycle 0~32 */
|
||||
uint8_t write_instruction_code; /*!< write instruction code */
|
||||
qspi_xip_addrlen_type write_address_length; /*!< write address legnth */
|
||||
qspi_operate_mode_type write_operation_mode; /*!< write operation mode */
|
||||
uint8_t write_second_dummy_cycle_num; /*!< write number of second dummy state cycle 0~32 */
|
||||
qspi_xip_write_sel_type write_select_mode; /*!< write mode d or mode t selection */
|
||||
uint8_t write_time_counter; /*!< write count for mode t */
|
||||
uint8_t write_data_counter; /*!< write count for mode d */
|
||||
qspi_xip_read_sel_type read_select_mode; /*!< read mode d or mode t selection */
|
||||
uint8_t read_time_counter; /*!< read count for mode t */
|
||||
uint8_t read_data_counter; /*!< read count for mode d */
|
||||
} qspi_xip_type;
|
||||
|
||||
/**
|
||||
* @brief type define qspi register all
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
/**
|
||||
* @brief qspi cmd_w0 register, offset:0x00
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t cmd_w0;
|
||||
struct
|
||||
{
|
||||
|
||||
__IO uint32_t spiadr : 32;/* [31:0] */
|
||||
} cmd_w0_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief qspi cmd_w1 register, offset:0x04
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t cmd_w1;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t adrlen : 3; /* [2:0] */
|
||||
__IO uint32_t reserved1 : 13;/* [15:3] */
|
||||
__IO uint32_t dum2 : 8; /* [23:16] */
|
||||
__IO uint32_t inslen : 2; /* [25:24] */
|
||||
__IO uint32_t reserved2 : 2; /* [27:26] */
|
||||
__IO uint32_t pemen : 1; /* [28] */
|
||||
__IO uint32_t reserved3 : 3; /* [31:29] */
|
||||
} cmd_w1_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief qspi cmd_w2 register, offset:0x08
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t cmd_w2;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t dcnt : 32;/* [31:0] */
|
||||
} cmd_w2_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief qspi cmd_w3 register, offset:0x0C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t cmd_w3;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t reserved1 : 1; /* [0] */
|
||||
__IO uint32_t wen : 1; /* [1] */
|
||||
__IO uint32_t rstsen : 1; /* [2] */
|
||||
__IO uint32_t rstsc : 1; /* [3] */
|
||||
__IO uint32_t reserved2 : 1; /* [4] */
|
||||
__IO uint32_t opmode : 3; /* [7:5] */
|
||||
__IO uint32_t reserved3 : 8; /* [15:8] */
|
||||
__IO uint32_t pemopc : 8; /* [23:16] */
|
||||
__IO uint32_t insc : 8; /* [31:24] */
|
||||
} cmd_w3_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief qspi ctrl register, offset:0x10
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ctrl;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t clkdiv : 3; /* [2:0] */
|
||||
__IO uint32_t reserved1 : 1; /* [3] */
|
||||
__IO uint32_t sckmode : 1; /* [4] */
|
||||
__IO uint32_t reserved2 : 2; /* [6:5] */
|
||||
__IO uint32_t xipidle : 1; /* [7] */
|
||||
__IO uint32_t abort : 1; /* [8] */
|
||||
__IO uint32_t reserved3 : 7; /* [15:9] */
|
||||
__IO uint32_t busy : 3; /* [18:16] */
|
||||
__IO uint32_t xiprcmdf : 1; /* [19] */
|
||||
__IO uint32_t xipsel : 1; /* [20] */
|
||||
__IO uint32_t keyen : 1; /* [21] */
|
||||
__IO uint32_t reserved4 : 10;/* [31:22] */
|
||||
} ctrl_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief qspi actr register, offset:0x14
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t actr;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t csdly : 4; /* [3:0] */
|
||||
__IO uint32_t reserved1 : 28;/* [31:4] */
|
||||
} actr_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief qspi fifosts register, offset:0x18
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t fifosts;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t txfifordy : 1; /* [0] */
|
||||
__IO uint32_t rxfifordy : 1; /* [1] */
|
||||
__IO uint32_t reserved1 : 30;/* [31:2] */
|
||||
} fifosts_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief qspi reserved register, offset:0x1C
|
||||
*/
|
||||
__IO uint32_t reserved1;
|
||||
|
||||
/**
|
||||
* @brief qspi ctrl2 register, offset:0x20
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ctrl2;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t dmaen : 1; /* [0] */
|
||||
__IO uint32_t cmdie : 1; /* [1] */
|
||||
__IO uint32_t reserved1 : 6; /* [7:2] */
|
||||
__IO uint32_t txfifo_thod : 2; /* [9:8] */
|
||||
__IO uint32_t reserved2 : 2; /* [11:10] */
|
||||
__IO uint32_t rxfifo_thod : 2; /* [13:12] */
|
||||
__IO uint32_t reserved3 : 18;/* [31:14] */
|
||||
} ctrl2_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief qspi cmdsts register, offset:0x24
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t cmdsts;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t cmdsts : 1; /* [0] */
|
||||
__IO uint32_t reserved1 : 31;/* [31:1] */
|
||||
} cmdsts_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief qspi rsts register, offset:0x28
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t rsts;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t spists : 8; /* [7:0] */
|
||||
__IO uint32_t reserved1 : 24;/* [31:8] */
|
||||
} rsts_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief qspi fsize register, offset:0x2C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t fsize;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t spifsize : 32;/* [31:0] */
|
||||
} fsize_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief qspi xip_cmd_w0 register, offset:0x30
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t xip_cmd_w0;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t xipr_dum2 : 8; /* [7:0] */
|
||||
__IO uint32_t xipr_opmode : 3; /* [10:8] */
|
||||
__IO uint32_t xipr_adrlen : 1; /* [11] */
|
||||
__IO uint32_t xipr_insc : 8; /* [19:12] */
|
||||
__IO uint32_t reserved1 : 12;/* [31:20] */
|
||||
} xip_cmd_w0_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief qspi xip_cmd_w1 register, offset:0x34
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t xip_cmd_w1;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t xipr_dum2 : 8; /* [7:0] */
|
||||
__IO uint32_t xipr_opmode : 3; /* [10:8] */
|
||||
__IO uint32_t xipr_adrlen : 1; /* [11] */
|
||||
__IO uint32_t xipr_insc : 8; /* [19:12] */
|
||||
__IO uint32_t reserved1 : 12;/* [31:20] */
|
||||
} xip_cmd_w1_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief qspi xip_cmd_w2 register, offset:0x38
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t xip_cmd_w2;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t xipr_dcnt : 6; /* [5:0] */
|
||||
__IO uint32_t reserved1 : 2; /* [7:6] */
|
||||
__IO uint32_t xipr_tcnt : 7; /* [14:8] */
|
||||
__IO uint32_t xipr_sel : 1; /* [15] */
|
||||
__IO uint32_t xipw_dcnt : 6; /* [21:16] */
|
||||
__IO uint32_t reserved2 : 2; /* [23:22] */
|
||||
__IO uint32_t xipw_tcnt : 7; /* [30:24] */
|
||||
__IO uint32_t xipw_sel : 1; /* [31] */
|
||||
} xip_cmd_w2_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief qspi xip_cmd_w3 register, offset:0x3C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t xip_cmd_w3;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t bypassc : 1; /* [0] */
|
||||
__IO uint32_t reserved1 : 2; /* [2:1] */
|
||||
__IO uint32_t csts : 1; /* [3] */
|
||||
__IO uint32_t reserved2 : 28;/* [31:4] */
|
||||
} xip_cmd_w3_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief qspi reserved register, offset:0x40~4C
|
||||
*/
|
||||
__IO uint32_t reserved2[4];
|
||||
|
||||
/**
|
||||
* @brief qspi rev register, offset:0x50
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t rev;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t rev : 32;/* [31:0] */
|
||||
} rev_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief qspi reserved register, offset:0x54~FC
|
||||
*/
|
||||
__IO uint32_t reserved3[43];
|
||||
|
||||
/**
|
||||
* @brief qspi dt register, offset:0x100
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint8_t dt_u8;
|
||||
__IO uint16_t dt_u16;
|
||||
__IO uint32_t dt;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t dt : 32;/* [31:0] */
|
||||
} dt_bit;
|
||||
};
|
||||
|
||||
} qspi_type;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#define QSPI1 ((qspi_type*)QSPI1_REG_BASE)
|
||||
#define QSPI2 ((qspi_type*)QSPI2_REG_BASE)
|
||||
|
||||
/** @defgroup QSPI_exported_functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void qspi_encryption_enable(qspi_type* qspi_x, confirm_state new_state);
|
||||
void qspi_sck_mode_set(qspi_type* qspi_x, qspi_clk_mode_type new_mode);
|
||||
void qspi_clk_division_set(qspi_type* qspi_x, qspi_clk_div_type new_clkdiv);
|
||||
void qspi_xip_cache_bypass_set(qspi_type* qspi_x, confirm_state new_state);
|
||||
void qspi_interrupt_enable(qspi_type* qspi_x, confirm_state new_state);
|
||||
flag_status qspi_flag_get(qspi_type* qspi_x, uint32_t flag);
|
||||
void qspi_flag_clear(qspi_type* qspi_x, uint32_t flag);
|
||||
void qspi_dma_rx_threshold_set(qspi_type* qspi_x, qspi_dma_fifo_thod_type new_threshold);
|
||||
void qspi_dma_tx_threshold_set(qspi_type* qspi_x, qspi_dma_fifo_thod_type new_threshold);
|
||||
void qspi_dma_enable(qspi_type* qspi_x, confirm_state new_state);
|
||||
void qspi_busy_config(qspi_type* qspi_x, qspi_busy_pos_type busy_pos);
|
||||
void qspi_xip_enable(qspi_type* qspi_x, confirm_state new_state);
|
||||
void qspi_cmd_operation_kick(qspi_type* qspi_x, qspi_cmd_type* qspi_cmd_struct);
|
||||
void qspi_xip_init(qspi_type* qspi_x, qspi_xip_type* xip_init_struct);
|
||||
uint8_t qspi_byte_read(qspi_type* qspi_x);
|
||||
uint16_t qspi_half_word_read(qspi_type* qspi_x);
|
||||
uint32_t qspi_word_read(qspi_type* qspi_x);
|
||||
void qspi_word_write(qspi_type* qspi_x, uint32_t value);
|
||||
void qspi_half_word_write(qspi_type* qspi_x, uint16_t value);
|
||||
void qspi_byte_write(qspi_type* qspi_x, uint8_t value);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,87 @@
|
||||
/*
|
||||
* rcc_at32f43x_periph.h
|
||||
*
|
||||
* Created on: 2022年3月19日
|
||||
* Author: emsr
|
||||
* 仿照hal 库，为at32 各外设直接定义对应的使能、重置位
|
||||
* offset= log2(mask)
|
||||
*/
|
||||
|
||||
#ifndef MAIN_DRIVERS_RCC_AT32F43X_PERIPH_H_
|
||||
#define MAIN_DRIVERS_RCC_AT32F43X_PERIPH_H_
|
||||
|
||||
|
||||
/******************** Bit definition for AT32F437 CRM PERIPH MASK ***************/
|
||||
/* AHB offset 0x30 */
|
||||
#define CRM_AHB1_GPIOA_PER_MASK ((uint32_t)0x00000001) /*!< gpiob periph clock */
|
||||
#define CRM_AHB1_GPIOB_PER_MASK ((uint32_t)0x00000002) /*!< gpiob periph clock */
|
||||
#define CRM_AHB1_GPIOC_PER_MASK ((uint32_t)0x00000004) /*!< gpioc periph clock */
|
||||
#define CRM_AHB1_GPIOD_PER_MASK ((uint32_t)0x00000008) /*!< gpiod periph clock */
|
||||
#define CRM_AHB1_GPIOE_PER_MASK ((uint32_t)0x00000010) /*!< gpioe periph clock */
|
||||
#define CRM_AHB1_GPIOF_PER_MASK ((uint32_t)0x00000020) /*!< gpiof periph clock */
|
||||
#define CRM_AHB1_GPIOG_PER_MASK ((uint32_t)0x00000040) /*!< gpiog periph clock */
|
||||
#define CRM_AHB1_GPIOH_PER_MASK ((uint32_t)0x00000080) /*!< gpioh periph clock */
|
||||
#define CRM_AHB1_CRC_PER_MASK ((uint32_t)0x00001000) /*!< crc periph clock */
|
||||
#define CRM_AHB1_EDMA_PER_MASK ((uint32_t)0x00200000) /*!< edma periph clock */
|
||||
#define CRM_AHB1_DMA1_PER_MASK ((uint32_t)0x00400000) /*!< dma1 periph clock */
|
||||
#define CRM_AHB1_DMA2_PER_MASK ((uint32_t)0x01000000) /*!< dma2 periph clock */
|
||||
#define CRM_AHB1_EMAC_PER_MASK ((uint32_t)0x02000000) /*!< emac periph clock */
|
||||
#define CRM_AHB1_EMACTX_PER_MASK ((uint32_t)0x04000000) /*!< emac tx periph clock */
|
||||
#define CRM_AHB1_EMACRX_PER_MASK ((uint32_t)0x08000000) /*!< emac rx periph clock */
|
||||
#define CRM_AHB1_EMACPTP_PER_MASK ((uint32_t)0x10000000) /*!< emac ptp periph clock */
|
||||
#define CRM_AHB1_OTGFS2_PER_MASK ((uint32_t)0x20000000) /*!< otgfs2 periph clock */
|
||||
/* ahb periph2 offset 0x34*/
|
||||
#define CRM_AHB2_DVP_PER_MASK ((uint32_t)0x00000001) /*!< dvp periph clock */
|
||||
#define CRM_AHB2_OTGFS1_PER_MASK ((uint32_t)0x00000080) /*!< otgfs1 periph clock */
|
||||
#define CRM_AHB2_SDIO1_PER_MASK ((uint32_t)0x00008000) /*!< sdio1 periph clock */
|
||||
/* ahb periph3 offset 0x38 */
|
||||
#define CRM_AHB3_XMC_PER_MASK ((uint32_t)0x00000001) /*!< xmc periph clock */
|
||||
#define CRM_AHB3_QSPI1_PER_MASK ((uint32_t)0x00000002) /*!< qspi1 periph clock */
|
||||
#define CRM_AHB3_QSPI2_PER_MASK ((uint32_t)0x00004000) /*!< qspi2 periph clock */
|
||||
#define CRM_AHB3_SDIO2_PER_MASK ((uint32_t)0x00008000) /*!< sdio2 periph clock */
|
||||
/* apb1 periph offset 0x40 */
|
||||
#define CRM_APB1_TMR2_PER_MASK ((uint32_t)0x00000001) /*!< tmr2 periph clock */
|
||||
#define CRM_APB1_TMR3_PER_MASK ((uint32_t)0x00000002) /*!< tmr3 periph clock */
|
||||
#define CRM_APB1_TMR4_PER_MASK ((uint32_t)0x00000004) /*!< tmr4 periph clock */
|
||||
#define CRM_APB1_TMR5_PER_MASK ((uint32_t)0x00000008) /*!< tmr5 periph clock */
|
||||
#define CRM_APB1_TMR6_PER_MASK ((uint32_t)0x00000010) /*!< tmr6 periph clock */
|
||||
#define CRM_APB1_TMR7_PER_MASK ((uint32_t)0x00000020) /*!< tmr7 periph clock */
|
||||
#define CRM_APB1_TMR12_PER_MASK ((uint32_t)0x00000040) /*!< tmr12 periph clock */
|
||||
#define CRM_APB1_TMR13_PER_MASK ((uint32_t)0x00000080) /*!< tmr13 periph clock */
|
||||
#define CRM_APB1_TMR14_PER_MASK ((uint32_t)0x00000100) /*!< tmr14 periph clock */
|
||||
#define CRM_APB1_WWDT_PER_MASK ((uint32_t)0x00000800) /*!< wwdt periph clock */
|
||||
#define CRM_APB1_SPI2_PER_MASK ((uint32_t)0x00004000) /*!< spi2 periph clock */
|
||||
#define CRM_APB1_SPI3_PER_MASK ((uint32_t)0x00008000) /*!< spi3 periph clock */
|
||||
#define CRM_APB1_USART2_PER_MASK ((uint32_t)0x00020000) /*!< usart2 periph clock */
|
||||
#define CRM_APB1_USART3_PER_MASK ((uint32_t)0x00040000) /*!< usart3 periph clock */
|
||||
#define CRM_APB1_UART4_PER_MASK ((uint32_t)0x00080000) /*!< uart4 periph clock */
|
||||
#define CRM_APB1_UART5_PER_MASK ((uint32_t)0x00100000) /*!< uart5 periph clock */
|
||||
#define CRM_APB1_I2C1_PER_MASK ((uint32_t)0x00200000) /*!< i2c1 periph clock */
|
||||
#define CRM_APB1_I2C2_PER_MASK ((uint32_t)0x00400000) /*!< i2c2 periph clock */
|
||||
#define CRM_APB1_I2C3_PER_MASK ((uint32_t)0x00800000) /*!< i2c3 periph clock */
|
||||
#define CRM_APB1_CAN1_PER_MASK ((uint32_t)0x02000000) /*!< can1 periph clock */
|
||||
#define CRM_APB1_CAN2_PER_MASK ((uint32_t)0x04000000) /*!< can2 periph clock */
|
||||
#define CRM_APB1_PWC_PER_MASK ((uint32_t)0x10000000) /*!< pwc periph clock */
|
||||
#define CRM_APB1_DAC_PER_MASK ((uint32_t)0x20000000) /*!< dac periph clock */
|
||||
#define CRM_APB1_UART7_PER_MASK ((uint32_t)0x40000000) /*!< uart7 periph clock */
|
||||
#define CRM_APB1_UART8_PER_MASK ((uint32_t)0x80000000) /*!< uart8 periph clock */
|
||||
/* apb2 periph offset 0x44 */
|
||||
#define CRM_APB2_TMR1_PER_MASK ((uint32_t)0x00000001) /*!< tmr1 periph clock */
|
||||
#define CRM_APB2_TMR8_PER_MASK ((uint32_t)0x00000002) /*!< tmr8 periph clock */
|
||||
#define CRM_APB2_USART1_PER_MASK ((uint32_t)0x00000010) /*!< usart1 periph clock */
|
||||
#define CRM_APB2_USART6_PER_MASK ((uint32_t)0x00000020) /*!< usart6 periph clock */
|
||||
#define CRM_APB2_ADC1_PER_MASK ((uint32_t)0x00000100) /*!< adc1 periph clock */
|
||||
#define CRM_APB2_ADC2_PER_MASK ((uint32_t)0x00000200) /*!< adc2 periph clock */
|
||||
#define CRM_APB2_ADC3_PER_MASK ((uint32_t)0x00000400) /*!< adc3 periph clock */
|
||||
#define CRM_APB2_SPI1_PER_MASK ((uint32_t)0x00001000) /*!< spi1 periph clock */
|
||||
#define CRM_APB2_SPI4_PER_MASK ((uint32_t)0x00002000) /*!< spi4 periph clock */
|
||||
#define CRM_APB2_SCFG_PER_MASK ((uint32_t)0x00004000) /*!< scfg periph clock */
|
||||
#define CRM_APB2_TMR9_PER_MASK ((uint32_t)0x00010000) /*!< tmr9 periph clock */
|
||||
#define CRM_APB2_TMR10_PER_MASK ((uint32_t)0x00020000) /*!< tmr10 periph clock */
|
||||
#define CRM_APB2_TMR11_PER_MASK ((uint32_t)0x00040000) /*!< tmr11 periph clock */
|
||||
#define CRM_APB2_TMR20_PER_MASK ((uint32_t)0x00100000) /*!< tmr20 periph clock */
|
||||
#define CRM_APB2_ACC_PER_MASK ((uint32_t)0x20000000) /*!< acc periph clock */
|
||||
|
||||
|
||||
|
||||
#endif /* MAIN_DRIVERS_RCC_AT32F43X_PERIPH_H_ */
|
||||
@@ -0,0 +1,321 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file at32f435_437_scfg.h
|
||||
* @brief at32f435_437 system config header file
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
/* define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __AT32F435_437_SCFG_H
|
||||
#define __AT32F435_437_SCFG_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "at32f435_437.h"
|
||||
|
||||
/** @addtogroup AT32F435_437_periph_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup SCFG
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SCFG_REG(value) PERIPH_REG(SCFG_BASE, value)
|
||||
#define SCFG_REG_BIT(value) PERIPH_REG_BIT(value)
|
||||
|
||||
/** @defgroup SCFG_exported_types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief scfg xmc addres mapping swap type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
SCFG_XMC_SWAP_NONE = 0x00, /* no swap */
|
||||
SCFG_XMC_SWAP_MODE1 = 0x01, /* sdram 0x60000000 and 0x70000000, nor psram sram nand2 0xC00000000 and 0xD0000000 */
|
||||
SCFG_XMC_SWAP_MODE2 = 0x02, /* qspi2 0x80000000, nand3 0xB0000000 */
|
||||
SCFG_XMC_SWAP_MODE3 = 0x03 /* sdram 0x60000000 and 0x70000000, nor psram sram nand2 0xC00000000 and 0xD0000000, qspi2 0x80000000, nand3 0xB0000000 */
|
||||
} scfg_xmc_swap_type;
|
||||
|
||||
/**
|
||||
* @brief scfg infrared modulation signal source selecting type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
SCFG_IR_SOURCE_TMR10 = 0x00, /* infrared signal source select tmr10 */
|
||||
SCFG_IR_SOURCE_USART1 = 0x01, /* infrared signal source select usart1 */
|
||||
SCFG_IR_SOURCE_USART2 = 0x02 /* infrared signal source select usart2 */
|
||||
} scfg_ir_source_type;
|
||||
|
||||
/**
|
||||
* @brief scfg infrared output polarity selecting type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
SCFG_IR_POLARITY_NO_AFFECTE = 0x00, /* infrared output polarity no affecte */
|
||||
SCFG_IR_POLARITY_REVERSE = 0x01 /* infrared output polarity reverse */
|
||||
} scfg_ir_polarity_type;
|
||||
|
||||
/**
|
||||
* @brief scfg memory address mapping selecting type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
SCFG_MEM_MAP_MAIN_MEMORY = 0x00, /* 0x00000000 address mapping from main memory */
|
||||
SCFG_MEM_MAP_BOOT_MEMORY = 0x01, /* 0x00000000 address mapping from boot memory */
|
||||
SCFG_MEM_MAP_XMC_BANK1 = 0x02, /* 0x00000000 address mapping from xmc bank1 */
|
||||
SCFG_MEM_MAP_INTERNAL_SRAM = 0x03, /* 0x00000000 address mapping from internal sram */
|
||||
SCFG_MEM_MAP_XMC_SDRAM_BANK1 = 0x04 /* 0x00000000 address mapping from xmc sdram bank1 */
|
||||
} scfg_mem_map_type;
|
||||
|
||||
/**
|
||||
* @brief scfg pin source type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
SCFG_PINS_SOURCE0 = 0x00,
|
||||
SCFG_PINS_SOURCE1 = 0x01,
|
||||
SCFG_PINS_SOURCE2 = 0x02,
|
||||
SCFG_PINS_SOURCE3 = 0x03,
|
||||
SCFG_PINS_SOURCE4 = 0x04,
|
||||
SCFG_PINS_SOURCE5 = 0x05,
|
||||
SCFG_PINS_SOURCE6 = 0x06,
|
||||
SCFG_PINS_SOURCE7 = 0x07,
|
||||
SCFG_PINS_SOURCE8 = 0x08,
|
||||
SCFG_PINS_SOURCE9 = 0x09,
|
||||
SCFG_PINS_SOURCE10 = 0x0A,
|
||||
SCFG_PINS_SOURCE11 = 0x0B,
|
||||
SCFG_PINS_SOURCE12 = 0x0C,
|
||||
SCFG_PINS_SOURCE13 = 0x0D,
|
||||
SCFG_PINS_SOURCE14 = 0x0E,
|
||||
SCFG_PINS_SOURCE15 = 0x0F
|
||||
} scfg_pins_source_type;
|
||||
|
||||
/**
|
||||
* @brief gpio port source type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
SCFG_PORT_SOURCE_GPIOA = 0x00,
|
||||
SCFG_PORT_SOURCE_GPIOB = 0x01,
|
||||
SCFG_PORT_SOURCE_GPIOC = 0x02,
|
||||
SCFG_PORT_SOURCE_GPIOD = 0x03,
|
||||
SCFG_PORT_SOURCE_GPIOE = 0x04,
|
||||
SCFG_PORT_SOURCE_GPIOF = 0x05,
|
||||
SCFG_PORT_SOURCE_GPIOG = 0x06,
|
||||
SCFG_PORT_SOURCE_GPIOH = 0x07
|
||||
} scfg_port_source_type;
|
||||
|
||||
/**
|
||||
* @brief scfg emac interface selecting type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
SCFG_EMAC_SELECT_MII = 0x00, /* emac interface select mii mode */
|
||||
SCFG_EMAC_SELECT_RMII = 0x01 /* emac interface select rmii mode */
|
||||
} scfg_emac_interface_type;
|
||||
|
||||
/**
|
||||
* @brief scfg ultra high sourcing/sinking strength pins type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
SCFG_ULTRA_DRIVEN_PB3 = MAKE_VALUE(0x2C, 0),
|
||||
SCFG_ULTRA_DRIVEN_PB9 = MAKE_VALUE(0x2C, 1),
|
||||
SCFG_ULTRA_DRIVEN_PB10 = MAKE_VALUE(0x2C, 2),
|
||||
SCFG_ULTRA_DRIVEN_PD12 = MAKE_VALUE(0x2C, 5),
|
||||
SCFG_ULTRA_DRIVEN_PD13 = MAKE_VALUE(0x2C, 6),
|
||||
SCFG_ULTRA_DRIVEN_PD14 = MAKE_VALUE(0x2C, 7),
|
||||
SCFG_ULTRA_DRIVEN_PD15 = MAKE_VALUE(0x2C, 8),
|
||||
SCFG_ULTRA_DRIVEN_PF14 = MAKE_VALUE(0x2C, 9),
|
||||
SCFG_ULTRA_DRIVEN_PF15 = MAKE_VALUE(0x2C, 10)
|
||||
} scfg_ultra_driven_pins_type;
|
||||
|
||||
/**
|
||||
* @brief type define system config register all
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
/**
|
||||
* @brief scfg cfg1 register, offset:0x00
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t cfg1;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t mem_map_sel : 3; /* [2:0] */
|
||||
__IO uint32_t reserved1 : 2; /* [4:3] */
|
||||
__IO uint32_t ir_pol : 1; /* [5] */
|
||||
__IO uint32_t ir_src_sel : 2; /* [7:6] */
|
||||
__IO uint32_t reserved2 : 2; /* [9:8] */
|
||||
__IO uint32_t swap_xmc : 2; /* [11:10] */
|
||||
__IO uint32_t reserved3 : 20;/* [31:12] */
|
||||
} cfg1_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief scfg cfg2 register, offset:0x04
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t cfg2;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t reserved1 : 23;/* [22:0] */
|
||||
__IO uint32_t mii_rmii_sel : 1; /* [23] */
|
||||
__IO uint32_t reserved2 : 8; /* [31:24] */
|
||||
} cfg2_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief scfg exintc1 register, offset:0x08
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t exintc1;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t exint0 : 4; /* [3:0] */
|
||||
__IO uint32_t exint1 : 4; /* [7:4] */
|
||||
__IO uint32_t exint2 : 4; /* [11:8] */
|
||||
__IO uint32_t exint3 : 4; /* [15:12] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:16] */
|
||||
} exintc1_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief scfg exintc2 register, offset:0x0C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t exintc2;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t exint4 : 4; /* [3:0] */
|
||||
__IO uint32_t exint5 : 4; /* [7:4] */
|
||||
__IO uint32_t exint6 : 4; /* [11:8] */
|
||||
__IO uint32_t exint7 : 4; /* [15:12] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:16] */
|
||||
} exintc2_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief scfg exintc3 register, offset:0x10
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t exintc3;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t exint8 : 4; /* [3:0] */
|
||||
__IO uint32_t exint9 : 4; /* [7:4] */
|
||||
__IO uint32_t exint10 : 4; /* [11:8] */
|
||||
__IO uint32_t exint11 : 4; /* [15:12] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:16] */
|
||||
} exintc3_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief scfg exintc4 register, offset:0x14
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t exintc4;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t exint12 : 4; /* [3:0] */
|
||||
__IO uint32_t exint13 : 4; /* [7:4] */
|
||||
__IO uint32_t exint14 : 4; /* [11:8] */
|
||||
__IO uint32_t exint15 : 4; /* [15:12] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:16] */
|
||||
} exintc4_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief crm reserved1 register, offset:0x18~0x28
|
||||
*/
|
||||
__IO uint32_t reserved1[5];
|
||||
|
||||
/**
|
||||
* @brief scfg uhdrv register, offset:0x2C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t uhdrv;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t pb3_uh : 1; /* [0] */
|
||||
__IO uint32_t pb9_uh : 1; /* [1] */
|
||||
__IO uint32_t pb10_uh : 1; /* [2] */
|
||||
__IO uint32_t reserved1 : 2; /* [4:3] */
|
||||
__IO uint32_t pd12_uh : 1; /* [5] */
|
||||
__IO uint32_t pd13_uh : 1; /* [6] */
|
||||
__IO uint32_t pd14_uh : 1; /* [7] */
|
||||
__IO uint32_t pd15_uh : 1; /* [8] */
|
||||
__IO uint32_t pf14_uh : 1; /* [9] */
|
||||
__IO uint32_t pf15_uh : 1; /* [10] */
|
||||
__IO uint32_t reserved2 : 21;/* [31:11] */
|
||||
} uhdrv_bit;
|
||||
};
|
||||
|
||||
} scfg_type;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#define SCFG ((scfg_type *) SCFG_BASE)
|
||||
|
||||
/** @defgroup SCFG_exported_functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void scfg_reset(void);
|
||||
void scfg_xmc_mapping_swap_set(scfg_xmc_swap_type xmc_swap);
|
||||
void scfg_infrared_config(scfg_ir_source_type source, scfg_ir_polarity_type polarity);
|
||||
void scfg_mem_map_set(scfg_mem_map_type mem_map);
|
||||
void scfg_emac_interface_set(scfg_emac_interface_type mode);
|
||||
void scfg_exint_line_config(scfg_port_source_type port_source, scfg_pins_source_type pin_source);
|
||||
void scfg_pins_ultra_driven_enable(scfg_ultra_driven_pins_type value, confirm_state new_state);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,622 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file at32f435_437_sdio.h
|
||||
* @brief at32f435_437 sdio header file
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
/* define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __AT32F435_437_SDIO_H
|
||||
#define __AT32F435_437_SDIO_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* includes ------------------------------------------------------------------*/
|
||||
#include "at32f435_437.h"
|
||||
|
||||
/** @addtogroup AT32F435_437_periph_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup SDIO
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_interrupts_definition
|
||||
* @brief sdio interrupt
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SDIO_CMDFAIL_INT ((uint32_t)0x00000001) /*!< command response received check failed interrupt */
|
||||
#define SDIO_DTFAIL_INT ((uint32_t)0x00000002) /*!< data block sent/received check failed interrupt */
|
||||
#define SDIO_CMDTIMEOUT_INT ((uint32_t)0x00000004) /*!< command response timerout interrupt */
|
||||
#define SDIO_DTTIMEOUT_INT ((uint32_t)0x00000008) /*!< data timeout interrupt */
|
||||
#define SDIO_TXERRU_INT ((uint32_t)0x00000010) /*!< transmit underrun error interrupt */
|
||||
#define SDIO_RXERRO_INT ((uint32_t)0x00000020) /*!< received overrun error interrupt */
|
||||
#define SDIO_CMDRSPCMPL_INT ((uint32_t)0x00000040) /*!< command response received interrupt */
|
||||
#define SDIO_CMDCMPL_INT ((uint32_t)0x00000080) /*!< command sent interrupt */
|
||||
#define SDIO_DTCMP_INT ((uint32_t)0x00000100) /*!< data sent interrupt */
|
||||
#define SDIO_SBITERR_INT ((uint32_t)0x00000200) /*!< start bit not detected on data bus interrupt */
|
||||
#define SDIO_DTBLKCMPL_INT ((uint32_t)0x00000400) /*!< data block sent/received interrupt */
|
||||
#define SDIO_DOCMD_INT ((uint32_t)0x00000800) /*!< command transfer in progress interrupt */
|
||||
#define SDIO_DOTX_INT ((uint32_t)0x00001000) /*!< data transmit in progress interrupt */
|
||||
#define SDIO_DORX_INT ((uint32_t)0x00002000) /*!< data receive in progress interrupt */
|
||||
#define SDIO_TXBUFH_INT ((uint32_t)0x00004000) /*!< transmit buf half empty interrupt */
|
||||
#define SDIO_RXBUFH_INT ((uint32_t)0x00008000) /*!< receive buf half full interrupt */
|
||||
#define SDIO_TXBUFF_INT ((uint32_t)0x00010000) /*!< transmit buf full interrupt */
|
||||
#define SDIO_RXBUFF_INT ((uint32_t)0x00020000) /*!< receive buf full interrupt */
|
||||
#define SDIO_TXBUFE_INT ((uint32_t)0x00040000) /*!< transmit buf empty interrupt */
|
||||
#define SDIO_RXBUFE_INT ((uint32_t)0x00080000) /*!< receive buf empty interrupt */
|
||||
#define SDIO_TXBUF_INT ((uint32_t)0x00100000) /*!< data available in transmit interrupt */
|
||||
#define SDIO_RXBUF_INT ((uint32_t)0x00200000) /*!< data available in receive interrupt */
|
||||
#define SDIO_SDIOIF_INT ((uint32_t)0x00400000) /*!< sdio interface received interrupt */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_flags_definition
|
||||
* @brief sdio flag
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SDIO_CMDFAIL_FLAG ((uint32_t)0x00000001) /*!< command response received check failed flag */
|
||||
#define SDIO_DTFAIL_FLAG ((uint32_t)0x00000002) /*!< data block sent/received check failed flag */
|
||||
#define SDIO_CMDTIMEOUT_FLAG ((uint32_t)0x00000004) /*!< command response timerout flag */
|
||||
#define SDIO_DTTIMEOUT_FLAG ((uint32_t)0x00000008) /*!< data timeout flag */
|
||||
#define SDIO_TXERRU_FLAG ((uint32_t)0x00000010) /*!< transmit underrun error flag */
|
||||
#define SDIO_RXERRO_FLAG ((uint32_t)0x00000020) /*!< received overrun error flag */
|
||||
#define SDIO_CMDRSPCMPL_FLAG ((uint32_t)0x00000040) /*!< command response received flag */
|
||||
#define SDIO_CMDCMPL_FLAG ((uint32_t)0x00000080) /*!< command sent flag */
|
||||
#define SDIO_DTCMPL_FLAG ((uint32_t)0x00000100) /*!< data sent flag */
|
||||
#define SDIO_SBITERR_FLAG ((uint32_t)0x00000200) /*!< start bit not detected on data bus flag */
|
||||
#define SDIO_DTBLKCMPL_FLAG ((uint32_t)0x00000400) /*!< data block sent/received flag */
|
||||
#define SDIO_DOCMD_FLAG ((uint32_t)0x00000800) /*!< command transfer in progress flag */
|
||||
#define SDIO_DOTX_FLAG ((uint32_t)0x00001000) /*!< data transmit in progress flag */
|
||||
#define SDIO_DORX_FLAG ((uint32_t)0x00002000) /*!< data receive in progress flag */
|
||||
#define SDIO_TXBUFH_FLAG ((uint32_t)0x00004000) /*!< transmit buf half empty flag */
|
||||
#define SDIO_RXBUFH_FLAG ((uint32_t)0x00008000) /*!< receive buf half full flag */
|
||||
#define SDIO_TXBUFF_FLAG ((uint32_t)0x00010000) /*!< transmit buf full flag */
|
||||
#define SDIO_RXBUFF_FLAG ((uint32_t)0x00020000) /*!< receive buf full flag */
|
||||
#define SDIO_TXBUFE_FLAG ((uint32_t)0x00040000) /*!< transmit buf empty flag */
|
||||
#define SDIO_RXBUFE_FLAG ((uint32_t)0x00080000) /*!< receive buf empty flag */
|
||||
#define SDIO_TXBUF_FLAG ((uint32_t)0x00100000) /*!< data available in transmit flag */
|
||||
#define SDIO_RXBUF_FLAG ((uint32_t)0x00200000) /*!< data available in receive flag */
|
||||
#define SDIO_SDIOIF_FLAG ((uint32_t)0x00400000) /*!< sdio interface received flag */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_exported_types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief sdio power state
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
SDIO_POWER_OFF = 0x00, /*!< power-off, clock to card is stopped */
|
||||
SDIO_POWER_ON = 0x03 /*!< power-on, the card is clocked */
|
||||
} sdio_power_state_type;
|
||||
|
||||
/**
|
||||
* @brief sdio edge phase
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
SDIO_CLOCK_EDGE_RISING = 0x00, /*!< sdio bus clock generated on the rising edge of the master clock */
|
||||
SDIO_CLOCK_EDGE_FALLING = 0x01 /*!< sdio bus clock generated on the falling edge of the master clock */
|
||||
} sdio_edge_phase_type;
|
||||
|
||||
/**
|
||||
* @brief sdio bus width
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
SDIO_BUS_WIDTH_D1 = 0x00, /*!< sdio wide bus select 1-bit */
|
||||
SDIO_BUS_WIDTH_D4 = 0x01, /*!< sdio wide bus select 4-bit */
|
||||
SDIO_BUS_WIDTH_D8 = 0x02 /*!< sdio wide bus select 8-bit */
|
||||
} sdio_bus_width_type;
|
||||
|
||||
/**
|
||||
* @brief sdio response type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
SDIO_RESPONSE_NO = 0x00, /*!< no response */
|
||||
SDIO_RESPONSE_SHORT = 0x01, /*!< short response */
|
||||
SDIO_RESPONSE_LONG = 0x03 /*!< long response */
|
||||
} sdio_reponse_type;
|
||||
|
||||
/**
|
||||
* @brief sdio wait type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
SDIO_WAIT_FOR_NO = 0x00, /*!< no wait */
|
||||
SDIO_WAIT_FOR_INT = 0x01, /*!< wait interrupt request */
|
||||
SDIO_WAIT_FOR_PEND = 0x02 /*!< wait end of transfer */
|
||||
} sdio_wait_type;
|
||||
|
||||
/**
|
||||
* @brief sdio response register index
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
SDIO_RSP1_INDEX = 0x00, /*!< response index 1, corresponding to sdio_rsp register 1 */
|
||||
SDIO_RSP2_INDEX = 0x01, /*!< response index 2, corresponding to sdio_rsp register 2 */
|
||||
SDIO_RSP3_INDEX = 0x02, /*!< response index 3, corresponding to sdio_rsp register 3 */
|
||||
SDIO_RSP4_INDEX = 0x03 /*!< response index 4, corresponding to sdio_rsp register 4 */
|
||||
} sdio_rsp_index_type;
|
||||
|
||||
/**
|
||||
* @brief sdio data block size
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
SDIO_DATA_BLOCK_SIZE_1B = 0x00, /*!< data block size 1 byte */
|
||||
SDIO_DATA_BLOCK_SIZE_2B = 0x01, /*!< data block size 2 bytes */
|
||||
SDIO_DATA_BLOCK_SIZE_4B = 0x02, /*!< data block size 4 bytes */
|
||||
SDIO_DATA_BLOCK_SIZE_8B = 0x03, /*!< data block size 8 bytes */
|
||||
SDIO_DATA_BLOCK_SIZE_16B = 0x04, /*!< data block size 16 bytes */
|
||||
SDIO_DATA_BLOCK_SIZE_32B = 0x05, /*!< data block size 32 bytes */
|
||||
SDIO_DATA_BLOCK_SIZE_64B = 0x06, /*!< data block size 64 bytes */
|
||||
SDIO_DATA_BLOCK_SIZE_128B = 0x07, /*!< data block size 128 bytes */
|
||||
SDIO_DATA_BLOCK_SIZE_256B = 0x08, /*!< data block size 256 bytes */
|
||||
SDIO_DATA_BLOCK_SIZE_512B = 0x09, /*!< data block size 512 bytes */
|
||||
SDIO_DATA_BLOCK_SIZE_1024B = 0x0A, /*!< data block size 1024 bytes */
|
||||
SDIO_DATA_BLOCK_SIZE_2048B = 0x0B, /*!< data block size 2048 bytes */
|
||||
SDIO_DATA_BLOCK_SIZE_4096B = 0x0C, /*!< data block size 4096 bytes */
|
||||
SDIO_DATA_BLOCK_SIZE_8192B = 0x0D, /*!< data block size 8192 bytes */
|
||||
SDIO_DATA_BLOCK_SIZE_16384B = 0x0E /*!< data block size 16384 bytes */
|
||||
} sdio_block_size_type;
|
||||
|
||||
/**
|
||||
* @brief sdio data transfer mode
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
SDIO_DATA_BLOCK_TRANSFER = 0x00, /*!< the sdio block transfer mode */
|
||||
SDIO_DATA_STREAM_TRANSFER = 0x01 /*!< the sdio stream transfer mode */
|
||||
} sdio_transfer_mode_type;
|
||||
|
||||
/**
|
||||
* @brief sdio data transfer direction
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
SDIO_DATA_TRANSFER_TO_CARD = 0x00, /*!< the sdio controller write */
|
||||
SDIO_DATA_TRANSFER_TO_CONTROLLER = 0x01 /*!< the sdio controller read */
|
||||
} sdio_transfer_direction_type;
|
||||
|
||||
/**
|
||||
* @brief sdio read wait mode
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
SDIO_READ_WAIT_CONTROLLED_BY_D2 = 0x00, /*!< the sdio read wait on data2 line */
|
||||
SDIO_READ_WAIT_CONTROLLED_BY_CK = 0x01 /*!< the sdio read wait on clock line */
|
||||
} sdio_read_wait_mode_type;
|
||||
|
||||
/**
|
||||
* @brief sdio command structure
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t argument; /*!< the sdio command argument is sent to a card as part of command message */
|
||||
uint8_t cmd_index; /*!< the sdio command index */
|
||||
sdio_reponse_type rsp_type; /*!< the sdio response type */
|
||||
sdio_wait_type wait_type; /*!< the sdio wait for interrupt request is enabled or disable */
|
||||
} sdio_command_struct_type;
|
||||
|
||||
/**
|
||||
* @brief sdio data structure
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t timeout; /*!< the sdio data timeout period in car bus clock periods */
|
||||
uint32_t data_length; /*!< the sdio data length */
|
||||
sdio_block_size_type block_size; /*!< the sdio data block size of block transfer mode */
|
||||
sdio_transfer_mode_type transfer_mode; /*!< the sdio transfer mode, block or stream */
|
||||
sdio_transfer_direction_type transfer_direction; /*!< the sdio data transfer direction */
|
||||
} sdio_data_struct_type;
|
||||
|
||||
/**
|
||||
* @brief type define sdio register all
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
/**
|
||||
* @brief sdio pwrctrl register, offset:0x00
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t pwrctrl;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t ps : 2; /* [1:0] */
|
||||
__IO uint32_t reserved1 : 30;/* [31:2] */
|
||||
} pwrctrl_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief sdio clkctrl register, offset:0x04
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t clkctrl;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t clkdiv_l : 8; /* [7:0] */
|
||||
__IO uint32_t clkoen : 1; /* [8] */
|
||||
__IO uint32_t pwrsven : 1; /* [9] */
|
||||
__IO uint32_t bypsen : 1; /* [10] */
|
||||
__IO uint32_t busws : 2; /* [12:11] */
|
||||
__IO uint32_t clkegs : 1; /* [13] */
|
||||
__IO uint32_t hfcen : 1; /* [14] */
|
||||
__IO uint32_t clkdiv_h : 2; /* [16:15] */
|
||||
__IO uint32_t reserved1 : 15;/* [31:17] */
|
||||
} clkctrl_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief sdio argu register, offset:0x08
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t argu;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t argu : 32;/* [31:0] */
|
||||
} argu_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief sdio cmdctrl register, offset:0x0C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t cmdctrl;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t cmdidx : 6; /* [5:0] */
|
||||
__IO uint32_t rspwt : 2; /* [7:6] */
|
||||
__IO uint32_t intwt : 1; /* [8] */
|
||||
__IO uint32_t pndwt : 1; /* [9] */
|
||||
__IO uint32_t ccsmen : 1; /* [10] */
|
||||
__IO uint32_t iosusp : 1; /* [11] */
|
||||
__IO uint32_t reserved1 : 20;/* [31:12] */
|
||||
} cmdctrl_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief sdio rspcmd register, offset:0x10
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t rspcmd;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t rspcmd : 6; /* [5:0] */
|
||||
__IO uint32_t reserved1 : 26;/* [31:6] */
|
||||
} rspcmd_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief sdio rsp1 register, offset:0x14
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t rsp1;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t cardsts1 : 32;/* [31:0] */
|
||||
} rsp1_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief sdio rsp2 register, offset:0x18
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t rsp2;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t cardsts2 : 32;/* [31:0] */
|
||||
} rsp2_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief sdio rsp3 register, offset:0x1C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t rsp3;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t cardsts3 : 32;/* [31:0] */
|
||||
} rsp3_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief sdio rsp4 register, offset:0x20
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t rsp4;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t cardsts4 : 32;/* [31:0] */
|
||||
} rsp4_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief sdio dttmr register, offset:0x24
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t dttmr;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t timeout : 32;/* [31:0] */
|
||||
} dttmr_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief sdio dtlen register, offset:0x28
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t dtlen;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t dtlen : 25;/* [24:0] */
|
||||
__IO uint32_t reserved1 : 7; /* [31:25] */
|
||||
} dtlen_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief sdio dtctrl register, offset:0x2C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t dtctrl;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t tfren : 1; /* [0] */
|
||||
__IO uint32_t tfrdir : 1; /* [1] */
|
||||
__IO uint32_t tfrmode : 1; /* [2] */
|
||||
__IO uint32_t dmaen : 1; /* [3] */
|
||||
__IO uint32_t blksize : 4; /* [7:4] */
|
||||
__IO uint32_t rdwtstart : 1; /* [8] */
|
||||
__IO uint32_t rdwtstop : 1; /* [9] */
|
||||
__IO uint32_t rdwtmode : 1; /* [10] */
|
||||
__IO uint32_t ioen : 1; /* [11] */
|
||||
__IO uint32_t reserved1 : 20;/* [31:12] */
|
||||
} dtctrl_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief sdio dtcnt register, offset:0x30
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t dtcnt;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t cnt : 25;/* [24:0] */
|
||||
__IO uint32_t reserved1 : 7; /* [31:25] */
|
||||
} dtcnt_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief sdio sts register, offset:0x34
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t sts;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t cmdfail : 1; /* [0] */
|
||||
__IO uint32_t dtfail : 1; /* [1] */
|
||||
__IO uint32_t cmdtimeout : 1; /* [2] */
|
||||
__IO uint32_t dttimeout : 1; /* [3] */
|
||||
__IO uint32_t txerru : 1; /* [4] */
|
||||
__IO uint32_t rxerro : 1; /* [5] */
|
||||
__IO uint32_t cmdrspcmpl : 1; /* [6] */
|
||||
__IO uint32_t cmdcmpl : 1; /* [7] */
|
||||
__IO uint32_t dtcmpl : 1; /* [8] */
|
||||
__IO uint32_t sbiterr : 1; /* [9] */
|
||||
__IO uint32_t dtblkcmpl : 1; /* [10] */
|
||||
__IO uint32_t docmd : 1; /* [11] */
|
||||
__IO uint32_t dotx : 1; /* [12] */
|
||||
__IO uint32_t dorx : 1; /* [13] */
|
||||
__IO uint32_t txbufh : 1; /* [14] */
|
||||
__IO uint32_t rxbufh : 1; /* [15] */
|
||||
__IO uint32_t txbuff : 1; /* [16] */
|
||||
__IO uint32_t rxbuff : 1; /* [17] */
|
||||
__IO uint32_t txbufe : 1; /* [18] */
|
||||
__IO uint32_t rxbufe : 1; /* [19] */
|
||||
__IO uint32_t txbuf : 1; /* [20] */
|
||||
__IO uint32_t rxbuf : 1; /* [21] */
|
||||
__IO uint32_t ioif : 1; /* [22] */
|
||||
__IO uint32_t reserved1 : 9; /* [31:23] */
|
||||
} sts_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief sdio intclr register, offset:0x38
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t intclr;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t cmdfail : 1; /* [0] */
|
||||
__IO uint32_t dtfail : 1; /* [1] */
|
||||
__IO uint32_t cmdtimeout : 1; /* [2] */
|
||||
__IO uint32_t dttimeout : 1; /* [3] */
|
||||
__IO uint32_t txerru : 1; /* [4] */
|
||||
__IO uint32_t rxerro : 1; /* [5] */
|
||||
__IO uint32_t cmdrspcmpl : 1; /* [6] */
|
||||
__IO uint32_t cmdcmpl : 1; /* [7] */
|
||||
__IO uint32_t dtcmpl : 1; /* [8] */
|
||||
__IO uint32_t sbiterr : 1; /* [9] */
|
||||
__IO uint32_t dtblkcmpl : 1; /* [10] */
|
||||
__IO uint32_t reserved1 : 11;/* [21:11] */
|
||||
__IO uint32_t ioif : 1; /* [22] */
|
||||
__IO uint32_t reserved2 : 9; /* [31:23] */
|
||||
} intclr_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief sdio inten register, offset:0x3C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t inten;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t cmdfailien : 1; /* [0] */
|
||||
__IO uint32_t dtfailien : 1; /* [1] */
|
||||
__IO uint32_t cmdtimeoutien : 1; /* [2] */
|
||||
__IO uint32_t dttimeoutien : 1; /* [3] */
|
||||
__IO uint32_t txerruien : 1; /* [4] */
|
||||
__IO uint32_t rxerroien : 1; /* [5] */
|
||||
__IO uint32_t cmdrspcmplien : 1; /* [6] */
|
||||
__IO uint32_t cmdcmplien : 1; /* [7] */
|
||||
__IO uint32_t dtcmplien : 1; /* [8] */
|
||||
__IO uint32_t sbiterrien : 1; /* [9] */
|
||||
__IO uint32_t dtblkcmplien : 1; /* [10] */
|
||||
__IO uint32_t docmdien : 1; /* [11] */
|
||||
__IO uint32_t dotxien : 1; /* [12] */
|
||||
__IO uint32_t dorxien : 1; /* [13] */
|
||||
__IO uint32_t txbufhien : 1; /* [14] */
|
||||
__IO uint32_t rxbufhien : 1; /* [15] */
|
||||
__IO uint32_t txbuffien : 1; /* [16] */
|
||||
__IO uint32_t rxbuffien : 1; /* [17] */
|
||||
__IO uint32_t txbufeien : 1; /* [18] */
|
||||
__IO uint32_t rxbufeien : 1; /* [19] */
|
||||
__IO uint32_t txbufien : 1; /* [20] */
|
||||
__IO uint32_t rxbufien : 1; /* [21] */
|
||||
__IO uint32_t ioifien : 1; /* [22] */
|
||||
__IO uint32_t reserved1 : 9; /* [31:23] */
|
||||
} inten_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief sdio reserved1 register, offset:0x40~0x44
|
||||
*/
|
||||
__IO uint32_t reserved1[2];
|
||||
|
||||
/**
|
||||
* @brief sdio bufcnt register, offset:0x48
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t bufcnt;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t cnt : 24;/* [23:0] */
|
||||
__IO uint32_t reserved1 : 8; /* [31:24] */
|
||||
} bufcnt_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief sdio reserved2 register, offset:0x4C~0x7C
|
||||
*/
|
||||
__IO uint32_t reserved2[13];
|
||||
|
||||
/**
|
||||
* @brief sdio buf register, offset:0x80
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t buf;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t dt : 32;/* [31:0] */
|
||||
} buf_bit;
|
||||
};
|
||||
|
||||
} sdio_type;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#define SDIO1 ((sdio_type *) SDIO1_BASE)
|
||||
#define SDIO2 ((sdio_type *) SDIO2_BASE)
|
||||
|
||||
/** @defgroup SDIO_exported_functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void sdio_reset(sdio_type *sdio_x);
|
||||
void sdio_power_set(sdio_type *sdio_x, sdio_power_state_type power_state);
|
||||
sdio_power_state_type sdio_power_status_get(sdio_type *sdio_x);
|
||||
void sdio_clock_config(sdio_type *sdio_x, uint16_t clk_div, sdio_edge_phase_type clk_edg);
|
||||
void sdio_bus_width_config(sdio_type *sdio_x, sdio_bus_width_type width);
|
||||
void sdio_clock_bypass(sdio_type *sdio_x, confirm_state new_state);
|
||||
void sdio_power_saving_mode_enable(sdio_type *sdio_x, confirm_state new_state);
|
||||
void sdio_flow_control_enable(sdio_type *sdio_x, confirm_state new_state);
|
||||
void sdio_clock_enable(sdio_type *sdio_x, confirm_state new_state);
|
||||
void sdio_dma_enable(sdio_type *sdio_x, confirm_state new_state);
|
||||
void sdio_interrupt_enable(sdio_type *sdio_x, uint32_t int_opt, confirm_state new_state);
|
||||
flag_status sdio_flag_get(sdio_type *sdio_x, uint32_t flag);
|
||||
void sdio_flag_clear(sdio_type *sdio_x, uint32_t flag);
|
||||
void sdio_command_config(sdio_type *sdio_x, sdio_command_struct_type *command_struct);
|
||||
void sdio_command_state_machine_enable(sdio_type *sdio_x, confirm_state new_state);
|
||||
uint8_t sdio_command_response_get(sdio_type *sdio_x);
|
||||
uint32_t sdio_response_get(sdio_type *sdio_x, sdio_rsp_index_type reg_index);
|
||||
void sdio_data_config(sdio_type *sdio_x, sdio_data_struct_type *data_struct);
|
||||
void sdio_data_state_machine_enable(sdio_type *sdio_x, confirm_state new_state);
|
||||
uint32_t sdio_data_counter_get(sdio_type *sdio_x);
|
||||
uint32_t sdio_data_read(sdio_type *sdio_x);
|
||||
uint32_t sdio_buffer_counter_get(sdio_type *sdio_x);
|
||||
void sdio_data_write(sdio_type *sdio_x, uint32_t data);
|
||||
void sdio_read_wait_mode_set(sdio_type *sdio_x, sdio_read_wait_mode_type mode);
|
||||
void sdio_read_wait_start(sdio_type *sdio_x, confirm_state new_state);
|
||||
void sdio_read_wait_stop(sdio_type *sdio_x, confirm_state new_state);
|
||||
void sdio_io_function_enable(sdio_type *sdio_x, confirm_state new_state);
|
||||
void sdio_io_suspend_command_set(sdio_type *sdio_x, confirm_state new_state);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,503 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file at32f435_437_spi.h
|
||||
* @brief at32f435_437 spi header file
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __AT32F435_437_SPI_H
|
||||
#define __AT32F435_437_SPI_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "at32f435_437.h"
|
||||
|
||||
/** @addtogroup AT32F435_437_periph_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup SPI
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup SPI_I2S_flags_definition
|
||||
* @brief spi i2s flag
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_I2S_RDBF_FLAG 0x0001 /*!< spi or i2s receive data buffer full flag */
|
||||
#define SPI_I2S_TDBE_FLAG 0x0002 /*!< spi or i2s transmit data buffer empty flag */
|
||||
#define I2S_ACS_FLAG 0x0004 /*!< i2s audio channel state flag */
|
||||
#define I2S_TUERR_FLAG 0x0008 /*!< i2s transmitter underload error flag */
|
||||
#define SPI_CCERR_FLAG 0x0010 /*!< spi crc calculation error flag */
|
||||
#define SPI_MMERR_FLAG 0x0020 /*!< spi master mode error flag */
|
||||
#define SPI_I2S_ROERR_FLAG 0x0040 /*!< spi or i2s receiver overflow error flag */
|
||||
#define SPI_I2S_BF_FLAG 0x0080 /*!< spi or i2s busy flag */
|
||||
#define SPI_CSPAS_FLAG 0x0100 /*!< spi cs pulse abnormal setting fiag */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup SPI_I2S_interrupts_definition
|
||||
* @brief spi i2s interrupt
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_I2S_ERROR_INT 0x0020 /*!< error interrupt */
|
||||
#define SPI_I2S_RDBF_INT 0x0040 /*!< receive data buffer full interrupt */
|
||||
#define SPI_I2S_TDBE_INT 0x0080 /*!< transmit data buffer empty interrupt */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_exported_types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief spi frame bit num type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
SPI_FRAME_8BIT = 0x00, /*!< 8-bit data frame format */
|
||||
SPI_FRAME_16BIT = 0x01 /*!< 16-bit data frame format */
|
||||
} spi_frame_bit_num_type;
|
||||
|
||||
/**
|
||||
* @brief spi master/slave mode type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
SPI_MODE_SLAVE = 0x00, /*!< select as slave mode */
|
||||
SPI_MODE_MASTER = 0x01 /*!< select as master mode */
|
||||
} spi_master_slave_mode_type;
|
||||
|
||||
/**
|
||||
* @brief spi clock polarity (clkpol) type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
SPI_CLOCK_POLARITY_LOW = 0x00, /*!< sck keeps low at idle state */
|
||||
SPI_CLOCK_POLARITY_HIGH = 0x01 /*!< sck keeps high at idle state */
|
||||
} spi_clock_polarity_type;
|
||||
|
||||
/**
|
||||
* @brief spi clock phase (clkpha) type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
SPI_CLOCK_PHASE_1EDGE = 0x00, /*!< data capture start from the first clock edge */
|
||||
SPI_CLOCK_PHASE_2EDGE = 0x01 /*!< data capture start from the second clock edge */
|
||||
} spi_clock_phase_type;
|
||||
|
||||
/**
|
||||
* @brief spi cs mode type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
SPI_CS_HARDWARE_MODE = 0x00, /*!< cs is hardware mode */
|
||||
SPI_CS_SOFTWARE_MODE = 0x01 /*!< cs is software mode */
|
||||
} spi_cs_mode_type;
|
||||
|
||||
/**
|
||||
* @brief spi master clock frequency division type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
SPI_MCLK_DIV_2 = 0x00, /*!< master clock frequency division 2 */
|
||||
SPI_MCLK_DIV_3 = 0x0A, /*!< master clock frequency division 3 */
|
||||
SPI_MCLK_DIV_4 = 0x01, /*!< master clock frequency division 4 */
|
||||
SPI_MCLK_DIV_8 = 0x02, /*!< master clock frequency division 8 */
|
||||
SPI_MCLK_DIV_16 = 0x03, /*!< master clock frequency division 16 */
|
||||
SPI_MCLK_DIV_32 = 0x04, /*!< master clock frequency division 32 */
|
||||
SPI_MCLK_DIV_64 = 0x05, /*!< master clock frequency division 64 */
|
||||
SPI_MCLK_DIV_128 = 0x06, /*!< master clock frequency division 128 */
|
||||
SPI_MCLK_DIV_256 = 0x07, /*!< master clock frequency division 256 */
|
||||
SPI_MCLK_DIV_512 = 0x08, /*!< master clock frequency division 512 */
|
||||
SPI_MCLK_DIV_1024 = 0x09 /*!< master clock frequency division 1024 */
|
||||
} spi_mclk_freq_div_type;
|
||||
|
||||
/**
|
||||
* @brief spi transmit first bit (lsb/msb) type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
SPI_FIRST_BIT_MSB = 0x00, /*!< the frame format is msb first */
|
||||
SPI_FIRST_BIT_LSB = 0x01 /*!< the frame format is lsb first */
|
||||
} spi_first_bit_type;
|
||||
|
||||
/**
|
||||
* @brief spi transmission mode type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
SPI_TRANSMIT_FULL_DUPLEX = 0x00, /*!< dual line unidirectional full-duplex mode(slben = 0 and ora = 0) */
|
||||
SPI_TRANSMIT_SIMPLEX_RX = 0x01, /*!< dual line unidirectional simplex receive-only mode(slben = 0 and ora = 1) */
|
||||
SPI_TRANSMIT_HALF_DUPLEX_RX = 0x02, /*!< single line bidirectional half duplex mode-receiving(slben = 1 and slbtd = 0) */
|
||||
SPI_TRANSMIT_HALF_DUPLEX_TX = 0x03 /*!< single line bidirectional half duplex mode-transmitting(slben = 1 and slbtd = 1) */
|
||||
} spi_transmission_mode_type;
|
||||
|
||||
/**
|
||||
* @brief spi crc direction type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
SPI_CRC_RX = 0x0014, /*!< crc direction is rx */
|
||||
SPI_CRC_TX = 0x0018 /*!< crc direction is tx */
|
||||
} spi_crc_direction_type;
|
||||
|
||||
/**
|
||||
* @brief spi single line bidirectional direction type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
SPI_HALF_DUPLEX_DIRECTION_RX = 0x00, /*!< single line bidirectional half duplex mode direction: receive(slbtd = 0) */
|
||||
SPI_HALF_DUPLEX_DIRECTION_TX = 0x01 /*!< single line bidirectional half duplex mode direction: transmit(slbtd = 1) */
|
||||
} spi_half_duplex_direction_type;
|
||||
|
||||
/**
|
||||
* @brief spi software cs internal level type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
SPI_SWCS_INTERNAL_LEVEL_LOW = 0x00, /*!< internal level low */
|
||||
SPI_SWCS_INTERNAL_LEVEL_HIGHT = 0x01 /*!< internal level high */
|
||||
} spi_software_cs_level_type;
|
||||
|
||||
/**
|
||||
* @brief i2s audio protocol type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
I2S_AUDIO_PROTOCOL_PHILLIPS = 0x00, /*!< i2s philip standard */
|
||||
I2S_AUDIO_PROTOCOL_MSB = 0x01, /*!< msb-justified standard */
|
||||
I2S_AUDIO_PROTOCOL_LSB = 0x02, /*!< lsb-justified standard */
|
||||
I2S_AUDIO_PROTOCOL_PCM_SHORT = 0x03, /*!< pcm standard-short frame */
|
||||
I2S_AUDIO_PROTOCOL_PCM_LONG = 0x04 /*!< pcm standard-long frame */
|
||||
} i2s_audio_protocol_type;
|
||||
|
||||
/**
|
||||
* @brief i2s audio frequency type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
I2S_AUDIO_FREQUENCY_DEFAULT = 2, /*!< i2s audio sampling frequency default */
|
||||
I2S_AUDIO_FREQUENCY_8K = 8000, /*!< i2s audio sampling frequency 8k */
|
||||
I2S_AUDIO_FREQUENCY_11_025K = 11025, /*!< i2s audio sampling frequency 11.025k */
|
||||
I2S_AUDIO_FREQUENCY_16K = 16000, /*!< i2s audio sampling frequency 16k */
|
||||
I2S_AUDIO_FREQUENCY_22_05K = 22050, /*!< i2s audio sampling frequency 22.05k */
|
||||
I2S_AUDIO_FREQUENCY_32K = 32000, /*!< i2s audio sampling frequency 32k */
|
||||
I2S_AUDIO_FREQUENCY_44_1K = 44100, /*!< i2s audio sampling frequency 44.1k */
|
||||
I2S_AUDIO_FREQUENCY_48K = 48000, /*!< i2s audio sampling frequency 48k */
|
||||
I2S_AUDIO_FREQUENCY_96K = 96000, /*!< i2s audio sampling frequency 96k */
|
||||
I2S_AUDIO_FREQUENCY_192K = 192000 /*!< i2s audio sampling frequency 192k */
|
||||
} i2s_audio_sampling_freq_type;
|
||||
|
||||
/**
|
||||
* @brief i2s data bit num and channel bit num type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
I2S_DATA_16BIT_CHANNEL_16BIT = 0x01, /*!< 16-bit data packed in 16-bit channel frame */
|
||||
I2S_DATA_16BIT_CHANNEL_32BIT = 0x02, /*!< 16-bit data packed in 32-bit channel frame */
|
||||
I2S_DATA_24BIT_CHANNEL_32BIT = 0x03, /*!< 24-bit data packed in 32-bit channel frame */
|
||||
I2S_DATA_32BIT_CHANNEL_32BIT = 0x04 /*!< 32-bit data packed in 32-bit channel frame */
|
||||
} i2s_data_channel_format_type;
|
||||
|
||||
/**
|
||||
* @brief i2s operation mode type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
I2S_MODE_SLAVE_TX = 0x00, /*!< slave transmission mode */
|
||||
I2S_MODE_SLAVE_RX = 0x01, /*!< slave reception mode */
|
||||
I2S_MODE_MASTER_TX = 0x02, /*!< master transmission mode */
|
||||
I2S_MODE_MASTER_RX = 0x03 /*!< master reception mode */
|
||||
} i2s_operation_mode_type;
|
||||
|
||||
/**
|
||||
* @brief i2s clock polarity type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
I2S_CLOCK_POLARITY_LOW = 0x00, /*!< i2s clock steady state is low level */
|
||||
I2S_CLOCK_POLARITY_HIGH = 0x01 /*!< i2s clock steady state is high level */
|
||||
} i2s_clock_polarity_type;
|
||||
|
||||
/**
|
||||
* @brief spi init type
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
spi_transmission_mode_type transmission_mode; /*!< transmission mode selection */
|
||||
spi_master_slave_mode_type master_slave_mode; /*!< master or slave mode selection */
|
||||
spi_mclk_freq_div_type mclk_freq_division; /*!< master clock frequency division selection */
|
||||
spi_first_bit_type first_bit_transmission;/*!< transmit lsb or msb selection */
|
||||
spi_frame_bit_num_type frame_bit_num; /*!< frame bit num 8 or 16 bit selection */
|
||||
spi_clock_polarity_type clock_polarity; /*!< clock polarity selection */
|
||||
spi_clock_phase_type clock_phase; /*!< clock phase selection */
|
||||
spi_cs_mode_type cs_mode_selection; /*!< hardware or software cs mode selection */
|
||||
} spi_init_type;
|
||||
|
||||
/**
|
||||
* @brief i2s init type
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
i2s_operation_mode_type operation_mode; /*!< operation mode selection */
|
||||
i2s_audio_protocol_type audio_protocol; /*!< audio protocol selection */
|
||||
i2s_audio_sampling_freq_type audio_sampling_freq; /*!< audio frequency selection */
|
||||
i2s_data_channel_format_type data_channel_format; /*!< data bit num and channel bit num selection */
|
||||
i2s_clock_polarity_type clock_polarity; /*!< clock polarity selection */
|
||||
confirm_state mclk_output_enable; /*!< mclk_output selection */
|
||||
} i2s_init_type;
|
||||
|
||||
/**
|
||||
* @brief type define spi register all
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
|
||||
/**
|
||||
* @brief spi ctrl1 register, offset:0x00
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ctrl1;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t clkpha : 1; /* [0] */
|
||||
__IO uint32_t clkpol : 1; /* [1] */
|
||||
__IO uint32_t msten : 1; /* [2] */
|
||||
__IO uint32_t mdiv_l : 3; /* [5:3] */
|
||||
__IO uint32_t spien : 1; /* [6] */
|
||||
__IO uint32_t ltf : 1; /* [7] */
|
||||
__IO uint32_t swcsil : 1; /* [8] */
|
||||
__IO uint32_t swcsen : 1; /* [9] */
|
||||
__IO uint32_t ora : 1; /* [10] */
|
||||
__IO uint32_t fbn : 1; /* [11] */
|
||||
__IO uint32_t ntc : 1; /* [12] */
|
||||
__IO uint32_t ccen : 1; /* [13] */
|
||||
__IO uint32_t slbtd : 1; /* [14] */
|
||||
__IO uint32_t slben : 1; /* [15] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:16] */
|
||||
} ctrl1_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief spi ctrl2 register, offset:0x04
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ctrl2;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t dmaren : 1; /* [0] */
|
||||
__IO uint32_t dmaten : 1; /* [1] */
|
||||
__IO uint32_t hwcsoe : 1; /* [2] */
|
||||
__IO uint32_t reserved1 : 1; /* [3] */
|
||||
__IO uint32_t tien : 1; /* [4] */
|
||||
__IO uint32_t errie : 1; /* [5] */
|
||||
__IO uint32_t rdbfie : 1; /* [6] */
|
||||
__IO uint32_t tdbeie : 1; /* [7] */
|
||||
__IO uint32_t mdiv_h : 1; /* [8] */
|
||||
__IO uint32_t mdiv3en : 1; /* [9] */
|
||||
__IO uint32_t reserved2 : 22;/* [31:10] */
|
||||
} ctrl2_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief spi sts register, offset:0x08
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t sts;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t rdbf : 1; /* [0] */
|
||||
__IO uint32_t tdbe : 1; /* [1] */
|
||||
__IO uint32_t acs : 1; /* [2] */
|
||||
__IO uint32_t tuerr : 1; /* [3] */
|
||||
__IO uint32_t ccerr : 1; /* [4] */
|
||||
__IO uint32_t mmerr : 1; /* [5] */
|
||||
__IO uint32_t roerr : 1; /* [6] */
|
||||
__IO uint32_t bf : 1; /* [7] */
|
||||
__IO uint32_t cspas : 1; /* [8] */
|
||||
__IO uint32_t reserved1 : 23;/* [31:9] */
|
||||
} sts_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief spi dt register, offset:0x0C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t dt;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t dt : 16;/* [15:0] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:16] */
|
||||
} dt_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief spi cpoly register, offset:0x10
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t cpoly;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t cpoly : 16;/* [15:0] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:16] */
|
||||
} cpoly_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief spi rcrc register, offset:0x14
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t rcrc;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t rcrc : 16;/* [15:0] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:16] */
|
||||
} rcrc_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief spi tcrc register, offset:0x18
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t tcrc;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t tcrc : 16;/* [15:0] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:16] */
|
||||
} tcrc_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief spi i2sctrl register, offset:0x1C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t i2sctrl;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t i2scbn : 1; /* [0] */
|
||||
__IO uint32_t i2sdbn : 2; /* [2:1] */
|
||||
__IO uint32_t i2sclkpol : 1; /* [3] */
|
||||
__IO uint32_t stdsel : 2; /* [5:4] */
|
||||
__IO uint32_t reserved1 : 1; /* [6] */
|
||||
__IO uint32_t pcmfssel : 1; /* [7] */
|
||||
__IO uint32_t opersel : 2; /* [9:8] */
|
||||
__IO uint32_t i2sen : 1; /* [10] */
|
||||
__IO uint32_t i2smsel : 1; /* [11] */
|
||||
__IO uint32_t reserved2 : 20;/* [31:12] */
|
||||
} i2sctrl_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief spi i2sclk register, offset:0x20
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t i2sclk;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t i2sdiv_l : 8; /* [7:0] */
|
||||
__IO uint32_t i2sodd : 1; /* [8] */
|
||||
__IO uint32_t i2smclkoe : 1; /* [9] */
|
||||
__IO uint32_t i2sdiv_h : 2; /* [11:10] */
|
||||
__IO uint32_t reserved1 : 20;/* [31:12] */
|
||||
} i2sclk_bit;
|
||||
};
|
||||
|
||||
} spi_type;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#define SPI1 ((spi_type *) SPI1_BASE)
|
||||
#define SPI2 ((spi_type *) SPI2_BASE)
|
||||
#define SPI3 ((spi_type *) SPI3_BASE)
|
||||
#define SPI4 ((spi_type *) SPI4_BASE)
|
||||
#define I2S2EXT ((spi_type *) I2S2EXT_BASE)
|
||||
#define I2S3EXT ((spi_type *) I2S3EXT_BASE)
|
||||
|
||||
/** @defgroup SPI_exported_functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void spi_i2s_reset(spi_type *spi_x);
|
||||
void spi_default_para_init(spi_init_type* spi_init_struct);
|
||||
void spi_init(spi_type* spi_x, spi_init_type* spi_init_struct);
|
||||
void spi_ti_mode_enable(spi_type* spi_x, confirm_state new_state);
|
||||
void spi_crc_next_transmit(spi_type* spi_x);
|
||||
void spi_crc_polynomial_set(spi_type* spi_x, uint16_t crc_poly);
|
||||
uint16_t spi_crc_polynomial_get(spi_type* spi_x);
|
||||
void spi_crc_enable(spi_type* spi_x, confirm_state new_state);
|
||||
uint16_t spi_crc_value_get(spi_type* spi_x, spi_crc_direction_type crc_direction);
|
||||
void spi_hardware_cs_output_enable(spi_type* spi_x, confirm_state new_state);
|
||||
void spi_software_cs_internal_level_set(spi_type* spi_x, spi_software_cs_level_type level);
|
||||
void spi_frame_bit_num_set(spi_type* spi_x, spi_frame_bit_num_type bit_num);
|
||||
void spi_half_duplex_direction_set(spi_type* spi_x, spi_half_duplex_direction_type direction);
|
||||
void spi_enable(spi_type* spi_x, confirm_state new_state);
|
||||
void i2s_default_para_init(i2s_init_type* i2s_init_struct);
|
||||
void i2s_init(spi_type* spi_x, i2s_init_type* i2s_init_struct);
|
||||
void i2s_enable(spi_type* spi_x, confirm_state new_state);
|
||||
void spi_i2s_interrupt_enable(spi_type* spi_x, uint32_t spi_i2s_int, confirm_state new_state);
|
||||
void spi_i2s_dma_transmitter_enable(spi_type* spi_x, confirm_state new_state);
|
||||
void spi_i2s_dma_receiver_enable(spi_type* spi_x, confirm_state new_state);
|
||||
void spi_i2s_data_transmit(spi_type* spi_x, uint16_t tx_data);
|
||||
uint16_t spi_i2s_data_receive(spi_type* spi_x);
|
||||
flag_status spi_i2s_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag);
|
||||
void spi_i2s_flag_clear(spi_type* spi_x, uint32_t spi_i2s_flag);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,413 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file at32f435_437_usart.h
|
||||
* @brief at32f435_437 usart header file
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
/* define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __AT32F435_437_USART_H
|
||||
#define __AT32F435_437_USART_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* includes ------------------------------------------------------------------*/
|
||||
#include "at32f435_437.h"
|
||||
|
||||
/** @addtogroup AT32F435_437_periph_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup USART
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup USART_flags_definition
|
||||
* @brief usart flag
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_PERR_FLAG ((uint32_t)0x00000001) /*!< usart parity error flag */
|
||||
#define USART_FERR_FLAG ((uint32_t)0x00000002) /*!< usart framing error flag */
|
||||
#define USART_NERR_FLAG ((uint32_t)0x00000004) /*!< usart noise error flag */
|
||||
#define USART_ROERR_FLAG ((uint32_t)0x00000008) /*!< usart receiver overflow error flag */
|
||||
#define USART_IDLEF_FLAG ((uint32_t)0x00000010) /*!< usart idle flag */
|
||||
#define USART_RDBF_FLAG ((uint32_t)0x00000020) /*!< usart receive data buffer full flag */
|
||||
#define USART_TDC_FLAG ((uint32_t)0x00000040) /*!< usart transmit data complete flag */
|
||||
#define USART_TDBE_FLAG ((uint32_t)0x00000080) /*!< usart transmit data buffer empty flag */
|
||||
#define USART_BFF_FLAG ((uint32_t)0x00000100) /*!< usart break frame flag */
|
||||
#define USART_CTSCF_FLAG ((uint32_t)0x00000200) /*!< usart cts change flag */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_interrupts_definition
|
||||
* @brief usart interrupt
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_IDLE_INT MAKE_VALUE(0x0C,0x04) /*!< usart idle interrupt */
|
||||
#define USART_RDBF_INT MAKE_VALUE(0x0C,0x05) /*!< usart receive data buffer full interrupt */
|
||||
#define USART_TDC_INT MAKE_VALUE(0x0C,0x06) /*!< usart transmit data complete interrupt */
|
||||
#define USART_TDBE_INT MAKE_VALUE(0x0C,0x07) /*!< usart transmit data buffer empty interrupt */
|
||||
#define USART_PERR_INT MAKE_VALUE(0x0C,0x08) /*!< usart parity error interrupt */
|
||||
#define USART_BF_INT MAKE_VALUE(0x10,0x06) /*!< usart break frame interrupt */
|
||||
#define USART_ERR_INT MAKE_VALUE(0x14,0x00) /*!< usart error interrupt */
|
||||
#define USART_CTSCF_INT MAKE_VALUE(0x14,0x0A) /*!< usart cts change interrupt */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_exported_types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief usart parity selection type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
USART_PARITY_NONE = 0x00, /*!< usart no parity */
|
||||
USART_PARITY_EVEN = 0x01, /*!< usart even parity */
|
||||
USART_PARITY_ODD = 0x02 /*!< usart odd parity */
|
||||
} usart_parity_selection_type;
|
||||
|
||||
/**
|
||||
* @brief usart wakeup mode type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
USART_WAKEUP_BY_IDLE_FRAME = 0x00, /*!< usart wakeup by idle frame */
|
||||
USART_WAKEUP_BY_MATCHING_ID = 0x01 /*!< usart wakeup by matching id */
|
||||
} usart_wakeup_mode_type;
|
||||
|
||||
/**
|
||||
* @brief usart data bit num type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
USART_DATA_7BITS = 0x00, /*!< usart data size is 7 bits */
|
||||
USART_DATA_8BITS = 0x01, /*!< usart data size is 8 bits */
|
||||
USART_DATA_9BITS = 0x02 /*!< usart data size is 9 bits */
|
||||
} usart_data_bit_num_type;
|
||||
|
||||
/**
|
||||
* @brief usart break frame bit num type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
USART_BREAK_10BITS = 0x00, /*!< usart lin mode berak frame detection 10 bits */
|
||||
USART_BREAK_11BITS = 0x01 /*!< usart lin mode berak frame detection 11 bits */
|
||||
} usart_break_bit_num_type;
|
||||
|
||||
/**
|
||||
* @brief usart phase of the clock type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
USART_CLOCK_PHASE_1EDGE = 0x00, /*!< usart data capture is done on the clock leading edge */
|
||||
USART_CLOCK_PHASE_2EDGE = 0x01 /*!< usart data capture is done on the clock trailing edge */
|
||||
} usart_clock_phase_type;
|
||||
|
||||
/**
|
||||
* @brief usart polarity of the clock type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
USART_CLOCK_POLARITY_LOW = 0x00, /*!< usart clock stay low level outside transmission window */
|
||||
USART_CLOCK_POLARITY_HIGH = 0x01 /*!< usart clock stay high level outside transmission window */
|
||||
} usart_clock_polarity_type;
|
||||
|
||||
/**
|
||||
* @brief usart last bit clock pulse type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
USART_CLOCK_LAST_BIT_NONE = 0x00, /*!< usart clock pulse of the last data bit is not outputted */
|
||||
USART_CLOCK_LAST_BIT_OUTPUT = 0x01 /*!< usart clock pulse of the last data bit is outputted */
|
||||
} usart_lbcp_type;
|
||||
|
||||
/**
|
||||
* @brief usart stop bit num type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
USART_STOP_1_BIT = 0x00, /*!< usart stop bits num is 1 */
|
||||
USART_STOP_0_5_BIT = 0x01, /*!< usart stop bits num is 0.5 */
|
||||
USART_STOP_2_BIT = 0x02, /*!< usart stop bits num is 2 */
|
||||
USART_STOP_1_5_BIT = 0x03 /*!< usart stop bits num is 1.5 */
|
||||
} usart_stop_bit_num_type;
|
||||
|
||||
/**
|
||||
* @brief usart hardware flow control type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
USART_HARDWARE_FLOW_NONE = 0x00, /*!< usart without hardware flow */
|
||||
USART_HARDWARE_FLOW_RTS = 0x01, /*!< usart hardware flow only rts */
|
||||
USART_HARDWARE_FLOW_CTS = 0x02, /*!< usart hardware flow only cts */
|
||||
USART_HARDWARE_FLOW_RTS_CTS = 0x03 /*!< usart hardware flow both rts and cts */
|
||||
} usart_hardware_flow_control_type;
|
||||
|
||||
/**
|
||||
* @brief usart identification bit num type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
USART_ID_FIXED_4_BIT = 0x00, /*!< usart id bit num fixed 4 bits */
|
||||
USART_ID_RELATED_DATA_BIT = 0x01 /*!< usart id bit num related data bits */
|
||||
} usart_identification_bit_num_type;
|
||||
|
||||
/**
|
||||
* @brief usart de polarity type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
USART_DE_POLARITY_HIGH = 0x00, /*!< usart de polarity high */
|
||||
USART_DE_POLARITY_LOW = 0x01 /*!< usart de polarity low */
|
||||
} usart_de_polarity_type;
|
||||
|
||||
/**
|
||||
* @brief type define usart register all
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
/**
|
||||
* @brief usart sts register, offset:0x00
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t sts;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t perr : 1; /* [0] */
|
||||
__IO uint32_t ferr : 1; /* [1] */
|
||||
__IO uint32_t nerr : 1; /* [2] */
|
||||
__IO uint32_t roerr : 1; /* [3] */
|
||||
__IO uint32_t idlef : 1; /* [4] */
|
||||
__IO uint32_t rdbf : 1; /* [5] */
|
||||
__IO uint32_t tdc : 1; /* [6] */
|
||||
__IO uint32_t tdbe : 1; /* [7] */
|
||||
__IO uint32_t bff : 1; /* [8] */
|
||||
__IO uint32_t ctscf : 1; /* [9] */
|
||||
__IO uint32_t reserved1 : 22;/* [31:10] */
|
||||
} sts_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief usart dt register, offset:0x04
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t dt;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t dt : 9; /* [8:0] */
|
||||
__IO uint32_t reserved1 : 23;/* [31:9] */
|
||||
} dt_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief usart baudr register, offset:0x08
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t baudr;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t div : 16;/* [15:0] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:16] */
|
||||
} baudr_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief usart ctrl1 register, offset:0x0C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ctrl1;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t sbf : 1; /* [0] */
|
||||
__IO uint32_t rm : 1; /* [1] */
|
||||
__IO uint32_t ren : 1; /* [2] */
|
||||
__IO uint32_t ten : 1; /* [3] */
|
||||
__IO uint32_t idleien : 1; /* [4] */
|
||||
__IO uint32_t rdbfien : 1; /* [5] */
|
||||
__IO uint32_t tdcien : 1; /* [6] */
|
||||
__IO uint32_t tdbeien : 1; /* [7] */
|
||||
__IO uint32_t perrien : 1; /* [8] */
|
||||
__IO uint32_t psel : 1; /* [9] */
|
||||
__IO uint32_t pen : 1; /* [10] */
|
||||
__IO uint32_t wum : 1; /* [11] */
|
||||
__IO uint32_t dbn_l : 1; /* [12] */
|
||||
__IO uint32_t uen : 1; /* [13] */
|
||||
__IO uint32_t reserved1 : 2; /* [15:14] */
|
||||
__IO uint32_t tcdt : 5; /* [20:16] */
|
||||
__IO uint32_t tsdt : 5; /* [25:21] */
|
||||
__IO uint32_t reserved2 : 2; /* [27:26] */
|
||||
__IO uint32_t dbn_h : 1; /* [28] */
|
||||
__IO uint32_t reserved3 : 3; /* [31:29] */
|
||||
} ctrl1_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief usart ctrl2 register, offset:0x10
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ctrl2;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t id_l : 4; /* [3:0] */
|
||||
__IO uint32_t idbn : 1; /* [4] */
|
||||
__IO uint32_t bfbn : 1; /* [5] */
|
||||
__IO uint32_t bfien : 1; /* [6] */
|
||||
__IO uint32_t reserved1 : 1; /* [7] */
|
||||
__IO uint32_t lbcp : 1; /* [8] */
|
||||
__IO uint32_t clkpha : 1; /* [9] */
|
||||
__IO uint32_t clkpol : 1; /* [10] */
|
||||
__IO uint32_t clken : 1; /* [11] */
|
||||
__IO uint32_t stopbn : 2; /* [13:12] */
|
||||
__IO uint32_t linen : 1; /* [14] */
|
||||
__IO uint32_t trpswap : 1; /* [15] */
|
||||
__IO uint32_t reserved2 : 12;/* [27:16] */
|
||||
__IO uint32_t id_h : 4; /* [31:28] */
|
||||
} ctrl2_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief usart ctrl3 register, offset:0x14
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ctrl3;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t errien : 1; /* [0] */
|
||||
__IO uint32_t irdaen : 1; /* [1] */
|
||||
__IO uint32_t irdalp : 1; /* [2] */
|
||||
__IO uint32_t slben : 1; /* [3] */
|
||||
__IO uint32_t scnacken : 1; /* [4] */
|
||||
__IO uint32_t scmen : 1; /* [5] */
|
||||
__IO uint32_t dmaren : 1; /* [6] */
|
||||
__IO uint32_t dmaten : 1; /* [7] */
|
||||
__IO uint32_t rtsen : 1; /* [8] */
|
||||
__IO uint32_t ctsen : 1; /* [9] */
|
||||
__IO uint32_t ctscfien : 1; /* [10] */
|
||||
__IO uint32_t reserved1 : 3; /* [13:11] */
|
||||
__IO uint32_t rs485en : 1; /* [14] */
|
||||
__IO uint32_t dep : 1; /* [15] */
|
||||
__IO uint32_t reserved2 : 16;/* [31:16] */
|
||||
} ctrl3_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief usart gdiv register, offset:0x18
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t gdiv;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t isdiv : 8; /* [7:0] */
|
||||
__IO uint32_t scgt : 8; /* [15:8] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:16] */
|
||||
} gdiv_bit;
|
||||
};
|
||||
} usart_type;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#define USART1 ((usart_type *) USART1_BASE)
|
||||
#define USART2 ((usart_type *) USART2_BASE)
|
||||
#define USART3 ((usart_type *) USART3_BASE)
|
||||
#define UART4 ((usart_type *) UART4_BASE)
|
||||
#define UART5 ((usart_type *) UART5_BASE)
|
||||
#define USART6 ((usart_type *) USART6_BASE)
|
||||
#define UART7 ((usart_type *) UART7_BASE)
|
||||
#if defined (AT32F435Zx) || defined (AT32F435Vx) || defined (AT32F435Rx) || \
|
||||
defined (AT32F437Zx) || defined (AT32F437Vx) || defined (AT32F437Rx)
|
||||
#define UART8 ((usart_type *) UART8_BASE)
|
||||
#endif
|
||||
|
||||
/** @defgroup USART_exported_functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void usart_reset(usart_type* usart_x);
|
||||
void usart_init(usart_type* usart_x, uint32_t baud_rate, usart_data_bit_num_type data_bit, usart_stop_bit_num_type stop_bit);
|
||||
void usart_parity_selection_config(usart_type* usart_x, usart_parity_selection_type parity);
|
||||
void usart_enable(usart_type* usart_x, confirm_state new_state);
|
||||
void usart_transmitter_enable(usart_type* usart_x, confirm_state new_state);
|
||||
void usart_receiver_enable(usart_type* usart_x, confirm_state new_state);
|
||||
void usart_clock_config(usart_type* usart_x, usart_clock_polarity_type clk_pol, usart_clock_phase_type clk_pha, usart_lbcp_type clk_lb);
|
||||
void usart_clock_enable(usart_type* usart_x, confirm_state new_state);
|
||||
void usart_interrupt_enable(usart_type* usart_x, uint32_t usart_int, confirm_state new_state);
|
||||
void usart_dma_transmitter_enable(usart_type* usart_x, confirm_state new_state);
|
||||
void usart_dma_receiver_enable(usart_type* usart_x, confirm_state new_state);
|
||||
void usart_wakeup_id_set(usart_type* usart_x, uint8_t usart_id);
|
||||
void usart_wakeup_mode_set(usart_type* usart_x, usart_wakeup_mode_type wakeup_mode);
|
||||
void usart_receiver_mute_enable(usart_type* usart_x, confirm_state new_state);
|
||||
void usart_break_bit_num_set(usart_type* usart_x, usart_break_bit_num_type break_bit);
|
||||
void usart_lin_mode_enable(usart_type* usart_x, confirm_state new_state);
|
||||
void usart_data_transmit(usart_type* usart_x, uint16_t data);
|
||||
uint16_t usart_data_receive(usart_type* usart_x);
|
||||
void usart_break_send(usart_type* usart_x);
|
||||
void usart_smartcard_guard_time_set(usart_type* usart_x, uint8_t guard_time_val);
|
||||
void usart_irda_smartcard_division_set(usart_type* usart_x, uint8_t div_val);
|
||||
void usart_smartcard_mode_enable(usart_type* usart_x, confirm_state new_state);
|
||||
void usart_smartcard_nack_set(usart_type* usart_x, confirm_state new_state);
|
||||
void usart_single_line_halfduplex_select(usart_type* usart_x, confirm_state new_state);
|
||||
void usart_irda_mode_enable(usart_type* usart_x, confirm_state new_state);
|
||||
void usart_irda_low_power_enable(usart_type* usart_x, confirm_state new_state);
|
||||
void usart_hardware_flow_control_set(usart_type* usart_x,usart_hardware_flow_control_type flow_state);
|
||||
flag_status usart_flag_get(usart_type* usart_x, uint32_t flag);
|
||||
void usart_flag_clear(usart_type* usart_x, uint32_t flag);
|
||||
void usart_rs485_delay_time_config(usart_type* usart_x, uint8_t start_delay_time, uint8_t complete_delay_time);
|
||||
void usart_transmit_receive_pin_swap(usart_type* usart_x, confirm_state new_state);
|
||||
void usart_id_bit_num_set(usart_type* usart_x, usart_identification_bit_num_type id_bit_num);
|
||||
void usart_de_polarity_set(usart_type* usart_x, usart_de_polarity_type de_polarity);
|
||||
void usart_rs485_mode_enable(usart_type* usart_x, confirm_state new_state);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,195 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file at32f435_437_wdt.h
|
||||
* @brief at32f435_437 wdt header file
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __AT32F435_437_WDT_H
|
||||
#define __AT32F435_437_WDT_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "at32f435_437.h"
|
||||
|
||||
/** @addtogroup AT32F435_437_periph_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup WDT
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup WDT_flags_definition
|
||||
* @brief wdt flag
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define WDT_DIVF_UPDATE_FLAG ((uint16_t)0x0001) /*!< wdt division value update complete flag */
|
||||
#define WDT_RLDF_UPDATE_FLAG ((uint16_t)0x0002) /*!< wdt reload value update complete flag */
|
||||
#define WDT_WINF_UPDATE_FLAG ((uint16_t)0x0004) /*!< wdt window value update complete flag */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup WDT_exported_types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief wdt division value type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
WDT_CLK_DIV_4 = 0x00, /*!< wdt clock divider value is 4 */
|
||||
WDT_CLK_DIV_8 = 0x01, /*!< wdt clock divider value is 8 */
|
||||
WDT_CLK_DIV_16 = 0x02, /*!< wdt clock divider value is 16 */
|
||||
WDT_CLK_DIV_32 = 0x03, /*!< wdt clock divider value is 32 */
|
||||
WDT_CLK_DIV_64 = 0x04, /*!< wdt clock divider value is 64 */
|
||||
WDT_CLK_DIV_128 = 0x05, /*!< wdt clock divider value is 128 */
|
||||
WDT_CLK_DIV_256 = 0x06 /*!< wdt clock divider value is 256 */
|
||||
} wdt_division_type;
|
||||
|
||||
/**
|
||||
* @brief wdt cmd value type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
WDT_CMD_LOCK = 0x0000, /*!< disable write protection command */
|
||||
WDT_CMD_UNLOCK = 0x5555, /*!< enable write protection command */
|
||||
WDT_CMD_ENABLE = 0xCCCC, /*!< enable wdt command */
|
||||
WDT_CMD_RELOAD = 0xAAAA /*!< reload command */
|
||||
} wdt_cmd_value_type;
|
||||
|
||||
/**
|
||||
* @brief type define wdt register all
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
|
||||
/**
|
||||
* @brief wdt cmd register, offset:0x00
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t cmd;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t cmd : 16;/* [15:0] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:16] */
|
||||
} cmd_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief wdt div register, offset:0x04
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t div;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t div : 3; /* [2:0] */
|
||||
__IO uint32_t reserved1 : 29;/* [31:3] */
|
||||
} div_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief wdt rld register, offset:0x08
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t rld;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t rld : 12;/* [11:0] */
|
||||
__IO uint32_t reserved1 : 20;/* [31:12] */
|
||||
} rld_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief wdt sts register, offset:0x0C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t sts;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t divf : 1; /* [0] */
|
||||
__IO uint32_t rldf : 1; /* [1] */
|
||||
__IO uint32_t reserved1 : 30;/* [31:2] */
|
||||
} sts_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief wdt win register, offset:0x10
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t win;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t win : 12;/* [11:0] */
|
||||
__IO uint32_t reserved1 : 20;/* [31:12] */
|
||||
} win_bit;
|
||||
};
|
||||
} wdt_type;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#define WDT ((wdt_type *) WDT_BASE)
|
||||
|
||||
/** @defgroup WDT_exported_functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void wdt_enable(void);
|
||||
void wdt_counter_reload(void);
|
||||
void wdt_reload_value_set(uint16_t reload_value);
|
||||
void wdt_divider_set(wdt_division_type division);
|
||||
void wdt_register_write_enable( confirm_state new_state);
|
||||
flag_status wdt_flag_get(uint16_t wdt_flag);
|
||||
void wdt_window_counter_set(uint16_t window_cnt);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,156 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file at32f435_437_wwdt.h
|
||||
* @brief at32f435_437 wwdt header file
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __AT32F435_437_WWDT_H
|
||||
#define __AT32F435_437_WWDT_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "at32f435_437.h"
|
||||
|
||||
/** @addtogroup AT32F435_437_periph_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup WWDT
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup WWDT_enable_bit_definition
|
||||
* @brief wwdt enable bit
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define WWDT_EN_BIT ((uint32_t)0x00000080) /*!< wwdt enable bit */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup WWDT_exported_types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief wwdt division type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
WWDT_PCLK1_DIV_4096 = 0x00, /*!< wwdt counter clock = (pclk1/4096)/1) */
|
||||
WWDT_PCLK1_DIV_8192 = 0x01, /*!< wwdt counter clock = (pclk1/4096)/2) */
|
||||
WWDT_PCLK1_DIV_16384 = 0x02, /*!< wwdt counter clock = (pclk1/4096)/4) */
|
||||
WWDT_PCLK1_DIV_32768 = 0x03 /*!< wwdt counter clock = (pclk1/4096)/8) */
|
||||
} wwdt_division_type;
|
||||
|
||||
/**
|
||||
* @brief type define wwdt register all
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
|
||||
/**
|
||||
* @brief wwdt ctrl register, offset:0x00
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ctrl;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t cnt : 7; /* [6:0] */
|
||||
__IO uint32_t wwdten : 1; /* [7] */
|
||||
__IO uint32_t reserved1 : 24;/* [31:8] */
|
||||
} ctrl_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief wwdt cfg register, offset:0x04
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t cfg;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t win : 7; /* [6:0] */
|
||||
__IO uint32_t div : 2; /* [8:7] */
|
||||
__IO uint32_t rldien : 1; /* [9] */
|
||||
__IO uint32_t reserved1 : 22;/* [31:10] */
|
||||
} cfg_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief wwdt cfg register, offset:0x08
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t sts;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t rldf : 1; /* [0] */
|
||||
__IO uint32_t reserved1 : 31;/* [31:1] */
|
||||
} sts_bit;
|
||||
};
|
||||
|
||||
} wwdt_type;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#define WWDT ((wwdt_type *) WWDT_BASE)
|
||||
|
||||
/** @defgroup WWDT_exported_functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void wwdt_reset(void);
|
||||
void wwdt_divider_set(wwdt_division_type division);
|
||||
void wwdt_flag_clear(void);
|
||||
void wwdt_enable(uint8_t wwdt_cnt);
|
||||
void wwdt_interrupt_enable(void);
|
||||
flag_status wwdt_flag_get(void);
|
||||
void wwdt_counter_set(uint8_t wwdt_cnt);
|
||||
void wwdt_window_counter_set(uint8_t window_cnt);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user