302 lines
8.1 KiB
C
302 lines
8.1 KiB
C
/**
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* @file nrf24l01.c
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* @brief NRF24L01+ driver implementation using SPI
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*/
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#include <string.h>
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#include "freertos/FreeRTOS.h"
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#include "freertos/task.h"
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#include "driver/spi_master.h"
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#include "driver/gpio.h"
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#include "esp_log.h"
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#include "nrf24l01.h"
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static const char *TAG = "nrf24";
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/* SPI device handle */
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static spi_device_handle_t nrf_spi = NULL;
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static int nrf_ce_gpio = -1;
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/* Default 5-byte address */
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static const uint8_t default_addr[5] = {0xE7, 0xE7, 0xE7, 0xE7, 0xE7};
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/* SPI transaction helper */
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static uint8_t nrf_spi_transfer(uint8_t byte)
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{
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spi_transaction_t t = {
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.length = 8,
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.tx_buffer = &byte,
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.rx_buffer = &byte,
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};
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spi_device_transmit(nrf_spi, &t);
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return byte;
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}
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/* Write a register */
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static void nrf_write_reg(uint8_t reg, uint8_t value)
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{
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gpio_set_level(nrf_ce_gpio, 0);
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nrf_spi_transfer(NRF_CMD_W_REGISTER | reg);
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nrf_spi_transfer(value);
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}
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/* Read a register */
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static uint8_t nrf_read_reg(uint8_t reg)
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{
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gpio_set_level(nrf_ce_gpio, 0);
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nrf_spi_transfer(NRF_CMD_R_REGISTER | reg);
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return nrf_spi_transfer(NRF_CMD_NOP);
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}
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/* Write multiple bytes to a register (for addresses) */
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static void nrf_write_multi(uint8_t reg, const uint8_t *data, uint8_t len)
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{
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gpio_set_level(nrf_ce_gpio, 0);
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nrf_spi_transfer(NRF_CMD_W_REGISTER | reg);
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for (int i = 0; i < len; i++) {
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nrf_spi_transfer(data[i]);
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}
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}
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/* Read multiple bytes from a register */
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static void nrf_read_multi(uint8_t reg, uint8_t *data, uint8_t len)
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{
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gpio_set_level(nrf_ce_gpio, 0);
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nrf_spi_transfer(NRF_CMD_R_REGISTER | reg);
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for (int i = 0; i < len; i++) {
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data[i] = nrf_spi_transfer(NRF_CMD_NOP);
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}
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}
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esp_err_t nrf24_init(int mosi, int miso, int sclk, int cs, int ce, int irq)
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{
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nrf_ce_gpio = ce;
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/* Configure SPI bus */
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spi_bus_config_t bus_cfg = {
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.mosi_io_num = mosi,
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.miso_io_num = miso,
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.sclk_io_num = sclk,
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.quadwp_io_num = -1,
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.quadhd_io_num = -1,
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.max_transfer_sz = 32,
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};
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spi_device_interface_config_t dev_cfg = {
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.mode = 0, /* SPI mode 0: CPOL=0, CPHA=0 */
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.clock_speed_hz = 10 * 1000 * 1000, /* 10 MHz */
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.spics_io_num = cs,
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.queue_size = 1,
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.flags = SPI_DEVICE_HALFDUPLEX,
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};
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ESP_ERROR_CHECK(spi_bus_initialize(SPI2_HOST, &bus_cfg, SPI_DMA_CH_AUTO));
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ESP_ERROR_CHECK(spi_bus_add_device(SPI2_HOST, &dev_cfg, &nrf_spi));
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/* Configure CE pin */
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gpio_config_t ce_conf = {
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.pin_bit_mask = (1ULL << ce),
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.mode = GPIO_MODE_OUTPUT,
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.pull_up_en = GPIO_PULLUP_DISABLE,
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.pull_down_en = GPIO_PULLDOWN_DISABLE,
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.intr_type = GPIO_INTR_DISABLE,
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};
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gpio_config(&ce_conf);
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gpio_set_level(ce, 0);
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/* Wait for power-on */
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vTaskDelay(pdMS_TO_TICKS(5));
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/* Configure NRF24L01 */
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/* Disable auto-ack on all pipes (we use ACK payload) */
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nrf_write_reg(NRF_REG_EN_AA, 0x01); /* Only pipe 0 auto-ack */
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nrf_write_reg(NRF_REG_EN_RXADDR, 0x01); /* Enable pipe 0 */
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nrf_write_reg(NRF_REG_SETUP_AW, 0x03); /* 5-byte address */
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nrf_write_reg(NRF_REG_SETUP_RETR, 0x1A); /* 250us retry, 10 retransmits */
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nrf_write_reg(NRF_REG_RF_CH, 100); /* Default channel */
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nrf_write_reg(NRF_REG_RF_SETUP, 0x06); /* 1Mbps, 0dBm */
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nrf_write_reg(NRF_REG_STATUS, 0x70); /* Clear interrupts */
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/* Set default address */
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nrf_write_multi(NRF_REG_TX_ADDR, default_addr, 5);
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nrf_write_multi(NRF_REG_RX_ADDR_P0, default_addr, 5);
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/* Set payload width for pipe 0 */
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nrf_write_reg(NRF_REG_RX_PW_P0, 32);
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/* Enable dynamic payload length and ACK payload */
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nrf_write_reg(NRF_REG_FEATURE, 0x06); /* EN_DPL | EN_ACK_PAY */
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nrf_write_reg(NRF_REG_DYNPD, 0x01); /* DPL for pipe 0 */
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/* Power up in RX mode by default */
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nrf_write_reg(NRF_REG_CONFIG, NRF_CONFIG_EN_CRC | NRF_CONFIG_CRCO | NRF_CONFIG_PWR_UP | NRF_CONFIG_PRIM_RX);
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gpio_set_level(ce, 1);
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vTaskDelay(pdMS_TO_TICKS(2));
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ESP_LOGI(TAG, "NRF24L01 initialized");
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return ESP_OK;
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}
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void nrf24_set_channel(uint8_t channel)
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{
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if (channel > 125) channel = 125;
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nrf_write_reg(NRF_REG_RF_CH, channel);
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}
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void nrf24_set_data_rate(nrf_data_rate_t rate)
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{
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uint8_t rf_setup = nrf_read_reg(NRF_REG_RF_SETUP);
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rf_setup &= 0xD7; /* Clear RF_DR bits */
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switch (rate) {
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case NRF_1MBPS:
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rf_setup |= (0 << 3); /* RF_DR_LOW=0, RF_DR_HIGH=0 */
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break;
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case NRF_2MBPS:
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rf_setup |= (1 << 3); /* RF_DR_HIGH=1 */
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break;
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case NRF_250KBPS:
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rf_setup |= (1 << 5) | (0 << 3); /* RF_DR_LOW=1 */
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break;
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}
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nrf_write_reg(NRF_REG_RF_SETUP, rf_setup);
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}
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void nrf24_set_power(nrf_pa_power_t power)
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{
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uint8_t rf_setup = nrf_read_reg(NRF_REG_RF_SETUP);
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rf_setup &= 0xF9; /* Clear PWR bits */
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rf_setup |= (power << 1);
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nrf_write_reg(NRF_REG_RF_SETUP, rf_setup);
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}
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void nrf24_set_tx_addr(const uint8_t *addr)
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{
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nrf_write_multi(NRF_REG_TX_ADDR, addr, 5);
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}
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void nrf24_set_rx_addr(const uint8_t *addr, uint8_t pipe)
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{
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if (pipe == 0) {
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nrf_write_multi(NRF_REG_RX_ADDR_P0, addr, 5);
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} else if (pipe <= 5) {
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nrf_write_reg(NRF_REG_RX_ADDR_P0 + pipe, addr[4]); /* Only LSB */
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}
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}
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void nrf24_power_up_tx(void)
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{
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uint8_t config = nrf_read_reg(NRF_REG_CONFIG);
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config &= ~NRF_CONFIG_PRIM_RX; /* Set PTX */
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config |= NRF_CONFIG_PWR_UP;
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nrf_write_reg(NRF_REG_CONFIG, config);
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gpio_set_level(nrf_ce_gpio, 0);
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vTaskDelay(pdMS_TO_TICKS(2));
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}
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void nrf24_power_up_rx(void)
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{
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uint8_t config = nrf_read_reg(NRF_REG_CONFIG);
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config |= NRF_CONFIG_PWR_UP | NRF_CONFIG_PRIM_RX;
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nrf_write_reg(NRF_REG_CONFIG, config);
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gpio_set_level(nrf_ce_gpio, 1);
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vTaskDelay(pdMS_TO_TICKS(2));
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}
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void nrf24_power_down(void)
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{
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uint8_t config = nrf_read_reg(NRF_REG_CONFIG);
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config &= ~NRF_CONFIG_PWR_UP;
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nrf_write_reg(NRF_REG_CONFIG, config);
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gpio_set_level(nrf_ce_gpio, 0);
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}
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esp_err_t nrf24_tx_payload(const uint8_t *data, uint8_t len)
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{
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if (len > 32) len = 32;
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nrf24_power_up_tx();
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/* Write payload */
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gpio_set_level(nrf_ce_gpio, 0);
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nrf_spi_transfer(NRF_CMD_W_TX_PAYLOAD);
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for (int i = 0; i < len; i++) {
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nrf_spi_transfer(data[i]);
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}
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/* Pulse CE to start transmission */
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gpio_set_level(nrf_ce_gpio, 1);
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vTaskDelay(pdMS_TO_TICKS(1));
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gpio_set_level(nrf_ce_gpio, 0);
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/* Wait for TX_DS or MAX_RT */
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int timeout = 100;
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while (timeout--) {
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uint8_t status = nrf24_get_status();
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if (status & (1 << 5)) { /* TX_DS */
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nrf_write_reg(NRF_REG_STATUS, 0x20); /* Clear TX_DS */
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return ESP_OK;
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}
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if (status & (1 << 4)) { /* MAX_RT */
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nrf_write_reg(NRF_REG_STATUS, 0x10); /* Clear MAX_RT */
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nrf24_flush_tx();
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return ESP_FAIL;
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}
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vTaskDelay(pdMS_TO_TICKS(1));
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}
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return ESP_ERR_TIMEOUT;
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}
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esp_err_t nrf24_rx_payload(uint8_t *data, uint8_t *len)
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{
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if (!nrf24_data_available()) {
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return ESP_ERR_NOT_FOUND;
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}
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/* Get payload width */
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gpio_set_level(nrf_ce_gpio, 0);
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nrf_spi_transfer(NRF_CMD_R_RX_PL_WID);
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*len = nrf_spi_transfer(NRF_CMD_NOP);
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if (*len > 32 || *len == 0) {
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nrf24_flush_rx();
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return ESP_ERR_INVALID_SIZE;
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}
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/* Read payload */
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gpio_set_level(nrf_ce_gpio, 0);
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nrf_spi_transfer(NRF_CMD_R_RX_PAYLOAD);
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for (int i = 0; i < *len; i++) {
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data[i] = nrf_spi_transfer(NRF_CMD_NOP);
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}
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/* Clear RX_DR */
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nrf_write_reg(NRF_REG_STATUS, 0x40);
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return ESP_OK;
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}
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uint8_t nrf24_data_available(void)
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{
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uint8_t status = nrf24_get_status();
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return (status & (1 << 6)) ? 1 : 0; /* RX_DR */
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}
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uint8_t nrf24_get_status(void)
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{
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return nrf_spi_transfer(NRF_CMD_NOP);
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}
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void nrf24_flush_tx(void)
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{
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gpio_set_level(nrf_ce_gpio, 0);
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nrf_spi_transfer(NRF_CMD_FLUSH_TX);
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}
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void nrf24_flush_rx(void)
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{
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gpio_set_level(nrf_ce_gpio, 0);
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nrf_spi_transfer(NRF_CMD_FLUSH_RX);
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}
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