1016 lines
27 KiB
NASM
1016 lines
27 KiB
NASM
;--------------------------------------------------------
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; File Created by SDCC : free open source ANSI-C Compiler
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; Version 4.2.0 #13081 (Linux)
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;--------------------------------------------------------
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.module nrf24l01
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.optsdcc -mmcs51 --model-small
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;--------------------------------------------------------
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; Public variables in this module
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;--------------------------------------------------------
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.globl _gpio_write
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.globl _gpio_set_mode
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.globl _delay_ms
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.globl _delay_us
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.globl _spi_transfer
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.globl _EADC
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.globl _ET1
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.globl _ET0
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.globl _ES
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.globl _EA
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.globl _REN
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.globl _RI
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.globl _TI
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.globl _TR1
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.globl _TF1
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.globl _IT0
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.globl _IE0
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.globl _TR0
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.globl _TF0
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.globl _CMPCR2
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.globl _CMPCR1
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.globl _TA
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.globl _IRCBAND_REG
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.globl _IAP_TPS
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.globl _IAP_CONTR
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.globl _IAP_TRIG
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.globl _IAP_CMD
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.globl _IAP_ADDRL
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.globl _IAP_ADDRH
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.globl _IAP_DATA
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.globl _WDT_CONTR
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.globl _PCA_PWM3
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.globl _PCA_PWM2
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.globl _PCA_PWM1
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.globl _PCA_PWM0
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.globl _CCAP3L
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.globl _CCAP2L
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.globl _CCAP1L
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.globl _CCAP0L
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.globl _CCAPM3
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.globl _CCAPM2
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.globl _CCAPM1
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.globl _CCAPM0
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.globl _CMOD
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.globl _CCON
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.globl _ADCTIM_X
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.globl _ADCCFG
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.globl _ADC_RESL
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.globl _ADC_RES
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.globl _ADC_CONTR
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.globl _SPDAT
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.globl _SPCTL
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.globl _SPSTAT
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.globl _IP2H
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.globl _IP2
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.globl _IP
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.globl _IE2
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.globl _IE
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.globl _BRT
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.globl _P_SW1
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.globl _SADEN
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.globl _SADDR
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.globl _S2BUF
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.globl _S2CON
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.globl _SBUF
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.globl _SCON
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.globl _TM4PS_X
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.globl _TM3PS_X
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.globl _TM2PS_X
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.globl _T4T3M
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.globl _T4L
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.globl _T4H
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.globl _T3L
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.globl _T3H
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.globl _T2L
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.globl _T2H
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.globl _INTCLKO
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.globl _AUXR
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.globl _TH1
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.globl _TH0
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.globl _TL1
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.globl _TL0
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.globl _TMOD
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.globl _TCON
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.globl _P_SW2
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.globl _P5M0
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.globl _P5M1
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.globl _P4M0
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.globl _P4M1
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.globl _P3M0
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.globl _P3M1
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.globl _P2M0
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.globl _P2M1
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.globl _P1M0
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.globl _P1M1
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.globl _P0M0
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.globl _P0M1
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.globl _PSW
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.globl _B
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.globl _ACC
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.globl _PCON
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.globl _DPH
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.globl _DPL
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.globl _SP
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.globl _P5
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.globl _P4
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.globl _P3
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.globl _P2
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.globl _P1
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.globl _P0
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.globl _g_nrf_status
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.globl _nrf24_init
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.globl _nrf24_check
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.globl _nrf24_set_channel
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.globl _nrf24_set_address
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.globl _nrf24_set_rx_mode
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.globl _nrf24_data_ready
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.globl _nrf24_write_ack_payload
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.globl _nrf24_irq_handler
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;--------------------------------------------------------
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; special function registers
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;--------------------------------------------------------
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.area RSEG (ABS,DATA)
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.org 0x0000
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_P0 = 0x0080
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_P1 = 0x0090
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_P2 = 0x00a0
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_P3 = 0x00b0
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_P4 = 0x00c0
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_P5 = 0x00c8
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_SP = 0x0081
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_DPL = 0x0082
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_DPH = 0x0083
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_PCON = 0x0087
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_ACC = 0x00e0
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_B = 0x00f0
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_PSW = 0x00d0
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_P0M1 = 0x0093
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_P0M0 = 0x0094
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_P1M1 = 0x0091
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_P1M0 = 0x0092
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_P2M1 = 0x0095
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_P2M0 = 0x0096
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_P3M1 = 0x00b1
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_P3M0 = 0x00b2
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_P4M1 = 0x00b3
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_P4M0 = 0x00b4
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_P5M1 = 0x00c9
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_P5M0 = 0x00ca
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_P_SW2 = 0x00ba
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_TCON = 0x0088
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_TMOD = 0x0089
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_TL0 = 0x008a
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_TL1 = 0x008b
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_TH0 = 0x008c
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_TH1 = 0x008d
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_AUXR = 0x008e
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_INTCLKO = 0x008f
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_T2H = 0x00d6
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_T2L = 0x00d7
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_T3H = 0x00d4
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_T3L = 0x00d5
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_T4H = 0x00d2
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_T4L = 0x00d3
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_T4T3M = 0x00d1
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_TM2PS_X = 0xfea1
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_TM3PS_X = 0xfea2
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_TM4PS_X = 0xfea3
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_SCON = 0x0098
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_SBUF = 0x0099
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_S2CON = 0x009a
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_S2BUF = 0x009b
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_SADDR = 0x00a9
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_SADEN = 0x00b9
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_P_SW1 = 0x00a2
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_BRT = 0x009c
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_IE = 0x00a8
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_IE2 = 0x00af
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_IP = 0x00b8
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_IP2 = 0x00b6
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_IP2H = 0x00b7
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_SPSTAT = 0x00cd
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_SPCTL = 0x00ce
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_SPDAT = 0x00cf
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_ADC_CONTR = 0x00bc
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_ADC_RES = 0x00bd
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_ADC_RESL = 0x00be
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_ADCCFG = 0x00de
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_ADCTIM_X = 0xfea8
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_CCON = 0x00d8
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_CMOD = 0x00d9
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_CCAPM0 = 0x00da
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_CCAPM1 = 0x00db
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_CCAPM2 = 0x00dc
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_CCAPM3 = 0x00dd
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_CCAP0L = 0x00ea
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_CCAP1L = 0x00eb
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_CCAP2L = 0x00ec
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_CCAP3L = 0x00ed
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_PCA_PWM0 = 0x00f2
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_PCA_PWM1 = 0x00f3
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_PCA_PWM2 = 0x00f4
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_PCA_PWM3 = 0x00f5
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_WDT_CONTR = 0x00c1
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_IAP_DATA = 0x00c2
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_IAP_ADDRH = 0x00c3
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_IAP_ADDRL = 0x00c4
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_IAP_CMD = 0x00c5
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_IAP_TRIG = 0x00c6
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_IAP_CONTR = 0x00c7
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_IAP_TPS = 0x00f7
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_IRCBAND_REG = 0x009d
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_TA = 0x00ae
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_CMPCR1 = 0x00e6
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_CMPCR2 = 0x00e7
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;--------------------------------------------------------
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; special function bits
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;--------------------------------------------------------
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.area RSEG (ABS,DATA)
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.org 0x0000
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_TF0 = 0x008d
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_TR0 = 0x008c
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_IE0 = 0x0089
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_IT0 = 0x0088
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_TF1 = 0x008f
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_TR1 = 0x008e
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_TI = 0x0099
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_RI = 0x0098
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_REN = 0x009c
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_EA = 0x00af
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_ES = 0x00ac
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_ET0 = 0x00a9
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_ET1 = 0x00ab
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_EADC = 0x00ad
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;--------------------------------------------------------
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; overlayable register banks
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;--------------------------------------------------------
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.area REG_BANK_0 (REL,OVR,DATA)
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.ds 8
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;--------------------------------------------------------
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; internal ram data
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;--------------------------------------------------------
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.area DSEG (DATA)
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_nrf_w_reg_PARM_2:
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.ds 1
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_nrf_w_buf_PARM_2:
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.ds 3
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_nrf_w_buf_PARM_3:
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.ds 1
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_nrf_r_buf_PARM_2:
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.ds 3
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_nrf_r_buf_PARM_3:
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.ds 1
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_nrf24_check_buf_65536_33:
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.ds 5
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_nrf24_check_rb_65536_33:
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.ds 5
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;--------------------------------------------------------
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; overlayable items in internal ram
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;--------------------------------------------------------
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;--------------------------------------------------------
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; indirectly addressable internal ram data
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;--------------------------------------------------------
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.area ISEG (DATA)
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;--------------------------------------------------------
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; absolute internal ram data
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;--------------------------------------------------------
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.area IABS (ABS,DATA)
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.area IABS (ABS,DATA)
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;--------------------------------------------------------
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; bit data
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;--------------------------------------------------------
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.area BSEG (BIT)
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;--------------------------------------------------------
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; paged external ram data
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;--------------------------------------------------------
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.area PSEG (PAG,XDATA)
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;--------------------------------------------------------
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; external ram data
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;--------------------------------------------------------
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.area XSEG (XDATA)
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_g_nrf_status::
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.ds 36
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;--------------------------------------------------------
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; absolute external ram data
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;--------------------------------------------------------
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.area XABS (ABS,XDATA)
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;--------------------------------------------------------
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; external initialized ram data
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;--------------------------------------------------------
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.area XISEG (XDATA)
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.area HOME (CODE)
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.area GSINIT0 (CODE)
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.area GSINIT1 (CODE)
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.area GSINIT2 (CODE)
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.area GSINIT3 (CODE)
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.area GSINIT4 (CODE)
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.area GSINIT5 (CODE)
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.area GSINIT (CODE)
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.area GSFINAL (CODE)
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.area CSEG (CODE)
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;--------------------------------------------------------
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; global & static initialisations
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;--------------------------------------------------------
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.area HOME (CODE)
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.area GSINIT (CODE)
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.area GSFINAL (CODE)
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.area GSINIT (CODE)
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;--------------------------------------------------------
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; Home
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;--------------------------------------------------------
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.area HOME (CODE)
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.area HOME (CODE)
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;--------------------------------------------------------
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; code
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;--------------------------------------------------------
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.area CSEG (CODE)
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;------------------------------------------------------------
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;Allocation info for local variables in function 'nrf_w_reg'
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;------------------------------------------------------------
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;val Allocated with name '_nrf_w_reg_PARM_2'
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;reg Allocated to registers r7
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;r Allocated to registers r7
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;------------------------------------------------------------
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; src/nrf24l01.c:21: static uint8_t nrf_w_reg(uint8_t reg, uint8_t val)
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; -----------------------------------------
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; function nrf_w_reg
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; -----------------------------------------
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_nrf_w_reg:
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ar7 = 0x07
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ar6 = 0x06
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ar5 = 0x05
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ar4 = 0x04
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ar3 = 0x03
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ar2 = 0x02
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ar1 = 0x01
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ar0 = 0x00
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mov r7,dpl
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; src/nrf24l01.c:24: CSN_L();
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mov _gpio_write_PARM_2,#0x04
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mov _gpio_write_PARM_3,#0x00
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mov dpl,#0x05
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push ar7
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lcall _gpio_write
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pop ar7
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; src/nrf24l01.c:25: r = spi_transfer(reg);
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mov dpl,r7
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lcall _spi_transfer
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mov r7,dpl
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; src/nrf24l01.c:26: spi_transfer(val);
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mov dpl,_nrf_w_reg_PARM_2
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push ar7
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lcall _spi_transfer
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; src/nrf24l01.c:27: CSN_H();
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mov _gpio_write_PARM_2,#0x04
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mov _gpio_write_PARM_3,#0x01
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mov dpl,#0x05
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lcall _gpio_write
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pop ar7
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; src/nrf24l01.c:28: return r;
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mov dpl,r7
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; src/nrf24l01.c:29: }
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ret
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;------------------------------------------------------------
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;Allocation info for local variables in function 'nrf_w_buf'
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;------------------------------------------------------------
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;buf Allocated with name '_nrf_w_buf_PARM_2'
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;len Allocated with name '_nrf_w_buf_PARM_3'
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;reg Allocated to registers r7
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;r Allocated to registers r7
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;------------------------------------------------------------
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; src/nrf24l01.c:31: static uint8_t nrf_w_buf(uint8_t reg, const uint8_t *buf, uint8_t len)
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; -----------------------------------------
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; function nrf_w_buf
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; -----------------------------------------
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_nrf_w_buf:
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mov r7,dpl
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; src/nrf24l01.c:34: CSN_L();
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mov _gpio_write_PARM_2,#0x04
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mov _gpio_write_PARM_3,#0x00
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mov dpl,#0x05
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push ar7
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lcall _gpio_write
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pop ar7
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; src/nrf24l01.c:35: r = spi_transfer(reg);
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mov dpl,r7
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lcall _spi_transfer
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mov r7,dpl
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; src/nrf24l01.c:36: while (len--) spi_transfer(*buf++);
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mov r4,_nrf_w_buf_PARM_2
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mov r5,(_nrf_w_buf_PARM_2 + 1)
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mov r6,(_nrf_w_buf_PARM_2 + 2)
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mov r3,_nrf_w_buf_PARM_3
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00101$:
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mov ar2,r3
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dec r3
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mov a,r2
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jz 00103$
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mov dpl,r4
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mov dph,r5
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mov b,r6
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lcall __gptrget
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mov r2,a
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inc dptr
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mov r4,dpl
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mov r5,dph
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mov dpl,r2
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push ar7
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push ar6
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push ar5
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push ar4
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push ar3
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lcall _spi_transfer
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pop ar3
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pop ar4
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pop ar5
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pop ar6
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pop ar7
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sjmp 00101$
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00103$:
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; src/nrf24l01.c:37: CSN_H();
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mov _gpio_write_PARM_2,#0x04
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mov _gpio_write_PARM_3,#0x01
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mov dpl,#0x05
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push ar7
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lcall _gpio_write
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pop ar7
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; src/nrf24l01.c:38: return r;
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mov dpl,r7
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; src/nrf24l01.c:39: }
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ret
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;------------------------------------------------------------
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;Allocation info for local variables in function 'nrf_r_reg'
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;------------------------------------------------------------
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;reg Allocated to registers r7
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;v Allocated to registers r7
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;------------------------------------------------------------
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; src/nrf24l01.c:41: static uint8_t nrf_r_reg(uint8_t reg)
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; -----------------------------------------
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; function nrf_r_reg
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; -----------------------------------------
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_nrf_r_reg:
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mov r7,dpl
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; src/nrf24l01.c:44: CSN_L();
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mov _gpio_write_PARM_2,#0x04
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mov _gpio_write_PARM_3,#0x00
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mov dpl,#0x05
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push ar7
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lcall _gpio_write
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pop ar7
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; src/nrf24l01.c:45: spi_transfer(reg);
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mov dpl,r7
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lcall _spi_transfer
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; src/nrf24l01.c:46: v = spi_transfer(0xFF);
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mov dpl,#0xff
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lcall _spi_transfer
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mov r7,dpl
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; src/nrf24l01.c:47: CSN_H();
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mov _gpio_write_PARM_2,#0x04
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mov _gpio_write_PARM_3,#0x01
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mov dpl,#0x05
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push ar7
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lcall _gpio_write
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pop ar7
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; src/nrf24l01.c:48: return v;
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mov dpl,r7
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; src/nrf24l01.c:49: }
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ret
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;------------------------------------------------------------
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;Allocation info for local variables in function 'nrf_r_buf'
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;------------------------------------------------------------
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;buf Allocated with name '_nrf_r_buf_PARM_2'
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;len Allocated with name '_nrf_r_buf_PARM_3'
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;reg Allocated to registers r7
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;r Allocated to registers r7
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;------------------------------------------------------------
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; src/nrf24l01.c:51: static uint8_t nrf_r_buf(uint8_t reg, uint8_t *buf, uint8_t len)
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; -----------------------------------------
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; function nrf_r_buf
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; -----------------------------------------
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_nrf_r_buf:
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mov r7,dpl
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; src/nrf24l01.c:54: CSN_L();
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mov _gpio_write_PARM_2,#0x04
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mov _gpio_write_PARM_3,#0x00
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mov dpl,#0x05
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push ar7
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lcall _gpio_write
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pop ar7
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; src/nrf24l01.c:55: r = spi_transfer(reg);
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mov dpl,r7
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lcall _spi_transfer
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mov r7,dpl
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; src/nrf24l01.c:56: while (len--) *buf++ = spi_transfer(0xFF);
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mov r4,_nrf_r_buf_PARM_2
|
|
mov r5,(_nrf_r_buf_PARM_2 + 1)
|
|
mov r6,(_nrf_r_buf_PARM_2 + 2)
|
|
mov r3,_nrf_r_buf_PARM_3
|
|
00101$:
|
|
mov ar2,r3
|
|
dec r3
|
|
mov a,r2
|
|
jz 00103$
|
|
mov dpl,#0xff
|
|
push ar7
|
|
push ar6
|
|
push ar5
|
|
push ar4
|
|
push ar3
|
|
lcall _spi_transfer
|
|
mov r2,dpl
|
|
pop ar3
|
|
pop ar4
|
|
pop ar5
|
|
pop ar6
|
|
pop ar7
|
|
mov dpl,r4
|
|
mov dph,r5
|
|
mov b,r6
|
|
mov a,r2
|
|
lcall __gptrput
|
|
inc dptr
|
|
mov r4,dpl
|
|
mov r5,dph
|
|
sjmp 00101$
|
|
00103$:
|
|
; src/nrf24l01.c:57: CSN_H();
|
|
mov _gpio_write_PARM_2,#0x04
|
|
mov _gpio_write_PARM_3,#0x01
|
|
mov dpl,#0x05
|
|
push ar7
|
|
lcall _gpio_write
|
|
pop ar7
|
|
; src/nrf24l01.c:58: return r;
|
|
mov dpl,r7
|
|
; src/nrf24l01.c:59: }
|
|
ret
|
|
;------------------------------------------------------------
|
|
;Allocation info for local variables in function 'nrf_flush_rx'
|
|
;------------------------------------------------------------
|
|
; src/nrf24l01.c:61: static void nrf_flush_rx(void) { CSN_L(); spi_transfer(NRF_CMD_FLUSH_RX); CSN_H(); }
|
|
; -----------------------------------------
|
|
; function nrf_flush_rx
|
|
; -----------------------------------------
|
|
_nrf_flush_rx:
|
|
mov _gpio_write_PARM_2,#0x04
|
|
mov _gpio_write_PARM_3,#0x00
|
|
mov dpl,#0x05
|
|
lcall _gpio_write
|
|
mov dpl,#0xe2
|
|
lcall _spi_transfer
|
|
mov _gpio_write_PARM_2,#0x04
|
|
mov _gpio_write_PARM_3,#0x01
|
|
mov dpl,#0x05
|
|
ljmp _gpio_write
|
|
;------------------------------------------------------------
|
|
;Allocation info for local variables in function 'nrf_flush_tx'
|
|
;------------------------------------------------------------
|
|
; src/nrf24l01.c:62: static void nrf_flush_tx(void) { CSN_L(); spi_transfer(NRF_CMD_FLUSH_TX); CSN_H(); }
|
|
; -----------------------------------------
|
|
; function nrf_flush_tx
|
|
; -----------------------------------------
|
|
_nrf_flush_tx:
|
|
mov _gpio_write_PARM_2,#0x04
|
|
mov _gpio_write_PARM_3,#0x00
|
|
mov dpl,#0x05
|
|
lcall _gpio_write
|
|
mov dpl,#0xe1
|
|
lcall _spi_transfer
|
|
mov _gpio_write_PARM_2,#0x04
|
|
mov _gpio_write_PARM_3,#0x01
|
|
mov dpl,#0x05
|
|
ljmp _gpio_write
|
|
;------------------------------------------------------------
|
|
;Allocation info for local variables in function 'nrf24_init'
|
|
;------------------------------------------------------------
|
|
;s Allocated to registers
|
|
;------------------------------------------------------------
|
|
; src/nrf24l01.c:64: void nrf24_init(void)
|
|
; -----------------------------------------
|
|
; function nrf24_init
|
|
; -----------------------------------------
|
|
_nrf24_init:
|
|
; src/nrf24l01.c:67: gpio_set_mode(NRF_CSN_PORT, NRF_CSN_BIT, GPIO_MODE_PUSHPULL);
|
|
mov _gpio_set_mode_PARM_2,#0x04
|
|
mov _gpio_set_mode_PARM_3,#0x01
|
|
mov dpl,#0x05
|
|
lcall _gpio_set_mode
|
|
; src/nrf24l01.c:68: gpio_set_mode(NRF_CE_PORT, NRF_CE_BIT, GPIO_MODE_PUSHPULL);
|
|
mov _gpio_set_mode_PARM_2,#0x06
|
|
mov _gpio_set_mode_PARM_3,#0x01
|
|
mov dpl,#0x01
|
|
lcall _gpio_set_mode
|
|
; src/nrf24l01.c:70: gpio_set_mode(NRF_IRQ_PORT, NRF_IRQ_BIT, GPIO_MODE_INPUT);
|
|
mov _gpio_set_mode_PARM_2,#0x07
|
|
mov _gpio_set_mode_PARM_3,#0x02
|
|
mov dpl,#0x01
|
|
lcall _gpio_set_mode
|
|
; src/nrf24l01.c:72: CE_L();
|
|
mov _gpio_write_PARM_2,#0x06
|
|
mov _gpio_write_PARM_3,#0x00
|
|
mov dpl,#0x01
|
|
lcall _gpio_write
|
|
; src/nrf24l01.c:73: CSN_H();
|
|
mov _gpio_write_PARM_2,#0x04
|
|
mov _gpio_write_PARM_3,#0x01
|
|
mov dpl,#0x05
|
|
lcall _gpio_write
|
|
; src/nrf24l01.c:74: delay_ms(100);
|
|
mov dptr,#0x0064
|
|
lcall _delay_ms
|
|
; src/nrf24l01.c:77: nrf_w_buf(NRF_CMD_W_REGISTER + NRF_REG_RX_ADDR_P0, DEFAULT_ADDR, 5);
|
|
mov _nrf_w_buf_PARM_2,#_DEFAULT_ADDR
|
|
mov (_nrf_w_buf_PARM_2 + 1),#(_DEFAULT_ADDR >> 8)
|
|
mov (_nrf_w_buf_PARM_2 + 2),#0x80
|
|
mov _nrf_w_buf_PARM_3,#0x05
|
|
mov dpl,#0x2a
|
|
lcall _nrf_w_buf
|
|
; src/nrf24l01.c:78: nrf_w_buf(NRF_CMD_W_REGISTER + NRF_REG_TX_ADDR, DEFAULT_ADDR, 5);
|
|
mov _nrf_w_buf_PARM_2,#_DEFAULT_ADDR
|
|
mov (_nrf_w_buf_PARM_2 + 1),#(_DEFAULT_ADDR >> 8)
|
|
mov (_nrf_w_buf_PARM_2 + 2),#0x80
|
|
mov _nrf_w_buf_PARM_3,#0x05
|
|
mov dpl,#0x30
|
|
lcall _nrf_w_buf
|
|
; src/nrf24l01.c:80: nrf_w_reg(NRF_CMD_W_REGISTER + NRF_REG_EN_AA, 0x01); /* 通道0 自动应答 */
|
|
mov _nrf_w_reg_PARM_2,#0x01
|
|
mov dpl,#0x21
|
|
lcall _nrf_w_reg
|
|
; src/nrf24l01.c:81: nrf_w_reg(NRF_CMD_W_REGISTER + NRF_REG_EN_RXADDR, 0x01);
|
|
mov _nrf_w_reg_PARM_2,#0x01
|
|
mov dpl,#0x22
|
|
lcall _nrf_w_reg
|
|
; src/nrf24l01.c:82: nrf_w_reg(NRF_CMD_W_REGISTER + NRF_REG_SETUP_AW, 0x03); /* 5 字节 */
|
|
mov _nrf_w_reg_PARM_2,#0x03
|
|
mov dpl,#0x23
|
|
lcall _nrf_w_reg
|
|
; src/nrf24l01.c:83: nrf_w_reg(NRF_CMD_W_REGISTER + NRF_REG_SETUP_RETR, 0x1A);
|
|
mov _nrf_w_reg_PARM_2,#0x1a
|
|
mov dpl,#0x24
|
|
lcall _nrf_w_reg
|
|
; src/nrf24l01.c:84: nrf_w_reg(NRF_CMD_W_REGISTER + NRF_REG_RF_CH, DEFAULT_RF_CH);
|
|
mov _nrf_w_reg_PARM_2,#0x4c
|
|
mov dpl,#0x25
|
|
lcall _nrf_w_reg
|
|
; src/nrf24l01.c:85: nrf_w_reg(NRF_CMD_W_REGISTER + NRF_REG_RF_SETUP, 0x0F); /* 0dBm, 2Mbps */
|
|
mov _nrf_w_reg_PARM_2,#0x0f
|
|
mov dpl,#0x26
|
|
lcall _nrf_w_reg
|
|
; src/nrf24l01.c:86: nrf_w_reg(NRF_CMD_W_REGISTER + NRF_REG_RX_PW_P0, NRF_PAYLOAD_LEN);
|
|
mov _nrf_w_reg_PARM_2,#0x20
|
|
mov dpl,#0x31
|
|
lcall _nrf_w_reg
|
|
; src/nrf24l01.c:87: nrf_w_reg(NRF_CMD_W_REGISTER + NRF_REG_DYNPD, 0x01); /* 动态载荷 (P0) */
|
|
mov _nrf_w_reg_PARM_2,#0x01
|
|
mov dpl,#0x3c
|
|
lcall _nrf_w_reg
|
|
; src/nrf24l01.c:88: nrf_w_reg(NRF_CMD_W_REGISTER + NRF_REG_FEATURE, 0x06); /* EN_DPL | EN_ACK_PAY */
|
|
mov _nrf_w_reg_PARM_2,#0x06
|
|
mov dpl,#0x3d
|
|
lcall _nrf_w_reg
|
|
; src/nrf24l01.c:91: nrf_w_reg(NRF_CMD_W_REGISTER + NRF_REG_CONFIG, 0x0F);
|
|
mov _nrf_w_reg_PARM_2,#0x0f
|
|
mov dpl,#0x20
|
|
lcall _nrf_w_reg
|
|
; src/nrf24l01.c:95: uint8_t s = nrf_r_reg(NRF_REG_STATUS);
|
|
mov dpl,#0x07
|
|
lcall _nrf_r_reg
|
|
mov _nrf_w_reg_PARM_2,dpl
|
|
; src/nrf24l01.c:96: nrf_w_reg(NRF_CMD_W_REGISTER + NRF_REG_STATUS, s);
|
|
mov dpl,#0x27
|
|
lcall _nrf_w_reg
|
|
; src/nrf24l01.c:99: g_nrf_status.last_status = 0;
|
|
mov dptr,#_g_nrf_status
|
|
clr a
|
|
movx @dptr,a
|
|
; src/nrf24l01.c:100: g_nrf_status.rx_count = 0;
|
|
mov dptr,#(_g_nrf_status + 0x0001)
|
|
movx @dptr,a
|
|
; src/nrf24l01.c:101: g_nrf_status.ack_pending = 0;
|
|
mov dptr,#(_g_nrf_status + 0x0003)
|
|
movx @dptr,a
|
|
; src/nrf24l01.c:102: }
|
|
ret
|
|
;------------------------------------------------------------
|
|
;Allocation info for local variables in function 'nrf24_check'
|
|
;------------------------------------------------------------
|
|
;buf Allocated with name '_nrf24_check_buf_65536_33'
|
|
;rb Allocated with name '_nrf24_check_rb_65536_33'
|
|
;i Allocated to registers r7
|
|
;------------------------------------------------------------
|
|
; src/nrf24l01.c:104: uint8_t nrf24_check(void)
|
|
; -----------------------------------------
|
|
; function nrf24_check
|
|
; -----------------------------------------
|
|
_nrf24_check:
|
|
; src/nrf24l01.c:106: uint8_t buf[5] = { 0xA5, 0xA5, 0xA5, 0xA5, 0xA5 };
|
|
mov _nrf24_check_buf_65536_33,#0xa5
|
|
mov (_nrf24_check_buf_65536_33 + 0x0001),#0xa5
|
|
mov (_nrf24_check_buf_65536_33 + 0x0002),#0xa5
|
|
mov (_nrf24_check_buf_65536_33 + 0x0003),#0xa5
|
|
mov (_nrf24_check_buf_65536_33 + 0x0004),#0xa5
|
|
; src/nrf24l01.c:108: nrf_w_buf(NRF_CMD_W_REGISTER + NRF_REG_TX_ADDR, buf, 5);
|
|
mov _nrf_w_buf_PARM_2,#_nrf24_check_buf_65536_33
|
|
mov (_nrf_w_buf_PARM_2 + 1),#0x00
|
|
mov (_nrf_w_buf_PARM_2 + 2),#0x40
|
|
mov _nrf_w_buf_PARM_3,#0x05
|
|
mov dpl,#0x30
|
|
lcall _nrf_w_buf
|
|
; src/nrf24l01.c:109: nrf_r_buf(NRF_REG_TX_ADDR, rb, 5);
|
|
mov _nrf_r_buf_PARM_2,#_nrf24_check_rb_65536_33
|
|
mov (_nrf_r_buf_PARM_2 + 1),#0x00
|
|
mov (_nrf_r_buf_PARM_2 + 2),#0x40
|
|
mov _nrf_r_buf_PARM_3,#0x05
|
|
mov dpl,#0x10
|
|
lcall _nrf_r_buf
|
|
; src/nrf24l01.c:110: for (uint8_t i = 0; i < 5; i++) if (rb[i] != 0xA5) return NRF_ERR_CHECK;
|
|
mov r7,#0x00
|
|
00105$:
|
|
cjne r7,#0x05,00121$
|
|
00121$:
|
|
jnc 00103$
|
|
mov a,r7
|
|
add a,#_nrf24_check_rb_65536_33
|
|
mov r1,a
|
|
mov ar6,@r1
|
|
cjne r6,#0xa5,00123$
|
|
sjmp 00106$
|
|
00123$:
|
|
mov dpl,#0x01
|
|
ret
|
|
00106$:
|
|
inc r7
|
|
sjmp 00105$
|
|
00103$:
|
|
; src/nrf24l01.c:112: nrf_w_buf(NRF_CMD_W_REGISTER + NRF_REG_TX_ADDR, DEFAULT_ADDR, 5);
|
|
mov _nrf_w_buf_PARM_2,#_DEFAULT_ADDR
|
|
mov (_nrf_w_buf_PARM_2 + 1),#(_DEFAULT_ADDR >> 8)
|
|
mov (_nrf_w_buf_PARM_2 + 2),#0x80
|
|
mov _nrf_w_buf_PARM_3,#0x05
|
|
mov dpl,#0x30
|
|
lcall _nrf_w_buf
|
|
; src/nrf24l01.c:113: return NRF_OK;
|
|
mov dpl,#0x00
|
|
; src/nrf24l01.c:114: }
|
|
ret
|
|
;------------------------------------------------------------
|
|
;Allocation info for local variables in function 'nrf24_set_channel'
|
|
;------------------------------------------------------------
|
|
;ch Allocated to registers r7
|
|
;------------------------------------------------------------
|
|
; src/nrf24l01.c:116: void nrf24_set_channel(uint8_t ch)
|
|
; -----------------------------------------
|
|
; function nrf24_set_channel
|
|
; -----------------------------------------
|
|
_nrf24_set_channel:
|
|
; src/nrf24l01.c:118: if (ch > 125) ch = 125;
|
|
mov a,dpl
|
|
mov r7,a
|
|
add a,#0xff - 0x7d
|
|
jnc 00102$
|
|
mov r7,#0x7d
|
|
00102$:
|
|
; src/nrf24l01.c:119: nrf_w_reg(NRF_CMD_W_REGISTER + NRF_REG_RF_CH, ch);
|
|
mov _nrf_w_reg_PARM_2,r7
|
|
mov dpl,#0x25
|
|
; src/nrf24l01.c:120: }
|
|
ljmp _nrf_w_reg
|
|
;------------------------------------------------------------
|
|
;Allocation info for local variables in function 'nrf24_set_address'
|
|
;------------------------------------------------------------
|
|
;addr5 Allocated to registers r5 r6 r7
|
|
;------------------------------------------------------------
|
|
; src/nrf24l01.c:122: void nrf24_set_address(const uint8_t *addr5)
|
|
; -----------------------------------------
|
|
; function nrf24_set_address
|
|
; -----------------------------------------
|
|
_nrf24_set_address:
|
|
mov r5,dpl
|
|
mov r6,dph
|
|
mov r7,b
|
|
; src/nrf24l01.c:124: nrf_w_buf(NRF_CMD_W_REGISTER + NRF_REG_RX_ADDR_P0, addr5, 5);
|
|
mov _nrf_w_buf_PARM_2,r5
|
|
mov (_nrf_w_buf_PARM_2 + 1),r6
|
|
mov (_nrf_w_buf_PARM_2 + 2),r7
|
|
mov _nrf_w_buf_PARM_3,#0x05
|
|
mov dpl,#0x2a
|
|
push ar7
|
|
push ar6
|
|
push ar5
|
|
lcall _nrf_w_buf
|
|
pop ar5
|
|
pop ar6
|
|
pop ar7
|
|
; src/nrf24l01.c:125: nrf_w_buf(NRF_CMD_W_REGISTER + NRF_REG_TX_ADDR, addr5, 5);
|
|
mov _nrf_w_buf_PARM_2,r5
|
|
mov (_nrf_w_buf_PARM_2 + 1),r6
|
|
mov (_nrf_w_buf_PARM_2 + 2),r7
|
|
mov _nrf_w_buf_PARM_3,#0x05
|
|
mov dpl,#0x30
|
|
; src/nrf24l01.c:126: }
|
|
ljmp _nrf_w_buf
|
|
;------------------------------------------------------------
|
|
;Allocation info for local variables in function 'nrf24_set_rx_mode'
|
|
;------------------------------------------------------------
|
|
;cfg Allocated to registers
|
|
;------------------------------------------------------------
|
|
; src/nrf24l01.c:128: void nrf24_set_rx_mode(void)
|
|
; -----------------------------------------
|
|
; function nrf24_set_rx_mode
|
|
; -----------------------------------------
|
|
_nrf24_set_rx_mode:
|
|
; src/nrf24l01.c:130: uint8_t cfg = nrf_r_reg(NRF_REG_CONFIG);
|
|
mov dpl,#0x00
|
|
lcall _nrf_r_reg
|
|
mov a,dpl
|
|
; src/nrf24l01.c:131: nrf_w_reg(NRF_CMD_W_REGISTER + NRF_REG_CONFIG, (cfg & 0x7C) | 0x0F); /* PWR_UP, CRC 2B, PRIM_RX */
|
|
anl a,#0x7c
|
|
orl a,#0x0f
|
|
mov _nrf_w_reg_PARM_2,a
|
|
mov dpl,#0x20
|
|
lcall _nrf_w_reg
|
|
; src/nrf24l01.c:132: CE_H();
|
|
mov _gpio_write_PARM_2,#0x06
|
|
mov _gpio_write_PARM_3,#0x01
|
|
mov dpl,#0x01
|
|
lcall _gpio_write
|
|
; src/nrf24l01.c:133: delay_us(130); /* ≥130us 进入接收 */
|
|
mov dptr,#0x0082
|
|
; src/nrf24l01.c:134: }
|
|
ljmp _delay_us
|
|
;------------------------------------------------------------
|
|
;Allocation info for local variables in function 'nrf24_data_ready'
|
|
;------------------------------------------------------------
|
|
;status Allocated to registers r7
|
|
;------------------------------------------------------------
|
|
; src/nrf24l01.c:136: uint8_t nrf24_data_ready(void)
|
|
; -----------------------------------------
|
|
; function nrf24_data_ready
|
|
; -----------------------------------------
|
|
_nrf24_data_ready:
|
|
; src/nrf24l01.c:138: uint8_t status = nrf_r_reg(NRF_REG_STATUS);
|
|
mov dpl,#0x07
|
|
lcall _nrf_r_reg
|
|
; src/nrf24l01.c:139: if (status & NRF_STATUS_RX_DR) {
|
|
mov a,dpl
|
|
mov r7,a
|
|
jnb acc.6,00102$
|
|
; src/nrf24l01.c:141: nrf_r_buf(NRF_CMD_R_RX_PAYLOAD, g_nrf_status.ack_payload, NRF_PAYLOAD_LEN);
|
|
mov _nrf_r_buf_PARM_2,#(_g_nrf_status + 0x0004)
|
|
mov (_nrf_r_buf_PARM_2 + 1),#((_g_nrf_status + 0x0004) >> 8)
|
|
mov (_nrf_r_buf_PARM_2 + 2),#0x00
|
|
mov _nrf_r_buf_PARM_3,#0x20
|
|
mov dpl,#0x61
|
|
push ar7
|
|
lcall _nrf_r_buf
|
|
; src/nrf24l01.c:142: nrf_flush_rx();
|
|
lcall _nrf_flush_rx
|
|
pop ar7
|
|
; src/nrf24l01.c:143: nrf_w_reg(NRF_CMD_W_REGISTER + NRF_REG_STATUS, status);
|
|
mov _nrf_w_reg_PARM_2,r7
|
|
mov dpl,#0x27
|
|
push ar7
|
|
lcall _nrf_w_reg
|
|
pop ar7
|
|
; src/nrf24l01.c:144: g_nrf_status.last_status = status;
|
|
mov dptr,#_g_nrf_status
|
|
mov a,r7
|
|
movx @dptr,a
|
|
; src/nrf24l01.c:145: g_nrf_status.rx_count++;
|
|
mov dptr,#(_g_nrf_status + 0x0001)
|
|
movx a,@dptr
|
|
mov r7,a
|
|
inc r7
|
|
mov dptr,#(_g_nrf_status + 0x0001)
|
|
mov a,r7
|
|
movx @dptr,a
|
|
; src/nrf24l01.c:146: return 1;
|
|
mov dpl,#0x01
|
|
ret
|
|
00102$:
|
|
; src/nrf24l01.c:148: return 0;
|
|
mov dpl,#0x00
|
|
; src/nrf24l01.c:149: }
|
|
ret
|
|
;------------------------------------------------------------
|
|
;Allocation info for local variables in function 'nrf24_write_ack_payload'
|
|
;------------------------------------------------------------
|
|
;buf Allocated to registers r5 r6 r7
|
|
;i Allocated to registers r4
|
|
;------------------------------------------------------------
|
|
; src/nrf24l01.c:151: void nrf24_write_ack_payload(const uint8_t *buf)
|
|
; -----------------------------------------
|
|
; function nrf24_write_ack_payload
|
|
; -----------------------------------------
|
|
_nrf24_write_ack_payload:
|
|
mov r5,dpl
|
|
mov r6,dph
|
|
mov r7,b
|
|
; src/nrf24l01.c:154: CSN_L();
|
|
mov _gpio_write_PARM_2,#0x04
|
|
mov _gpio_write_PARM_3,#0x00
|
|
mov dpl,#0x05
|
|
push ar7
|
|
push ar6
|
|
push ar5
|
|
lcall _gpio_write
|
|
; src/nrf24l01.c:155: spi_transfer(NRF_CMD_W_ACK_PAYLOAD); /* P0 */
|
|
mov dpl,#0xa8
|
|
lcall _spi_transfer
|
|
pop ar5
|
|
pop ar6
|
|
pop ar7
|
|
; src/nrf24l01.c:156: for (uint8_t i = 0; i < NRF_PAYLOAD_LEN; i++) {
|
|
mov r4,#0x00
|
|
00103$:
|
|
cjne r4,#0x20,00116$
|
|
00116$:
|
|
jnc 00101$
|
|
; src/nrf24l01.c:157: spi_transfer(buf[i]);
|
|
mov a,r4
|
|
add a,r5
|
|
mov r1,a
|
|
clr a
|
|
addc a,r6
|
|
mov r2,a
|
|
mov ar3,r7
|
|
mov dpl,r1
|
|
mov dph,r2
|
|
mov b,r3
|
|
lcall __gptrget
|
|
mov dpl,a
|
|
push ar7
|
|
push ar6
|
|
push ar5
|
|
push ar4
|
|
lcall _spi_transfer
|
|
pop ar4
|
|
pop ar5
|
|
pop ar6
|
|
pop ar7
|
|
; src/nrf24l01.c:156: for (uint8_t i = 0; i < NRF_PAYLOAD_LEN; i++) {
|
|
inc r4
|
|
sjmp 00103$
|
|
00101$:
|
|
; src/nrf24l01.c:159: CSN_H();
|
|
mov _gpio_write_PARM_2,#0x04
|
|
mov _gpio_write_PARM_3,#0x01
|
|
mov dpl,#0x05
|
|
; src/nrf24l01.c:160: }
|
|
ljmp _gpio_write
|
|
;------------------------------------------------------------
|
|
;Allocation info for local variables in function 'nrf24_irq_handler'
|
|
;------------------------------------------------------------
|
|
;status Allocated to registers r7
|
|
;------------------------------------------------------------
|
|
; src/nrf24l01.c:162: void nrf24_irq_handler(void)
|
|
; -----------------------------------------
|
|
; function nrf24_irq_handler
|
|
; -----------------------------------------
|
|
_nrf24_irq_handler:
|
|
; src/nrf24l01.c:164: uint8_t status = nrf_r_reg(NRF_REG_STATUS);
|
|
mov dpl,#0x07
|
|
lcall _nrf_r_reg
|
|
mov r7,dpl
|
|
; src/nrf24l01.c:165: nrf_w_reg(NRF_CMD_W_REGISTER + NRF_REG_STATUS, status);
|
|
mov _nrf_w_reg_PARM_2,r7
|
|
mov dpl,#0x27
|
|
push ar7
|
|
lcall _nrf_w_reg
|
|
pop ar7
|
|
; src/nrf24l01.c:166: g_nrf_status.last_status = status;
|
|
mov dptr,#_g_nrf_status
|
|
mov a,r7
|
|
movx @dptr,a
|
|
; src/nrf24l01.c:168: if (status & NRF_STATUS_RX_DR) {
|
|
mov a,r7
|
|
jnb acc.6,00102$
|
|
; src/nrf24l01.c:169: g_nrf_status.rx_count++;
|
|
mov dptr,#(_g_nrf_status + 0x0001)
|
|
movx a,@dptr
|
|
mov r6,a
|
|
inc r6
|
|
mov dptr,#(_g_nrf_status + 0x0001)
|
|
mov a,r6
|
|
movx @dptr,a
|
|
00102$:
|
|
; src/nrf24l01.c:171: if (status & NRF_STATUS_MAX_RT) {
|
|
mov a,r7
|
|
jnb acc.4,00105$
|
|
; src/nrf24l01.c:172: nrf_flush_tx();
|
|
; src/nrf24l01.c:174: }
|
|
ljmp _nrf_flush_tx
|
|
00105$:
|
|
ret
|
|
.area CSEG (CODE)
|
|
.area CONST (CODE)
|
|
_DEFAULT_ADDR:
|
|
.db #0xe7 ; 231
|
|
.db #0xe7 ; 231
|
|
.db #0xe7 ; 231
|
|
.db #0xe7 ; 231
|
|
.db #0xc2 ; 194
|
|
.area XINIT (CODE)
|
|
.area CABS (ABS,CODE)
|