1190 lines
22 KiB
NASM
1190 lines
22 KiB
NASM
;--------------------------------------------------------
|
|
; File Created by SDCC : free open source ANSI-C Compiler
|
|
; Version 4.2.0 #13081 (Linux)
|
|
;--------------------------------------------------------
|
|
.module gpio
|
|
.optsdcc -mmcs51 --model-small
|
|
|
|
;--------------------------------------------------------
|
|
; Public variables in this module
|
|
;--------------------------------------------------------
|
|
.globl _gpio_toggle_PARM_2
|
|
.globl _gpio_read_PARM_2
|
|
.globl _gpio_write_PARM_3
|
|
.globl _gpio_write_PARM_2
|
|
.globl _EADC
|
|
.globl _ET1
|
|
.globl _ET0
|
|
.globl _ES
|
|
.globl _EA
|
|
.globl _REN
|
|
.globl _RI
|
|
.globl _TI
|
|
.globl _TR1
|
|
.globl _TF1
|
|
.globl _IT0
|
|
.globl _IE0
|
|
.globl _TR0
|
|
.globl _TF0
|
|
.globl _P5M0_REG
|
|
.globl _P5M1_REG
|
|
.globl _P4M0_REG
|
|
.globl _P4M1_REG
|
|
.globl _P3M0_REG
|
|
.globl _P3M1_REG
|
|
.globl _P2M0_REG
|
|
.globl _P2M1_REG
|
|
.globl _P1M0_REG
|
|
.globl _P1M1_REG
|
|
.globl _P0M0_REG
|
|
.globl _P0M1_REG
|
|
.globl _P5_REG
|
|
.globl _P4_REG
|
|
.globl _P3_REG
|
|
.globl _P2_REG
|
|
.globl _P1_REG
|
|
.globl _P0_REG
|
|
.globl _CMPCR2
|
|
.globl _CMPCR1
|
|
.globl _TA
|
|
.globl _IRCBAND_REG
|
|
.globl _IAP_TPS
|
|
.globl _IAP_CONTR
|
|
.globl _IAP_TRIG
|
|
.globl _IAP_CMD
|
|
.globl _IAP_ADDRL
|
|
.globl _IAP_ADDRH
|
|
.globl _IAP_DATA
|
|
.globl _WDT_CONTR
|
|
.globl _PCA_PWM3
|
|
.globl _PCA_PWM2
|
|
.globl _PCA_PWM1
|
|
.globl _PCA_PWM0
|
|
.globl _CCAP3L
|
|
.globl _CCAP2L
|
|
.globl _CCAP1L
|
|
.globl _CCAP0L
|
|
.globl _CCAPM3
|
|
.globl _CCAPM2
|
|
.globl _CCAPM1
|
|
.globl _CCAPM0
|
|
.globl _CMOD
|
|
.globl _CCON
|
|
.globl _ADCTIM_X
|
|
.globl _ADCCFG
|
|
.globl _ADC_RESL
|
|
.globl _ADC_RES
|
|
.globl _ADC_CONTR
|
|
.globl _SPDAT
|
|
.globl _SPCTL
|
|
.globl _SPSTAT
|
|
.globl _IP2H
|
|
.globl _IP2
|
|
.globl _IP
|
|
.globl _IE2
|
|
.globl _IE
|
|
.globl _BRT
|
|
.globl _P_SW1
|
|
.globl _SADEN
|
|
.globl _SADDR
|
|
.globl _S2BUF
|
|
.globl _S2CON
|
|
.globl _SBUF
|
|
.globl _SCON
|
|
.globl _TM4PS_X
|
|
.globl _TM3PS_X
|
|
.globl _TM2PS_X
|
|
.globl _T4T3M
|
|
.globl _T4L
|
|
.globl _T4H
|
|
.globl _T3L
|
|
.globl _T3H
|
|
.globl _T2L
|
|
.globl _T2H
|
|
.globl _INTCLKO
|
|
.globl _AUXR
|
|
.globl _TH1
|
|
.globl _TH0
|
|
.globl _TL1
|
|
.globl _TL0
|
|
.globl _TMOD
|
|
.globl _TCON
|
|
.globl _P_SW2
|
|
.globl _P5M0
|
|
.globl _P5M1
|
|
.globl _P4M0
|
|
.globl _P4M1
|
|
.globl _P3M0
|
|
.globl _P3M1
|
|
.globl _P2M0
|
|
.globl _P2M1
|
|
.globl _P1M0
|
|
.globl _P1M1
|
|
.globl _P0M0
|
|
.globl _P0M1
|
|
.globl _PSW
|
|
.globl _B
|
|
.globl _ACC
|
|
.globl _PCON
|
|
.globl _DPH
|
|
.globl _DPL
|
|
.globl _SP
|
|
.globl _P5
|
|
.globl _P4
|
|
.globl _P3
|
|
.globl _P2
|
|
.globl _P1
|
|
.globl _P0
|
|
.globl _gpio_set_mode_PARM_3
|
|
.globl _gpio_set_mode_PARM_2
|
|
.globl _gpio_set_mode
|
|
.globl _gpio_write
|
|
.globl _gpio_read
|
|
.globl _gpio_toggle
|
|
;--------------------------------------------------------
|
|
; special function registers
|
|
;--------------------------------------------------------
|
|
.area RSEG (ABS,DATA)
|
|
.org 0x0000
|
|
_P0 = 0x0080
|
|
_P1 = 0x0090
|
|
_P2 = 0x00a0
|
|
_P3 = 0x00b0
|
|
_P4 = 0x00c0
|
|
_P5 = 0x00c8
|
|
_SP = 0x0081
|
|
_DPL = 0x0082
|
|
_DPH = 0x0083
|
|
_PCON = 0x0087
|
|
_ACC = 0x00e0
|
|
_B = 0x00f0
|
|
_PSW = 0x00d0
|
|
_P0M1 = 0x0093
|
|
_P0M0 = 0x0094
|
|
_P1M1 = 0x0091
|
|
_P1M0 = 0x0092
|
|
_P2M1 = 0x0095
|
|
_P2M0 = 0x0096
|
|
_P3M1 = 0x00b1
|
|
_P3M0 = 0x00b2
|
|
_P4M1 = 0x00b3
|
|
_P4M0 = 0x00b4
|
|
_P5M1 = 0x00c9
|
|
_P5M0 = 0x00ca
|
|
_P_SW2 = 0x00ba
|
|
_TCON = 0x0088
|
|
_TMOD = 0x0089
|
|
_TL0 = 0x008a
|
|
_TL1 = 0x008b
|
|
_TH0 = 0x008c
|
|
_TH1 = 0x008d
|
|
_AUXR = 0x008e
|
|
_INTCLKO = 0x008f
|
|
_T2H = 0x00d6
|
|
_T2L = 0x00d7
|
|
_T3H = 0x00d4
|
|
_T3L = 0x00d5
|
|
_T4H = 0x00d2
|
|
_T4L = 0x00d3
|
|
_T4T3M = 0x00d1
|
|
_TM2PS_X = 0xfea1
|
|
_TM3PS_X = 0xfea2
|
|
_TM4PS_X = 0xfea3
|
|
_SCON = 0x0098
|
|
_SBUF = 0x0099
|
|
_S2CON = 0x009a
|
|
_S2BUF = 0x009b
|
|
_SADDR = 0x00a9
|
|
_SADEN = 0x00b9
|
|
_P_SW1 = 0x00a2
|
|
_BRT = 0x009c
|
|
_IE = 0x00a8
|
|
_IE2 = 0x00af
|
|
_IP = 0x00b8
|
|
_IP2 = 0x00b6
|
|
_IP2H = 0x00b7
|
|
_SPSTAT = 0x00cd
|
|
_SPCTL = 0x00ce
|
|
_SPDAT = 0x00cf
|
|
_ADC_CONTR = 0x00bc
|
|
_ADC_RES = 0x00bd
|
|
_ADC_RESL = 0x00be
|
|
_ADCCFG = 0x00de
|
|
_ADCTIM_X = 0xfea8
|
|
_CCON = 0x00d8
|
|
_CMOD = 0x00d9
|
|
_CCAPM0 = 0x00da
|
|
_CCAPM1 = 0x00db
|
|
_CCAPM2 = 0x00dc
|
|
_CCAPM3 = 0x00dd
|
|
_CCAP0L = 0x00ea
|
|
_CCAP1L = 0x00eb
|
|
_CCAP2L = 0x00ec
|
|
_CCAP3L = 0x00ed
|
|
_PCA_PWM0 = 0x00f2
|
|
_PCA_PWM1 = 0x00f3
|
|
_PCA_PWM2 = 0x00f4
|
|
_PCA_PWM3 = 0x00f5
|
|
_WDT_CONTR = 0x00c1
|
|
_IAP_DATA = 0x00c2
|
|
_IAP_ADDRH = 0x00c3
|
|
_IAP_ADDRL = 0x00c4
|
|
_IAP_CMD = 0x00c5
|
|
_IAP_TRIG = 0x00c6
|
|
_IAP_CONTR = 0x00c7
|
|
_IAP_TPS = 0x00f7
|
|
_IRCBAND_REG = 0x009d
|
|
_TA = 0x00ae
|
|
_CMPCR1 = 0x00e6
|
|
_CMPCR2 = 0x00e7
|
|
_P0_REG = 0x0080
|
|
_P1_REG = 0x0090
|
|
_P2_REG = 0x00a0
|
|
_P3_REG = 0x00b0
|
|
_P4_REG = 0x00c0
|
|
_P5_REG = 0x00c8
|
|
_P0M1_REG = 0x0093
|
|
_P0M0_REG = 0x0094
|
|
_P1M1_REG = 0x0091
|
|
_P1M0_REG = 0x0092
|
|
_P2M1_REG = 0x0095
|
|
_P2M0_REG = 0x0096
|
|
_P3M1_REG = 0x00b1
|
|
_P3M0_REG = 0x00b2
|
|
_P4M1_REG = 0x00b3
|
|
_P4M0_REG = 0x00b4
|
|
_P5M1_REG = 0x00c9
|
|
_P5M0_REG = 0x00ca
|
|
;--------------------------------------------------------
|
|
; special function bits
|
|
;--------------------------------------------------------
|
|
.area RSEG (ABS,DATA)
|
|
.org 0x0000
|
|
_TF0 = 0x008d
|
|
_TR0 = 0x008c
|
|
_IE0 = 0x0089
|
|
_IT0 = 0x0088
|
|
_TF1 = 0x008f
|
|
_TR1 = 0x008e
|
|
_TI = 0x0099
|
|
_RI = 0x0098
|
|
_REN = 0x009c
|
|
_EA = 0x00af
|
|
_ES = 0x00ac
|
|
_ET0 = 0x00a9
|
|
_ET1 = 0x00ab
|
|
_EADC = 0x00ad
|
|
;--------------------------------------------------------
|
|
; overlayable register banks
|
|
;--------------------------------------------------------
|
|
.area REG_BANK_0 (REL,OVR,DATA)
|
|
.ds 8
|
|
;--------------------------------------------------------
|
|
; internal ram data
|
|
;--------------------------------------------------------
|
|
.area DSEG (DATA)
|
|
_gpio_set_mode_PARM_2:
|
|
.ds 1
|
|
_gpio_set_mode_PARM_3:
|
|
.ds 1
|
|
;--------------------------------------------------------
|
|
; overlayable items in internal ram
|
|
;--------------------------------------------------------
|
|
.area OSEG (OVR,DATA)
|
|
_set_m0_PARM_2:
|
|
.ds 1
|
|
_set_m0_PARM_3:
|
|
.ds 1
|
|
.area OSEG (OVR,DATA)
|
|
_set_m1_PARM_2:
|
|
.ds 1
|
|
_set_m1_PARM_3:
|
|
.ds 1
|
|
.area OSEG (OVR,DATA)
|
|
_gpio_write_PARM_2:
|
|
.ds 1
|
|
_gpio_write_PARM_3:
|
|
.ds 1
|
|
.area OSEG (OVR,DATA)
|
|
_gpio_read_PARM_2:
|
|
.ds 1
|
|
.area OSEG (OVR,DATA)
|
|
_gpio_toggle_PARM_2:
|
|
.ds 1
|
|
;--------------------------------------------------------
|
|
; indirectly addressable internal ram data
|
|
;--------------------------------------------------------
|
|
.area ISEG (DATA)
|
|
;--------------------------------------------------------
|
|
; absolute internal ram data
|
|
;--------------------------------------------------------
|
|
.area IABS (ABS,DATA)
|
|
.area IABS (ABS,DATA)
|
|
;--------------------------------------------------------
|
|
; bit data
|
|
;--------------------------------------------------------
|
|
.area BSEG (BIT)
|
|
;--------------------------------------------------------
|
|
; paged external ram data
|
|
;--------------------------------------------------------
|
|
.area PSEG (PAG,XDATA)
|
|
;--------------------------------------------------------
|
|
; external ram data
|
|
;--------------------------------------------------------
|
|
.area XSEG (XDATA)
|
|
;--------------------------------------------------------
|
|
; absolute external ram data
|
|
;--------------------------------------------------------
|
|
.area XABS (ABS,XDATA)
|
|
;--------------------------------------------------------
|
|
; external initialized ram data
|
|
;--------------------------------------------------------
|
|
.area XISEG (XDATA)
|
|
.area HOME (CODE)
|
|
.area GSINIT0 (CODE)
|
|
.area GSINIT1 (CODE)
|
|
.area GSINIT2 (CODE)
|
|
.area GSINIT3 (CODE)
|
|
.area GSINIT4 (CODE)
|
|
.area GSINIT5 (CODE)
|
|
.area GSINIT (CODE)
|
|
.area GSFINAL (CODE)
|
|
.area CSEG (CODE)
|
|
;--------------------------------------------------------
|
|
; global & static initialisations
|
|
;--------------------------------------------------------
|
|
.area HOME (CODE)
|
|
.area GSINIT (CODE)
|
|
.area GSFINAL (CODE)
|
|
.area GSINIT (CODE)
|
|
;--------------------------------------------------------
|
|
; Home
|
|
;--------------------------------------------------------
|
|
.area HOME (CODE)
|
|
.area HOME (CODE)
|
|
;--------------------------------------------------------
|
|
; code
|
|
;--------------------------------------------------------
|
|
.area CSEG (CODE)
|
|
;------------------------------------------------------------
|
|
;Allocation info for local variables in function 'set_m0'
|
|
;------------------------------------------------------------
|
|
;pin Allocated with name '_set_m0_PARM_2'
|
|
;bit Allocated with name '_set_m0_PARM_3'
|
|
;port Allocated to registers r7
|
|
;------------------------------------------------------------
|
|
; src/gpio.c:28: static void set_m0(uint8_t port, uint8_t pin, uint8_t bit)
|
|
; -----------------------------------------
|
|
; function set_m0
|
|
; -----------------------------------------
|
|
_set_m0:
|
|
ar7 = 0x07
|
|
ar6 = 0x06
|
|
ar5 = 0x05
|
|
ar4 = 0x04
|
|
ar3 = 0x03
|
|
ar2 = 0x02
|
|
ar1 = 0x01
|
|
ar0 = 0x00
|
|
; src/gpio.c:30: switch (port) {
|
|
mov a,dpl
|
|
mov r7,a
|
|
add a,#0xff - 0x05
|
|
jnc 00156$
|
|
ret
|
|
00156$:
|
|
mov a,r7
|
|
add a,r7
|
|
add a,r7
|
|
mov dptr,#00157$
|
|
jmp @a+dptr
|
|
00157$:
|
|
ljmp 00101$
|
|
ljmp 00105$
|
|
ljmp 00109$
|
|
ljmp 00113$
|
|
ljmp 00117$
|
|
ljmp 00121$
|
|
; src/gpio.c:31: case 0: if (bit) P0M0_REG |= (1 << pin); else P0M0_REG &= ~(1 << pin); break;
|
|
00101$:
|
|
mov a,_set_m0_PARM_3
|
|
jz 00103$
|
|
mov r7,_set_m0_PARM_2
|
|
mov b,r7
|
|
inc b
|
|
mov a,#0x01
|
|
sjmp 00161$
|
|
00159$:
|
|
add a,acc
|
|
00161$:
|
|
djnz b,00159$
|
|
orl _P0M0_REG,a
|
|
ret
|
|
00103$:
|
|
mov r7,_set_m0_PARM_2
|
|
mov b,r7
|
|
inc b
|
|
mov a,#0x01
|
|
sjmp 00164$
|
|
00162$:
|
|
add a,acc
|
|
00164$:
|
|
djnz b,00162$
|
|
cpl a
|
|
anl _P0M0_REG,a
|
|
ret
|
|
; src/gpio.c:32: case 1: if (bit) P1M0_REG |= (1 << pin); else P1M0_REG &= ~(1 << pin); break;
|
|
00105$:
|
|
mov a,_set_m0_PARM_3
|
|
jz 00107$
|
|
mov r7,_set_m0_PARM_2
|
|
mov b,r7
|
|
inc b
|
|
mov a,#0x01
|
|
sjmp 00168$
|
|
00166$:
|
|
add a,acc
|
|
00168$:
|
|
djnz b,00166$
|
|
orl _P1M0_REG,a
|
|
ret
|
|
00107$:
|
|
mov r7,_set_m0_PARM_2
|
|
mov b,r7
|
|
inc b
|
|
mov a,#0x01
|
|
sjmp 00171$
|
|
00169$:
|
|
add a,acc
|
|
00171$:
|
|
djnz b,00169$
|
|
cpl a
|
|
anl _P1M0_REG,a
|
|
ret
|
|
; src/gpio.c:33: case 2: if (bit) P2M0_REG |= (1 << pin); else P2M0_REG &= ~(1 << pin); break;
|
|
00109$:
|
|
mov a,_set_m0_PARM_3
|
|
jz 00111$
|
|
mov r7,_set_m0_PARM_2
|
|
mov b,r7
|
|
inc b
|
|
mov a,#0x01
|
|
sjmp 00175$
|
|
00173$:
|
|
add a,acc
|
|
00175$:
|
|
djnz b,00173$
|
|
orl _P2M0_REG,a
|
|
ret
|
|
00111$:
|
|
mov r7,_set_m0_PARM_2
|
|
mov b,r7
|
|
inc b
|
|
mov a,#0x01
|
|
sjmp 00178$
|
|
00176$:
|
|
add a,acc
|
|
00178$:
|
|
djnz b,00176$
|
|
cpl a
|
|
anl _P2M0_REG,a
|
|
ret
|
|
; src/gpio.c:34: case 3: if (bit) P3M0_REG |= (1 << pin); else P3M0_REG &= ~(1 << pin); break;
|
|
00113$:
|
|
mov a,_set_m0_PARM_3
|
|
jz 00115$
|
|
mov r7,_set_m0_PARM_2
|
|
mov b,r7
|
|
inc b
|
|
mov a,#0x01
|
|
sjmp 00182$
|
|
00180$:
|
|
add a,acc
|
|
00182$:
|
|
djnz b,00180$
|
|
orl _P3M0_REG,a
|
|
ret
|
|
00115$:
|
|
mov r7,_set_m0_PARM_2
|
|
mov b,r7
|
|
inc b
|
|
mov a,#0x01
|
|
sjmp 00185$
|
|
00183$:
|
|
add a,acc
|
|
00185$:
|
|
djnz b,00183$
|
|
cpl a
|
|
anl _P3M0_REG,a
|
|
; src/gpio.c:35: case 4: if (bit) P4M0_REG |= (1 << pin); else P4M0_REG &= ~(1 << pin); break;
|
|
ret
|
|
00117$:
|
|
mov a,_set_m0_PARM_3
|
|
jz 00119$
|
|
mov r7,_set_m0_PARM_2
|
|
mov b,r7
|
|
inc b
|
|
mov a,#0x01
|
|
sjmp 00189$
|
|
00187$:
|
|
add a,acc
|
|
00189$:
|
|
djnz b,00187$
|
|
orl _P4M0_REG,a
|
|
ret
|
|
00119$:
|
|
mov r7,_set_m0_PARM_2
|
|
mov b,r7
|
|
inc b
|
|
mov a,#0x01
|
|
sjmp 00192$
|
|
00190$:
|
|
add a,acc
|
|
00192$:
|
|
djnz b,00190$
|
|
cpl a
|
|
anl _P4M0_REG,a
|
|
; src/gpio.c:36: case 5: if (bit) P5M0_REG |= (1 << pin); else P5M0_REG &= ~(1 << pin); break;
|
|
ret
|
|
00121$:
|
|
mov a,_set_m0_PARM_3
|
|
jz 00123$
|
|
mov r7,_set_m0_PARM_2
|
|
mov b,r7
|
|
inc b
|
|
mov a,#0x01
|
|
sjmp 00196$
|
|
00194$:
|
|
add a,acc
|
|
00196$:
|
|
djnz b,00194$
|
|
orl _P5M0_REG,a
|
|
ret
|
|
00123$:
|
|
mov r7,_set_m0_PARM_2
|
|
mov b,r7
|
|
inc b
|
|
mov a,#0x01
|
|
sjmp 00199$
|
|
00197$:
|
|
add a,acc
|
|
00199$:
|
|
djnz b,00197$
|
|
cpl a
|
|
anl _P5M0_REG,a
|
|
; src/gpio.c:37: }
|
|
; src/gpio.c:38: }
|
|
ret
|
|
;------------------------------------------------------------
|
|
;Allocation info for local variables in function 'set_m1'
|
|
;------------------------------------------------------------
|
|
;pin Allocated with name '_set_m1_PARM_2'
|
|
;bit Allocated with name '_set_m1_PARM_3'
|
|
;port Allocated to registers r7
|
|
;------------------------------------------------------------
|
|
; src/gpio.c:40: static void set_m1(uint8_t port, uint8_t pin, uint8_t bit)
|
|
; -----------------------------------------
|
|
; function set_m1
|
|
; -----------------------------------------
|
|
_set_m1:
|
|
; src/gpio.c:42: switch (port) {
|
|
mov a,dpl
|
|
mov r7,a
|
|
add a,#0xff - 0x05
|
|
jnc 00156$
|
|
ret
|
|
00156$:
|
|
mov a,r7
|
|
add a,r7
|
|
add a,r7
|
|
mov dptr,#00157$
|
|
jmp @a+dptr
|
|
00157$:
|
|
ljmp 00101$
|
|
ljmp 00105$
|
|
ljmp 00109$
|
|
ljmp 00113$
|
|
ljmp 00117$
|
|
ljmp 00121$
|
|
; src/gpio.c:43: case 0: if (bit) P0M1_REG |= (1 << pin); else P0M1_REG &= ~(1 << pin); break;
|
|
00101$:
|
|
mov a,_set_m1_PARM_3
|
|
jz 00103$
|
|
mov r7,_set_m1_PARM_2
|
|
mov b,r7
|
|
inc b
|
|
mov a,#0x01
|
|
sjmp 00161$
|
|
00159$:
|
|
add a,acc
|
|
00161$:
|
|
djnz b,00159$
|
|
orl _P0M1_REG,a
|
|
ret
|
|
00103$:
|
|
mov r7,_set_m1_PARM_2
|
|
mov b,r7
|
|
inc b
|
|
mov a,#0x01
|
|
sjmp 00164$
|
|
00162$:
|
|
add a,acc
|
|
00164$:
|
|
djnz b,00162$
|
|
cpl a
|
|
anl _P0M1_REG,a
|
|
ret
|
|
; src/gpio.c:44: case 1: if (bit) P1M1_REG |= (1 << pin); else P1M1_REG &= ~(1 << pin); break;
|
|
00105$:
|
|
mov a,_set_m1_PARM_3
|
|
jz 00107$
|
|
mov r7,_set_m1_PARM_2
|
|
mov b,r7
|
|
inc b
|
|
mov a,#0x01
|
|
sjmp 00168$
|
|
00166$:
|
|
add a,acc
|
|
00168$:
|
|
djnz b,00166$
|
|
orl _P1M1_REG,a
|
|
ret
|
|
00107$:
|
|
mov r7,_set_m1_PARM_2
|
|
mov b,r7
|
|
inc b
|
|
mov a,#0x01
|
|
sjmp 00171$
|
|
00169$:
|
|
add a,acc
|
|
00171$:
|
|
djnz b,00169$
|
|
cpl a
|
|
anl _P1M1_REG,a
|
|
ret
|
|
; src/gpio.c:45: case 2: if (bit) P2M1_REG |= (1 << pin); else P2M1_REG &= ~(1 << pin); break;
|
|
00109$:
|
|
mov a,_set_m1_PARM_3
|
|
jz 00111$
|
|
mov r7,_set_m1_PARM_2
|
|
mov b,r7
|
|
inc b
|
|
mov a,#0x01
|
|
sjmp 00175$
|
|
00173$:
|
|
add a,acc
|
|
00175$:
|
|
djnz b,00173$
|
|
orl _P2M1_REG,a
|
|
ret
|
|
00111$:
|
|
mov r7,_set_m1_PARM_2
|
|
mov b,r7
|
|
inc b
|
|
mov a,#0x01
|
|
sjmp 00178$
|
|
00176$:
|
|
add a,acc
|
|
00178$:
|
|
djnz b,00176$
|
|
cpl a
|
|
anl _P2M1_REG,a
|
|
ret
|
|
; src/gpio.c:46: case 3: if (bit) P3M1_REG |= (1 << pin); else P3M1_REG &= ~(1 << pin); break;
|
|
00113$:
|
|
mov a,_set_m1_PARM_3
|
|
jz 00115$
|
|
mov r7,_set_m1_PARM_2
|
|
mov b,r7
|
|
inc b
|
|
mov a,#0x01
|
|
sjmp 00182$
|
|
00180$:
|
|
add a,acc
|
|
00182$:
|
|
djnz b,00180$
|
|
orl _P3M1_REG,a
|
|
ret
|
|
00115$:
|
|
mov r7,_set_m1_PARM_2
|
|
mov b,r7
|
|
inc b
|
|
mov a,#0x01
|
|
sjmp 00185$
|
|
00183$:
|
|
add a,acc
|
|
00185$:
|
|
djnz b,00183$
|
|
cpl a
|
|
anl _P3M1_REG,a
|
|
; src/gpio.c:47: case 4: if (bit) P4M1_REG |= (1 << pin); else P4M1_REG &= ~(1 << pin); break;
|
|
ret
|
|
00117$:
|
|
mov a,_set_m1_PARM_3
|
|
jz 00119$
|
|
mov r7,_set_m1_PARM_2
|
|
mov b,r7
|
|
inc b
|
|
mov a,#0x01
|
|
sjmp 00189$
|
|
00187$:
|
|
add a,acc
|
|
00189$:
|
|
djnz b,00187$
|
|
orl _P4M1_REG,a
|
|
ret
|
|
00119$:
|
|
mov r7,_set_m1_PARM_2
|
|
mov b,r7
|
|
inc b
|
|
mov a,#0x01
|
|
sjmp 00192$
|
|
00190$:
|
|
add a,acc
|
|
00192$:
|
|
djnz b,00190$
|
|
cpl a
|
|
anl _P4M1_REG,a
|
|
; src/gpio.c:48: case 5: if (bit) P5M1_REG |= (1 << pin); else P5M1_REG &= ~(1 << pin); break;
|
|
ret
|
|
00121$:
|
|
mov a,_set_m1_PARM_3
|
|
jz 00123$
|
|
mov r7,_set_m1_PARM_2
|
|
mov b,r7
|
|
inc b
|
|
mov a,#0x01
|
|
sjmp 00196$
|
|
00194$:
|
|
add a,acc
|
|
00196$:
|
|
djnz b,00194$
|
|
orl _P5M1_REG,a
|
|
ret
|
|
00123$:
|
|
mov r7,_set_m1_PARM_2
|
|
mov b,r7
|
|
inc b
|
|
mov a,#0x01
|
|
sjmp 00199$
|
|
00197$:
|
|
add a,acc
|
|
00199$:
|
|
djnz b,00197$
|
|
cpl a
|
|
anl _P5M1_REG,a
|
|
; src/gpio.c:49: }
|
|
; src/gpio.c:50: }
|
|
ret
|
|
;------------------------------------------------------------
|
|
;Allocation info for local variables in function 'gpio_set_mode'
|
|
;------------------------------------------------------------
|
|
;pin Allocated with name '_gpio_set_mode_PARM_2'
|
|
;mode Allocated with name '_gpio_set_mode_PARM_3'
|
|
;port Allocated to registers r7
|
|
;m0_bit Allocated to registers
|
|
;m1_bit Allocated to registers r6
|
|
;------------------------------------------------------------
|
|
; src/gpio.c:52: void gpio_set_mode(uint8_t port, uint8_t pin, GPIOMode_e mode)
|
|
; -----------------------------------------
|
|
; function gpio_set_mode
|
|
; -----------------------------------------
|
|
_gpio_set_mode:
|
|
; src/gpio.c:54: if (port > 5 || pin > 7) return;
|
|
mov a,dpl
|
|
mov r7,a
|
|
add a,#0xff - 0x05
|
|
jc 00101$
|
|
mov a,_gpio_set_mode_PARM_2
|
|
add a,#0xff - 0x07
|
|
jnc 00102$
|
|
00101$:
|
|
ret
|
|
00102$:
|
|
; src/gpio.c:55: uint8_t m0_bit = (mode >> 0) & 0x01;
|
|
mov a,_gpio_set_mode_PARM_3
|
|
anl a,#0x01
|
|
mov _set_m0_PARM_3,a
|
|
; src/gpio.c:56: uint8_t m1_bit = (mode >> 1) & 0x01;
|
|
mov a,_gpio_set_mode_PARM_3
|
|
rr a
|
|
anl a,#0x01
|
|
mov r6,a
|
|
; src/gpio.c:57: set_m0(port, pin, m0_bit);
|
|
mov _set_m0_PARM_2,_gpio_set_mode_PARM_2
|
|
mov dpl,r7
|
|
push ar7
|
|
push ar6
|
|
lcall _set_m0
|
|
pop ar6
|
|
pop ar7
|
|
; src/gpio.c:58: set_m1(port, pin, m1_bit);
|
|
mov _set_m1_PARM_2,_gpio_set_mode_PARM_2
|
|
mov _set_m1_PARM_3,r6
|
|
mov dpl,r7
|
|
; src/gpio.c:59: }
|
|
ljmp _set_m1
|
|
;------------------------------------------------------------
|
|
;Allocation info for local variables in function 'gpio_write'
|
|
;------------------------------------------------------------
|
|
;pin Allocated with name '_gpio_write_PARM_2'
|
|
;val Allocated with name '_gpio_write_PARM_3'
|
|
;port Allocated to registers r7
|
|
;mask Allocated to registers r5
|
|
;------------------------------------------------------------
|
|
; src/gpio.c:61: void gpio_write(uint8_t port, uint8_t pin, uint8_t val)
|
|
; -----------------------------------------
|
|
; function gpio_write
|
|
; -----------------------------------------
|
|
_gpio_write:
|
|
mov r7,dpl
|
|
; src/gpio.c:63: if (port > 5 || pin > 7) return;
|
|
clr c
|
|
mov a,#0x05
|
|
subb a,r7
|
|
clr a
|
|
rlc a
|
|
mov r6,a
|
|
jnz 00101$
|
|
mov a,_gpio_write_PARM_2
|
|
add a,#0xff - 0x07
|
|
jnc 00102$
|
|
00101$:
|
|
ret
|
|
00102$:
|
|
; src/gpio.c:64: uint8_t mask = (1 << pin);
|
|
mov r5,_gpio_write_PARM_2
|
|
mov b,r5
|
|
inc b
|
|
mov a,#0x01
|
|
sjmp 00167$
|
|
00165$:
|
|
add a,acc
|
|
00167$:
|
|
djnz b,00165$
|
|
mov r5,a
|
|
; src/gpio.c:65: switch (port) {
|
|
mov a,r6
|
|
jz 00168$
|
|
ret
|
|
00168$:
|
|
mov a,r7
|
|
add a,r7
|
|
; src/gpio.c:66: case 0: if (val) P0_REG |= mask; else P0_REG &= ~mask; break;
|
|
mov dptr,#00169$
|
|
jmp @a+dptr
|
|
00169$:
|
|
sjmp 00104$
|
|
sjmp 00108$
|
|
sjmp 00112$
|
|
sjmp 00116$
|
|
sjmp 00120$
|
|
sjmp 00124$
|
|
00104$:
|
|
mov a,_gpio_write_PARM_3
|
|
jz 00106$
|
|
mov a,r5
|
|
orl _P0_REG,a
|
|
ret
|
|
00106$:
|
|
mov a,r5
|
|
cpl a
|
|
anl _P0_REG,a
|
|
; src/gpio.c:67: case 1: if (val) P1_REG |= mask; else P1_REG &= ~mask; break;
|
|
ret
|
|
00108$:
|
|
mov a,_gpio_write_PARM_3
|
|
jz 00110$
|
|
mov a,r5
|
|
orl _P1_REG,a
|
|
ret
|
|
00110$:
|
|
mov a,r5
|
|
cpl a
|
|
anl _P1_REG,a
|
|
; src/gpio.c:68: case 2: if (val) P2_REG |= mask; else P2_REG &= ~mask; break;
|
|
ret
|
|
00112$:
|
|
mov a,_gpio_write_PARM_3
|
|
jz 00114$
|
|
mov a,r5
|
|
orl _P2_REG,a
|
|
ret
|
|
00114$:
|
|
mov a,r5
|
|
cpl a
|
|
anl _P2_REG,a
|
|
; src/gpio.c:69: case 3: if (val) P3_REG |= mask; else P3_REG &= ~mask; break;
|
|
ret
|
|
00116$:
|
|
mov a,_gpio_write_PARM_3
|
|
jz 00118$
|
|
mov a,r5
|
|
orl _P3_REG,a
|
|
ret
|
|
00118$:
|
|
mov a,r5
|
|
cpl a
|
|
anl _P3_REG,a
|
|
; src/gpio.c:70: case 4: if (val) P4_REG |= mask; else P4_REG &= ~mask; break;
|
|
ret
|
|
00120$:
|
|
mov a,_gpio_write_PARM_3
|
|
jz 00122$
|
|
mov a,r5
|
|
orl _P4_REG,a
|
|
ret
|
|
00122$:
|
|
mov a,r5
|
|
cpl a
|
|
anl _P4_REG,a
|
|
; src/gpio.c:71: case 5: if (val) P5_REG |= mask; else P5_REG &= ~mask; break;
|
|
ret
|
|
00124$:
|
|
mov a,_gpio_write_PARM_3
|
|
jz 00126$
|
|
mov a,r5
|
|
orl _P5_REG,a
|
|
ret
|
|
00126$:
|
|
mov a,r5
|
|
cpl a
|
|
anl _P5_REG,a
|
|
; src/gpio.c:72: }
|
|
; src/gpio.c:73: }
|
|
ret
|
|
;------------------------------------------------------------
|
|
;Allocation info for local variables in function 'gpio_read'
|
|
;------------------------------------------------------------
|
|
;pin Allocated with name '_gpio_read_PARM_2'
|
|
;port Allocated to registers r7
|
|
;mask Allocated to registers r5
|
|
;------------------------------------------------------------
|
|
; src/gpio.c:75: uint8_t gpio_read(uint8_t port, uint8_t pin)
|
|
; -----------------------------------------
|
|
; function gpio_read
|
|
; -----------------------------------------
|
|
_gpio_read:
|
|
mov r7,dpl
|
|
; src/gpio.c:77: if (port > 5 || pin > 7) return 0;
|
|
clr c
|
|
mov a,#0x05
|
|
subb a,r7
|
|
clr a
|
|
rlc a
|
|
mov r6,a
|
|
jnz 00101$
|
|
mov a,_gpio_read_PARM_2
|
|
add a,#0xff - 0x07
|
|
jnc 00102$
|
|
00101$:
|
|
mov dpl,#0x00
|
|
ret
|
|
00102$:
|
|
; src/gpio.c:78: uint8_t mask = (1 << pin);
|
|
mov r5,_gpio_read_PARM_2
|
|
mov b,r5
|
|
inc b
|
|
mov a,#0x01
|
|
sjmp 00161$
|
|
00159$:
|
|
add a,acc
|
|
00161$:
|
|
djnz b,00159$
|
|
mov r5,a
|
|
; src/gpio.c:79: switch (port) {
|
|
mov a,r6
|
|
jz 00162$
|
|
ljmp 00110$
|
|
00162$:
|
|
mov a,r7
|
|
add a,r7
|
|
; src/gpio.c:80: case 0: return (P0_REG & mask) ? 1 : 0;
|
|
mov dptr,#00163$
|
|
jmp @a+dptr
|
|
00163$:
|
|
sjmp 00104$
|
|
sjmp 00105$
|
|
sjmp 00106$
|
|
sjmp 00107$
|
|
sjmp 00108$
|
|
sjmp 00109$
|
|
00104$:
|
|
mov a,r5
|
|
anl a,_P0_REG
|
|
jz 00113$
|
|
mov r6,#0x01
|
|
mov r7,#0x00
|
|
sjmp 00114$
|
|
00113$:
|
|
mov r6,#0x00
|
|
mov r7,#0x00
|
|
00114$:
|
|
mov dpl,r6
|
|
; src/gpio.c:81: case 1: return (P1_REG & mask) ? 1 : 0;
|
|
ret
|
|
00105$:
|
|
mov a,r5
|
|
anl a,_P1_REG
|
|
jz 00115$
|
|
mov r6,#0x01
|
|
mov r7,#0x00
|
|
sjmp 00116$
|
|
00115$:
|
|
mov r6,#0x00
|
|
mov r7,#0x00
|
|
00116$:
|
|
mov dpl,r6
|
|
; src/gpio.c:82: case 2: return (P2_REG & mask) ? 1 : 0;
|
|
ret
|
|
00106$:
|
|
mov a,r5
|
|
anl a,_P2_REG
|
|
jz 00117$
|
|
mov r6,#0x01
|
|
mov r7,#0x00
|
|
sjmp 00118$
|
|
00117$:
|
|
mov r6,#0x00
|
|
mov r7,#0x00
|
|
00118$:
|
|
mov dpl,r6
|
|
; src/gpio.c:83: case 3: return (P3_REG & mask) ? 1 : 0;
|
|
ret
|
|
00107$:
|
|
mov a,r5
|
|
anl a,_P3_REG
|
|
jz 00119$
|
|
mov r6,#0x01
|
|
mov r7,#0x00
|
|
sjmp 00120$
|
|
00119$:
|
|
mov r6,#0x00
|
|
mov r7,#0x00
|
|
00120$:
|
|
mov dpl,r6
|
|
; src/gpio.c:84: case 4: return (P4_REG & mask) ? 1 : 0;
|
|
ret
|
|
00108$:
|
|
mov a,r5
|
|
anl a,_P4_REG
|
|
jz 00121$
|
|
mov r6,#0x01
|
|
mov r7,#0x00
|
|
sjmp 00122$
|
|
00121$:
|
|
mov r6,#0x00
|
|
mov r7,#0x00
|
|
00122$:
|
|
mov dpl,r6
|
|
; src/gpio.c:85: case 5: return (P5_REG & mask) ? 1 : 0;
|
|
ret
|
|
00109$:
|
|
mov a,r5
|
|
anl a,_P5_REG
|
|
jz 00123$
|
|
mov r6,#0x01
|
|
mov r7,#0x00
|
|
sjmp 00124$
|
|
00123$:
|
|
mov r6,#0x00
|
|
mov r7,#0x00
|
|
00124$:
|
|
mov dpl,r6
|
|
; src/gpio.c:86: }
|
|
ret
|
|
00110$:
|
|
; src/gpio.c:87: return 0;
|
|
mov dpl,#0x00
|
|
; src/gpio.c:88: }
|
|
ret
|
|
;------------------------------------------------------------
|
|
;Allocation info for local variables in function 'gpio_toggle'
|
|
;------------------------------------------------------------
|
|
;pin Allocated with name '_gpio_toggle_PARM_2'
|
|
;port Allocated to registers r7
|
|
;mask Allocated to registers r5
|
|
;------------------------------------------------------------
|
|
; src/gpio.c:90: void gpio_toggle(uint8_t port, uint8_t pin)
|
|
; -----------------------------------------
|
|
; function gpio_toggle
|
|
; -----------------------------------------
|
|
_gpio_toggle:
|
|
mov r7,dpl
|
|
; src/gpio.c:92: if (port > 5 || pin > 7) return;
|
|
clr c
|
|
mov a,#0x05
|
|
subb a,r7
|
|
clr a
|
|
rlc a
|
|
mov r6,a
|
|
jnz 00101$
|
|
mov a,_gpio_toggle_PARM_2
|
|
add a,#0xff - 0x07
|
|
jnc 00102$
|
|
00101$:
|
|
ret
|
|
00102$:
|
|
; src/gpio.c:93: uint8_t mask = (1 << pin);
|
|
mov r5,_gpio_toggle_PARM_2
|
|
mov b,r5
|
|
inc b
|
|
mov a,#0x01
|
|
sjmp 00125$
|
|
00123$:
|
|
add a,acc
|
|
00125$:
|
|
djnz b,00123$
|
|
mov r5,a
|
|
; src/gpio.c:94: switch (port) {
|
|
mov a,r6
|
|
jnz 00111$
|
|
mov a,r7
|
|
add a,r7
|
|
; src/gpio.c:95: case 0: P0_REG ^= mask; break;
|
|
mov dptr,#00127$
|
|
jmp @a+dptr
|
|
00127$:
|
|
sjmp 00104$
|
|
sjmp 00105$
|
|
sjmp 00106$
|
|
sjmp 00107$
|
|
sjmp 00108$
|
|
sjmp 00109$
|
|
00104$:
|
|
mov a,r5
|
|
xrl _P0_REG,a
|
|
; src/gpio.c:96: case 1: P1_REG ^= mask; break;
|
|
ret
|
|
00105$:
|
|
mov a,r5
|
|
xrl _P1_REG,a
|
|
; src/gpio.c:97: case 2: P2_REG ^= mask; break;
|
|
ret
|
|
00106$:
|
|
mov a,r5
|
|
xrl _P2_REG,a
|
|
; src/gpio.c:98: case 3: P3_REG ^= mask; break;
|
|
ret
|
|
00107$:
|
|
mov a,r5
|
|
xrl _P3_REG,a
|
|
; src/gpio.c:99: case 4: P4_REG ^= mask; break;
|
|
ret
|
|
00108$:
|
|
mov a,r5
|
|
xrl _P4_REG,a
|
|
; src/gpio.c:100: case 5: P5_REG ^= mask; break;
|
|
ret
|
|
00109$:
|
|
mov a,r5
|
|
xrl _P5_REG,a
|
|
; src/gpio.c:101: }
|
|
00111$:
|
|
; src/gpio.c:102: }
|
|
ret
|
|
.area CSEG (CODE)
|
|
.area CONST (CODE)
|
|
.area XINIT (CODE)
|
|
.area CABS (ABS,CODE)
|