;-------------------------------------------------------- ; File Created by SDCC : free open source ANSI-C Compiler ; Version 4.2.0 #13081 (Linux) ;-------------------------------------------------------- .module nrf24l01 .optsdcc -mmcs51 --model-small ;-------------------------------------------------------- ; Public variables in this module ;-------------------------------------------------------- .globl _gpio_write .globl _gpio_set_mode .globl _delay_ms .globl _delay_us .globl _spi_transfer .globl _EADC .globl _ET1 .globl _ET0 .globl _ES .globl _EA .globl _REN .globl _RI .globl _TI .globl _TR1 .globl _TF1 .globl _IT0 .globl _IE0 .globl _TR0 .globl _TF0 .globl _CMPCR2 .globl _CMPCR1 .globl _TA .globl _IRCBAND_REG .globl _IAP_TPS .globl _IAP_CONTR .globl _IAP_TRIG .globl _IAP_CMD .globl _IAP_ADDRL .globl _IAP_ADDRH .globl _IAP_DATA .globl _WDT_CONTR .globl _PCA_PWM3 .globl _PCA_PWM2 .globl _PCA_PWM1 .globl _PCA_PWM0 .globl _CCAP3L .globl _CCAP2L .globl _CCAP1L .globl _CCAP0L .globl _CCAPM3 .globl _CCAPM2 .globl _CCAPM1 .globl _CCAPM0 .globl _CMOD .globl _CCON .globl _ADCTIM_X .globl _ADCCFG .globl _ADC_RESL .globl _ADC_RES .globl _ADC_CONTR .globl _SPDAT .globl _SPCTL .globl _SPSTAT .globl _IP2H .globl _IP2 .globl _IP .globl _IE2 .globl _IE .globl _BRT .globl _P_SW1 .globl _SADEN .globl _SADDR .globl _S2BUF .globl _S2CON .globl _SBUF .globl _SCON .globl _TM4PS_X .globl _TM3PS_X .globl _TM2PS_X .globl _T4T3M .globl _T4L .globl _T4H .globl _T3L .globl _T3H .globl _T2L .globl _T2H .globl _INTCLKO .globl _AUXR .globl _TH1 .globl _TH0 .globl _TL1 .globl _TL0 .globl _TMOD .globl _TCON .globl _P_SW2 .globl _P5M0 .globl _P5M1 .globl _P4M0 .globl _P4M1 .globl _P3M0 .globl _P3M1 .globl _P2M0 .globl _P2M1 .globl _P1M0 .globl _P1M1 .globl _P0M0 .globl _P0M1 .globl _PSW .globl _B .globl _ACC .globl _PCON .globl _DPH .globl _DPL .globl _SP .globl _P5 .globl _P4 .globl _P3 .globl _P2 .globl _P1 .globl _P0 .globl _g_nrf_status .globl _nrf24_init .globl _nrf24_check .globl _nrf24_set_channel .globl _nrf24_set_address .globl _nrf24_set_rx_mode .globl _nrf24_data_ready .globl _nrf24_write_ack_payload .globl _nrf24_irq_handler ;-------------------------------------------------------- ; special function registers ;-------------------------------------------------------- .area RSEG (ABS,DATA) .org 0x0000 _P0 = 0x0080 _P1 = 0x0090 _P2 = 0x00a0 _P3 = 0x00b0 _P4 = 0x00c0 _P5 = 0x00c8 _SP = 0x0081 _DPL = 0x0082 _DPH = 0x0083 _PCON = 0x0087 _ACC = 0x00e0 _B = 0x00f0 _PSW = 0x00d0 _P0M1 = 0x0093 _P0M0 = 0x0094 _P1M1 = 0x0091 _P1M0 = 0x0092 _P2M1 = 0x0095 _P2M0 = 0x0096 _P3M1 = 0x00b1 _P3M0 = 0x00b2 _P4M1 = 0x00b3 _P4M0 = 0x00b4 _P5M1 = 0x00c9 _P5M0 = 0x00ca _P_SW2 = 0x00ba _TCON = 0x0088 _TMOD = 0x0089 _TL0 = 0x008a _TL1 = 0x008b _TH0 = 0x008c _TH1 = 0x008d _AUXR = 0x008e _INTCLKO = 0x008f _T2H = 0x00d6 _T2L = 0x00d7 _T3H = 0x00d4 _T3L = 0x00d5 _T4H = 0x00d2 _T4L = 0x00d3 _T4T3M = 0x00d1 _TM2PS_X = 0xfea1 _TM3PS_X = 0xfea2 _TM4PS_X = 0xfea3 _SCON = 0x0098 _SBUF = 0x0099 _S2CON = 0x009a _S2BUF = 0x009b _SADDR = 0x00a9 _SADEN = 0x00b9 _P_SW1 = 0x00a2 _BRT = 0x009c _IE = 0x00a8 _IE2 = 0x00af _IP = 0x00b8 _IP2 = 0x00b6 _IP2H = 0x00b7 _SPSTAT = 0x00cd _SPCTL = 0x00ce _SPDAT = 0x00cf _ADC_CONTR = 0x00bc _ADC_RES = 0x00bd _ADC_RESL = 0x00be _ADCCFG = 0x00de _ADCTIM_X = 0xfea8 _CCON = 0x00d8 _CMOD = 0x00d9 _CCAPM0 = 0x00da _CCAPM1 = 0x00db _CCAPM2 = 0x00dc _CCAPM3 = 0x00dd _CCAP0L = 0x00ea _CCAP1L = 0x00eb _CCAP2L = 0x00ec _CCAP3L = 0x00ed _PCA_PWM0 = 0x00f2 _PCA_PWM1 = 0x00f3 _PCA_PWM2 = 0x00f4 _PCA_PWM3 = 0x00f5 _WDT_CONTR = 0x00c1 _IAP_DATA = 0x00c2 _IAP_ADDRH = 0x00c3 _IAP_ADDRL = 0x00c4 _IAP_CMD = 0x00c5 _IAP_TRIG = 0x00c6 _IAP_CONTR = 0x00c7 _IAP_TPS = 0x00f7 _IRCBAND_REG = 0x009d _TA = 0x00ae _CMPCR1 = 0x00e6 _CMPCR2 = 0x00e7 ;-------------------------------------------------------- ; special function bits ;-------------------------------------------------------- .area RSEG (ABS,DATA) .org 0x0000 _TF0 = 0x008d _TR0 = 0x008c _IE0 = 0x0089 _IT0 = 0x0088 _TF1 = 0x008f _TR1 = 0x008e _TI = 0x0099 _RI = 0x0098 _REN = 0x009c _EA = 0x00af _ES = 0x00ac _ET0 = 0x00a9 _ET1 = 0x00ab _EADC = 0x00ad ;-------------------------------------------------------- ; overlayable register banks ;-------------------------------------------------------- .area REG_BANK_0 (REL,OVR,DATA) .ds 8 ;-------------------------------------------------------- ; internal ram data ;-------------------------------------------------------- .area DSEG (DATA) _nrf_w_reg_PARM_2: .ds 1 _nrf_w_buf_PARM_2: .ds 3 _nrf_w_buf_PARM_3: .ds 1 _nrf_r_buf_PARM_2: .ds 3 _nrf_r_buf_PARM_3: .ds 1 _nrf24_check_buf_65536_33: .ds 5 _nrf24_check_rb_65536_33: .ds 5 ;-------------------------------------------------------- ; overlayable items in internal ram ;-------------------------------------------------------- ;-------------------------------------------------------- ; indirectly addressable internal ram data ;-------------------------------------------------------- .area ISEG (DATA) ;-------------------------------------------------------- ; absolute internal ram data ;-------------------------------------------------------- .area IABS (ABS,DATA) .area IABS (ABS,DATA) ;-------------------------------------------------------- ; bit data ;-------------------------------------------------------- .area BSEG (BIT) ;-------------------------------------------------------- ; paged external ram data ;-------------------------------------------------------- .area PSEG (PAG,XDATA) ;-------------------------------------------------------- ; external ram data ;-------------------------------------------------------- .area XSEG (XDATA) _g_nrf_status:: .ds 36 ;-------------------------------------------------------- ; absolute external ram data ;-------------------------------------------------------- .area XABS (ABS,XDATA) ;-------------------------------------------------------- ; external initialized ram data ;-------------------------------------------------------- .area XISEG (XDATA) .area HOME (CODE) .area GSINIT0 (CODE) .area GSINIT1 (CODE) .area GSINIT2 (CODE) .area GSINIT3 (CODE) .area GSINIT4 (CODE) .area GSINIT5 (CODE) .area GSINIT (CODE) .area GSFINAL (CODE) .area CSEG (CODE) ;-------------------------------------------------------- ; global & static initialisations ;-------------------------------------------------------- .area HOME (CODE) .area GSINIT (CODE) .area GSFINAL (CODE) .area GSINIT (CODE) ;-------------------------------------------------------- ; Home ;-------------------------------------------------------- .area HOME (CODE) .area HOME (CODE) ;-------------------------------------------------------- ; code ;-------------------------------------------------------- .area CSEG (CODE) ;------------------------------------------------------------ ;Allocation info for local variables in function 'nrf_w_reg' ;------------------------------------------------------------ ;val Allocated with name '_nrf_w_reg_PARM_2' ;reg Allocated to registers r7 ;r Allocated to registers r7 ;------------------------------------------------------------ ; src/nrf24l01.c:21: static uint8_t nrf_w_reg(uint8_t reg, uint8_t val) ; ----------------------------------------- ; function nrf_w_reg ; ----------------------------------------- _nrf_w_reg: ar7 = 0x07 ar6 = 0x06 ar5 = 0x05 ar4 = 0x04 ar3 = 0x03 ar2 = 0x02 ar1 = 0x01 ar0 = 0x00 mov r7,dpl ; src/nrf24l01.c:24: CSN_L(); mov _gpio_write_PARM_2,#0x04 mov _gpio_write_PARM_3,#0x00 mov dpl,#0x05 push ar7 lcall _gpio_write pop ar7 ; src/nrf24l01.c:25: r = spi_transfer(reg); mov dpl,r7 lcall _spi_transfer mov r7,dpl ; src/nrf24l01.c:26: spi_transfer(val); mov dpl,_nrf_w_reg_PARM_2 push ar7 lcall _spi_transfer ; src/nrf24l01.c:27: CSN_H(); mov _gpio_write_PARM_2,#0x04 mov _gpio_write_PARM_3,#0x01 mov dpl,#0x05 lcall _gpio_write pop ar7 ; src/nrf24l01.c:28: return r; mov dpl,r7 ; src/nrf24l01.c:29: } ret ;------------------------------------------------------------ ;Allocation info for local variables in function 'nrf_w_buf' ;------------------------------------------------------------ ;buf Allocated with name '_nrf_w_buf_PARM_2' ;len Allocated with name '_nrf_w_buf_PARM_3' ;reg Allocated to registers r7 ;r Allocated to registers r7 ;------------------------------------------------------------ ; src/nrf24l01.c:31: static uint8_t nrf_w_buf(uint8_t reg, const uint8_t *buf, uint8_t len) ; ----------------------------------------- ; function nrf_w_buf ; ----------------------------------------- _nrf_w_buf: mov r7,dpl ; src/nrf24l01.c:34: CSN_L(); mov _gpio_write_PARM_2,#0x04 mov _gpio_write_PARM_3,#0x00 mov dpl,#0x05 push ar7 lcall _gpio_write pop ar7 ; src/nrf24l01.c:35: r = spi_transfer(reg); mov dpl,r7 lcall _spi_transfer mov r7,dpl ; src/nrf24l01.c:36: while (len--) spi_transfer(*buf++); mov r4,_nrf_w_buf_PARM_2 mov r5,(_nrf_w_buf_PARM_2 + 1) mov r6,(_nrf_w_buf_PARM_2 + 2) mov r3,_nrf_w_buf_PARM_3 00101$: mov ar2,r3 dec r3 mov a,r2 jz 00103$ mov dpl,r4 mov dph,r5 mov b,r6 lcall __gptrget mov r2,a inc dptr mov r4,dpl mov r5,dph mov dpl,r2 push ar7 push ar6 push ar5 push ar4 push ar3 lcall _spi_transfer pop ar3 pop ar4 pop ar5 pop ar6 pop ar7 sjmp 00101$ 00103$: ; src/nrf24l01.c:37: CSN_H(); mov _gpio_write_PARM_2,#0x04 mov _gpio_write_PARM_3,#0x01 mov dpl,#0x05 push ar7 lcall _gpio_write pop ar7 ; src/nrf24l01.c:38: return r; mov dpl,r7 ; src/nrf24l01.c:39: } ret ;------------------------------------------------------------ ;Allocation info for local variables in function 'nrf_r_reg' ;------------------------------------------------------------ ;reg Allocated to registers r7 ;v Allocated to registers r7 ;------------------------------------------------------------ ; src/nrf24l01.c:41: static uint8_t nrf_r_reg(uint8_t reg) ; ----------------------------------------- ; function nrf_r_reg ; ----------------------------------------- _nrf_r_reg: mov r7,dpl ; src/nrf24l01.c:44: CSN_L(); mov _gpio_write_PARM_2,#0x04 mov _gpio_write_PARM_3,#0x00 mov dpl,#0x05 push ar7 lcall _gpio_write pop ar7 ; src/nrf24l01.c:45: spi_transfer(reg); mov dpl,r7 lcall _spi_transfer ; src/nrf24l01.c:46: v = spi_transfer(0xFF); mov dpl,#0xff lcall _spi_transfer mov r7,dpl ; src/nrf24l01.c:47: CSN_H(); mov _gpio_write_PARM_2,#0x04 mov _gpio_write_PARM_3,#0x01 mov dpl,#0x05 push ar7 lcall _gpio_write pop ar7 ; src/nrf24l01.c:48: return v; mov dpl,r7 ; src/nrf24l01.c:49: } ret ;------------------------------------------------------------ ;Allocation info for local variables in function 'nrf_r_buf' ;------------------------------------------------------------ ;buf Allocated with name '_nrf_r_buf_PARM_2' ;len Allocated with name '_nrf_r_buf_PARM_3' ;reg Allocated to registers r7 ;r Allocated to registers r7 ;------------------------------------------------------------ ; src/nrf24l01.c:51: static uint8_t nrf_r_buf(uint8_t reg, uint8_t *buf, uint8_t len) ; ----------------------------------------- ; function nrf_r_buf ; ----------------------------------------- _nrf_r_buf: mov r7,dpl ; src/nrf24l01.c:54: CSN_L(); mov _gpio_write_PARM_2,#0x04 mov _gpio_write_PARM_3,#0x00 mov dpl,#0x05 push ar7 lcall _gpio_write pop ar7 ; src/nrf24l01.c:55: r = spi_transfer(reg); mov dpl,r7 lcall _spi_transfer mov r7,dpl ; src/nrf24l01.c:56: while (len--) *buf++ = spi_transfer(0xFF); mov r4,_nrf_r_buf_PARM_2 mov r5,(_nrf_r_buf_PARM_2 + 1) mov r6,(_nrf_r_buf_PARM_2 + 2) mov r3,_nrf_r_buf_PARM_3 00101$: mov ar2,r3 dec r3 mov a,r2 jz 00103$ mov dpl,#0xff push ar7 push ar6 push ar5 push ar4 push ar3 lcall _spi_transfer mov r2,dpl pop ar3 pop ar4 pop ar5 pop ar6 pop ar7 mov dpl,r4 mov dph,r5 mov b,r6 mov a,r2 lcall __gptrput inc dptr mov r4,dpl mov r5,dph sjmp 00101$ 00103$: ; src/nrf24l01.c:57: CSN_H(); mov _gpio_write_PARM_2,#0x04 mov _gpio_write_PARM_3,#0x01 mov dpl,#0x05 push ar7 lcall _gpio_write pop ar7 ; src/nrf24l01.c:58: return r; mov dpl,r7 ; src/nrf24l01.c:59: } ret ;------------------------------------------------------------ ;Allocation info for local variables in function 'nrf_flush_rx' ;------------------------------------------------------------ ; src/nrf24l01.c:61: static void nrf_flush_rx(void) { CSN_L(); spi_transfer(NRF_CMD_FLUSH_RX); CSN_H(); } ; ----------------------------------------- ; function nrf_flush_rx ; ----------------------------------------- _nrf_flush_rx: mov _gpio_write_PARM_2,#0x04 mov _gpio_write_PARM_3,#0x00 mov dpl,#0x05 lcall _gpio_write mov dpl,#0xe2 lcall _spi_transfer mov _gpio_write_PARM_2,#0x04 mov _gpio_write_PARM_3,#0x01 mov dpl,#0x05 ljmp _gpio_write ;------------------------------------------------------------ ;Allocation info for local variables in function 'nrf_flush_tx' ;------------------------------------------------------------ ; src/nrf24l01.c:62: static void nrf_flush_tx(void) { CSN_L(); spi_transfer(NRF_CMD_FLUSH_TX); CSN_H(); } ; ----------------------------------------- ; function nrf_flush_tx ; ----------------------------------------- _nrf_flush_tx: mov _gpio_write_PARM_2,#0x04 mov _gpio_write_PARM_3,#0x00 mov dpl,#0x05 lcall _gpio_write mov dpl,#0xe1 lcall _spi_transfer mov _gpio_write_PARM_2,#0x04 mov _gpio_write_PARM_3,#0x01 mov dpl,#0x05 ljmp _gpio_write ;------------------------------------------------------------ ;Allocation info for local variables in function 'nrf24_init' ;------------------------------------------------------------ ;s Allocated to registers ;------------------------------------------------------------ ; src/nrf24l01.c:64: void nrf24_init(void) ; ----------------------------------------- ; function nrf24_init ; ----------------------------------------- _nrf24_init: ; src/nrf24l01.c:67: gpio_set_mode(NRF_CSN_PORT, NRF_CSN_BIT, GPIO_MODE_PUSHPULL); mov _gpio_set_mode_PARM_2,#0x04 mov _gpio_set_mode_PARM_3,#0x01 mov dpl,#0x05 lcall _gpio_set_mode ; src/nrf24l01.c:68: gpio_set_mode(NRF_CE_PORT, NRF_CE_BIT, GPIO_MODE_PUSHPULL); mov _gpio_set_mode_PARM_2,#0x06 mov _gpio_set_mode_PARM_3,#0x01 mov dpl,#0x01 lcall _gpio_set_mode ; src/nrf24l01.c:70: gpio_set_mode(NRF_IRQ_PORT, NRF_IRQ_BIT, GPIO_MODE_INPUT); mov _gpio_set_mode_PARM_2,#0x07 mov _gpio_set_mode_PARM_3,#0x02 mov dpl,#0x01 lcall _gpio_set_mode ; src/nrf24l01.c:72: CE_L(); mov _gpio_write_PARM_2,#0x06 mov _gpio_write_PARM_3,#0x00 mov dpl,#0x01 lcall _gpio_write ; src/nrf24l01.c:73: CSN_H(); mov _gpio_write_PARM_2,#0x04 mov _gpio_write_PARM_3,#0x01 mov dpl,#0x05 lcall _gpio_write ; src/nrf24l01.c:74: delay_ms(100); mov dptr,#0x0064 lcall _delay_ms ; src/nrf24l01.c:77: nrf_w_buf(NRF_CMD_W_REGISTER + NRF_REG_RX_ADDR_P0, DEFAULT_ADDR, 5); mov _nrf_w_buf_PARM_2,#_DEFAULT_ADDR mov (_nrf_w_buf_PARM_2 + 1),#(_DEFAULT_ADDR >> 8) mov (_nrf_w_buf_PARM_2 + 2),#0x80 mov _nrf_w_buf_PARM_3,#0x05 mov dpl,#0x2a lcall _nrf_w_buf ; src/nrf24l01.c:78: nrf_w_buf(NRF_CMD_W_REGISTER + NRF_REG_TX_ADDR, DEFAULT_ADDR, 5); mov _nrf_w_buf_PARM_2,#_DEFAULT_ADDR mov (_nrf_w_buf_PARM_2 + 1),#(_DEFAULT_ADDR >> 8) mov (_nrf_w_buf_PARM_2 + 2),#0x80 mov _nrf_w_buf_PARM_3,#0x05 mov dpl,#0x30 lcall _nrf_w_buf ; src/nrf24l01.c:80: nrf_w_reg(NRF_CMD_W_REGISTER + NRF_REG_EN_AA, 0x01); /* 通道0 自动应答 */ mov _nrf_w_reg_PARM_2,#0x01 mov dpl,#0x21 lcall _nrf_w_reg ; src/nrf24l01.c:81: nrf_w_reg(NRF_CMD_W_REGISTER + NRF_REG_EN_RXADDR, 0x01); mov _nrf_w_reg_PARM_2,#0x01 mov dpl,#0x22 lcall _nrf_w_reg ; src/nrf24l01.c:82: nrf_w_reg(NRF_CMD_W_REGISTER + NRF_REG_SETUP_AW, 0x03); /* 5 字节 */ mov _nrf_w_reg_PARM_2,#0x03 mov dpl,#0x23 lcall _nrf_w_reg ; src/nrf24l01.c:83: nrf_w_reg(NRF_CMD_W_REGISTER + NRF_REG_SETUP_RETR, 0x1A); mov _nrf_w_reg_PARM_2,#0x1a mov dpl,#0x24 lcall _nrf_w_reg ; src/nrf24l01.c:84: nrf_w_reg(NRF_CMD_W_REGISTER + NRF_REG_RF_CH, DEFAULT_RF_CH); mov _nrf_w_reg_PARM_2,#0x4c mov dpl,#0x25 lcall _nrf_w_reg ; src/nrf24l01.c:85: nrf_w_reg(NRF_CMD_W_REGISTER + NRF_REG_RF_SETUP, 0x0F); /* 0dBm, 2Mbps */ mov _nrf_w_reg_PARM_2,#0x0f mov dpl,#0x26 lcall _nrf_w_reg ; src/nrf24l01.c:86: nrf_w_reg(NRF_CMD_W_REGISTER + NRF_REG_RX_PW_P0, NRF_PAYLOAD_LEN); mov _nrf_w_reg_PARM_2,#0x20 mov dpl,#0x31 lcall _nrf_w_reg ; src/nrf24l01.c:87: nrf_w_reg(NRF_CMD_W_REGISTER + NRF_REG_DYNPD, 0x01); /* 动态载荷 (P0) */ mov _nrf_w_reg_PARM_2,#0x01 mov dpl,#0x3c lcall _nrf_w_reg ; src/nrf24l01.c:88: nrf_w_reg(NRF_CMD_W_REGISTER + NRF_REG_FEATURE, 0x06); /* EN_DPL | EN_ACK_PAY */ mov _nrf_w_reg_PARM_2,#0x06 mov dpl,#0x3d lcall _nrf_w_reg ; src/nrf24l01.c:91: nrf_w_reg(NRF_CMD_W_REGISTER + NRF_REG_CONFIG, 0x0F); mov _nrf_w_reg_PARM_2,#0x0f mov dpl,#0x20 lcall _nrf_w_reg ; src/nrf24l01.c:95: uint8_t s = nrf_r_reg(NRF_REG_STATUS); mov dpl,#0x07 lcall _nrf_r_reg mov _nrf_w_reg_PARM_2,dpl ; src/nrf24l01.c:96: nrf_w_reg(NRF_CMD_W_REGISTER + NRF_REG_STATUS, s); mov dpl,#0x27 lcall _nrf_w_reg ; src/nrf24l01.c:99: g_nrf_status.last_status = 0; mov dptr,#_g_nrf_status clr a movx @dptr,a ; src/nrf24l01.c:100: g_nrf_status.rx_count = 0; mov dptr,#(_g_nrf_status + 0x0001) movx @dptr,a ; src/nrf24l01.c:101: g_nrf_status.ack_pending = 0; mov dptr,#(_g_nrf_status + 0x0003) movx @dptr,a ; src/nrf24l01.c:102: } ret ;------------------------------------------------------------ ;Allocation info for local variables in function 'nrf24_check' ;------------------------------------------------------------ ;buf Allocated with name '_nrf24_check_buf_65536_33' ;rb Allocated with name '_nrf24_check_rb_65536_33' ;i Allocated to registers r7 ;------------------------------------------------------------ ; src/nrf24l01.c:104: uint8_t nrf24_check(void) ; ----------------------------------------- ; function nrf24_check ; ----------------------------------------- _nrf24_check: ; src/nrf24l01.c:106: uint8_t buf[5] = { 0xA5, 0xA5, 0xA5, 0xA5, 0xA5 }; mov _nrf24_check_buf_65536_33,#0xa5 mov (_nrf24_check_buf_65536_33 + 0x0001),#0xa5 mov (_nrf24_check_buf_65536_33 + 0x0002),#0xa5 mov (_nrf24_check_buf_65536_33 + 0x0003),#0xa5 mov (_nrf24_check_buf_65536_33 + 0x0004),#0xa5 ; src/nrf24l01.c:108: nrf_w_buf(NRF_CMD_W_REGISTER + NRF_REG_TX_ADDR, buf, 5); mov _nrf_w_buf_PARM_2,#_nrf24_check_buf_65536_33 mov (_nrf_w_buf_PARM_2 + 1),#0x00 mov (_nrf_w_buf_PARM_2 + 2),#0x40 mov _nrf_w_buf_PARM_3,#0x05 mov dpl,#0x30 lcall _nrf_w_buf ; src/nrf24l01.c:109: nrf_r_buf(NRF_REG_TX_ADDR, rb, 5); mov _nrf_r_buf_PARM_2,#_nrf24_check_rb_65536_33 mov (_nrf_r_buf_PARM_2 + 1),#0x00 mov (_nrf_r_buf_PARM_2 + 2),#0x40 mov _nrf_r_buf_PARM_3,#0x05 mov dpl,#0x10 lcall _nrf_r_buf ; src/nrf24l01.c:110: for (uint8_t i = 0; i < 5; i++) if (rb[i] != 0xA5) return NRF_ERR_CHECK; mov r7,#0x00 00105$: cjne r7,#0x05,00121$ 00121$: jnc 00103$ mov a,r7 add a,#_nrf24_check_rb_65536_33 mov r1,a mov ar6,@r1 cjne r6,#0xa5,00123$ sjmp 00106$ 00123$: mov dpl,#0x01 ret 00106$: inc r7 sjmp 00105$ 00103$: ; src/nrf24l01.c:112: nrf_w_buf(NRF_CMD_W_REGISTER + NRF_REG_TX_ADDR, DEFAULT_ADDR, 5); mov _nrf_w_buf_PARM_2,#_DEFAULT_ADDR mov (_nrf_w_buf_PARM_2 + 1),#(_DEFAULT_ADDR >> 8) mov (_nrf_w_buf_PARM_2 + 2),#0x80 mov _nrf_w_buf_PARM_3,#0x05 mov dpl,#0x30 lcall _nrf_w_buf ; src/nrf24l01.c:113: return NRF_OK; mov dpl,#0x00 ; src/nrf24l01.c:114: } ret ;------------------------------------------------------------ ;Allocation info for local variables in function 'nrf24_set_channel' ;------------------------------------------------------------ ;ch Allocated to registers r7 ;------------------------------------------------------------ ; src/nrf24l01.c:116: void nrf24_set_channel(uint8_t ch) ; ----------------------------------------- ; function nrf24_set_channel ; ----------------------------------------- _nrf24_set_channel: ; src/nrf24l01.c:118: if (ch > 125) ch = 125; mov a,dpl mov r7,a add a,#0xff - 0x7d jnc 00102$ mov r7,#0x7d 00102$: ; src/nrf24l01.c:119: nrf_w_reg(NRF_CMD_W_REGISTER + NRF_REG_RF_CH, ch); mov _nrf_w_reg_PARM_2,r7 mov dpl,#0x25 ; src/nrf24l01.c:120: } ljmp _nrf_w_reg ;------------------------------------------------------------ ;Allocation info for local variables in function 'nrf24_set_address' ;------------------------------------------------------------ ;addr5 Allocated to registers r5 r6 r7 ;------------------------------------------------------------ ; src/nrf24l01.c:122: void nrf24_set_address(const uint8_t *addr5) ; ----------------------------------------- ; function nrf24_set_address ; ----------------------------------------- _nrf24_set_address: mov r5,dpl mov r6,dph mov r7,b ; src/nrf24l01.c:124: nrf_w_buf(NRF_CMD_W_REGISTER + NRF_REG_RX_ADDR_P0, addr5, 5); mov _nrf_w_buf_PARM_2,r5 mov (_nrf_w_buf_PARM_2 + 1),r6 mov (_nrf_w_buf_PARM_2 + 2),r7 mov _nrf_w_buf_PARM_3,#0x05 mov dpl,#0x2a push ar7 push ar6 push ar5 lcall _nrf_w_buf pop ar5 pop ar6 pop ar7 ; src/nrf24l01.c:125: nrf_w_buf(NRF_CMD_W_REGISTER + NRF_REG_TX_ADDR, addr5, 5); mov _nrf_w_buf_PARM_2,r5 mov (_nrf_w_buf_PARM_2 + 1),r6 mov (_nrf_w_buf_PARM_2 + 2),r7 mov _nrf_w_buf_PARM_3,#0x05 mov dpl,#0x30 ; src/nrf24l01.c:126: } ljmp _nrf_w_buf ;------------------------------------------------------------ ;Allocation info for local variables in function 'nrf24_set_rx_mode' ;------------------------------------------------------------ ;cfg Allocated to registers ;------------------------------------------------------------ ; src/nrf24l01.c:128: void nrf24_set_rx_mode(void) ; ----------------------------------------- ; function nrf24_set_rx_mode ; ----------------------------------------- _nrf24_set_rx_mode: ; src/nrf24l01.c:130: uint8_t cfg = nrf_r_reg(NRF_REG_CONFIG); mov dpl,#0x00 lcall _nrf_r_reg mov a,dpl ; src/nrf24l01.c:131: nrf_w_reg(NRF_CMD_W_REGISTER + NRF_REG_CONFIG, (cfg & 0x7C) | 0x0F); /* PWR_UP, CRC 2B, PRIM_RX */ anl a,#0x7c orl a,#0x0f mov _nrf_w_reg_PARM_2,a mov dpl,#0x20 lcall _nrf_w_reg ; src/nrf24l01.c:132: CE_H(); mov _gpio_write_PARM_2,#0x06 mov _gpio_write_PARM_3,#0x01 mov dpl,#0x01 lcall _gpio_write ; src/nrf24l01.c:133: delay_us(130); /* ≥130us 进入接收 */ mov dptr,#0x0082 ; src/nrf24l01.c:134: } ljmp _delay_us ;------------------------------------------------------------ ;Allocation info for local variables in function 'nrf24_data_ready' ;------------------------------------------------------------ ;status Allocated to registers r7 ;------------------------------------------------------------ ; src/nrf24l01.c:136: uint8_t nrf24_data_ready(void) ; ----------------------------------------- ; function nrf24_data_ready ; ----------------------------------------- _nrf24_data_ready: ; src/nrf24l01.c:138: uint8_t status = nrf_r_reg(NRF_REG_STATUS); mov dpl,#0x07 lcall _nrf_r_reg ; src/nrf24l01.c:139: if (status & NRF_STATUS_RX_DR) { mov a,dpl mov r7,a jnb acc.6,00102$ ; src/nrf24l01.c:141: nrf_r_buf(NRF_CMD_R_RX_PAYLOAD, g_nrf_status.ack_payload, NRF_PAYLOAD_LEN); mov _nrf_r_buf_PARM_2,#(_g_nrf_status + 0x0004) mov (_nrf_r_buf_PARM_2 + 1),#((_g_nrf_status + 0x0004) >> 8) mov (_nrf_r_buf_PARM_2 + 2),#0x00 mov _nrf_r_buf_PARM_3,#0x20 mov dpl,#0x61 push ar7 lcall _nrf_r_buf ; src/nrf24l01.c:142: nrf_flush_rx(); lcall _nrf_flush_rx pop ar7 ; src/nrf24l01.c:143: nrf_w_reg(NRF_CMD_W_REGISTER + NRF_REG_STATUS, status); mov _nrf_w_reg_PARM_2,r7 mov dpl,#0x27 push ar7 lcall _nrf_w_reg pop ar7 ; src/nrf24l01.c:144: g_nrf_status.last_status = status; mov dptr,#_g_nrf_status mov a,r7 movx @dptr,a ; src/nrf24l01.c:145: g_nrf_status.rx_count++; mov dptr,#(_g_nrf_status + 0x0001) movx a,@dptr mov r7,a inc r7 mov dptr,#(_g_nrf_status + 0x0001) mov a,r7 movx @dptr,a ; src/nrf24l01.c:146: return 1; mov dpl,#0x01 ret 00102$: ; src/nrf24l01.c:148: return 0; mov dpl,#0x00 ; src/nrf24l01.c:149: } ret ;------------------------------------------------------------ ;Allocation info for local variables in function 'nrf24_write_ack_payload' ;------------------------------------------------------------ ;buf Allocated to registers r5 r6 r7 ;i Allocated to registers r4 ;------------------------------------------------------------ ; src/nrf24l01.c:151: void nrf24_write_ack_payload(const uint8_t *buf) ; ----------------------------------------- ; function nrf24_write_ack_payload ; ----------------------------------------- _nrf24_write_ack_payload: mov r5,dpl mov r6,dph mov r7,b ; src/nrf24l01.c:154: CSN_L(); mov _gpio_write_PARM_2,#0x04 mov _gpio_write_PARM_3,#0x00 mov dpl,#0x05 push ar7 push ar6 push ar5 lcall _gpio_write ; src/nrf24l01.c:155: spi_transfer(NRF_CMD_W_ACK_PAYLOAD); /* P0 */ mov dpl,#0xa8 lcall _spi_transfer pop ar5 pop ar6 pop ar7 ; src/nrf24l01.c:156: for (uint8_t i = 0; i < NRF_PAYLOAD_LEN; i++) { mov r4,#0x00 00103$: cjne r4,#0x20,00116$ 00116$: jnc 00101$ ; src/nrf24l01.c:157: spi_transfer(buf[i]); mov a,r4 add a,r5 mov r1,a clr a addc a,r6 mov r2,a mov ar3,r7 mov dpl,r1 mov dph,r2 mov b,r3 lcall __gptrget mov dpl,a push ar7 push ar6 push ar5 push ar4 lcall _spi_transfer pop ar4 pop ar5 pop ar6 pop ar7 ; src/nrf24l01.c:156: for (uint8_t i = 0; i < NRF_PAYLOAD_LEN; i++) { inc r4 sjmp 00103$ 00101$: ; src/nrf24l01.c:159: CSN_H(); mov _gpio_write_PARM_2,#0x04 mov _gpio_write_PARM_3,#0x01 mov dpl,#0x05 ; src/nrf24l01.c:160: } ljmp _gpio_write ;------------------------------------------------------------ ;Allocation info for local variables in function 'nrf24_irq_handler' ;------------------------------------------------------------ ;status Allocated to registers r7 ;------------------------------------------------------------ ; src/nrf24l01.c:162: void nrf24_irq_handler(void) ; ----------------------------------------- ; function nrf24_irq_handler ; ----------------------------------------- _nrf24_irq_handler: ; src/nrf24l01.c:164: uint8_t status = nrf_r_reg(NRF_REG_STATUS); mov dpl,#0x07 lcall _nrf_r_reg mov r7,dpl ; src/nrf24l01.c:165: nrf_w_reg(NRF_CMD_W_REGISTER + NRF_REG_STATUS, status); mov _nrf_w_reg_PARM_2,r7 mov dpl,#0x27 push ar7 lcall _nrf_w_reg pop ar7 ; src/nrf24l01.c:166: g_nrf_status.last_status = status; mov dptr,#_g_nrf_status mov a,r7 movx @dptr,a ; src/nrf24l01.c:168: if (status & NRF_STATUS_RX_DR) { mov a,r7 jnb acc.6,00102$ ; src/nrf24l01.c:169: g_nrf_status.rx_count++; mov dptr,#(_g_nrf_status + 0x0001) movx a,@dptr mov r6,a inc r6 mov dptr,#(_g_nrf_status + 0x0001) mov a,r6 movx @dptr,a 00102$: ; src/nrf24l01.c:171: if (status & NRF_STATUS_MAX_RT) { mov a,r7 jnb acc.4,00105$ ; src/nrf24l01.c:172: nrf_flush_tx(); ; src/nrf24l01.c:174: } ljmp _nrf_flush_tx 00105$: ret .area CSEG (CODE) .area CONST (CODE) _DEFAULT_ADDR: .db #0xe7 ; 231 .db #0xe7 ; 231 .db #0xe7 ; 231 .db #0xe7 ; 231 .db #0xc2 ; 194 .area XINIT (CODE) .area CABS (ABS,CODE)