1 ;-------------------------------------------------------- 2 ; File Created by SDCC : free open source ANSI-C Compiler 3 ; Version 4.2.0 #13081 (Linux) 4 ;-------------------------------------------------------- 5 .module gpio 6 .optsdcc -mmcs51 --model-small 7 8 ;-------------------------------------------------------- 9 ; Public variables in this module 10 ;-------------------------------------------------------- 11 .globl _gpio_toggle_PARM_2 12 .globl _gpio_read_PARM_2 13 .globl _gpio_write_PARM_3 14 .globl _gpio_write_PARM_2 15 .globl _EADC 16 .globl _ET1 17 .globl _ET0 18 .globl _ES 19 .globl _EA 20 .globl _REN 21 .globl _RI 22 .globl _TI 23 .globl _TR1 24 .globl _TF1 25 .globl _IT0 26 .globl _IE0 27 .globl _TR0 28 .globl _TF0 29 .globl _P5M0_REG 30 .globl _P5M1_REG 31 .globl _P4M0_REG 32 .globl _P4M1_REG 33 .globl _P3M0_REG 34 .globl _P3M1_REG 35 .globl _P2M0_REG 36 .globl _P2M1_REG 37 .globl _P1M0_REG 38 .globl _P1M1_REG 39 .globl _P0M0_REG 40 .globl _P0M1_REG 41 .globl _P5_REG 42 .globl _P4_REG 43 .globl _P3_REG 44 .globl _P2_REG 45 .globl _P1_REG 46 .globl _P0_REG 47 .globl _CMPCR2 48 .globl _CMPCR1 49 .globl _TA 50 .globl _IRCBAND_REG 51 .globl _IAP_TPS 52 .globl _IAP_CONTR 53 .globl _IAP_TRIG 54 .globl _IAP_CMD 55 .globl _IAP_ADDRL 56 .globl _IAP_ADDRH 57 .globl _IAP_DATA 58 .globl _WDT_CONTR 59 .globl _PCA_PWM3 60 .globl _PCA_PWM2 61 .globl _PCA_PWM1 62 .globl _PCA_PWM0 63 .globl _CCAP3L 64 .globl _CCAP2L 65 .globl _CCAP1L 66 .globl _CCAP0L 67 .globl _CCAPM3 68 .globl _CCAPM2 69 .globl _CCAPM1 70 .globl _CCAPM0 71 .globl _CMOD 72 .globl _CCON 73 .globl _ADCTIM_X 74 .globl _ADCCFG 75 .globl _ADC_RESL 76 .globl _ADC_RES 77 .globl _ADC_CONTR 78 .globl _SPDAT 79 .globl _SPCTL 80 .globl _SPSTAT 81 .globl _IP2H 82 .globl _IP2 83 .globl _IP 84 .globl _IE2 85 .globl _IE 86 .globl _BRT 87 .globl _P_SW1 88 .globl _SADEN 89 .globl _SADDR 90 .globl _S2BUF 91 .globl _S2CON 92 .globl _SBUF 93 .globl _SCON 94 .globl _TM4PS_X 95 .globl _TM3PS_X 96 .globl _TM2PS_X 97 .globl _T4T3M 98 .globl _T4L 99 .globl _T4H 100 .globl _T3L 101 .globl _T3H 102 .globl _T2L 103 .globl _T2H 104 .globl _INTCLKO 105 .globl _AUXR 106 .globl _TH1 107 .globl _TH0 108 .globl _TL1 109 .globl _TL0 110 .globl _TMOD 111 .globl _TCON 112 .globl _P_SW2 113 .globl _P5M0 114 .globl _P5M1 115 .globl _P4M0 116 .globl _P4M1 117 .globl _P3M0 118 .globl _P3M1 119 .globl _P2M0 120 .globl _P2M1 121 .globl _P1M0 122 .globl _P1M1 123 .globl _P0M0 124 .globl _P0M1 125 .globl _PSW 126 .globl _B 127 .globl _ACC 128 .globl _PCON 129 .globl _DPH 130 .globl _DPL 131 .globl _SP 132 .globl _P5 133 .globl _P4 134 .globl _P3 135 .globl _P2 136 .globl _P1 137 .globl _P0 138 .globl _gpio_set_mode_PARM_3 139 .globl _gpio_set_mode_PARM_2 140 .globl _gpio_set_mode 141 .globl _gpio_write 142 .globl _gpio_read 143 .globl _gpio_toggle 144 ;-------------------------------------------------------- 145 ; special function registers 146 ;-------------------------------------------------------- 147 .area RSEG (ABS,DATA) 000000 148 .org 0x0000 000080 149 _P0 = 0x0080 000090 150 _P1 = 0x0090 0000A0 151 _P2 = 0x00a0 0000B0 152 _P3 = 0x00b0 0000C0 153 _P4 = 0x00c0 0000C8 154 _P5 = 0x00c8 000081 155 _SP = 0x0081 000082 156 _DPL = 0x0082 000083 157 _DPH = 0x0083 000087 158 _PCON = 0x0087 0000E0 159 _ACC = 0x00e0 0000F0 160 _B = 0x00f0 0000D0 161 _PSW = 0x00d0 000093 162 _P0M1 = 0x0093 000094 163 _P0M0 = 0x0094 000091 164 _P1M1 = 0x0091 000092 165 _P1M0 = 0x0092 000095 166 _P2M1 = 0x0095 000096 167 _P2M0 = 0x0096 0000B1 168 _P3M1 = 0x00b1 0000B2 169 _P3M0 = 0x00b2 0000B3 170 _P4M1 = 0x00b3 0000B4 171 _P4M0 = 0x00b4 0000C9 172 _P5M1 = 0x00c9 0000CA 173 _P5M0 = 0x00ca 0000BA 174 _P_SW2 = 0x00ba 000088 175 _TCON = 0x0088 000089 176 _TMOD = 0x0089 00008A 177 _TL0 = 0x008a 00008B 178 _TL1 = 0x008b 00008C 179 _TH0 = 0x008c 00008D 180 _TH1 = 0x008d 00008E 181 _AUXR = 0x008e 00008F 182 _INTCLKO = 0x008f 0000D6 183 _T2H = 0x00d6 0000D7 184 _T2L = 0x00d7 0000D4 185 _T3H = 0x00d4 0000D5 186 _T3L = 0x00d5 0000D2 187 _T4H = 0x00d2 0000D3 188 _T4L = 0x00d3 0000D1 189 _T4T3M = 0x00d1 00FEA1 190 _TM2PS_X = 0xfea1 00FEA2 191 _TM3PS_X = 0xfea2 00FEA3 192 _TM4PS_X = 0xfea3 000098 193 _SCON = 0x0098 000099 194 _SBUF = 0x0099 00009A 195 _S2CON = 0x009a 00009B 196 _S2BUF = 0x009b 0000A9 197 _SADDR = 0x00a9 0000B9 198 _SADEN = 0x00b9 0000A2 199 _P_SW1 = 0x00a2 00009C 200 _BRT = 0x009c 0000A8 201 _IE = 0x00a8 0000AF 202 _IE2 = 0x00af 0000B8 203 _IP = 0x00b8 0000B6 204 _IP2 = 0x00b6 0000B7 205 _IP2H = 0x00b7 0000CD 206 _SPSTAT = 0x00cd 0000CE 207 _SPCTL = 0x00ce 0000CF 208 _SPDAT = 0x00cf 0000BC 209 _ADC_CONTR = 0x00bc 0000BD 210 _ADC_RES = 0x00bd 0000BE 211 _ADC_RESL = 0x00be 0000DE 212 _ADCCFG = 0x00de 00FEA8 213 _ADCTIM_X = 0xfea8 0000D8 214 _CCON = 0x00d8 0000D9 215 _CMOD = 0x00d9 0000DA 216 _CCAPM0 = 0x00da 0000DB 217 _CCAPM1 = 0x00db 0000DC 218 _CCAPM2 = 0x00dc 0000DD 219 _CCAPM3 = 0x00dd 0000EA 220 _CCAP0L = 0x00ea 0000EB 221 _CCAP1L = 0x00eb 0000EC 222 _CCAP2L = 0x00ec 0000ED 223 _CCAP3L = 0x00ed 0000F2 224 _PCA_PWM0 = 0x00f2 0000F3 225 _PCA_PWM1 = 0x00f3 0000F4 226 _PCA_PWM2 = 0x00f4 0000F5 227 _PCA_PWM3 = 0x00f5 0000C1 228 _WDT_CONTR = 0x00c1 0000C2 229 _IAP_DATA = 0x00c2 0000C3 230 _IAP_ADDRH = 0x00c3 0000C4 231 _IAP_ADDRL = 0x00c4 0000C5 232 _IAP_CMD = 0x00c5 0000C6 233 _IAP_TRIG = 0x00c6 0000C7 234 _IAP_CONTR = 0x00c7 0000F7 235 _IAP_TPS = 0x00f7 00009D 236 _IRCBAND_REG = 0x009d 0000AE 237 _TA = 0x00ae 0000E6 238 _CMPCR1 = 0x00e6 0000E7 239 _CMPCR2 = 0x00e7 000080 240 _P0_REG = 0x0080 000090 241 _P1_REG = 0x0090 0000A0 242 _P2_REG = 0x00a0 0000B0 243 _P3_REG = 0x00b0 0000C0 244 _P4_REG = 0x00c0 0000C8 245 _P5_REG = 0x00c8 000093 246 _P0M1_REG = 0x0093 000094 247 _P0M0_REG = 0x0094 000091 248 _P1M1_REG = 0x0091 000092 249 _P1M0_REG = 0x0092 000095 250 _P2M1_REG = 0x0095 000096 251 _P2M0_REG = 0x0096 0000B1 252 _P3M1_REG = 0x00b1 0000B2 253 _P3M0_REG = 0x00b2 0000B3 254 _P4M1_REG = 0x00b3 0000B4 255 _P4M0_REG = 0x00b4 0000C9 256 _P5M1_REG = 0x00c9 0000CA 257 _P5M0_REG = 0x00ca 258 ;-------------------------------------------------------- 259 ; special function bits 260 ;-------------------------------------------------------- 261 .area RSEG (ABS,DATA) 000000 262 .org 0x0000 00008D 263 _TF0 = 0x008d 00008C 264 _TR0 = 0x008c 000089 265 _IE0 = 0x0089 000088 266 _IT0 = 0x0088 00008F 267 _TF1 = 0x008f 00008E 268 _TR1 = 0x008e 000099 269 _TI = 0x0099 000098 270 _RI = 0x0098 00009C 271 _REN = 0x009c 0000AF 272 _EA = 0x00af 0000AC 273 _ES = 0x00ac 0000A9 274 _ET0 = 0x00a9 0000AB 275 _ET1 = 0x00ab 0000AD 276 _EADC = 0x00ad 277 ;-------------------------------------------------------- 278 ; overlayable register banks 279 ;-------------------------------------------------------- 280 .area REG_BANK_0 (REL,OVR,DATA) 000000 281 .ds 8 282 ;-------------------------------------------------------- 283 ; internal ram data 284 ;-------------------------------------------------------- 285 .area DSEG (DATA) 000000 286 _gpio_set_mode_PARM_2: 000000 287 .ds 1 000001 288 _gpio_set_mode_PARM_3: 000001 289 .ds 1 290 ;-------------------------------------------------------- 291 ; overlayable items in internal ram 292 ;-------------------------------------------------------- 293 .area OSEG (OVR,DATA) 000000 294 _set_m0_PARM_2: 000000 295 .ds 1 000001 296 _set_m0_PARM_3: 000001 297 .ds 1 298 .area OSEG (OVR,DATA) 000000 299 _set_m1_PARM_2: 000000 300 .ds 1 000001 301 _set_m1_PARM_3: 000001 302 .ds 1 303 .area OSEG (OVR,DATA) 000000 304 _gpio_write_PARM_2: 000000 305 .ds 1 000001 306 _gpio_write_PARM_3: 000001 307 .ds 1 308 .area OSEG (OVR,DATA) 000000 309 _gpio_read_PARM_2: 000000 310 .ds 1 311 .area OSEG (OVR,DATA) 000000 312 _gpio_toggle_PARM_2: 000000 313 .ds 1 314 ;-------------------------------------------------------- 315 ; indirectly addressable internal ram data 316 ;-------------------------------------------------------- 317 .area ISEG (DATA) 318 ;-------------------------------------------------------- 319 ; absolute internal ram data 320 ;-------------------------------------------------------- 321 .area IABS (ABS,DATA) 322 .area IABS (ABS,DATA) 323 ;-------------------------------------------------------- 324 ; bit data 325 ;-------------------------------------------------------- 326 .area BSEG (BIT) 327 ;-------------------------------------------------------- 328 ; paged external ram data 329 ;-------------------------------------------------------- 330 .area PSEG (PAG,XDATA) 331 ;-------------------------------------------------------- 332 ; external ram data 333 ;-------------------------------------------------------- 334 .area XSEG (XDATA) 335 ;-------------------------------------------------------- 336 ; absolute external ram data 337 ;-------------------------------------------------------- 338 .area XABS (ABS,XDATA) 339 ;-------------------------------------------------------- 340 ; external initialized ram data 341 ;-------------------------------------------------------- 342 .area XISEG (XDATA) 343 .area HOME (CODE) 344 .area GSINIT0 (CODE) 345 .area GSINIT1 (CODE) 346 .area GSINIT2 (CODE) 347 .area GSINIT3 (CODE) 348 .area GSINIT4 (CODE) 349 .area GSINIT5 (CODE) 350 .area GSINIT (CODE) 351 .area GSFINAL (CODE) 352 .area CSEG (CODE) 353 ;-------------------------------------------------------- 354 ; global & static initialisations 355 ;-------------------------------------------------------- 356 .area HOME (CODE) 357 .area GSINIT (CODE) 358 .area GSFINAL (CODE) 359 .area GSINIT (CODE) 360 ;-------------------------------------------------------- 361 ; Home 362 ;-------------------------------------------------------- 363 .area HOME (CODE) 364 .area HOME (CODE) 365 ;-------------------------------------------------------- 366 ; code 367 ;-------------------------------------------------------- 368 .area CSEG (CODE) 369 ;------------------------------------------------------------ 370 ;Allocation info for local variables in function 'set_m0' 371 ;------------------------------------------------------------ 372 ;pin Allocated with name '_set_m0_PARM_2' 373 ;bit Allocated with name '_set_m0_PARM_3' 374 ;port Allocated to registers r7 375 ;------------------------------------------------------------ 376 ; src/gpio.c:28: static void set_m0(uint8_t port, uint8_t pin, uint8_t bit) 377 ; ----------------------------------------- 378 ; function set_m0 379 ; ----------------------------------------- 000000 380 _set_m0: 000007 381 ar7 = 0x07 000006 382 ar6 = 0x06 000005 383 ar5 = 0x05 000004 384 ar4 = 0x04 000003 385 ar3 = 0x03 000002 386 ar2 = 0x02 000001 387 ar1 = 0x01 000000 388 ar0 = 0x00 389 ; src/gpio.c:30: switch (port) { 000000 E5 82 [12] 390 mov a,dpl 000002 FF [12] 391 mov r7,a 000003 24 FA [12] 392 add a,#0xff - 0x05 000005 50 01 [24] 393 jnc 00156$ 000007 22 [24] 394 ret 000008 395 00156$: 000008 EF [12] 396 mov a,r7 000009 2F [12] 397 add a,r7 00000A 2F [12] 398 add a,r7 00000B 90r00r0F [24] 399 mov dptr,#00157$ 00000E 73 [24] 400 jmp @a+dptr 00000F 401 00157$: 00000F 02r00r21 [24] 402 ljmp 00101$ 000012 02r00r4A [24] 403 ljmp 00105$ 000015 02r00r73 [24] 404 ljmp 00109$ 000018 02r00r9C [24] 405 ljmp 00113$ 00001B 02r00rC5 [24] 406 ljmp 00117$ 00001E 02r00rEE [24] 407 ljmp 00121$ 408 ; src/gpio.c:31: case 0: if (bit) P0M0_REG |= (1 << pin); else P0M0_REG &= ~(1 << pin); break; 000021 409 00101$: 000021 E5*01 [12] 410 mov a,_set_m0_PARM_3 000023 60 12 [24] 411 jz 00103$ 000025 AF*00 [24] 412 mov r7,_set_m0_PARM_2 000027 8F F0 [24] 413 mov b,r7 000029 05 F0 [12] 414 inc b 00002B 74 01 [12] 415 mov a,#0x01 00002D 80 02 [24] 416 sjmp 00161$ 00002F 417 00159$: 00002F 25 E0 [12] 418 add a,acc 000031 419 00161$: 000031 D5 F0 FB [24] 420 djnz b,00159$ 000034 42 94 [12] 421 orl _P0M0_REG,a 000036 22 [24] 422 ret 000037 423 00103$: 000037 AF*00 [24] 424 mov r7,_set_m0_PARM_2 000039 8F F0 [24] 425 mov b,r7 00003B 05 F0 [12] 426 inc b 00003D 74 01 [12] 427 mov a,#0x01 00003F 80 02 [24] 428 sjmp 00164$ 000041 429 00162$: 000041 25 E0 [12] 430 add a,acc 000043 431 00164$: 000043 D5 F0 FB [24] 432 djnz b,00162$ 000046 F4 [12] 433 cpl a 000047 52 94 [12] 434 anl _P0M0_REG,a 000049 22 [24] 435 ret 436 ; src/gpio.c:32: case 1: if (bit) P1M0_REG |= (1 << pin); else P1M0_REG &= ~(1 << pin); break; 00004A 437 00105$: 00004A E5*01 [12] 438 mov a,_set_m0_PARM_3 00004C 60 12 [24] 439 jz 00107$ 00004E AF*00 [24] 440 mov r7,_set_m0_PARM_2 000050 8F F0 [24] 441 mov b,r7 000052 05 F0 [12] 442 inc b 000054 74 01 [12] 443 mov a,#0x01 000056 80 02 [24] 444 sjmp 00168$ 000058 445 00166$: 000058 25 E0 [12] 446 add a,acc 00005A 447 00168$: 00005A D5 F0 FB [24] 448 djnz b,00166$ 00005D 42 92 [12] 449 orl _P1M0_REG,a 00005F 22 [24] 450 ret 000060 451 00107$: 000060 AF*00 [24] 452 mov r7,_set_m0_PARM_2 000062 8F F0 [24] 453 mov b,r7 000064 05 F0 [12] 454 inc b 000066 74 01 [12] 455 mov a,#0x01 000068 80 02 [24] 456 sjmp 00171$ 00006A 457 00169$: 00006A 25 E0 [12] 458 add a,acc 00006C 459 00171$: 00006C D5 F0 FB [24] 460 djnz b,00169$ 00006F F4 [12] 461 cpl a 000070 52 92 [12] 462 anl _P1M0_REG,a 000072 22 [24] 463 ret 464 ; src/gpio.c:33: case 2: if (bit) P2M0_REG |= (1 << pin); else P2M0_REG &= ~(1 << pin); break; 000073 465 00109$: 000073 E5*01 [12] 466 mov a,_set_m0_PARM_3 000075 60 12 [24] 467 jz 00111$ 000077 AF*00 [24] 468 mov r7,_set_m0_PARM_2 000079 8F F0 [24] 469 mov b,r7 00007B 05 F0 [12] 470 inc b 00007D 74 01 [12] 471 mov a,#0x01 00007F 80 02 [24] 472 sjmp 00175$ 000081 473 00173$: 000081 25 E0 [12] 474 add a,acc 000083 475 00175$: 000083 D5 F0 FB [24] 476 djnz b,00173$ 000086 42 96 [12] 477 orl _P2M0_REG,a 000088 22 [24] 478 ret 000089 479 00111$: 000089 AF*00 [24] 480 mov r7,_set_m0_PARM_2 00008B 8F F0 [24] 481 mov b,r7 00008D 05 F0 [12] 482 inc b 00008F 74 01 [12] 483 mov a,#0x01 000091 80 02 [24] 484 sjmp 00178$ 000093 485 00176$: 000093 25 E0 [12] 486 add a,acc 000095 487 00178$: 000095 D5 F0 FB [24] 488 djnz b,00176$ 000098 F4 [12] 489 cpl a 000099 52 96 [12] 490 anl _P2M0_REG,a 00009B 22 [24] 491 ret 492 ; src/gpio.c:34: case 3: if (bit) P3M0_REG |= (1 << pin); else P3M0_REG &= ~(1 << pin); break; 00009C 493 00113$: 00009C E5*01 [12] 494 mov a,_set_m0_PARM_3 00009E 60 12 [24] 495 jz 00115$ 0000A0 AF*00 [24] 496 mov r7,_set_m0_PARM_2 0000A2 8F F0 [24] 497 mov b,r7 0000A4 05 F0 [12] 498 inc b 0000A6 74 01 [12] 499 mov a,#0x01 0000A8 80 02 [24] 500 sjmp 00182$ 0000AA 501 00180$: 0000AA 25 E0 [12] 502 add a,acc 0000AC 503 00182$: 0000AC D5 F0 FB [24] 504 djnz b,00180$ 0000AF 42 B2 [12] 505 orl _P3M0_REG,a 0000B1 22 [24] 506 ret 0000B2 507 00115$: 0000B2 AF*00 [24] 508 mov r7,_set_m0_PARM_2 0000B4 8F F0 [24] 509 mov b,r7 0000B6 05 F0 [12] 510 inc b 0000B8 74 01 [12] 511 mov a,#0x01 0000BA 80 02 [24] 512 sjmp 00185$ 0000BC 513 00183$: 0000BC 25 E0 [12] 514 add a,acc 0000BE 515 00185$: 0000BE D5 F0 FB [24] 516 djnz b,00183$ 0000C1 F4 [12] 517 cpl a 0000C2 52 B2 [12] 518 anl _P3M0_REG,a 519 ; src/gpio.c:35: case 4: if (bit) P4M0_REG |= (1 << pin); else P4M0_REG &= ~(1 << pin); break; 0000C4 22 [24] 520 ret 0000C5 521 00117$: 0000C5 E5*01 [12] 522 mov a,_set_m0_PARM_3 0000C7 60 12 [24] 523 jz 00119$ 0000C9 AF*00 [24] 524 mov r7,_set_m0_PARM_2 0000CB 8F F0 [24] 525 mov b,r7 0000CD 05 F0 [12] 526 inc b 0000CF 74 01 [12] 527 mov a,#0x01 0000D1 80 02 [24] 528 sjmp 00189$ 0000D3 529 00187$: 0000D3 25 E0 [12] 530 add a,acc 0000D5 531 00189$: 0000D5 D5 F0 FB [24] 532 djnz b,00187$ 0000D8 42 B4 [12] 533 orl _P4M0_REG,a 0000DA 22 [24] 534 ret 0000DB 535 00119$: 0000DB AF*00 [24] 536 mov r7,_set_m0_PARM_2 0000DD 8F F0 [24] 537 mov b,r7 0000DF 05 F0 [12] 538 inc b 0000E1 74 01 [12] 539 mov a,#0x01 0000E3 80 02 [24] 540 sjmp 00192$ 0000E5 541 00190$: 0000E5 25 E0 [12] 542 add a,acc 0000E7 543 00192$: 0000E7 D5 F0 FB [24] 544 djnz b,00190$ 0000EA F4 [12] 545 cpl a 0000EB 52 B4 [12] 546 anl _P4M0_REG,a 547 ; src/gpio.c:36: case 5: if (bit) P5M0_REG |= (1 << pin); else P5M0_REG &= ~(1 << pin); break; 0000ED 22 [24] 548 ret 0000EE 549 00121$: 0000EE E5*01 [12] 550 mov a,_set_m0_PARM_3 0000F0 60 12 [24] 551 jz 00123$ 0000F2 AF*00 [24] 552 mov r7,_set_m0_PARM_2 0000F4 8F F0 [24] 553 mov b,r7 0000F6 05 F0 [12] 554 inc b 0000F8 74 01 [12] 555 mov a,#0x01 0000FA 80 02 [24] 556 sjmp 00196$ 0000FC 557 00194$: 0000FC 25 E0 [12] 558 add a,acc 0000FE 559 00196$: 0000FE D5 F0 FB [24] 560 djnz b,00194$ 000101 42 CA [12] 561 orl _P5M0_REG,a 000103 22 [24] 562 ret 000104 563 00123$: 000104 AF*00 [24] 564 mov r7,_set_m0_PARM_2 000106 8F F0 [24] 565 mov b,r7 000108 05 F0 [12] 566 inc b 00010A 74 01 [12] 567 mov a,#0x01 00010C 80 02 [24] 568 sjmp 00199$ 00010E 569 00197$: 00010E 25 E0 [12] 570 add a,acc 000110 571 00199$: 000110 D5 F0 FB [24] 572 djnz b,00197$ 000113 F4 [12] 573 cpl a 000114 52 CA [12] 574 anl _P5M0_REG,a 575 ; src/gpio.c:37: } 576 ; src/gpio.c:38: } 000116 22 [24] 577 ret 578 ;------------------------------------------------------------ 579 ;Allocation info for local variables in function 'set_m1' 580 ;------------------------------------------------------------ 581 ;pin Allocated with name '_set_m1_PARM_2' 582 ;bit Allocated with name '_set_m1_PARM_3' 583 ;port Allocated to registers r7 584 ;------------------------------------------------------------ 585 ; src/gpio.c:40: static void set_m1(uint8_t port, uint8_t pin, uint8_t bit) 586 ; ----------------------------------------- 587 ; function set_m1 588 ; ----------------------------------------- 000117 589 _set_m1: 590 ; src/gpio.c:42: switch (port) { 000117 E5 82 [12] 591 mov a,dpl 000119 FF [12] 592 mov r7,a 00011A 24 FA [12] 593 add a,#0xff - 0x05 00011C 50 01 [24] 594 jnc 00156$ 00011E 22 [24] 595 ret 00011F 596 00156$: 00011F EF [12] 597 mov a,r7 000120 2F [12] 598 add a,r7 000121 2F [12] 599 add a,r7 000122 90r01r26 [24] 600 mov dptr,#00157$ 000125 73 [24] 601 jmp @a+dptr 000126 602 00157$: 000126 02r01r38 [24] 603 ljmp 00101$ 000129 02r01r61 [24] 604 ljmp 00105$ 00012C 02r01r8A [24] 605 ljmp 00109$ 00012F 02r01rB3 [24] 606 ljmp 00113$ 000132 02r01rDC [24] 607 ljmp 00117$ 000135 02r02r05 [24] 608 ljmp 00121$ 609 ; src/gpio.c:43: case 0: if (bit) P0M1_REG |= (1 << pin); else P0M1_REG &= ~(1 << pin); break; 000138 610 00101$: 000138 E5*01 [12] 611 mov a,_set_m1_PARM_3 00013A 60 12 [24] 612 jz 00103$ 00013C AF*00 [24] 613 mov r7,_set_m1_PARM_2 00013E 8F F0 [24] 614 mov b,r7 000140 05 F0 [12] 615 inc b 000142 74 01 [12] 616 mov a,#0x01 000144 80 02 [24] 617 sjmp 00161$ 000146 618 00159$: 000146 25 E0 [12] 619 add a,acc 000148 620 00161$: 000148 D5 F0 FB [24] 621 djnz b,00159$ 00014B 42 93 [12] 622 orl _P0M1_REG,a 00014D 22 [24] 623 ret 00014E 624 00103$: 00014E AF*00 [24] 625 mov r7,_set_m1_PARM_2 000150 8F F0 [24] 626 mov b,r7 000152 05 F0 [12] 627 inc b 000154 74 01 [12] 628 mov a,#0x01 000156 80 02 [24] 629 sjmp 00164$ 000158 630 00162$: 000158 25 E0 [12] 631 add a,acc 00015A 632 00164$: 00015A D5 F0 FB [24] 633 djnz b,00162$ 00015D F4 [12] 634 cpl a 00015E 52 93 [12] 635 anl _P0M1_REG,a 000160 22 [24] 636 ret 637 ; src/gpio.c:44: case 1: if (bit) P1M1_REG |= (1 << pin); else P1M1_REG &= ~(1 << pin); break; 000161 638 00105$: 000161 E5*01 [12] 639 mov a,_set_m1_PARM_3 000163 60 12 [24] 640 jz 00107$ 000165 AF*00 [24] 641 mov r7,_set_m1_PARM_2 000167 8F F0 [24] 642 mov b,r7 000169 05 F0 [12] 643 inc b 00016B 74 01 [12] 644 mov a,#0x01 00016D 80 02 [24] 645 sjmp 00168$ 00016F 646 00166$: 00016F 25 E0 [12] 647 add a,acc 000171 648 00168$: 000171 D5 F0 FB [24] 649 djnz b,00166$ 000174 42 91 [12] 650 orl _P1M1_REG,a 000176 22 [24] 651 ret 000177 652 00107$: 000177 AF*00 [24] 653 mov r7,_set_m1_PARM_2 000179 8F F0 [24] 654 mov b,r7 00017B 05 F0 [12] 655 inc b 00017D 74 01 [12] 656 mov a,#0x01 00017F 80 02 [24] 657 sjmp 00171$ 000181 658 00169$: 000181 25 E0 [12] 659 add a,acc 000183 660 00171$: 000183 D5 F0 FB [24] 661 djnz b,00169$ 000186 F4 [12] 662 cpl a 000187 52 91 [12] 663 anl _P1M1_REG,a 000189 22 [24] 664 ret 665 ; src/gpio.c:45: case 2: if (bit) P2M1_REG |= (1 << pin); else P2M1_REG &= ~(1 << pin); break; 00018A 666 00109$: 00018A E5*01 [12] 667 mov a,_set_m1_PARM_3 00018C 60 12 [24] 668 jz 00111$ 00018E AF*00 [24] 669 mov r7,_set_m1_PARM_2 000190 8F F0 [24] 670 mov b,r7 000192 05 F0 [12] 671 inc b 000194 74 01 [12] 672 mov a,#0x01 000196 80 02 [24] 673 sjmp 00175$ 000198 674 00173$: 000198 25 E0 [12] 675 add a,acc 00019A 676 00175$: 00019A D5 F0 FB [24] 677 djnz b,00173$ 00019D 42 95 [12] 678 orl _P2M1_REG,a 00019F 22 [24] 679 ret 0001A0 680 00111$: 0001A0 AF*00 [24] 681 mov r7,_set_m1_PARM_2 0001A2 8F F0 [24] 682 mov b,r7 0001A4 05 F0 [12] 683 inc b 0001A6 74 01 [12] 684 mov a,#0x01 0001A8 80 02 [24] 685 sjmp 00178$ 0001AA 686 00176$: 0001AA 25 E0 [12] 687 add a,acc 0001AC 688 00178$: 0001AC D5 F0 FB [24] 689 djnz b,00176$ 0001AF F4 [12] 690 cpl a 0001B0 52 95 [12] 691 anl _P2M1_REG,a 0001B2 22 [24] 692 ret 693 ; src/gpio.c:46: case 3: if (bit) P3M1_REG |= (1 << pin); else P3M1_REG &= ~(1 << pin); break; 0001B3 694 00113$: 0001B3 E5*01 [12] 695 mov a,_set_m1_PARM_3 0001B5 60 12 [24] 696 jz 00115$ 0001B7 AF*00 [24] 697 mov r7,_set_m1_PARM_2 0001B9 8F F0 [24] 698 mov b,r7 0001BB 05 F0 [12] 699 inc b 0001BD 74 01 [12] 700 mov a,#0x01 0001BF 80 02 [24] 701 sjmp 00182$ 0001C1 702 00180$: 0001C1 25 E0 [12] 703 add a,acc 0001C3 704 00182$: 0001C3 D5 F0 FB [24] 705 djnz b,00180$ 0001C6 42 B1 [12] 706 orl _P3M1_REG,a 0001C8 22 [24] 707 ret 0001C9 708 00115$: 0001C9 AF*00 [24] 709 mov r7,_set_m1_PARM_2 0001CB 8F F0 [24] 710 mov b,r7 0001CD 05 F0 [12] 711 inc b 0001CF 74 01 [12] 712 mov a,#0x01 0001D1 80 02 [24] 713 sjmp 00185$ 0001D3 714 00183$: 0001D3 25 E0 [12] 715 add a,acc 0001D5 716 00185$: 0001D5 D5 F0 FB [24] 717 djnz b,00183$ 0001D8 F4 [12] 718 cpl a 0001D9 52 B1 [12] 719 anl _P3M1_REG,a 720 ; src/gpio.c:47: case 4: if (bit) P4M1_REG |= (1 << pin); else P4M1_REG &= ~(1 << pin); break; 0001DB 22 [24] 721 ret 0001DC 722 00117$: 0001DC E5*01 [12] 723 mov a,_set_m1_PARM_3 0001DE 60 12 [24] 724 jz 00119$ 0001E0 AF*00 [24] 725 mov r7,_set_m1_PARM_2 0001E2 8F F0 [24] 726 mov b,r7 0001E4 05 F0 [12] 727 inc b 0001E6 74 01 [12] 728 mov a,#0x01 0001E8 80 02 [24] 729 sjmp 00189$ 0001EA 730 00187$: 0001EA 25 E0 [12] 731 add a,acc 0001EC 732 00189$: 0001EC D5 F0 FB [24] 733 djnz b,00187$ 0001EF 42 B3 [12] 734 orl _P4M1_REG,a 0001F1 22 [24] 735 ret 0001F2 736 00119$: 0001F2 AF*00 [24] 737 mov r7,_set_m1_PARM_2 0001F4 8F F0 [24] 738 mov b,r7 0001F6 05 F0 [12] 739 inc b 0001F8 74 01 [12] 740 mov a,#0x01 0001FA 80 02 [24] 741 sjmp 00192$ 0001FC 742 00190$: 0001FC 25 E0 [12] 743 add a,acc 0001FE 744 00192$: 0001FE D5 F0 FB [24] 745 djnz b,00190$ 000201 F4 [12] 746 cpl a 000202 52 B3 [12] 747 anl _P4M1_REG,a 748 ; src/gpio.c:48: case 5: if (bit) P5M1_REG |= (1 << pin); else P5M1_REG &= ~(1 << pin); break; 000204 22 [24] 749 ret 000205 750 00121$: 000205 E5*01 [12] 751 mov a,_set_m1_PARM_3 000207 60 12 [24] 752 jz 00123$ 000209 AF*00 [24] 753 mov r7,_set_m1_PARM_2 00020B 8F F0 [24] 754 mov b,r7 00020D 05 F0 [12] 755 inc b 00020F 74 01 [12] 756 mov a,#0x01 000211 80 02 [24] 757 sjmp 00196$ 000213 758 00194$: 000213 25 E0 [12] 759 add a,acc 000215 760 00196$: 000215 D5 F0 FB [24] 761 djnz b,00194$ 000218 42 C9 [12] 762 orl _P5M1_REG,a 00021A 22 [24] 763 ret 00021B 764 00123$: 00021B AF*00 [24] 765 mov r7,_set_m1_PARM_2 00021D 8F F0 [24] 766 mov b,r7 00021F 05 F0 [12] 767 inc b 000221 74 01 [12] 768 mov a,#0x01 000223 80 02 [24] 769 sjmp 00199$ 000225 770 00197$: 000225 25 E0 [12] 771 add a,acc 000227 772 00199$: 000227 D5 F0 FB [24] 773 djnz b,00197$ 00022A F4 [12] 774 cpl a 00022B 52 C9 [12] 775 anl _P5M1_REG,a 776 ; src/gpio.c:49: } 777 ; src/gpio.c:50: } 00022D 22 [24] 778 ret 779 ;------------------------------------------------------------ 780 ;Allocation info for local variables in function 'gpio_set_mode' 781 ;------------------------------------------------------------ 782 ;pin Allocated with name '_gpio_set_mode_PARM_2' 783 ;mode Allocated with name '_gpio_set_mode_PARM_3' 784 ;port Allocated to registers r7 785 ;m0_bit Allocated to registers 786 ;m1_bit Allocated to registers r6 787 ;------------------------------------------------------------ 788 ; src/gpio.c:52: void gpio_set_mode(uint8_t port, uint8_t pin, GPIOMode_e mode) 789 ; ----------------------------------------- 790 ; function gpio_set_mode 791 ; ----------------------------------------- 00022E 792 _gpio_set_mode: 793 ; src/gpio.c:54: if (port > 5 || pin > 7) return; 00022E E5 82 [12] 794 mov a,dpl 000230 FF [12] 795 mov r7,a 000231 24 FA [12] 796 add a,#0xff - 0x05 000233 40 06 [24] 797 jc 00101$ 000235 E5*00 [12] 798 mov a,_gpio_set_mode_PARM_2 000237 24 F8 [12] 799 add a,#0xff - 0x07 000239 50 01 [24] 800 jnc 00102$ 00023B 801 00101$: 00023B 22 [24] 802 ret 00023C 803 00102$: 804 ; src/gpio.c:55: uint8_t m0_bit = (mode >> 0) & 0x01; 00023C E5*01 [12] 805 mov a,_gpio_set_mode_PARM_3 00023E 54 01 [12] 806 anl a,#0x01 000240 F5*01 [12] 807 mov _set_m0_PARM_3,a 808 ; src/gpio.c:56: uint8_t m1_bit = (mode >> 1) & 0x01; 000242 E5*01 [12] 809 mov a,_gpio_set_mode_PARM_3 000244 03 [12] 810 rr a 000245 54 01 [12] 811 anl a,#0x01 000247 FE [12] 812 mov r6,a 813 ; src/gpio.c:57: set_m0(port, pin, m0_bit); 000248 85*00*00 [24] 814 mov _set_m0_PARM_2,_gpio_set_mode_PARM_2 00024B 8F 82 [24] 815 mov dpl,r7 00024D C0 07 [24] 816 push ar7 00024F C0 06 [24] 817 push ar6 000251 12r00r00 [24] 818 lcall _set_m0 000254 D0 06 [24] 819 pop ar6 000256 D0 07 [24] 820 pop ar7 821 ; src/gpio.c:58: set_m1(port, pin, m1_bit); 000258 85*00*00 [24] 822 mov _set_m1_PARM_2,_gpio_set_mode_PARM_2 00025B 8E*01 [24] 823 mov _set_m1_PARM_3,r6 00025D 8F 82 [24] 824 mov dpl,r7 825 ; src/gpio.c:59: } 00025F 02r01r17 [24] 826 ljmp _set_m1 827 ;------------------------------------------------------------ 828 ;Allocation info for local variables in function 'gpio_write' 829 ;------------------------------------------------------------ 830 ;pin Allocated with name '_gpio_write_PARM_2' 831 ;val Allocated with name '_gpio_write_PARM_3' 832 ;port Allocated to registers r7 833 ;mask Allocated to registers r5 834 ;------------------------------------------------------------ 835 ; src/gpio.c:61: void gpio_write(uint8_t port, uint8_t pin, uint8_t val) 836 ; ----------------------------------------- 837 ; function gpio_write 838 ; ----------------------------------------- 000262 839 _gpio_write: 000262 AF 82 [24] 840 mov r7,dpl 841 ; src/gpio.c:63: if (port > 5 || pin > 7) return; 000264 C3 [12] 842 clr c 000265 74 05 [12] 843 mov a,#0x05 000267 9F [12] 844 subb a,r7 000268 E4 [12] 845 clr a 000269 33 [12] 846 rlc a 00026A FE [12] 847 mov r6,a 00026B 70 06 [24] 848 jnz 00101$ 00026D E5*00 [12] 849 mov a,_gpio_write_PARM_2 00026F 24 F8 [12] 850 add a,#0xff - 0x07 000271 50 01 [24] 851 jnc 00102$ 000273 852 00101$: 000273 22 [24] 853 ret 000274 854 00102$: 855 ; src/gpio.c:64: uint8_t mask = (1 << pin); 000274 AD*00 [24] 856 mov r5,_gpio_write_PARM_2 000276 8D F0 [24] 857 mov b,r5 000278 05 F0 [12] 858 inc b 00027A 74 01 [12] 859 mov a,#0x01 00027C 80 02 [24] 860 sjmp 00167$ 00027E 861 00165$: 00027E 25 E0 [12] 862 add a,acc 000280 863 00167$: 000280 D5 F0 FB [24] 864 djnz b,00165$ 000283 FD [12] 865 mov r5,a 866 ; src/gpio.c:65: switch (port) { 000284 EE [12] 867 mov a,r6 000285 60 01 [24] 868 jz 00168$ 000287 22 [24] 869 ret 000288 870 00168$: 000288 EF [12] 871 mov a,r7 000289 2F [12] 872 add a,r7 873 ; src/gpio.c:66: case 0: if (val) P0_REG |= mask; else P0_REG &= ~mask; break; 00028A 90r02r8E [24] 874 mov dptr,#00169$ 00028D 73 [24] 875 jmp @a+dptr 00028E 876 00169$: 00028E 80 0A [24] 877 sjmp 00104$ 000290 80 15 [24] 878 sjmp 00108$ 000292 80 20 [24] 879 sjmp 00112$ 000294 80 2B [24] 880 sjmp 00116$ 000296 80 36 [24] 881 sjmp 00120$ 000298 80 41 [24] 882 sjmp 00124$ 00029A 883 00104$: 00029A E5*01 [12] 884 mov a,_gpio_write_PARM_3 00029C 60 04 [24] 885 jz 00106$ 00029E ED [12] 886 mov a,r5 00029F 42 80 [12] 887 orl _P0_REG,a 0002A1 22 [24] 888 ret 0002A2 889 00106$: 0002A2 ED [12] 890 mov a,r5 0002A3 F4 [12] 891 cpl a 0002A4 52 80 [12] 892 anl _P0_REG,a 893 ; src/gpio.c:67: case 1: if (val) P1_REG |= mask; else P1_REG &= ~mask; break; 0002A6 22 [24] 894 ret 0002A7 895 00108$: 0002A7 E5*01 [12] 896 mov a,_gpio_write_PARM_3 0002A9 60 04 [24] 897 jz 00110$ 0002AB ED [12] 898 mov a,r5 0002AC 42 90 [12] 899 orl _P1_REG,a 0002AE 22 [24] 900 ret 0002AF 901 00110$: 0002AF ED [12] 902 mov a,r5 0002B0 F4 [12] 903 cpl a 0002B1 52 90 [12] 904 anl _P1_REG,a 905 ; src/gpio.c:68: case 2: if (val) P2_REG |= mask; else P2_REG &= ~mask; break; 0002B3 22 [24] 906 ret 0002B4 907 00112$: 0002B4 E5*01 [12] 908 mov a,_gpio_write_PARM_3 0002B6 60 04 [24] 909 jz 00114$ 0002B8 ED [12] 910 mov a,r5 0002B9 42 A0 [12] 911 orl _P2_REG,a 0002BB 22 [24] 912 ret 0002BC 913 00114$: 0002BC ED [12] 914 mov a,r5 0002BD F4 [12] 915 cpl a 0002BE 52 A0 [12] 916 anl _P2_REG,a 917 ; src/gpio.c:69: case 3: if (val) P3_REG |= mask; else P3_REG &= ~mask; break; 0002C0 22 [24] 918 ret 0002C1 919 00116$: 0002C1 E5*01 [12] 920 mov a,_gpio_write_PARM_3 0002C3 60 04 [24] 921 jz 00118$ 0002C5 ED [12] 922 mov a,r5 0002C6 42 B0 [12] 923 orl _P3_REG,a 0002C8 22 [24] 924 ret 0002C9 925 00118$: 0002C9 ED [12] 926 mov a,r5 0002CA F4 [12] 927 cpl a 0002CB 52 B0 [12] 928 anl _P3_REG,a 929 ; src/gpio.c:70: case 4: if (val) P4_REG |= mask; else P4_REG &= ~mask; break; 0002CD 22 [24] 930 ret 0002CE 931 00120$: 0002CE E5*01 [12] 932 mov a,_gpio_write_PARM_3 0002D0 60 04 [24] 933 jz 00122$ 0002D2 ED [12] 934 mov a,r5 0002D3 42 C0 [12] 935 orl _P4_REG,a 0002D5 22 [24] 936 ret 0002D6 937 00122$: 0002D6 ED [12] 938 mov a,r5 0002D7 F4 [12] 939 cpl a 0002D8 52 C0 [12] 940 anl _P4_REG,a 941 ; src/gpio.c:71: case 5: if (val) P5_REG |= mask; else P5_REG &= ~mask; break; 0002DA 22 [24] 942 ret 0002DB 943 00124$: 0002DB E5*01 [12] 944 mov a,_gpio_write_PARM_3 0002DD 60 04 [24] 945 jz 00126$ 0002DF ED [12] 946 mov a,r5 0002E0 42 C8 [12] 947 orl _P5_REG,a 0002E2 22 [24] 948 ret 0002E3 949 00126$: 0002E3 ED [12] 950 mov a,r5 0002E4 F4 [12] 951 cpl a 0002E5 52 C8 [12] 952 anl _P5_REG,a 953 ; src/gpio.c:72: } 954 ; src/gpio.c:73: } 0002E7 22 [24] 955 ret 956 ;------------------------------------------------------------ 957 ;Allocation info for local variables in function 'gpio_read' 958 ;------------------------------------------------------------ 959 ;pin Allocated with name '_gpio_read_PARM_2' 960 ;port Allocated to registers r7 961 ;mask Allocated to registers r5 962 ;------------------------------------------------------------ 963 ; src/gpio.c:75: uint8_t gpio_read(uint8_t port, uint8_t pin) 964 ; ----------------------------------------- 965 ; function gpio_read 966 ; ----------------------------------------- 0002E8 967 _gpio_read: 0002E8 AF 82 [24] 968 mov r7,dpl 969 ; src/gpio.c:77: if (port > 5 || pin > 7) return 0; 0002EA C3 [12] 970 clr c 0002EB 74 05 [12] 971 mov a,#0x05 0002ED 9F [12] 972 subb a,r7 0002EE E4 [12] 973 clr a 0002EF 33 [12] 974 rlc a 0002F0 FE [12] 975 mov r6,a 0002F1 70 06 [24] 976 jnz 00101$ 0002F3 E5*00 [12] 977 mov a,_gpio_read_PARM_2 0002F5 24 F8 [12] 978 add a,#0xff - 0x07 0002F7 50 04 [24] 979 jnc 00102$ 0002F9 980 00101$: 0002F9 75 82 00 [24] 981 mov dpl,#0x00 0002FC 22 [24] 982 ret 0002FD 983 00102$: 984 ; src/gpio.c:78: uint8_t mask = (1 << pin); 0002FD AD*00 [24] 985 mov r5,_gpio_read_PARM_2 0002FF 8D F0 [24] 986 mov b,r5 000301 05 F0 [12] 987 inc b 000303 74 01 [12] 988 mov a,#0x01 000305 80 02 [24] 989 sjmp 00161$ 000307 990 00159$: 000307 25 E0 [12] 991 add a,acc 000309 992 00161$: 000309 D5 F0 FB [24] 993 djnz b,00159$ 00030C FD [12] 994 mov r5,a 995 ; src/gpio.c:79: switch (port) { 00030D EE [12] 996 mov a,r6 00030E 60 03 [24] 997 jz 00162$ 000310 02r03r91 [24] 998 ljmp 00110$ 000313 999 00162$: 000313 EF [12] 1000 mov a,r7 000314 2F [12] 1001 add a,r7 1002 ; src/gpio.c:80: case 0: return (P0_REG & mask) ? 1 : 0; 000315 90r03r19 [24] 1003 mov dptr,#00163$ 000318 73 [24] 1004 jmp @a+dptr 000319 1005 00163$: 000319 80 0A [24] 1006 sjmp 00104$ 00031B 80 1A [24] 1007 sjmp 00105$ 00031D 80 2A [24] 1008 sjmp 00106$ 00031F 80 3A [24] 1009 sjmp 00107$ 000321 80 4A [24] 1010 sjmp 00108$ 000323 80 5A [24] 1011 sjmp 00109$ 000325 1012 00104$: 000325 ED [12] 1013 mov a,r5 000326 55 80 [12] 1014 anl a,_P0_REG 000328 60 06 [24] 1015 jz 00113$ 00032A 7E 01 [12] 1016 mov r6,#0x01 00032C 7F 00 [12] 1017 mov r7,#0x00 00032E 80 04 [24] 1018 sjmp 00114$ 000330 1019 00113$: 000330 7E 00 [12] 1020 mov r6,#0x00 000332 7F 00 [12] 1021 mov r7,#0x00 000334 1022 00114$: 000334 8E 82 [24] 1023 mov dpl,r6 1024 ; src/gpio.c:81: case 1: return (P1_REG & mask) ? 1 : 0; 000336 22 [24] 1025 ret 000337 1026 00105$: 000337 ED [12] 1027 mov a,r5 000338 55 90 [12] 1028 anl a,_P1_REG 00033A 60 06 [24] 1029 jz 00115$ 00033C 7E 01 [12] 1030 mov r6,#0x01 00033E 7F 00 [12] 1031 mov r7,#0x00 000340 80 04 [24] 1032 sjmp 00116$ 000342 1033 00115$: 000342 7E 00 [12] 1034 mov r6,#0x00 000344 7F 00 [12] 1035 mov r7,#0x00 000346 1036 00116$: 000346 8E 82 [24] 1037 mov dpl,r6 1038 ; src/gpio.c:82: case 2: return (P2_REG & mask) ? 1 : 0; 000348 22 [24] 1039 ret 000349 1040 00106$: 000349 ED [12] 1041 mov a,r5 00034A 55 A0 [12] 1042 anl a,_P2_REG 00034C 60 06 [24] 1043 jz 00117$ 00034E 7E 01 [12] 1044 mov r6,#0x01 000350 7F 00 [12] 1045 mov r7,#0x00 000352 80 04 [24] 1046 sjmp 00118$ 000354 1047 00117$: 000354 7E 00 [12] 1048 mov r6,#0x00 000356 7F 00 [12] 1049 mov r7,#0x00 000358 1050 00118$: 000358 8E 82 [24] 1051 mov dpl,r6 1052 ; src/gpio.c:83: case 3: return (P3_REG & mask) ? 1 : 0; 00035A 22 [24] 1053 ret 00035B 1054 00107$: 00035B ED [12] 1055 mov a,r5 00035C 55 B0 [12] 1056 anl a,_P3_REG 00035E 60 06 [24] 1057 jz 00119$ 000360 7E 01 [12] 1058 mov r6,#0x01 000362 7F 00 [12] 1059 mov r7,#0x00 000364 80 04 [24] 1060 sjmp 00120$ 000366 1061 00119$: 000366 7E 00 [12] 1062 mov r6,#0x00 000368 7F 00 [12] 1063 mov r7,#0x00 00036A 1064 00120$: 00036A 8E 82 [24] 1065 mov dpl,r6 1066 ; src/gpio.c:84: case 4: return (P4_REG & mask) ? 1 : 0; 00036C 22 [24] 1067 ret 00036D 1068 00108$: 00036D ED [12] 1069 mov a,r5 00036E 55 C0 [12] 1070 anl a,_P4_REG 000370 60 06 [24] 1071 jz 00121$ 000372 7E 01 [12] 1072 mov r6,#0x01 000374 7F 00 [12] 1073 mov r7,#0x00 000376 80 04 [24] 1074 sjmp 00122$ 000378 1075 00121$: 000378 7E 00 [12] 1076 mov r6,#0x00 00037A 7F 00 [12] 1077 mov r7,#0x00 00037C 1078 00122$: 00037C 8E 82 [24] 1079 mov dpl,r6 1080 ; src/gpio.c:85: case 5: return (P5_REG & mask) ? 1 : 0; 00037E 22 [24] 1081 ret 00037F 1082 00109$: 00037F ED [12] 1083 mov a,r5 000380 55 C8 [12] 1084 anl a,_P5_REG 000382 60 06 [24] 1085 jz 00123$ 000384 7E 01 [12] 1086 mov r6,#0x01 000386 7F 00 [12] 1087 mov r7,#0x00 000388 80 04 [24] 1088 sjmp 00124$ 00038A 1089 00123$: 00038A 7E 00 [12] 1090 mov r6,#0x00 00038C 7F 00 [12] 1091 mov r7,#0x00 00038E 1092 00124$: 00038E 8E 82 [24] 1093 mov dpl,r6 1094 ; src/gpio.c:86: } 000390 22 [24] 1095 ret 000391 1096 00110$: 1097 ; src/gpio.c:87: return 0; 000391 75 82 00 [24] 1098 mov dpl,#0x00 1099 ; src/gpio.c:88: } 000394 22 [24] 1100 ret 1101 ;------------------------------------------------------------ 1102 ;Allocation info for local variables in function 'gpio_toggle' 1103 ;------------------------------------------------------------ 1104 ;pin Allocated with name '_gpio_toggle_PARM_2' 1105 ;port Allocated to registers r7 1106 ;mask Allocated to registers r5 1107 ;------------------------------------------------------------ 1108 ; src/gpio.c:90: void gpio_toggle(uint8_t port, uint8_t pin) 1109 ; ----------------------------------------- 1110 ; function gpio_toggle 1111 ; ----------------------------------------- 000395 1112 _gpio_toggle: 000395 AF 82 [24] 1113 mov r7,dpl 1114 ; src/gpio.c:92: if (port > 5 || pin > 7) return; 000397 C3 [12] 1115 clr c 000398 74 05 [12] 1116 mov a,#0x05 00039A 9F [12] 1117 subb a,r7 00039B E4 [12] 1118 clr a 00039C 33 [12] 1119 rlc a 00039D FE [12] 1120 mov r6,a 00039E 70 06 [24] 1121 jnz 00101$ 0003A0 E5*00 [12] 1122 mov a,_gpio_toggle_PARM_2 0003A2 24 F8 [12] 1123 add a,#0xff - 0x07 0003A4 50 01 [24] 1124 jnc 00102$ 0003A6 1125 00101$: 0003A6 22 [24] 1126 ret 0003A7 1127 00102$: 1128 ; src/gpio.c:93: uint8_t mask = (1 << pin); 0003A7 AD*00 [24] 1129 mov r5,_gpio_toggle_PARM_2 0003A9 8D F0 [24] 1130 mov b,r5 0003AB 05 F0 [12] 1131 inc b 0003AD 74 01 [12] 1132 mov a,#0x01 0003AF 80 02 [24] 1133 sjmp 00125$ 0003B1 1134 00123$: 0003B1 25 E0 [12] 1135 add a,acc 0003B3 1136 00125$: 0003B3 D5 F0 FB [24] 1137 djnz b,00123$ 0003B6 FD [12] 1138 mov r5,a 1139 ; src/gpio.c:94: switch (port) { 0003B7 EE [12] 1140 mov a,r6 0003B8 70 29 [24] 1141 jnz 00111$ 0003BA EF [12] 1142 mov a,r7 0003BB 2F [12] 1143 add a,r7 1144 ; src/gpio.c:95: case 0: P0_REG ^= mask; break; 0003BC 90r03rC0 [24] 1145 mov dptr,#00127$ 0003BF 73 [24] 1146 jmp @a+dptr 0003C0 1147 00127$: 0003C0 80 0A [24] 1148 sjmp 00104$ 0003C2 80 0C [24] 1149 sjmp 00105$ 0003C4 80 0E [24] 1150 sjmp 00106$ 0003C6 80 10 [24] 1151 sjmp 00107$ 0003C8 80 12 [24] 1152 sjmp 00108$ 0003CA 80 14 [24] 1153 sjmp 00109$ 0003CC 1154 00104$: 0003CC ED [12] 1155 mov a,r5 0003CD 62 80 [12] 1156 xrl _P0_REG,a 1157 ; src/gpio.c:96: case 1: P1_REG ^= mask; break; 0003CF 22 [24] 1158 ret 0003D0 1159 00105$: 0003D0 ED [12] 1160 mov a,r5 0003D1 62 90 [12] 1161 xrl _P1_REG,a 1162 ; src/gpio.c:97: case 2: P2_REG ^= mask; break; 0003D3 22 [24] 1163 ret 0003D4 1164 00106$: 0003D4 ED [12] 1165 mov a,r5 0003D5 62 A0 [12] 1166 xrl _P2_REG,a 1167 ; src/gpio.c:98: case 3: P3_REG ^= mask; break; 0003D7 22 [24] 1168 ret 0003D8 1169 00107$: 0003D8 ED [12] 1170 mov a,r5 0003D9 62 B0 [12] 1171 xrl _P3_REG,a 1172 ; src/gpio.c:99: case 4: P4_REG ^= mask; break; 0003DB 22 [24] 1173 ret 0003DC 1174 00108$: 0003DC ED [12] 1175 mov a,r5 0003DD 62 C0 [12] 1176 xrl _P4_REG,a 1177 ; src/gpio.c:100: case 5: P5_REG ^= mask; break; 0003DF 22 [24] 1178 ret 0003E0 1179 00109$: 0003E0 ED [12] 1180 mov a,r5 0003E1 62 C8 [12] 1181 xrl _P5_REG,a 1182 ; src/gpio.c:101: } 0003E3 1183 00111$: 1184 ; src/gpio.c:102: } 0003E3 22 [24] 1185 ret 1186 .area CSEG (CODE) 1187 .area CONST (CODE) 1188 .area XINIT (CODE) 1189 .area CABS (ABS,CODE)